DMA Controller 8237:

In I/O data transfer, data is transferred by using microprocessor. The microprocessor will read
data from I.O device and then will write data to memory.
In this case, there are two operations for single data transfer. If the data is less them processor
time will not waste. But to transfer huge amounts of data has to transferred them the rate of
transfer will slow down because of the processor intervention for every cycle.
To overcome this problem, the process can be speeded up by giving the I/O direct access to the
memory. This method of giving the I/O devices direct access to the buses of processor is called
as Direct Memory Access (DMA).
The I/O can have direct access to the processor bus but under supervision. The device which
supervises data transfer is named as DMA Controller.
Intel had first developed a DMA Controller 8257, which has four channels. On behalf of the
I/O devices this controller will request the processor for bus control and performs the operation
and also it has a priority resolver which will help in resolving which one to attend first in case
of multiple simultaneous requests.
Later, an advanced Programmable DMA Controller 8237 was developed, which provides a
better performance.
Comparison of 8257 and 8237:
Both are capable of transferring a byte or a bulk of data between system memory and peripheral
in either direction.
Memory to memory data transfer facility is available in 8237.
Both support four independent DMA channels which may be expanded to any number by
cascading a greater number of 8237.
The TC (Terminal Count) pin of 8257 is called EOP (End of Process), both indicate the same
operation.
When compared to 8257, 8237 provides many programmable controls and dynamic
reconfigurability features which enhance the data transfer rate of the system remarkably.
DMA Operations with 8237:
8237 operates in two cycles. 1. Passive cycle, 2. Active Cycle. Each cycle contains fixed
number of states. 8237 can have six states in Active cycle and during passive cycle it will be
in a single state called as Idle State SI.
Passive Cycle: 8237 will be initially in this cycle. This cycle has a single state called as Idle
State. In idle state 8237 does not have any valid pending DMA request. When there is a DMA
request, idle state ends and 8237 enters into active cycle.
Active Cycle: Once there is a DMA request, 8237 enters into state S0, which is the first state
of DMA operation. 8237 requests the processor for a DMA operation by sending HOLD signal.
If CPU has not acknowledged the request, the 8237 waits in S0 state until it receives the HLDA
signal from CPU. Once the Acknowledge signal is received that means the data transfer can
start.
The stages S1, S2, S3 and S4 are working states of DMA transfer, actual data transfer operation
happens here. If more time is needed to complete the DMA operation Wait states may be
inserted between the above states using READY pin.
A memory to memory transfer is a two-cycle operation, and requires a read from and a write
to memory cycle to complete each DMA transfer. Each of these two types of cycles, require
four states for its completion. Thus, a total of 8 cycles are required for one transfer operation.
The first four states are used for read from memory cycle and denoted by S11, S12, S13, S14
and the next four states are for write to memory cycle and denoted by S21, S22, S23 and S24,
Memory to Memory Transfer
To transfer a block of data from one memory to another memory this transfer method is used.
Using the LSB of Command register this mode can be enabled. Channel 0 is used as source
and channel 1 is used as destination in this transfer.
The channel 0 current address register acts as source pointer. The byte of data read from the
memory is stored in temporary register. Channel 1 current address register acts as destination
pointer to write data from temporary register to destination memory location. The pointers are
automatically incremented or decremented, depending on the programming. The channel 1-
word count register used as counter and on every transfer operation counter decrement and
when count reaches zero, EOP generated.
Internal Architecture of 8237:

Architecture of 8237 DMA Controller

 The 8237 contains three main blocks of its operational logic. Timing and control block,
program command control block and Priority Encoder block. The timing and control block
generate the internal timings and external control signals. It also derives necessary timings from
the LCK input. The program command control block decodes the various commands given to
the 8237 by the CPU before servicing a DMA request. It also decodes the mode control word
used to select the type of the programmed DMA transfer. The Priority Encoder block resolves
priority between the DMA channels requesting the services simultaneously.
Register Organization of 8237:
8237 has 12 types of registers. Some of these registers are present in 4 channels while
remaining are common for all the channels.
Current Address Register:

• Each of 4 channels has a current address register.

• It is a 16-bit register.
• Holds current memory address being accessed during the DMA transfer.
• Address is automatically incremented or decremented after each cycle and stored in the
same register.
• This can be reinitialized by an auto initialization command to its original value after
EOP.
Current Word Register:

• Each channel has a current word register.

• It is a 16-bit register.
• Holds the number of data byte transfers that are remaining.
• Word count is decremented after each DMA cycle and stored in the same register.
• When count becomes zero an EOP signal will be generated.
Base Address and Base Word count Registers:

• Each channel has a pair of these registers.

• Both of them are 16-bit registers.
• They store an original copy of the initial address and initial count that was stored in
CAR and CWR respectively.
• These are automatically written along with current registers during initialization of the
DMA operation. Used for auto initialization.
Temporary Register:

• It is an 8-bit register.
• Holds data during memory-to-memory data transfers.
• After the completion of the transfer operation, the last word transferred remains in the
temporary register till it is cleared by a reset operation.
Command Register:

• 8237 has 8-bit command register. This can be programmed by CPU and cleared by a
reset operation.

• B0: Enables the memory-to-memory transfer operation. Set this bit to start a memory
to memory transfer.
• B1: Set this bit to make channel 0 as source channel and enables channel 0 address. If
B0=0 then this bit is ignored.
• B2: To enable or disable to DMA controller.
• B3: If this bit is set, then the channel works will be compressed for the DMA operation
so that the time taken for the total transfer will decrease. This is used only for I/O
devices not for memory to memory transfers.
• B4: Set this bit to rotate the priority of the channels of DMA controller. If this bit is 0
then Controller will follow fixed priority.
 Fixed Priority Scheme: In fixed priority scheme, channel 3 has the lowest priority
followed by channels 2 and 1. Channel 0 has the highest priority.
Rotating Priority Scheme: In this scheme the priorities assigned to the channels are not
fixed. The channel which is served will go to lowest priority and immediate channel
will get the highest priority. If channel 0 has highest priority, it gets service and once it
is served it goes to the lowest priority and channel 1 becomes the highest priority
channel. Likewise, priority rotates.
• B5: Set this bit to extend the write cycle while dealing with slow peripherals to prevent
the loss of data. If compressed timing is chosen this bit is ignored.
• B6: If this bit is 1, DREQ pins act as active HIGH otherwise they are active LOW.
• B7: If this bit is 1, DACK pins act as active HIGH otherwise they are active LOW.
Mode Register:

• It is an 8-bit channel. Written by CPU in program mode.

• B0, B1: these bits determine which channel is to be used for the operation.
• B2, B3: these bits are used to specify which type of DMA transfer is to be performed
among read, write and verify transfer.
• B4: Set this bit to enable auto initialization during DMA operation.
• B5: If this bit is 1, then the CAR is to be decremented for each cycle whereas if it is 0
then the CAR incremented after each cycle.
 • B6, B7: These bits are used to select in which mode the selected channel should perform
the transfer. There are 4 modes among which the selection is shown above.
Request Register:

• It is an 8-bit register. Each channel has a request bit associated with it, in request
register.
• B0, B1: to select among the 4 channels.
• B2: If this bit is 1- Request bit corresponding to the channel selected will be set. If this
bit is 0, the request bit corresponding to the channel will be reset.
• All remaining bit will be ignored.
Mask Register:

Masking channels individually

Simultaneous Masking of channels

 • To disable a DMA channel this register is used. Each channel has a mask bit associated
with it. If this bit is set, then the channel will be masked viz. any request that comes at
this channel will be left un noticed.
• This masking can be done in two ways. The channels can be masked individually or
simultaneously. The register configuration for both types of masking is shown above.
• In individual masking, two bits are dedicated for channel selection and one bit used for
setting or resetting mask bit.
• In simultaneous masking, each channel has a bit to mask or unmask.
Status Register:

• It is an 8-bit register.
• It keeps track of all the DMA channel pending requests and the status of their terminal
counts.
• B0-B3: These four bits corresponds to four channels and set every time, when the
corresponding channel reached Terminal count or an external EOP occurs.
• B4-B7: These four bits corresponds to four channel and set if the corresponding channel
has pending request services.
Modes of operation of 8237:
The data transfer in 8237 can take place in 4 different types of transfer modes. These modes
can be programmed using mode register. They are:
Single Transfer Mode:

• In this mode, the device transfers only one byte per request. The word count is
decremented and the address is incremented or decremented after each such transfer.
The TC is reached when count becomes zero.
• For each transfer DREQ must be active until the DACK is activated.
• This mode is also called as ‘cycle stealing’.
Block Transfer Mode:

• 8237 is activated with a DREQ and a block of data is transferred.

• TC is reached after completing transfer of the whole data.
• Transfer cycle may be terminated by an external EOP. The DREQ needs to be activated
only till the DACK signal is activated by the DMA controller.
• Auto initialization can be programmed here.
Demand Transfer Mode:

• In this mode, the transfer takes place until a TC is reached or an external EOP is detected
or the DREQ signal goes inactive.
• A data transfer may exhaust the capacity of data transfer of an I/O device. After the I/O
device is able to catch up, the service may be re-established activating the DREQ signal
again.
• Only the EOP generated by TC or external EOP can cause the auto-initialization when
programmed for.
Cascaded Mode:

• In this mode, one master 8237 will be there and any number of 8237 can be connected
together to provide more than 4 DMA channels.
• The HRQ and HLDA pins of slave 8237 is connected to DREQ and DACK pins of each
channel of host 8237.
• The priorities of DMA requests may be preserved at each level. The first host device is
used only for prioritizing the additional devices, and it does not generate any address
or control signal of its own.
 Clock Generator (8284A)
8284A is an important component to the 8086/88 microprocessor. Without this, it requires
many additional circuits to generate the clock in this system. 8284 provides following basic
functions or signals to 8086/88 based system.
1. Clock generation.
2. RESET synchronization
3. READY synchronization
4. A TTL level peripheral clock signal which is important to interfacing
microprocessors.

Pin diagram of 8284A

• -AEN1, -AEN2(address enable): provided to qualify bus ready signal RDY1, RDY2
• RDY1, RDY2(bus ready): provided in conjunction with -AEN1, -AEN2 pins, to cause
wait states
• -ASYNC (ready synchronization) selection input: select either one or two stages of
synchronization for RDY1, RDY2
• READY: output pin that connects to 8086/88 READY input
• X1, X2(crystal oscillator): connect to external crystal used as timing source for clock
generator. Crystal selected must be able to produce 3 times of desired frequency.
Maximum frequency that can be produced using 8284A is 24 MHz.
• F/-C(frequency/crystal) input: choose clocking source
• F/-C=1: provided external clock to EFI input pin,
• F/-C=0: internal crystal oscillator
• EFI (external frequency input): supplies the timing whenever F/-C pin is pulled high
• CLK (clock output): provided
• CLK input to 8086/8088 and other components
• 1/3 of crystal or EFI input frequency
• 33% duty cycle which is required by 8086/8088
• PCLK (peripheral clock): provided peripheral 1/6 of crystal or EFI input frequency,
50% duty cycle
• OSC (oscillator output): TTL-level signal same frequency as crystal or EFI input
• -RES (reset input): often connected to RC network that provide power-on resetting
• RESET output: connected to 8086/8088 RESET input
• CSYNC (clock synchronization):
• used whenever EFI provides synchronization in system with multiple
processors
• must be grounded, if internal crystal oscillator is used
• GND (ground): connected to ground
• VCC (power supply): +5.0V ±10%
 Bus Controller (8288)
Provides signal eliminated from maximum mode operation.

Pin out of 8288

• -S2, -S1, -S0 (status) input: connected to status output on microprocessor
devoted to generate the timing signals for the system
• CLK input: connected CLK output of 8284A provides internal timing
• ALE (address latch enable) output: used to demultiplex the address/data bus
• DEN (data bus enables) output: control bi-directional data bus buffers
• DT/-R (data transmit/receive) output:
1- Data is being transmitted.
0- Data is being received.
• -AEN (address enable) input: cause to enable memory control signals
• CEN (control enable) input: enable the command output
• IOB (I/O bus mode) input: select either system bus or I/O bus mode operation
• -AIOWC (advanced I/O write command) output: provide I/O with its I/O write
control signal. Starts earlier than usual write signal. Used while dealing with
slower memories.
• -IOWC (I/O write): provide I/O with its main write signal
• -IORC (I/O read): provide I/O with its read signal.
• -AMWC (Advanced Memory write): Provide I/O with its write signal. Starts
earlier than usual write signal. Used while dealing with slower memories.
• -MWTC (Memory write): provide memory with write signal.
• -MRDC (Memory Read): provide memory with read signal.
• -INTA (interrupt acknowledge) output: generates interrupt acknowledge signal.
• MCE/-PDEN (master cascade/peripheral data) output: select cascade operation
for interrupt controller if IOB is 0, and enable the I/O bus transceivers if I/O is
1
 Bus Orbiter (8289)
Intel 8289 along with bus controller, provides full bus arbitration and control of multi-processor
systems. It is typically used in medium to large 80c86 or 80c88 systems where access to the
bus by several processors must be coordinated. It also provides high output current and
capacitive drive to eliminate the need of additional bus buffering.

Pin out of 8289

Functional diagram of 8289

• VCC: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is
recommended for decoupling.
• GND GROUND.
• -S0, - S1, - S2: STATUS INPUT PINS- The status input pins from an 80C86, 80C88
or 8089 processor. The 82C89 decodes these pins to initiate bus request and surrender
actions.
• CLK: CLOCK- From the 82C84A or 82C85 clock chip and serves to establish when
bus arbiter actions are initiated.
• -LOCK: A processor generated signal which when activated (low) prevents the arbiter
from surrendering the multi-master system bus to any other bus arbiter, regardless of
its priority.
• -CRQLCK: COMMON REQUEST LOCK- An active low signal which prevents the
arbiter from surrendering the multi-master system bus to any other bus arbiter
requesting the bus through the CBRQ input pin.
• RESB: RESIDENT BUS- A strapping option to configure the arbiter to operate in
systems having both a multi-master system bus and a Resident Bus. Strapped high, the
multi-master system bus is requested or surrendered as a function of the SYSB/RESB
input pin. Strapped low, the SYSB/RESB input is ignored.
• ANYRQST: ANY REQUEST- A strapping option which permits the multi-master
system bus to be surrendered to a lower priority arbiter as if it were an arbiter of higher
priority (i.e., when a lower priority arbiter requests the use of the multi-master system
bus, the bus is surrendered as soon as it is possible). When ANYRQST is strapped low,
the bus is surrendered according to Table A in Design Information. If ANYRQST is
strapped high and CBRQ is activated, the bus is surrendered at the end of the present
bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to
surrender the multi-master system bus after each transfer cycle. Note that when
surrender occurs BREQ is driven false (high).
• -IOB:IO BUS- A strapping option which configures the 82C89 Arbiter to operate in
systems having both an IO Bus (Peripheral Bus) and a multi-master system bus. The
arbiter requests and surrenders the use of the multi-master system bus as a function of
the status line, S2. The multi-master system bus is permitted to be surrendered while
the processor is performing IO commands and is requested whenever the processor
performs a memory command. Interrupt cycles are assumed as coming from the
peripheral bus and are treated as an IO command.
• -AEN: ADDRESS ENABLE- The output of the 82C89 Arbiter to the processor’s
address latches, to the 82C88 Bus Controller and 82C84A or 82C85 Clock Generator.
AEN serves to instruct the Bus Controller and address latches when to three-state their
output drivers.
• -INIT: INITIALIZE- An active low multi-master system bus input signal used to reset
all the bus arbiters on the multi-master system bus. After initialization, no arbiters have
the use of the multi-master system bus.
• SYSB/-RESB: SYSTEM BUS/RESIDENT BUS- An input signal when the arbiter is
configured in the System/Resident Mode (RESB is strapped high) which determines
 when the multi-master system bus is requested and multi-master system bus
surrendering is permitted. The signal is intended to originate from a form of address-
mapping circuitry, such as a decoder or PROM attached to the resident address bus. If
a glitch occurs, the arbiter may capture or miss it, and the multi-master system bus may
be requested or surrendered, depending upon the state of the glitch. The arbiter requests
the multi-master system bus in the System/Resident Mode when the state of the
SYSB/RESB pin is high and permits the bus to be surrendered when this pin is low.
• -CBRQ: COMMON BUS REQUEST- An input signal which instructs the arbiter if
there are any other arbiters of lower priority requesting the use of the multi-master
system bus.
• -BCLK: BUS CLOCK- The multi-master system bus clock to which all multi-master
system bus interface signals are synchronized.
• -BREQ: BUS REQUEST- An active low output signal in the Parallel Priority Resolving
Scheme which the arbiter activates to request the use of the multi-master system bus.
• -BPRO: BUS PRIORITY OUT- An active low output signal used in the serial priority
resolving scheme where BPRO is daisy-chained to BPRN of the next lower priority
arbiter.
• -BUSY: BUSY- An active low open-drain multi-master system bus interface signal
used to instruct all the arbiters on the bus when the multi-master system bus is available.
When the multi-master system bus is available the highest requesting arbiter
(determined by BPRN) seizes the bus and pulls BUSY low to keep other arbiters off of
the bus. When the arbiter is done with the bus, it releases the BUSY signal, permitting
it to go high and thereby allowing another arbiter to acquire the multi-master system
bus.