Direct Memory Access(DMA)

and
The DMA Controller(DMAC)
8237

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DMA
• DMA is an I/O technique commonly used for high
speed data transfer(memory to peripheral device).
• Status check I/O and interrupt I/O, data transfer is
relatively slow because each instruction needs to
be fetched and executed.
• In DMA , The MPU releases the control of the
buses to a device called DMA controller.
• The controller manages the data transfer between
memory to peripheral device under its control.
• For this operation, uses two signals like HOLD and
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HLDA.
HOLD and HLDA
• Hold: Active high signal. When MPU receives this signal,
then MPU releases its address and data bus control.
• HLDA(hold Acknowledge): Active high output signal that
The MPU releases the bus control.

DMA controller(DMAC) uses these signals as if it were a

peripheral requesting the MPU for the control of the buses.
MPU communicates with the controller by using the Chip
select line, buses and control signals.
In this case The DMA controller plays the role of processor
for data transfer.
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DMAC(DMA controller)
• To perform this function the DMA controller
should have:
• 1. a data bus
• 2. an Address bus
• 3. Read/ Write control signals
• 4. Control signals to disable its role as a
peripheral and to enable its role as a processor

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8237 DMA Controller
• Features:
1. 8237 is a programmable DMA controller housed in a 40
pin package.
2. It has four independent channels with each channel
capable of transferring 64K bytes.
3. It must interface with two types of devices: MPU and
Peripherals
4. It is an I/O to the microprocessor(Slave mode) and it is a
data transfer processor to peripherals(Master mode).
5. It needs additional signal lines to communicate with the
addresses of 64K data types. And these signal must be
generated externally by using latches and buffers. 5
8237 block diagram

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8237 pin diagram

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8237 DMAC REGISTER DESCRIPTION

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Current Address Register
• Each channel has a 16-bit Current Address
register.
• This register holds the value of the address used
during DMA transfers.
• The address is automatically incremented or
decremented after each transfer and the
intermediate values of the address are stored in
the Current Address register during the transfer.
• This register is written or read by the
microprocessor in successive 8-bit bytes. 9
 Base Address and Base Word Count
Registers
• Each channel has a pair of Base Address and
Base Word Count registers.
• These 16-bit registers store the original value
of their associated current registers.
• The base registers are written simultaneously
with their corresponding current register in
8-bit bytes in the Program Condition by the
microprocessor.
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Command Register
• This 8-bit register
controls the
operation of the
8237A.
• It is programmed
by the
microprocessor in
the Program
Condition and is
cleared by Reset or
a Master Clear
instruction. 11
Mode Register
• Each channel has a
6-bit Mode register
associated with it.
• When the register is
being written to by
the microprocessor
in the Program
Condition, bits 0 and
1 determine which
channel Mode
register is to be
written.
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 Request Register

• The 8237A can respond to requests for DMA service which are
initiated by software as well as by a DREQ. Each channel has a
request bit associated with it in the 4-bit Request register.

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 Mask Register

• Each channel has associated with it a mask bit which can be set to
disable the incoming DREQ.
• Each mask bit is set when its associated channel produces an EOP if
the channel is not programmed for Auto initialize.
• Each bit of the 4-bit Mask register may also be set or cleared
separately under software control. The entire register is also set by a 14
Reset.
Status Register

• The Status register is available to be read out of the 8237A by

the microprocessor.
• It contains information about the status of the devices at this
point.
• This information includes which channels have reached a
terminal count and which channels have pending DMA requests.
• Bits 0-3 are set every time a TC is reached by that channel or an
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external EOP is applied.
Temporary Register
• The Temporary register is used to hold data
during memory-to-memory transfers.
• The Temporary register always contains the last
byte transferred in the previous memory-to-
memory operation, unless cleared by a Reset.

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8237 DMA controller with Internal Registers

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 Programming With 8237
• Write initialization instructions for the DMA controller (Refer to
the previous interfacing circuit)to meet the following
specifications:
1. Disable DMA controller and begin writing initialization
instructions.
2. Initialize channel#3(CH3) to transfer 1K of bytes from the
system memory to the floppy disk assigned to Ch3.
3. The starting address of the data block is 4075 and subsequent
data bytes have memory addresses in increasing order.
4. Count 03FFH
5. The command parameters should be normal timing, fixed
priority, late write. DREQ and DACK are both active low.
6. Set up demand mode whereby the DMA can complete the 18
data transfer without any interruption.
 Port addresses
• Port addresses of internal registers:
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 =00H( CH0 MAR)
0 0 0 0 0 0 0 1 =01H(CH0 count reg)
…………………………
…………………………………………………..
………………………………………………………………
0 0 0 0 1 1 1 1 =0F Mask Reg.

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Port Addresses of Internal register

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• Command register:

MVI A, 00000100B
OUT 08H ; send to command register.
• Mode register:

• MVI A,00000111B
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• OUT 0BH ; send to mode register
22
• MVI A, 01000000B
• OUT 08H ; send to command register.
Incorrect

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Full Program

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