Topic 1 :16 Bit Microprocessor: 8086 (16 Marks)

1.18086 Microprocessor,
● Salient features
● Pin descriptions
● Architecture of 8086 - Functional Block diagram
● Register organization,
● Concepts of pipelining,
● Memory segmentation
● Physical memory addresses generation.

State four important features of 8086.

Ans: (Any 8 point : 1/2 Mark each)

1. 20 bit address lines so 220 = 1Mbyte of memory can be addressed and data bus is 16 bit,.
2. Operating clock frequencies 5MHz, 8MHz, 10MHz.
3. Arithmetic operation can be performed on 8-bit or 16-bit signed & unsigned data including
multiplication and division.
4. Arithmetic operation can be performed on 8 bit or 16 bit signed and unsigned data including
multiplication and division.
5. The instruction set is powerful, flexible and can be programmed in high level language like C
language.
6. Can operate in single processor and multiprocessor configuration i.e. operating modes.
7. Provides 6-bytes instruction queue for pipelining of instructions executions.
8. Provides 256 types of vectored software interrupts.
9. Operate in maximum and minimum mode to achieve high performance level.
10. Provides separate instructions for string manipulation.
11. Generate 8 bit of 16 bit I/O address so it can access maximum 64K I/O devices.
12. Operate in maximum and minimum mode to achieve high performance.
13. 8086 uses memory banks:-The 8086 uses a memory banking system. It means entire data is not
stored sequentially in a single memory of 1 MB but memory is divided into two banks of 512KB.
14. Interrupts:-8086 has 256 vectored interrupts
 Pin Diagram of 8086 microprocessor.

AD0-AD15
• These lines are time multiplexed bidirectional address/data bus.
• During T1 clock cycle of the bus cycle , they carry lower order 16-bit address.
• During T2,T3, and T4 , they carry 16-bit data.
• AD0-AD7 lines carry lower order byte of data
• AD8-AD15 lines carry high order byte of data.

A19/S6,A18/S5,A17/S4,A16/S3

• Time multiplexed address and status lines.

• During T1 clock cycle, these lines carry upper four-bit address and during I/O operation , these
lines are low.
• During T2, T3,T4 identify memory segments.
• S5 interrupt enable status signal, updated at beginning of every clock cycle.

/ S7(Bus High enable /Status)

• Used to indicate the transfer of data over higher order(D15-D8) data bus.
• with A0 determines whether byte or word will be transferred from / to memory.
 • / S7 is time multiplexed line, during T2 to T4 status signal S7 transmitted on line otherwise
always high.

• It is an active low signal issued by the processor to indicate that processor is performing read
operation with memory or I/O depending of status of M/ signal.
• Remain tristate during hold acknowledge.

READY

• This is acknowledgement from slower I/O device or memory.

• It is Active high signal.
• When high, it indicates that the peripheral device is ready to transfer data.
• μp samples the ready input pin during T3 state of a machine cycle.
• If device is ready it send a 1 on the Ready pin else send a 0.
• If ready pin is 0 , μp inserts wait-state between T3 & T4 will come out of wait state when Ready
becomes 1 thereby ensuring that the device is ready.

RESET
• This is reset input signal (system reset).
• Provided by 8284 clock generator.
• Clears FLAGS,DS,ES,SS,IP ,set bit of CS register.
• When this signal goes high, processor enter into reset state , terminate current activity and start
execution from FFFF0 H(reset vector address)

INTR(Interrupt Request)

• This is a level triggered interrupt request input

• Checked during last clock cycle of each instruction to determine the availability of request.
• If any interrupt request is occurred, the processor enters the interrupt acknowledge cycle.

NMI
• Edge triggered input request which cause a Type-2 interrupt.
• NMI is Not-maskable by software.

• This signal is used to test the status of math co-processor 8087.

• BUSY of 8087 is Connected to 8086.
• If signal goes low, execution will continue, else processor remains in an idle state.
• Input signal is examined by a WAIT instruction.

CLK(Clock input)
• Clock input provide basic timing for processor operation and bus control activity.
 • It is symmetric square wave with 33% duty cycle.
• Frequency range for different 8086 version 5MHz to 10MHz.
• Vcc = +5V , for operation of internal circuit.
• GND= Ground for internal circuit.
MN/
• This pin indicates operating mode of 8086, minimum or maximum.
• When this pin connected to
1) Vcc, the processor operates in minimum mode,
2) ground , processor operates in maximum mode.

Minimum Mode operation (pin 24-

31) Pin 24: INTA( Interrupt
acknowledge)

• It is active low output signal.

• When processor receive INTR signal, processor complete current machine cycle , and
acknowledge interrupt by generating this signal.

Pin 25:ALE(Address Latch Enable)

• It is active high, pulse issued by processor during T1 state of bus cycle to indicate availability of
valid address on AD0-AD15.
• This pin is Connected to latch enable pin of latch 8282 or 74LS373.

Minimum Mode operation (pin 24-

31) Pin 26: (Data enable)

● It is an active low signal , issued by processor during middle of T2 until middle of T4 , to indicate
availability of valid data over AD0-AD15.
● This signal is used to enable transreceivers(bi-directional buffers) 8286 or 74LS245 to separate
data from multiplexed address/data signal.

DT/ (Pin no :27)

• This output signal used to decide the direction of data flow through transreceivers(bi-directional
buffers) 8286 or 74LS245
• When processor sends data out, this signal is high, when processor receives data , this signal is low.

Pin no : 28 M/

• This signal is issued by processor to distinguish memory access from I/O access.
• When this signal high memory is accessed and when this signal is low , an I/O device is accessed

Pin no:29
• It is an active low signal used to write data to memory or I/O device depending on status of M/ .

Pin no:30 HLDA:

• This is an active high output signal generated by processor after receiving HOLD signal.

Pin no:31 HOLD:

 • When another master device needs the use of the address, data, control bus, it sends a HOLD request
to the processor through this line.
• It is an active high input signal.

Maximum Mode operation (pin 24-31) (MN/ =0)

Pin 24,25: QS1,QS2

These lines provide information about the status of instruction queue during clock cycle

Pin 26,27,28: , ,

• These status signal reflect type of operation being carried out by the processor and required by
bus controller 8288 to generates all memory or I/O access control signals.
• These becomes active from T4 of previous cycle , and remain active during T1 and T2 of the current
cycle

Pin 29:

• When this signal goes low , all interrupts are masked and HOLD request is not granted.

Pin 30,31 / , /

• These pins are used by other local master in maximum mode to force the processor to release the
local bus at the end of processor’s current bus cycle.
• These pins are bidirectional with / having higher priority than /
 • After receiving request on these lines, CPU sends acknowledge signal on same lines.

Draw architecture of 8086 and label it. Write the function of BIU and EU.
( Diagram :4 Marks; Any TWO functions of each unit : 2M)
Ans:

FIG. Architecture of 8086

FUNCTIONS OF EXECUTION UNIT:

1. To tell BIU to fetch the instructions or data from memory

2. To decode the instructions.
3. To generate different internal and external controls signal.
4. To execute the instructions.
5. To perform Arithmetic and Logic Operations

Execution Unit (EU)

• It fetches instructions from the queue in BIU, decodes and executes it.
• EU has 16-bit ALU, which can perform arithmetic and logical operation on 8 bit data as well as 16-bit
data.
• It sends request signals to the BIU to access the external module.
• During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction.
 General Purpose Registers

List all the 16 bit registers of 8086 and write their function.

(List 2 marks, Function 2marks)

Ans. 16 bit registers: AX,BX,CX,DX,CS,SS,DS,ES,BP,SP,SI,DI,IP,FLAG REGISTER

1. AX (Accumulator) – Used to store the result for arithmetic / logical operations

All I/O data transfer using IN & OUT instructions use “A” register(AH / AL or AX).
2. BX – Base – used to hold the offset address or data in indirect addressing mode.

3. CX – acts as a counter for repeating or looping instructions.

4. DX – Used with AX to hold 32 bit values during multiplication and division.

Used to hold address of I/O port in indirect addressing mode.

5. CS – Code Segment – holds base address for all executable instructions in a program

6. SS - holds the Base address of the stack

7. DS – Data Segment – default base address for variables.

8. ES – Extra Segment – additional base address for memory variables in extra segment.
9. BP – Base Pointer BP can hold offset address of any location in the stack
segment. It is used to access random locations of stack.

10. SP – Stack Pointer – Contains the offset of the top of the stack.
SP is used with SS register to calculate 20-bit physical address.
Used during instructions like PUSH,POP,CALL,RET etc.

11. SI – Source Index – Used in string movement instructions. Holds offset address of source data in Data
segment during string operations.
Used to hold offset address of data segment.

12. DI – Destination Index – acts as the destination for string movement instructions
Used to hold offset address of Extra segment.
13. IP – Instruction Pointer – Contains 16 bit offset address of instruction that is to be executed in code
segment..

14. Flags Register – individual bit positions within register show status of CPU or results of arithmetic
operations.
 Flag Register of 8086

Conditional /Status Flags

C-Carry Flag : It is set when carry/borrow is generated out of MSB of result. (i.e D 7 bit for 8-bit operation,
D15 bit for a 16 bit operation).

P-Parity Flag This flag is set to 1 if the lower byte of the result contains even number of 1’s otherwise it is
reset.

AC-Auxiliary Carry Flag This is set if a carry is generated out of the lower nibble, (i.e.from D3 to D4
bit)to the higher nibble ,. It is used only in 8-bit operations like DAA & DAS.

Z-Zero Flag This flag is set if the result is zero after performing ALU operations. Otherwise it is reset.

S-Sign Flag This flag is set if the MSB of the result is equal to 1 after performing ALU operation ,
otherwise it is reset.

For 8-bit data it is set when D7=1

For 16-bit data it is set when D151=1
For signed operations if MSB=1 => -ve
O-Overflow Flag This flag is set if an overflow occurs, i.e. if the result of a signed operation is large enough
to be accommodated in destination register.

Control Flags

T-Trap Flag If this flag is set ,the processor enters the single step execution mode. In other words a

Trap interrupt is generated after execution of each instruction .

I-Interrupt Flag it is used to mask(disable) or unmask(enable)the INTR interrupt. When this flag is
set,8086 recognizes interrupt INTR. When it is reset INTR is masked.

D-D irection Flag It selects either increment or decrement mode for DI &/or SI register during string
instructions.

Functions of BIU:

1. Generates physical address

2. Sends address to memory or I/O
3. Fetch instruction from memory
4. Read data from memory or I/O
5. Write data to memory or I/O
6. Supports instruction queuing
7. Provides address relocation facility

The Instruction Queue(6 byte Pre-Fetch queue or Instruction Stream / Pipelining ))

• It is a 6 byte register.
• Used to store 6 bytes which are fetched from code segment memory.
• The 6 bytes are stored in register in FIFO form.
• The BIU fetches next byte when EU is executing the current instruction. When EU is ready for the
next instruction , it simply reads from queue register instead of from memory.
• Fetching the next instruction , while executing the current instruction is called pipelining.
• Pipelining Increases efficiency, speed of µp.

What is pipelining ? State its need and how it is done in 8086

(Definition -1mark, Description -3marks)

Ans:

Definition: Process of fetching the next instruction while the current instruction is executing is called
pipelining which will reduce the execution time.

Description: The technique used to enable an instruction to complete with each clock cycle. Normally, on
a non – pipelined processor, nine clock cycles are required for fetch, decode and execute cycles for the three
instructions as shown in Fig(a). This takes longer time when compared to pipelined processor . In this ,the
fetch, decode and execute operations are performed in parallel, so only five clock cycles are required to
execute the same three instructions as shown Fig(b). In 8086, pipelining is implemented by providing 6 byte
queue where as long as 6 one byte instruction can be stored well in advance and then one by one instruction
goes for decoding and executions.
So, while executing first instruction in a queue, processor decodes second instruction and fetches 3 ed
 instruction from the memory

In this way ,8086 perform fetch , decode and execute operation in parallel i.e. in single clock cycle as
shown in above fig(b)

Needs of Pipelining:

● Pipelining enables many instructions to be execute at the same time.

● It allows execution to be done in fewer cycles.
● Speed up the execution speed of the processor
● More efficient use of processor

Describe memory segmentation in 8086 microprocessor and list it’s four advantages.
Memory Segmentation: The memory in an 8086 microprocessor is organized as a segmented memory. The
physical memory is divided into 4 segments namely,- Data segment, Code Segment, Stack Segment and
Extra Segment.
Description:
● Data segment is used to hold data, Code segment for the executable program, Extra segment also
holds data specifically in strings and stack segment is used to store stack data.
● Each segment is 64Kbytes & addressed by one segment register. i.e CS,DS,ES or SS
● The 16 bit segment register holds the starting address of the segment
● The offset address to this segment address is specified as a 16-bit displacement (offset) between
0000 to FFFFH. Hence maximum size of any segment is 216=64K locations.
● Since the memory size of 8086 is 1Mbytes, total 16 segments are possible with each having
64Kbytes.
 ● The offset address values are from 0000H to FFFFH so the physical address range from 00000H to
FFFFFH.
● 16 bit displacement is added to 16 bit segment base register by shifting the content of it towards
left by one digit to get 20 bit physical address.

Advantages of segmentation

1) With the use of segmentation the instruction and data is never overlapped.
2) The major advantage of segmentation is Dynamic relocatability of program which means that a
program can easily be transferred from one code memory segment to another code memory
segment without changing the effective address.
3) Segmentation can be used in multi-user time shared system.
4) Segmentation allows two processes to share data.
5) Segmentation allows you to extend the addressability of a processor i.e., address up to 1MB
although the actual addresses to be handled are of 16 bit size.
6) Programs and data can be stored separately from each other in segmentation.

Define logical address and physical address. Explain 20-bit physical address generation with example.

Physical Address:- The 8086 has 20 address lines so each memory location have 20 bit address which is actually
put on address bus known as physical address. The address can have range of 00000H to FFFFFH for 8086.
Physical address is calculated with the help of logical address and base address which is always present in
segment register.
Logical Address:- the logical address is normally stored in the 16-bit base register(SP, BP) or pointer
register(BP, SP) or index register(SI, DI) which is an offset from location 0 of a respective
segment(CS,DS,SS,ES).

Generation of a physical address in 8086 :- Segment registers carry 16 bit data, which is also known as base
address. BIU attaches four 0 bits to LSB of the base address. So now this address becomes 20-bit address. Any
base/pointer or index register carry 16 bit offset. Offset address is added into 20-bit base address which finally
forms 20 bit physical address of memory location.

Example:- Assume CS = 1000h, IP =1234h

CS= 10000h……. 0 added by BIU
+ IP= 1234h

11234h
Assume DS= 1000h, SI=1234h…..(with DS offset address may be stored in BX/BP/SI/DI)
DS=20000h… 0 added by BIU
+ SI= 4567h

24567h
(OR) Given : CS = 2000H, IP = 1122H
CS : 20000H 0 added by BIU(or Hardwired 0)
+ IP : 1122H

21122H
If CS:348A ,IP:4214 , find 20 bit physical address.

Example:- Given : CS = 2000H, IP = 1122H

CS : 20000H 0 added by BIU(or Hardwired 0)
+ IP : 1122H

21122H

Why 8086 memory is divided into two banks? 4M

1. As 8086 has 16-bit data bus it should be able to access 16 bit data in 1 bus cycle
to do so it needs to read from 2 memory locations
2. As one memory location carries only one byte
3. If 2 memory location on same chip can’t be accessed at the same time. Because
Address bus can not contain 2 addresses simultaneously.
4. The 8086 memory address space can be viewed as a sequence of one million
bytes in which any byte may contain an 8-bit data element and any two consecutive bytes may contain
a 16-bit data element.
5. There is no constraint on byte or word address boundaries. The address space is
physically connected to a 16-bit data bus by dividing the address space into two 8-bit banks of up to
512K bytes each.
6. One bank is connected to the lower half of the 16-bit data bus (D0 – D7) and
contains even address bytes. i.e., when A0 bit is low, the bank is selected.
7. The other bank is connected to the upper half of the data bus (D8 -D15) and
contains odd address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the odd bank is
selected. A specific byte within each bank is selected by address lines A1-A19.
8. Data can be accessed from the memory in four different ways. They are:
● 8 bit data from Lower (Even) address Bank.
● 8 bit data from Higher (Odd) address Bank.
● 16 bit data starting from Even Address.
● 16 bit data starting from Odd Address.
 (8086 memory divided into 2 bank)