History of Microprocessors

Name Date Transistors Microns Clock speed

4004 1971 2,300 10 0.1MHz

8080 1974 6,000 6 2 MHz

8086 1978 29,000 3 5MHz

8088 1979 29,000 3 5 MHz

80286 1982 134,000 1.5 6 MHz

80386 1985 275,000 1.5 16 MHz

80486 1989 1,200,000 1 25 MHz

Pentium 1993 3,100,000 0.8 60 MHz

Pentium II 1997 7,500,000 0.35 233 MHz

Pentium III 1999 9,500,000 0.25 450 MHz

Pentium 4 2000 42,000,000 0.18 1.5 GHz

Pentium 4 "Prescott" 2004 125,000,000 0.09 3.6 GHz

Pentium D processor 2005 291,000,000 0.065 3.2GHz

Dual Core 2006 1,720,000,000 0.09 1.66Ghz

Quad Core Xeon 2007 820,000,000 0.045 3 GHz

Microprocessors Family
8086 Family:
8086: First 16-bit processor
80186: 16-bit 8086 with peripheral devices
80286: Advanced version of 8086 used for multitasking.
80386: 32-bit processor architecture
80486: 32-bit processor architecture with floating point
processor(80387) integrated into the chip.
8088 Family:
8088: Same as 8086 but 8-bit databus.
80188: 8088 with peripheral devices.
 Features of 8086
• It is a 16-bit Microprocessor(μp).

• It’s ALU, internal registers works with 16 bit binary word.

• 8086 has a 20 bit address bus & can access up to 220= 1 MB

memory locations.

• 8086 has a 16 bit data bus. It can read or write data to a

memory/port either 16 bits or 8 bits at a time.

• It can support up to 64K I/O ports.

• It provides 14, 16 -bit registers.

• Frequency range of 8086 is 6-10 MHz.

 Features of 8086

• It has multiplexed address and data bus AD0- AD15 and

A16 – A19.

• It requires single phase clock with 33% duty cycle to provide

internal timing.

• Clock is generated by separate peripheral chip 8284( clock

Generator )

• It can prefetch upto 6 instruction bytes from memory and

queues them in order to speed up instruction execution.

• It requires +5V power supply.

• A 40 pin dual in line package (DIP).

 Features of 8086
• 8086 comes with different versions.

• 8086 runs at 5 MHz

• 8086-2 runs at 8 MHz
• 8086-1 runs at 10 MHz

• 8086 is designed to operate in two modes –

• Minimum mode (Single Processor ) configuration.

• Maximum mode. (Multiprocessor ) configuration.

 The minimum mode is selected by applying logic 1 to the

MN / MX input pin.

 The maximum mode is selected by applying logic 0 to

the MN / MX input pin.
 Features of 8086
• Based on Pipelined Architecture i.e. 6 bytes of instructions are
prefetched and stored in an instruction queue to speed up the
execution.

• Uses a memory banking system i.e entire data is not stored

sequentialy in a single memory of 1 MB , the memory is divided
into two banks of 512 KB Each.

• Uses the memory segmentation to access the 1 MB (20 address

lines , 220) of memory through the 16-bit address.

• Here the entire memory can be divided into 16 logical segments

of 64 KB each. (Code , Stack , Data and extra segments )

• Provides powerful instruction set , that supports MULTIPLY and

DIVIDE operations also.
8086 Pin Diagram
 Pin Description
 The 8086 signals can be categorized in three groups.

 The first are the signals having common functions in

minimum as well as maximum mode.

 The second are the signals which have special

functions in minimum mode.

 Third are the signals having special functions for

maximum mode
 Pin Description
signals having common functions in minimum as well as maximum mode.

AD15-AD0:
 These are the time multiplexed memory I/O address and
data lines.

 Address remains on the lines during T1 state, while the data

is available on the data bus during T2, T3, TW and T4.

 Here T1, T2, T3, T4 and TW are the clock states of a machine
cycle. TW is a wait state.

 These lines are active high and float to a tristate during

interrupt acknowledge and local bus hold acknowledge
cycles.
 Pin Description
signals having common functions in minimum as well as maximum mode.
A19/S6, A18/S5, A17/S4, A16/S3:
 These are the time multiplexed address and status lines.

 During T1, these are the most significant address lines or memory operations.

 During I/O operations, these lines are low.

 During memory or I/O operations, status information is available on those

lines for T2, T3, TW and T4 .

 The status of the interrupt enable flag bit(displayed on S5) is updated at the
beginning of each clock cycle.

 The S4 and S3 combinedly indicate which segment register is presently being

used for memory accesses as shown in Table.

 These lines float to tri-state off (tristated) during the local bus hold aknowledge
 Pin Description
signals having common functions in minimum as well as maximum mode.

 The status line S6 is always low( Not Used ).

 The address bits are separated from the status bits using latches
controlled by the ALE signal.

 S5 indicates the value of interrupt enable Flag bit.

 Pin Description
signals having common functions in minimum as well as maximum mode.
BHE/S7-Bus High Enable/Status:

 The bus high enable signal is used to indicate the transfer of data over the
higher order (D15-D8) data bus as shown in Table .

 It goes low for the data transfers over D15-D8 and is used to derive chip selects
of odd address memory bank or peripherals.

 BHE is low during T1 for read, write and interrupt acknowledge cycles, when-
ever a byte is to be transferred on the higher byte of the data bus.

 The status information is available during T2, T3 and T4.

 The signal is active low and is tristated during 'hold'.

 It is low during T1 for the first pulse of the interrupt acknowledge cycle.
 Pin Description
signals having common functions in minimum as well as maximum mode.

 BHE/S7-Bus High Enable/Status:

 Pin Description
signals having common functions in minimum as well as maximum mode.
RD-Read: Read signal
 when low, indicates the peripherals that the processor is performing a memory
or I/O read operation.

 RD is active low and shows the state for T2,T3, TW of any read cycle.

 The signal remains tristated during the 'hold acknowledge'.

READY:

 This is the acknowledgement from the slow devices or memory that they have
completed the data transfer. The signal is active high.

 The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the 8086.
 Pin Description
signals having common functions in minimum as well as maximum mode.
INTR-lnterrupt Request:

 This is a level triggered interrupt input.

 This is checked during the last clock cycle of each instruction to

determine the availability of the interrupt request.

 If any interrupt request is pending, the processor enters the

interrupt acknowledge cycle.

 This can be internally masked by resetting the interrupt enable

flag. This signal is active high and internally synchronized.
 Pin Description
signals having common functions in minimum as well as maximum mode.

TEST:

 This input is examined by a 'WAIT' instruction.

 If the TEST input goes low, execution will continue, else, the
processor remains in an idle state.

 The input is synchronized internally during each clock cycle on

leading edge of clock.
 Pin Description
signals having common functions in minimum as well as maximum mode.

NMI-Non-maskable Interrupt:

 This is an edge-triggered input which causes a Type2 interrrupt.


 The NMI is not maskable internally by software.

 A transition from low to high initiates the interrupt response at

the end of the current instruction.

 This input is internally synchronized.

 Pin Description
signals having common functions in minimum as well as maximum mode.

RESET:

 This input causes the processor to terminate the current activity

and start execution from FFFF0H.

 The signal is active high and must be active for at least four clock
cycles.

 It restarts execution when the RESET returns low.

 RESET is also internally synchronized.

 Pin Description
signals having common functions in minimum as well as maximum mode.
CLK-Clock Input:
 The clock input provides the basic timing for processor operation
and bus control activity.
 Its an asymmetric square wave with 33% duty cycle.

 The range of frequency for different 8086 versions is from 5MHz

to 10MHz.

VCC :
 +5V power supply for the operation of the internal circuit.

GND:
 Ground for the internal circuit.
 Pin Description
signals having common functions in minimum as well as maximum mode.

MN/MX :

 The logic level at this pin decides whether the processor is to

operate in either minimum (single processor) or maximum
(multiprocessor) mode.
 Pin Description
The following pin functions are for the
minimum mode operation of 8086.
M/IO -Memory/IO:
 It is an Output Pin.

 When it is low, it indicates the CPU is having an I/O operation.

 When it is high, it indicates that the CPU is having a memory

operation.

 This line becomes active in the previous T4 and remains active till
final T4 of the current cycle.

 It is tristated during local bus "hold acknowledge“

 Pin Description
The following pin functions are for the minimum mode
operation of 8086.
INTA -Interrupt Acknowledge:

 This signal is related to the non-vectored interrupt INTR.

 When it goes low, it means that the processor has accepted the
interrupt Request.

 It is active low during T2, T3 and TW of each interrupt

acknowledge cycle.

 In response to this INTA the microprocessor receives an 8-bit

interrupt type number from an I/O port or a programmable
interrupt controller.
 Pin Description
The following pin functions are for the minimum mode
operation of 8086.

ALE-Address latch Enable:

 This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch
enable input of latches. This signal is active high.

DT /R -Data Transmit/Receive:
 This output is used to decide the direction of data flow
through the transreceivers (bidirectional buffers). When the
processor sends out data, this signal is high and when the
processor is receiving data, this signal is low.
 Pin Description
The following pin functions are for the minimum mode operation of 8086.

 DEN-Data Enable:

 This signal indicates the availability of valid data over the

address/data lines.

 It is used to enable the trans receivers (bi-directional buffers)

to separate the data from the multiplexed address/data
signal.

 It is active from the middle of T2 until the middle of T4

 DEN is tristated during 'hold acknowledge' cycle.

 Pin Description
The following pin functions are for the minimum mode operation of 8086.
HOLD, HLDA-Hold/Hold Acknowledge:
 The DMA Controller issues the HOLD input from another
master requesting local bus.

 When the HOLD line goes high, it indicates to the processor

that another master is requesting the bus access.

 The processor, after receiving the HOLD request, issues the

hold acknowledge signal on HLDA pin, after completing the
current bus (instruction) cycle.

 At the same time it releases the system bus for use by master.
 Pin Description
The following pin functions are for the minimum mode operation of 8086.

 If the DMA request is made while the CPU is performing a memory or

I/O cycle, it will release the local bus during T 4 provided:

1. The request occurs on or before T 2 state of the current cycle.

2. The current cycle is not operating over the lower byte of a word (or operating
on an odd address).

3. The current cycle is not the first acknowledge of an interrupt acknowledge

sequence.

4. A Lock instruction is not being executed.

 Pin Description
The following pin functions are applicable for
maximum mode operation of 8086.
S2, S1, S0 -Status Lines:
 These are the status lines which reflect the type of
operation, being carried out by the processor.

 These become active during T4 of the previous cycle and

remain active during T1 and T2 of the current bus cycle.

 The status lines return to passive state during T3 of the

current bus cycle so that they may again become active for
the next bus cycle during T4.
 These status lines are encoded in table.
 Pin Description
The following pin functions are applicable for maximum mode operation
of 8086.
 Pin Description
The following pin functions are applicable for maximum mode operation of 8086.
LOCK:
 This output pin indicates that other system bus masters can not
take control of system bus, while the LOCK signal is low.

 The LOCK signal is activated by the 'LOCK' prefix instruction and

remains active until the completion of the next instruction.

 When the CPU is executing a critical instruction which requires

the system bus, the LOCK prefix instruction ensures that other
processors connected in the system will not gain the control of the
bus.
 Pin Description
The following pin functions are applicable for maximum mode operation of 8086.
QS1, QS0-Queue Status:

 These lines give information about the status of the code

prefetch queue.
 These are active during the CLK cycle after which the queue
operation is performed.
 Pin Description
The following pin functions are applicable for maximum mode operation of 8086.

RQ0/GT0, RQ1/GT1- ReQuest/Grant:

 These pins are used in maximum mode, to force the

processor to release the local bus for the external bus master
(8089 or 8087 ) .

 Each of the pins is bidirectional .

 RQ0/GT0 have higher priority than RQ 1/ GT1.

 Pin Description
The following pin functions are applicable for maximum mode operation of 8086.
 The request! grant sequence is as follows:
1. The external bus master (8089 or 8087 ) sends an active low pulse to request for
control over the system bus.

2. During T4 (current) or T1 (next) clock cycle, 8086 sends a active low grant
pulse to the requesting master.

 This indicates that the 8086 has allowed the local bus to float and that it will be
used by another master.

 The CPU's bus interface unit is likely to be disconnected from the local bus of
the system.

3. A one clock wide pulse from the another master indicates to 8086 that the 'hold‘
request is about to end and the 8086 may regain control of the local bus at the
next clock cycle.
8086 Internal Architecture
8086 Architecture Description

 The 8086 CPU is divided into two independent

functional parts :

1) Bus Interface Unit (BIU)

2) Execution Unit (EU)

 Bus Interface Unit (BIU)
 The Bus Interface Unit contains
 Bus Interface Logic
 Segment registers
 Memory addressing logic
 Six byte instruction object code queue.

 Functions of BIU
 fetches instructions and place them in Instruction Queue.
 Reads and Writes data from / to memory / I/O.
 Computes the 20-bit address.

BIU handles all the data transfers and addresses on

the buses for EU.
 Bus Interface Unit (BIU)
The Queue:
 The BIU fetches up to 6 instruction bytes for the following instructions.

 The BIU stores these prefetched bytes in first-in-first-out register set called a
queue.

 When the EU is ready for its next instruction it simply reads the instruction
byte(s) for the instruction from the queue in the BIU.

 This is much faster than sending out an address to the system memory
and waiting for memory to send back the next instruction byte or bytes.

 Except in the case of JMP and CALL instructions, where the queue must be
dumped and then reloaded starting from a new address, this prefetch-and-
queue scheme greatly speeds up processing.

 Fetching the next instruction while the current instruction executes is called
pipelining.
Instruction Queue
 What is Pipelining ?

Advantages of Pipelining
Why is the 8086 Queue only 6 Bytes
long ?
 Execution Unit (EU)
The execution unit contains :
 General purpose registers
 Segment Registers
 Pointer and Index registers
 Arithmetic and Logic Unit
 Control Unit
 Flags Register

FUNCTIONS OF EXECUTION UNIT :

 EU tells the BIU where to fetch instructions and data.
 The EU decodes and executes the instructions using the 16-bit ALU.
 ALU can perform arithmetic and Logical operations.
 The Instruction Decoder translates instructions into series of actions which
EU carries out.
 Control Circuitry directs internal operation.
 The EU is decoding an instruction or executing an instruction which does not
require use of the buses.
 Register organization of 8086
 8086 has a powerful set of registers containing

 General Purpose Registers

 Can be used either 8-bit registers or 16-bit registers.
 The general purpose registers are either used for holding the data,
variables and intermediate results temporarily
 For other purpose like counter or for storing offset address for some
particular addressing modes etc.

 Special purpose Registers.

 The special purpose registers are used as segment registers,
pointers, index registers.
 As offset storage registers for particular addressing modes.

All the registers of 8086 are 16-bit registers.

 Register organization of 8086
ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS FLAGS Register
 Register organization of 8086
 Can be divided into four categories :

In total there are fourteen 16-bit registers in an 8086

 General data registers
AX Register:
 Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16- bit register AX.

 AL in this case contains the low-order byte of the word, and AH contains the
high-order byte.

 Accumulator can be used for I/O operations, rotate and string manipulation.

BX Register:
 This register is mainly used as a base register. It holds the starting base
location of a memory region within a data segment.

 It is used as offset storage for forming physical address in case of certain

addressing mode.
 General data registers
CX Register:
 It is used as default counter or count register in case of string and loop
instructions.

DX Register:
 Data register can be used as a port number in I/O operations and implicit
operand or destination in case of few instructions.

 In integer 32-bit multiply and divide instruction the DX register contains high-
order word of the initial or resulting number.
 Segment Registers
 There are 4 segment registers :
 Code Segment (CS ) Register
 Data Segment (DS ) Register
 Stack Segment (SS ) Register
 Extra Segment (ES ) Register

 These registers are used to hold the upper 16-bits of

starting address of four memory segments.

 BIU inserts zeros for the lower 4-bits in the contents of

segment registers to form 20-bit starting address for
memory segment.
 Pointer and Index Registers
 This group of registers include :

 Stack Pointer ( SP )Register

 Base Pointer (BP) Register
 Source Index (SI )Register
 Destination Index (DI) Register
 Instruction Pointer (IP)

 SP , BP , SI and DI stores the 16-bit Offset Address within

a memory segment. Each of these registers is associated
with one or more segment registers to generate the 20-bit
Physical Address of a memory location.
 Memory Architecture in 8086

 Total Memory size = 1 MB ( Mega Bytes )

 Uses two Memory Banks of 512 KB each.

 Whole 1MB memory is divided into 16 logical

segments of 64 KB each.
 Memory Bank System in 8086
 Since 8086 has 20 address lines , it can identify upto 220 =
I048576 (1 M ) addresses.

 Since one memory location can store 1 Byte , the memory capacity of
8086 is 1MByte.

 However , the data bus is 16 bit wide.

 So, how to store a data word (16-bits ) in Byte form ?

 This is done by storing 2 bytes of a word in consecutive memory addresses.

 Ex. if lower byte is stored at 03410 H , the higher Byte will be stored at 03411 H.
Storing a word in two consecutive memory locations

BUT , With this scheme , two machines cycles will be required to read
or write a data word (16-bits) in memory.
 Memory Bank System in 8086

 In order to read/write a word ( 2 Bytes ) in one machine cycle ,

the entire memory (1 MB) is divided into two memory banks
(512 KB each).

 EVEN addressed memory bank. (LOWER BANK )

 ODD addressed memory bank. (UPPER BANK )

 Address line Ao is used to enable lower bank and BHE pin is

used to enable upper bank.
Memory Bank System in 8086
 Memory Bank System in 8086

There are 4 possible ways to access data from memory in 8086 processor :

• 8- bit data ( 1 Byte ) from Even ( Lower ) Address Bank.

• 8- bit data ( 1 Byte ) from Odd ( Upper ) Address Bank.

• 16 – bit data ( 1 Word ) starting from Even Addresses.

• 16 – bit data ( 1 Word ) starting from Odd Addresses.

Accessing a Even Addressed Byte
Accessing a Odd Addressed Byte
Accessing a Even Addressed Word
Accessing a Odd Addressed Word
 Memory Segmentation in 8086
– Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 MB of
addressable memory.

– Addresses are expressed as 5 hex digits from 00000 – FFFFF

– Problem:
– But 20 bit addresses are TOO BIG to fit in 16 bit
registers ?

– Solution:
– Memory Segmentation
– In segmented memory architecture the available memory space is
divided into “chuncks” called as segments.
– In 8086 there are four types of segments CS , SS , DS , ES
 Memory Segmentation in 8086
– Rules of Memory Segmentation :

• Each segment is a block of 64K (65,536) consecutive memory bytes .

• A segment addressed by a 16 bit number called as segment address or Base

address. Segment address range from 0000 to FFFF .

• Within a segment, a particular memory location is specified with an offset

value called as Offset Address. An offset also ranges from 0000 to FFFF .

• Segment overlapping is allowed . When another segment starts within the

first segment , the two segments are called “Overlapping Segments “.

• In a minimum system all four segments can start with an address 00000H
Addressing a location in segmented memory
The complete physical address of a memory location is stored
in two different places –

1- A segment register ( 16- bit ) that stores the starting

address of a segment.
• Segment address can range from 0000 to FFFF .

2- Pointer and Index Registers ( 16- bit ) that stores the

offset address of a location within a segment .
• An offset address also ranges from 0000 to FFFF .

• Each segment register is associated with one or

more pointer and index registers.
 Memory FFFFF H Highest Address
Segmentation 7FFFF H Top of ES
64 K ES
 The complete ES Base
1Mbyte memory is 70000 H ES = 7000 H
divided into 16

1 MB Memory
logical segments.
5FFFF H Top of SS
 The complete 64 K SS
1Mbyte memory SS Base
segmentation is as
50000 H SS = 5000 H
shown in fig .
4489F H
Top of CS
 Each segment
contains 64Kbyte
64 K CS
CS Base
of memory. 348A0 H
CS = 348A H

 The segments can

2FFFF H Top of DS
be located as per
the need inside
64 K DS
whole range of
Bottom of DS
20000 H DS = 2000 H
1MB of memory.
00000 H Lowest address
Segmented Memory Architecture
 Physical Address Formation
• The 8086 addresses a segmented memory.

• The complete physical address which is 20-bits long is

generated using segment and offset registers each of
the size 16-bit.

• The content of a segment register also called as segment

address, and content of an offset register also called as
offset address.
• To get total physical address, put the lower nibble 0H to
segment address and add offset address.

• Fig shows formation of 20-bit physical address.

 Memory Address Generation
• An Offset is the distance from the beginning of a segment to
a particular instruction or variable.

• The Physical address of the instruction or data is obtained

by adding the Offset to Segment Register.

• Physical Address is specified as

Segment: Offset

• Physical Address of Instruction

CS:IP
• Physical Address of Stack
SS:SP
How BIU Generates 20 Bit Physical Address
Generating Address for Code Segment
 Advantages of Memory Segmentation

 Allow the memory capacity to be 1Mb even though the addresses

associated with the individual instructions are only 16 bits wide.

 Facilitate the use of separate memory areas for the program, its
data and the stack.

 Permit a program and/or its data to be put into different areas of

memory each time the program is executed.

 Multitasking becomes easy.

 Segment Registers
 There are four segment registers.
Code segment (CS) :

 It is a 16-bit register containing address of 64 KB segment with

processor instructions.

 The processor uses CS segment for all accesses to instructions referenced

by instruction pointer (IP) register.

 CS register cannot be changed directly.

 The CS register is automatically updated during far jump, far call and far
return instructions.

 It is used for addressing a memory location in the code segment of the

memory, where the executable program is stored.
 Segment Registers
Stack segment (SS) :

 The stack segment is that segment of memory, which is used to

store stack data.

 SS a 16-bit register containing address of 64KB segment with

program stack. It is used for addressing stack segment of memory.

 By default, the processor assumes that all data referenced by the

stack pointer (SP) and base pointer (BP) registers is located in the
stack segment.

 SS register can be changed directly using POP instruction.

 Segment Registers
Data segment (DS) :

 It points to the data segment memory where the data is resided.

 It is a 16-bit register containing address of 64KB segment with

Program data.

 By default, the processor assumes that all data referenced by

general registers (AX, BX, CX, DX) and index register (SI, DI) is
located in the data segment.

 DS register can be changed directly using POP and LDS

instructions.
 Segment Registers
Extra segment (ES) :

 It also refers to segment which essentially is another data segment of the

memory. It also contains data.

 It is a 16-bit register containing address of 64KB segment, usually with program

data.

 By default, the processor assumes that the DI register references the ES

segment in string manipulation instructions.

 ES register can be changed directly using POP and LES instructions.

Pointer & Index Registers
 Pointer & Index Registers
• Instruction Pointer (IP) : Points to Next Instruction in code
Memory.

 Stack Pointer (SP) is a 16-bit register pointing to program stack in

stack segment.

 Base Pointer (BP) is a 16-bit register pointing to data in stack segment.

BP register is usually used for based, based indexed or register indirect
addressing.

 Source Index (SI) is a 16-bit register. SI is used for indexed, based

indexed and register indirect addressing, as well as a source data
addresses in string manipulation instructions.

 Destination Index (DI) is a 16-bit register. DI is used for indexed,

based indexed and register indirect addressing, as well as a destination
data address in string manipulation instructions.
 Flag Registers
 Flags Register determines the current state of the processor.

 They are modified automatically by CPU after mathematical

operations.

 8086 has 9 active flags and they are divided into two categories:

1. Conditional (Status) Flags : 6

2. Control Flags. : 3
 Flag Registers

Carry flag
Overflow
Direction Parity flag

Interrupt enable Auxiliary flag

Trap Zero
6 are status flags
3 are control flag
Sign
 Flag Register Description
Carry Flag (CY):
This flag indicates an overflow condition for unsigned integer arithmetic. It is
also used in multiple-precision arithmetic.

Auxiliary Flag (AC):

If an operation performed in ALU generates a carry/barrow from lower nibble
(i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given
by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally
by the Processor to perform Binary to BCD conversion.

Parity Flag (PF):

This flag is used to indicate the parity of result. If lower order 8-bits of the result
contains even number of 1’s, the Parity Flag is set and for odd number of 1’s,
the Parity flag is reset.

Zero Flag (ZF):

It is set; if the result of arithmetic or logical operation is zero else it is reset.
 Flag Register Description
Sign Flag (SF):
In sign magnitude format the sign of number is indicated by MSB bit. If the
result of operation is negative, sign flag is set.

Over Flow flag :

This flag will be set if the result of a signed operation is too large to fit in the
number of bits available to represent it.
for example consider the addition of two signed 8-bit numbers

In 8-bit signed numbers the MSB represents the sign while remaining 7-bits are
used to represent magnitude (0 – 127 ).

0 111 0101 (+117)

0 011 0111 (+55)

1 010 1100 ( +172 )

Since the result is greater than 127 the OF Flag is set.

 Flag Register Description
Control Flags
Control flags are set or reset deliberately to control the operations of the
execution unit.

Trap Flag (TF):

It is used for single step control. It allows user to execute one instruction of a
program at a time for debugging. When trap flag is set, program can be run in
single step mode.

Interrupt Flag (IF):

It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086
is enabled and if it is reset, the interrupt is disabled. It can be set by executing
instruction sit and can be cleared by executing CLI instruction.

Direction Flag (DF):

It is used in string operation. If it is set, string bytes are accessed from higher
memory address to lower memory address. When it is reset, the string bytes
are accessed from lower memory address to higher memory address.
Minimum Mode Configuration of 8086
Memory Read Cycle in Minimum Mode
Configuration
Memory Write Cycle in Minimum Mode
Configuration
Maximum Mode Configuration of 8086
Memory Read Cycle in Minimum Mode
Configuration
Memory Write Cycle in Minimum Mode
Configuration
8086 Programming
There are three levels of languages in
8086 programming.
 Machine Language
 Assembly Language
 High-Level Language
Machine language
 Instructions are in the form of Binary Codes.
 The machine understands only binary codes as
instructions it is known as machine language.
 Disadvantages:
• Difficult to remember the binary codes
• Errors may occur and cannot be rectified easily.
High Level Languages
 Program statements are in English.
 Each Statement represents many machine code
instructions.
 The Interpreter or compiler converts the
statements into machine code.
 Examples are C, Pascal etc.
 Programs can be easily written, but compilation
and execution takes more time.
Assembly Language
 MNEMONICS are used to represent each
instruction.
 MNEMONICS are short forms of English words.
 Ex: MNEMONIC for Addition is ADD.
 Format of Instruction