8085 Complete Note PDF

INRODUCTION TO MICROPROCESSOR Prepared by: Er.
Sarbesh Chaudhary
INTRODUCTION TO MICROPROCESSORS
CHAPTER – 1
1.1 Introduction
MICROPROCESSOR: - The microprocessor is a programmable device having computing and

decision making power. It reads binary instruction from storage device called memory &
accepts binary data as an input and process data according to those instructions and provides
result as output. The characteristics of microprocessor are as follows:-
 Multipurpose
 Programmable
 Clock driven
 Register (Memory) based
The Microprocessor operates in bits i.e. “0” and “1”. Each Microprocessor processes a group of
bits known as “WORD”. Depending upon the word-length there are 8-bit, 16-bit, 32-bit and 64-
bit Microprocessors available.
1.2 History of Microprocessor
4004 - Introduced in 1971, first 4-bit μp (Microprocessor) having memory addressing capability
of 1 KB. It consist of 16 pin with clock signal of 750 HZ
8008- Introduced in 1972, 8-bit μp (Microprocessor), 40 pin
8080 - Introduced in 1973, 8-bit μp.
8085 - Introduce in 1976, 8-bit μp having addressing capability of 64kb. It consists of 40 pin with
3-6 MHZ clock signal.
8086 – Introduced in 1978, 16-bit μp having addressing capability of 1 MB. It consists of 40 pins
with 5-10 MHZ clock signal.
8088 - Introduced in 1980, 8/16-bit μp with memory addressing capability of 1 MB. It consists of
5-8 MHZ clock signal.
80286 - Introduced in 1982, 16-bit μp with memory addressing capacity of 16 MB. It consists of
68 pin with 6-12.5 MHZ clock signal.
80386 – Introduce in 1985, 32-bit μ p with 4 GB memory addressing capability. It consists of 132
pins with 22 to 33 MHZ clock signal.
DEX program, MMP 1|Page
INRODUCTION TO MICROPROCESSOR Prepared by: Er. Sarbesh Chaudhary
80486 - Introduced in 1989, 32-bit μp with 4 GB memory addressing capability. It consists of

168 pin with 26-100 MHZ clock signal.
Pentium - Introduced in 1993, 32-bit up with 4 GB of memory addressing capacity consists of

168 pins with 100 and 150 MHZ.
1.3 Stored Program concept and Von Neumann’s Architecture: The task of entering and
altering e programs for the ENIAC (electronic numerical integrator and computer) was
extremely tedious. The programming concept could be facilitated if the program could be
represented in a form suitable for storing in memory along with the data. Than a computer
could get its instruction by reading them form the memory and a program could be set or
altered by setting the values of a portion of memory. This approach is known stored program
concept. The Von Neumann architecture uses this stored program concept where data and
instructions are stored in the same memory unit.
Figure above shows the Von Neumann’s architecture here main memory is used to store both
data and instruction. ALU is capable for performing Arithmetic and logical operation binary
data. The CPU interprets the instruction in memory and causes them to be a execute. The
input/output unit helps inputting data and getting results.
The memory of Von-Neumann machine consists of thousand storage location called words of
40 binary digits (bits). Both data and instruction are stored in it.
1.4 Typical Block diagram of Microprocessor
Input Output

Fig: - Typical block diagram of Microprocessor
Input Devices: These devices are used to enter data or instructions in computer i.e. keyboard,
mouse etc. the processors read the instructions from the memory and processes them.
Output Devices: This device displays the result or output after processing. The output devices
may be monitor, keyboard etc.
ALU: This area of microprocessor performs various functions on data. The ALU performs
arithmetic operation like addition subtraction and logical operation like And, OR, XOR.
Register array: This area of microprocessor consists of various register identified by B, C, D, E, H

and L. These register are used to temporary store the data during the execution of a program.
Control Unit: This area provides the timing and control signal to all the operations in the
microcomputer. It contains the flow of data between the microprocessor memory and
peripheral.
1.5 Typical block diagram of Microcontroller
A microcontroller is an entire computer on a single chip. A microcontroller consists of

microprocessor unit (MPU), memory, input/output, peripherals, timer, A/D converter and other
components. It is very small in size. Microcontrollers are generally used in automation,
instrumentation, process control, home appliances and etc.
Fig: typical block diagram of Microcontroller

Microcontrollers are of 8, 16 and 32-bit. Example of 8-bit microcontroller is Intel 8051, 16-bit is
Intel 8096 series and 32-bit is Motorola MPC505.
1.6 General architecture of Microcomputer
Data bus
Microcomputer: A small computer that contains microprocessor is called microcomputer. They

range from 4-bit words that can address a few thousand bytes of memory to 32 bit words and
can address billions of bytes of memory. In microcomputer CPU is single integrated circuit
called microprocessor. The block diagram of microcomputer is shown above. The major parts
are central processing unit, memory, and input output ports. Each of these parts is connected
with each other through address bus, data bus, and control bus.
Memory: This consists of a mixture of RAM and ROM. It may also have magnetic floppy disk,
magnetic hard disk or optical disk. The memory is used to store data in computer. The speed of
CPU is very high, so speed of memory should match with it.
I/P port: The i/p section allows the computer to take in data from the outside world or send
data to the outside world for e.g. keyboard, video display terminals, printers, modems, etc. The
physical devices used to interface the computer buses to external systems are called ports. Two
ports are available i/p port example keyboard, mouse. O/p port example monitor, printer.
Central processing unit (CPU): The CPU controls the operation of computer. CPU consists of
arithmetic and logical unit & control unit, it performs all the arithmetic and logical operations
like add, subtract, multiply, AND, OR etc. CPU fetches binary coded instruction from memory.
Decode the instruction into a series of actions and carries out these actions in a sequence of
steps.
Address bus: The address bus consists of 16, 20, 24 or 32 parallel signal lines. On these lines the
CPU sends out the address of the memory location.

Data bus: The data bus consist of 8, 16 or 32 parallel signal lines and are bidirectional.it is used
to transfer the data from memory to CPU or vice versa and even from I/O to CPU or vice versa.
Control bus: The control bus consists of 4-10 parallel signal lines. The CPU sends out signal on
the control bus to enable the o/p of the address memory device. Control bus signal are memory
read, write, i/p read, o/p write.
1.7 Programming Languages
Computer doesn’t understand the common language of any country for e.g. English, Nepali etc.
Thus, in order to perform a task computer uses different kind of language which is called
“programming Language”. The programmer writes a sequence of instruction called “Program”
for the computer in order to perform specific task. A set of programs written for a particular
computer is known as “software” for that computer. Programming languages can be classified
into four generations, they are discussed below.
First Generation Language (1GL): Machine language is called 1GL. A program written in the
form of 0s and 1s is called “Machine language program”. In the machine language there is a
specific binary code for each instruction. For example, for Intel 8085 to add the contents of
register A and register B, the binary code is 1000 0000.
Demerits of machine language programs are:

1. Difficult to understand or debug the program.
2. Programs are long.
3. Program writing is difficult and tiresome.
4. Chances of errors in writing the program.
Second Generation Language (2GL): Assembly languages are called 2GL. In assembly language
program, programmer can easily write a program in alphanumeric symbols instead of 0s and 1s
as used in machine language. Meaningful and rememberable symbols are chosen for this
purpose. Examples are: ADD for addition, SUB for subtraction, CMP for comparison etc. such
symbols are called “mnemonics”. A program written in mnemonics is known as “Assembly
language program”. Both assembly and machine languages are microprocessor specific, thus,
these languages are also known as “Low-level language”.
Merits of assembly language are:

1. Computation time is less.
2. Faster to produce result.
3. Writing and understanding assembly language is much easier as compared to machine
language.
Demerits of assembly language are:
1. Programming is difficult and time consuming.

2. It is computer oriented, which means that the programmer must know the architecture
of the microprocessor for which he is writing programs.
3. It is longer as compared to high-level language program.
Third Generation Language (3GL): High-Level languages are called 3GL. This language
overcomes the difficulties associated with assembly languages. Instructions written in high-level
language are called “statement” rather than mnemonics and the “statement” more clearly
resemble English and Mathematics. These are procedure oriented language. In these languages
the programmer has to write ‘what to do’ as well as ‘how to do’. He has to write steps how to
perform the desired task. Examples of 3GLs are FORTRAN, PASCAL, COBOL, C, C++ etc.
Merits of High-Level languages are:

1. Instructions are very clear.
2. Writing program in high-level language is easier and faster as compared to write low-
level languages.
3. Program written in high-level language are portable.
4. The program is problem oriented rather than computer oriented.
5. It has standard syntax.
Demerits of High-level languages are:

1. Programmer has to learn the special rules to write specific high-level language.
2. Execution is slower.
3. Low efficiency of memory utilization.
4. Extensive hardware and software supports are required.
5. Compiler is required to convert high-level language into machine language. Compiler is
costly.
1.8 Instruction set of Microprocessors
An instruction is a command which asks the microprocessor to perform a specific task or job . An
instruction is a binary pattern design inside a microprocessor to perform a special function. The
entire different instructions that a particular microprocessor can handle is called its “Instruction
set”. It determines what functions the microprocessor can perform.
• Since the 8085 is an 8-bit device it can have up to 28 or 256 instructions.

• 8085 microprocessor has a total of 74 different instructions for performing different
operations or tasks.
1.9 Introduction to Simple As Possible (SAP) computers
The SAP computers have been designed for beginners. The main purpose of SAP is to introduce
all ideas behind computer operation with simple architecture. There are three generations of
SAP. These are: a. SAP1 b. SAP2 c. SAP3

SAP 1: It is the first stage in evolution of modern computers. The architecture of SAP 1
computer is given below.
Basically it consists of two units i.e. control unit and arithmetic and logic unit. As shown in the
figure above SAP 1 computer has following components:-
 Control Unit: It consists of five components which are illustrated below.
Program Counter: It is a part of control unit which is of 4-bit. It counts from 0000 to 1111. Its
job is to send the memory address of instruction which is to be executed next.

Input and Memory Address Register: It contains registers which are the part of input unit.
Before storing the address into the RAM it is first stored in memory address register only after
that it goes to RAM.
RAM: Control unit consists of 16×8 static RAM. It receives address from the memory address
register and performs read operation.
Instruction Register: It is also the part of control unit. It consists of the instructions required for
performing task.
Controller-sequencer: It generates the control signal in order to control the operation of

computer.
 ALU: It also consists of five components which are illustrated below.
Accumulator: it is a buffer register that stores intermediate results during execution of an

instruction.
Adder/Subtractor: It performs addition and subtraction using 2’s complement method.
Register B: it is another buffer register which is used in arithmetic opertions.
Output Register: it contains the output result. The result is loaded in this register from
accumulator. It is also known as output port.
Binary Display: It displays the result. It consists of a row of eight LEDs. Each LED connects to
one flip flop of the output port.
Instruction Set: SAP 1 computer consist of a set of five instructions. They are given below:
Instruction Operation comments

LDA Loads data into accumulator These are memory reference
ADD Performs addition instructions. They use data
SUB Performs subtraction stored in memory.
OUT Provides output into output These are non-memory
register reference instructions. They
HLT Stops the execution do not use data stored in
memory.
Machine Cycle: There are two machine cycles in SAP 1 computer, they are fetch cycle and
execute cycle. Each has three timing states (T-states), hence a total of 6 T-states.

SAP 2: It is the second computer system after SAP 1 in the evolution of modern computer
system. It is much more improved than that of SAP 1 computer system. The architecture of SAP
2 computer system is shown in the figure below.
Fig: SAP 2 Architecture
As shown in the figure above, various components of SAP 2 computer are illustrated below:

Input Ports: There are two input ports, they are input port I and input port II. A hexadecimal
keyboard encoder is connected to port I in order to enter data and instruction in hexadecimal
form. Two input ports are connected together.
Program Counter (PC): SAP 2 computer system consists of 16-bit program counter. Hence, it
can count from 0000 0000 0000 0000 to 1111 1111 1111 (0000H to FFFFH).
MAR and Memory: During the fetch cycle Memory Address Register (MAR) receives 16-bit
address from the program counter and then it addresses the memory location.
Memory Data Register (MDR): It is 8-bit buffer register which receives data from data bus
before a write operation and it sends received data to main bus after read operation.
Instruction Register: SAP 2 computer has more instructions than SAP 1 computer, so 8-bits are
used for op-code to accommodate 256 instructions.
Controller-Sequencer: it generates control words to control the operation of a computer.
Accumulator: It is a 8-bit register which is used to store intermediate results which can be
transferred later to ALU or Bus.
ALU & Flags: The Arithmetic and Logic Unit (ALU) performs all the arithmetic and logical
operations like add, subtract, multiply, AND, OR etc. It consists of five flip flop which serves as a
Flags. These flag sets or resets according to the conditions which arise during an arithmetic and
logical operation. The five flags are carry, parity, auxiliary carry, zero and sign flag.
TMP, B, C: These are data registers which stores data during execution of program.
Output Ports: SAP 2 has two output ports i.e. output port 3 and 4. The contents of accumulator
can be loaded on output port which then drives a hexadecimal display. Hexadecimal display
shows the hexadecimal output on the LED display.
Instruction Set of SAP 2: SAP 2 computers consist of 256 instructions set which are classified
below: -
1. Memory Reference instructions: It is an instruction which uses memory during

execution cycle. These are,
 LDA example: LDA 6285H
 STA example: SAT 6284H
 MVI example: MVI 32H

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2. Register Instructions: These are designed to move data from register to register without
having to go through memory. These are,
 MOV example: MOV A, B
 ADD example: ADD B
 SUB example: SUB C
 INR example: INR B
 DCR example: DCR C
3. Jump and Call Instructions: Jump instruction is used to jump to the instruction specified
by the address whereas call instruction is used to call the subroutine identified by the
address. These are,
 JMP example: JMP 3000H
 JZ example: JZ 0009H
 JNZ example: JNZ 3001H
 JM example: JM 3002H; jump if sign flag is set to 1.
 CALL example: CALL 6000H
 RET ;return instruction
4. Logic Instructions: These instructions are used to execute logical operations like OR,
AND, XOR, compare etc.
 CMA, ANA, ORA, XRA, ANI, ORI, XRI
5. Other Instructions: NOP, HLT, IN, OUT
DEX program, MMP 11 | P a g e

INRODUCTION TO MICROPROCESSOR, UNIT 2 Prepared by: Er. Sarbesh Chaudhary
UNIT 2
MICROPROCESSOR ARCHITECTURE AND THE INSTRUCTION SET
Internal Architecture of 8085:
Intel 8085 is an 8 bit general purpose microprocessor capable of addressing up to 64kB of memory.
It is a 40 pin IC package fabricated on a single LSI using an NMOS technology. Its clock speed is about
3 MHZ and uses a single 5v DC supply. The internal structure of 8085 is shown in figure. It consists of
three main sections.
1. Arithmetic and logic unit.
2. Timing and control unit.
3. Register array
ALU
The arithmetic and logical unit performs the addition, subtraction, logical AND, logical OR, logical
EXOR, complement, increment, decrement, left shift, rotate left, rotate right, clear etc. operations.
Timing and control unit
This unit is a section of the CPU. This unit synchronizes all the microprocessor operations with the
clock. It generates status, control and timing signals which are required for the operation of memory
and I/O devices in order to execute instructions.
REGISTER ARRAY
The 8085 has both 8 bit and 16 bit registers. It has eight addressable 8-bit registers and three 16-bit
registers. These registers can be classified as
a) General purpose register & b) Special purpose register.
a. General purpose register:
The 8085 has 6 general purpose registers to store 8 bit data during program execution. B, C, D, E,
H and L are 8-bit registers and can be used singly or 16-bit register pairs. BC, DE, HL. When used
in register pairs, the higher order byte resides in the first register (i.e. B when BC is used as
register pair) and lower order byte in second (i.e. c when BC is used). The register pair HL is used
to act as memory pointer and for this purpose it holds the 16-bit address of a memory location.
General purpose registers and accumulator is accessible to programmer.


b. Special purpose registers:
Accumulator: It is an 8-bit register used in arithmetic, logic, load and store operations as well in
input/output instructions. It is used to store intermediate results which can be transferred later to
ALU or Bus.
Temporary register: It is 8-bit register not accessible to the programmer while executing the
instruction. The 8085 places the date into temporary register for a brief period.
Program counter: The program counter acts as a pointer to the next instruction to be executed and
always contains 16-bit address of the memory location of the next instruction. The program counter
is updated by the processor and points to the next instruction after the processor has fetched the
previous instruction.
Stack pointer: The stack is an area of read write memory in which temporary information is stored
in first in last out basis. The stack pointer holds the address of last byte written on to the stack.
Instruction register and decoder: These are not accessible to the programmer. After fetching an
instruction from memory the processor load it in the instruction register. This instruction is decoded
by the decoder and the sequence of events is established for the execution of instruction.
Flags: The 8085 microprocessor consists of five flip flop which serves as a Flags. These flag sets or
resets according to the conditions which arise during an arithmetic and logical operation. It helps in
decision making process of microprocessor. The five flags are carry, parity, auxiliary carry, zero and
sign flag.
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY
UNDEFINED BITS
1. Carry flag (CY): whenever there is carry in the result, CY flag sets to “1” or else resets to “0”.
2. Sign flag (S): If data is signed data then bit D7 will be set to “1” or else resets to “0”.
3. Zero flag (Z): when result is zero, the bit D6 will set to”1” or else it will reset to “0”.
4. Auxiliary Carry flag (AC): In any arithmetic operation when a carry generated by one digit is
passed to another digit then this flag sets to “1”.
5. Parity flag (P): In the result if number of 1s are even, this flag sets or else resets. This is
generally used for error checking in data.

8085 Bus Organization:
8085 Microprocessor performs its functions by using three sets of communication lines known as
bus. The three buses are address, data and control bus, these are discussed below.
1. Address Bus: It is a group of 16 lines i.e. A0 to A15. The address bus is unidirectional which
means data can flow in only one direction from microprocessor to peripherals/memory. Each
peripheral or memory is identified by a binary number known as address. Address bus is
used to carry that 16-bit address. The 8085 with 16 lines can address 216= 65,536 memory
location. Hence, 8085 contains memory of 64 k.
2. Data Bus: The data bus is a group of eight lines used to carry data i.e. D0 to D7. It is
bidirectional which means data can flow in two directions i.e. from microprocessor to
peripherals/memory and vice versa. As data bus is 8-bit it can manipulate 8-bit data from
00H to FFH.
3. Control Bus: These are single lines which carries control signals. The microprocessor
generates specific signal for each operation, it can perform, for example memory read,
memory write, input read and output write. To read an instruction from memory,
microprocessor places 16-bit address on the address bus which is decoded by the decoder
logic to identify memory location. When memory read signal will be sent, the memory chip
will be activated and contents from that memory location will be placed on data bus and
brought to microprocessor.
The bus structure of 8085 microprocessor is shown in the figure below.

INSTRUCTION FORMAT
An instruction is a command to the microprocessor to perform a given task on specified data.
• Each instruction has two parts; one is the task to be performed called operation code or
“Opcode”.
• The second one is the data on which operation is done called “Operand”. The operand can be
specified in various ways. It may include 8 bit (or 16 bit) data, an internal register, a memory
location, or an 8-bit or 16-bit address. In some instructions, the operand is implicit.
The 8085 instruction is also classified into three groups according to word size or byte size. They are:
1. 1-byte Instructions
In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,
instructions are commonly referred to in terms of bytes rather than words.
1-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are internal
register and are coded into the instruction.
For example:
OPERATION MNEMONICS MACHINE CODE

OPCODE OPERAND BINARY HEX
CODE CODE
Copy contents of accumulator to register C. MOV C,A 0100 1111 4FH
Add the contents of register B with the contents of ADD B 1000 0000 80H
accumulator.
Invert (complement) each bit in the accumulator. CMA 0010 1111 2FH
2-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second byte specifies
the operand. Source operand is a data byte immediately following the opcode. For example:

OPCODE OPERAND BINARY CODE HEX CODE
Load data 32H into accumulator. MVI A,32H 0011 1110 3EH
0011 0010 32H
Load data F2H into register B. MVI B,F2H 0000 0110 06H
1111 0010 F2H

Write data to port 1. OUT PORT1 1101 0011 D3H

0000 0001 01H
These instructions require two memory locations each to store two binary data.
3-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two bytes specify
the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-
order address. Syntax: opcode + data byte + data byte
For example:

OPCODE OPERAND BINARY HEX
CODE CODE
Load the contents of memory location 2050H into LDA 2050H 0011 1110 3AH
accumulator. 0101 0000 50H
0010 0000 20H
Jump to the memory address 2085H. JMP 2085H 1100 0011 C3H
1000 0101 85H
0010 0000 20H
These instructions require three memory locations each to store three binary data.
DATA FORMATS
8085 microprocessor can handle 8-bit data at a time. So that, a memory location for 8085
microprocessor is designed to accommodate 8-bit data. If 16-bit data is to be stored, they are stored
in two consecutive memory locations. The address of memory location is of 16-bits i.e. 2 bytes. The
various techniques to specify data for instructions are listed below.
1. 8-bit or 16-bit data may be directly given in the instruction itself.

For e.g.: MOV BC, 45FFH
2. The address of memory location, I/O port or I/O device, where data resides may be given in
the instruction itself.
For e.g.: JMP 2001H
OUT PORT1
3. In some instructions only one register is specified. The content of the specified register is one
of the operands. It is understood that the other operand is in accumulator.
For e.g.: ADD B
4. Some instructions specify two registers. The contents of registers are the required data.
For e.g.: MOV B, C
5. In some instructions data is implied. The most instructions of this type operate on the
content of accumulator. For e.g.: RAL, RAR

INSTRUCTION SET CLASSIFICATION
An instruction is a binary pattern designed inside a microprocessor to perform a specific function.

The entire group of instructions, called the instruction set, determines what functions the
microprocessor can perform. These instructions can be classified into the following five functional
categories: data transfer (copy) operations, arithmetic operations, logical operations, branching
operations, and machine-control operations.
1. Data Transfer Operation: This instruction copies data from one location called source to another
location called destination without modifying the content of the source. The various types of data
transfer instructions are:
A) Between register: e.g. MOV A, B

B) Specific data byte to a register or memory location. E.g. MVI B, 32H
LDA, 2500H
LDAX B
C) Between a memory location and register. E.g. LXI B, 2000H (here LXI- load immediate at location).
D) Between an input/output device and location. E.g. IN 02H
OUT PORT 1
2. Arithmetic Operations: These instructions perform arithmetic operations such as addition,
subtraction, increment, and decrement.
i. Addition: Any 8 bit number or the content of register or the content of memory location
can be added to the content of accumulator and the sum is stored in the accumulator. No
two other 8 bit register can be added directly.
ADD B,
ADD M
ADI 06H
ii. Subtraction: Any 8 bit number or the content of register or can be subtracted from the
content of accumulator and result is stored in the accumulator.
SUB B
SUB M
SBI 06H
iii. Increment/Decrement: The 8 bit contents of register or memory location can be
increased or decreased by 1. Similarly, the 16-bit contents of a register pair (such as BC) can
be incremented or decrement by 1.
INR B
DCR B
INX H
DCX H
4. Logical instruction: The instruction of this group perform logical operation like AND, OR,
Compare, rotate etc.
CMP
RAL
ANA

ORA
5. Branch instruction: List instruction alters the sequence of program execution either conditionally
or unconditionally.
Jump: These instruction tests for certain condition and altered the program sequence when the
condition is met. E.g. JC, JZ, JNC, JNZ
Call, return and restart: These instructions change a sequence of program either by calling a
subroutine or returning from subroutine.
6. Machine controlled operation or instruction: This instruction control machine function such as
Halt, do nothing, and Enable interrupt. E.g.: HLT, NOP, EI
ADDRESING MODES
The various techniques to specify data for instructions are called “Addressing Modes”. It can be also
defined as the techniques which are used by an instruction to access data. The 8085 has five
addressing modes, they are described below.
1. Direct Addressing Mode: In this mode of addressing the address of the operand (data) is given in
the instruction directly. For example:
INSTRUCTIONS COMMENTS
IN 00H Accept the data from the port 00H and store them into the accumulator
OUT 01H Send the data from the accumulator to the port 01H.
STA 2004H The contents of accumulator is stored in memory location 2004H
2.Register Addressing Mode: The operand are one of the general purpose register. In this
addressing mode Data is provided through the registers.
MOV A, B Contents of register B will be moved to accumulator.
ADD B Contents of register B will be added with contents of accumulator.
3. Register Indirect Addressing Mode: In this mode of addressing the address of operand is
specified by the register pair as a pointer. This mode uses special register to refer to a memory
address. i.e. HL, where the data to be executed is stored.
MOV A, M Contents of memory location whose address is stored in HL register pair are
moved to accumulator.
ADD M Contents of memory location whose address is stored in HL register pair will be
added with contents of accumulator.

4. Immediate Addressing Mode: In this addressing mode the operand is a constant which is
specified within the instruction itself. In this mode, opcode is immediately followed by a data.
Mnemonics ending with “I” indicates that the opcode is immediate addressing.
MVI B, 32H Value 32H will be moved in register B.
ANI 2FH Logical AND operation will be performed on contents of accumulator and 2FH
5. Implied Addressing Mode: There are certain instructions which operate on the content of an
accumulator by default. The addressing mode which does not require the address of operand is
called implied addressing mode.
CMA Complement the content of accumulator.
HLT Stops the execution of program.
RAR The content of the accumulator is rotated right one bit through carry.
End of Unit-2

INTRODUCTION TO MICROPROCESSOR, UNIT 3 ER.SARBESH CHAUDHARY
UNIT 3
ASSEMBLY LANGUAGE PROGRAMMING FOR 8085
8085 Microprocessor pins description
Figure below shows the functional pin diagram of 8085 microprocessor. Intel 8085 contains 40
pins as shown in figure. Functions of each pin are described below.
DEPARTMENT OF ELECTRONICS, MMP 1

X1 & x2: These are input pin 1 & 2. These are terminals to connect to an external crystal
oscillator which drives on internal circuitry of the microprocessor to produce a suitable clock for
the operation of microprocessor.
RESET OUT: This is output pin 3. This signal indicates that the CPU is being reset.
_______
RESET IN: this is input pin 36. When this signal is low, then the microprocessor resets.
SOD: This is output pin 4. It is a data line for serial o/p. It can be used to o/p the most
significant bit of the accumulator.
SID: This is input pin 5. It is a data line for serial i/p. The data on this line is loaded into the
most significant bit of the accumulator.
CLK: This is output pin 37. It is a clock output for user which can be used for other digital ICs. Its
frequency is same at which processor operates.
VCC: This is input pin 40. It provides +5v DC supply for the microprocessor.
Vss: This is input pin 20. This is the ground reference.
RST 5.5, RST 6.5, RST 7.5 & TRAP: These are Pin 9, 8, 7 & 6 respectively. These are interrupt
signals. When interrupt is recognized, the next instruction is executed from a fixed location.
INTR: This is input pin 10. It is an interrupt request signal. When it goes high the program
counter does not increment its content. The microprocessor suspects its normal sequence of
instruction at hand it goes to the CALL instruction.
___
INTA: This is output pin 11. The microprocessor sends as interrupt acknowledgement signal
after INTR is received.
AD0 – AD7: These are input/output pins 12-19. These are time multiplexed address/data bus
which carries both data and address. It carries lower address bits A0 to A7, as well as it can be
used as data bus which Carries data of 8 bit.
A8 to A15: These are output pins 21 to 28. These lines are used for the most significant 8-bits
of the 16-bits address lines.
ALE (Address latch enable): This is output pin 30. It goes high during first clock cycle of a
machine cycle. When high, AD0 – AD7 is used as address bus.
___
WR: This is output pin 31. It controls WRITE operation. A low indicates a write operation being
performed into the selected memory or I/P device.
___
RD: This is output pin 32. It controls READ operation. When it goes low, the selected memory or
I/O device is read.
S0, S1: These are output pins 29 & 33. These are status signals and indicate the type of
operation performed.
S0 S1 Operation
0 0 HALT
0 1 READ
1 0 WRITE
1 1 FETCH (bring information from the memory to microprocessor)
__
IO/M: This is output pin 34. It distinguishes whether the address is fir memory or I/O. When
high the operation is performed between I/O and microprocessor. When low the operation is
performed between memory and microprocessor.
READY: This is input pin 35. It is used to sense whether a peripheral is ready to transfer data or
not. If READY is high, the peripheral is ready, if it is low, the μp waits till it goes high.
HOLD: This is input pin 39. When high it indicates another device is requesting the use of buses.
Having received a HOLD request the μP stops the use of the buses as soon as the current
instruction is completed. The processor regains the bus after the removal of the HOLD signal.
HLDA: This is output pin 38.This is a signal for HOLD acknowledgement. It indicates that the
HOLD request has been received. After the removal of a HOLD request the HLDA goes low.
ASSEMBLY LANGUAGE PROGRAMMING
Assembly languages are called 2nd generation language. In assembly language program,
programmer can easily write a program in alphanumeric symbols instead of 0s and 1s as used in
machine language. This is programming level in between the machine language and the high
level language. However the microprocessor can only understands the binary numbers and
hence a translator is used to convert assembly or high level program into binary machine
language so that microprocessor can execute the program.
ASSEMBLER
It is a program that translates assembly language mnemonics or source code into binary code
or object code. This translation requires that the source program be written strictly according
to the specified syntax of the assembler.
STACK
The stack is a portion of read/write memory set aside by the user for the purpose of storing
information temporarily. When the information is written on the stack, the operation is called
PUSH. When the information is read from the stack, the operation is called POP.

Stack is a ‘last-in first-out’ or LIFO type of memory. This means that data which is pushed last
into stack is popped out of it first. The stack is implemented with the help of special 16-bit
memory pointer register which is known as stack pointer (SP). During PUSH and POP operation
stack pointer register gives the address of the memory where the information is to be stored or
to be read. The stack pointer’s contents are automatically manipulated to point to the top of
stack. The memory location currently pointed by stack pointer is called top of stack.
The Size of the stack is limited only by the available memory. In the 8085, the stack is defined
by setting the SP (Stack Pointer) register; for eg:
LXI SP, FFFFH ; This sets the Stack Pointer to location FFFFH (end of memory for the 8085).
PUSH & POP INSTRUCTIONS
The 8085 provides two instructions i.e. PUSH and POP for storing information on the stack and
retrieving it back. Both PUSH and POP are 1 byte instructions and work with register pairs only.
PUSH Operation
The PUSH instruction decrements stack pointer by two and copies a word from some source to
the location in the stack where the stack pointer points. Here the source must be a WORD (16-
bit). The source of the word can be a general purpose register pair or memory. An example of
PUSH instruction is given below with the changes in stack.
Address Address
FFFB FFFB
FFFC FFFC
FFFD FFFD 3C STAK POINTER
FFFE FFFE 25
FFFF STAK POINTER FFFF
Figure (a): Stack before PUSH B operation Figure (b): Stack after PUSH B operation
PUSH B: It is a one byte instruction. This instruction performs the following steps
1. Decrement SP
2. Copy the contents of register B to the memory location pointed to by SP.
3. Decrement SP
4. Copy the contents of register C to the memory location pointed to by SP.
POP Operation
The POP instruction copies a word from the stack location pointed by the stack pointer to the
destination. The destination can be general purpose register pair or memory location. After the

word is copied from the specified destination, the stack pointer is automatically incremented by
2. An example of POP instruction is given below with the changes in stack.
Address Address
FFFB FFFB
FFFC FFFC
FFFD 3C STAK POINTER FFFD
FFFE 25 FFFE
FFFF FFFF STAK POINTER
Figure (a): Stack before POP B operation Figure (b): Stack after POP B operation
POP B: It is a one byte instruction. This instruction performs the following steps;
1. Copy the contents of the memory location (i.e. Lower order byte) pointed by the SP to
register C.
2. Increment SP
3. Copy the contents of the memory location (i.e. Higher order byte) pointed by the SP to
register B.
4. Increment SP.
SUBROUTINE
A subroutine is a group of instructions that perform a subtask. A subroutine is written as a

separate unit apart from the main program and the microprocessor transfers the program
execution sequence from main program to subroutine whenever it is called to perform a task
by using the CALL instruction. After the completion of subroutine task microprocessor returns
to main program using RET instruction. The subroutine technique eliminates the need to write a
subtask repeatedly, thus it uses memory efficiently. Before implementing the subroutine, the
stack must be defined; the stack is used to store the memory address of the instruction in the
main program that follows the subroutines call.
To implement subroutine there are two instructions CALL and RET.
CALL: This instruction is a 3 byte instruction and is used to call the subroutine unconditionally. It
saves the contents of program counter on the stack pointer. Loads the PC by jump address (16
bit memory) and executes the subroutine as shown in the figure below.
RET: This instruction is a 1 byte instruction. The RET instruction returns from the subroutine
unconditionally. It will return execution from the subroutine to the next instruction after the
CALL instruction in the calling program (i.e. Main program) as shown in the figure below.

Figure: Program execution flow while calling subroutine.
CC, CNC, CZ, CNZ, CP etc.

 Call subroutine conditionally.
 Same as CALL except that it executes on the basis of flag conditions.
RC, RNC, RZ, RNZ, RP etc.

 Return subroutine conditionally.
 Same as RET except that if executes on the basis of flag conditions.
E.g. Write an ALP to add two numbers using subroutines.
Main program Subroutine

2000 MVI B, 4AH 3000 MOV A, B
2002 MVI C, A0H 3001 ADD C
2004 CALL 3000H 3002 RET
2007 MOV B, A
2008 HLT
END OF UNIT 3

UNIT 4
INTERFACING I/O & MEMORY DEVICES
T-states
It is defined as one sub division of the operation performed in one clock period. These sub division are internal
states synchronized with system clock and each T states precisely equal to one clock period.
Machine cycle
It is defined as the time required to complete one operation of accessing memory, i/p, o/p or acknowledging and
external request. This cycle may consist of 3 to 6 T states.
Timing diagram
The necessary steps which are carried in a machine cycle can represented graphically. Such graphical
representation is called timing diagram.
Instruction cycle
The necessary steps that the CPU carries out to fetch an instruction and necessary data from the memory and to
execute it constitute and instruction cycle it is defined as the time required to complete the execution of an
instruction. An instruction cycle consists of fetch cycle and execute cycle. In fetch cycle CPU fetches opcode from
the memory . The necessary steps which are carried out to fetch an opcode from memory constitute a fetch cycle.
The necessary steps which are carried out to get data if any from the memory and to perform the specific
operation specified in an instruction constitute and execute cycle. The total time required to execute an
instruction given by IC = FC+ EC. The 8085 consists of 1-6 machine cycles or operations.
8085 Machine Cycles and their Timings
8085 has seven machine cycles. These are

1.Opcode Fetch Cycle 2.Memory Read Cycle 3.Memory Write Cycle
4.I/O Read Cycle 5.I/O Write Cycle 6.Interrupt Acknowledge
7.Bus Idle
Opcode Fetch Cycle
The first machine cycle of Microprocessor is always opcode fetch cycle in which Microprocessor finds the type of
instruction to be executed. Figure below shows the data flow and timing diagram for opcode fetch cycle. The
steps involved in opcode fetch cycle are illustrated below. Length of this cycle is 4 to 6 T-states.
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Step 1 (T1-state): In this state, 8085 places 16-bit memory address from the program counter on to the address
bus. The higher order byte of memory address is placed on A 7-A15 and the lower-order byte is placed on AD0-AD7
lines which stays ON till T1. Thus, Microprocessor activates ALE signal high.
8085 also sends three status signals i.e. IO/M= 0, which indicates it is memory related operation and signals S 1=1,
S2=1, which indicates this is opcode fetch operation.
Step 2 (T2-state): In T2, 8085 sends RD signal low in order to enable the addressed memory location. The memory
device then places the content of that memory location on to the data bus AD 0-AD7.
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Step 3 (T3-state): during T3, 8085 loads the data from data bus to the Instruction Register and makes RD signal
low to disable memory device.
Step 4 (T4-state): In T4, instruction decoder decodes the opcode and on the basis of the instruction received 8085
decides whether to enter T5 or to enter T1 of next machine cycles. One byte instructions which operate on 8-bit
data (operand) are executed in T4. For e.g.: MOV A,B ; ADD B etc.
Step 5 (T5 & T6): One byte instructions which operates on 16-bit data (operand) executes in T5 & T6. In these
states, 8085 performs stack write, internal 16-bit and conditional return operations depending upon the type of
instructions. For e.g.: INX H, DCX H, SPHL etc.
Memory READ Cycle
In order to execute 2-byte instructions consisting of an opcode and operand, two machine cycles are required.
Among these two machine cycles first one is opcode fetch and another one is memory read. 8085 executes
memory read cycle to read the contents of R/W memory or ROM. The length of this machine cycle is 3 T-states.
Figure below shows the and timing diagram for memory read cycle. The steps involved in memory read cycle are
illustrated below.
Step 1 (T1-state): In T1 8085 places the address on the address bus from stack pointer, general purpose register
pair or program counter and activates ALE signal HIGH in order to latch lower order byte of address. During T 1
8085 sends status signals i.e IO/M= 0 and S1=1, S0=0 for memory read machine cycle.
Step 2 (T2-state): In T2, 8085 sends RD signal high to enable the addressed memory location. The memory device
then places the content of that memory location on to the data bus AD 0-AD7.
Step 3 (T3-state): During T3, 8085 loads the data from the data bus to the specified register (A, B, C, D, E, H, L) and
raises RD to high which disables the memory device.
Memory WRITE Cycle
The 8085 executes the memory write machine cycle to store the data into data memory or stack memory. The
length of this machine cycle is 3 T-states. Figure below shows the timing diagram for memory write cycle. The
steps involved in memory write cycle are illustrated below.
Step 1 (T1-state): In T1 8085 places the address on the address bus from stack pointer, general purpose register
pair and activates ALE signal HIGH in order to latch lower order byte of address. During T 1 8085 sends status
signals i.e IO/M= 0 and S1=0, S0=1 for memory write machine cycle.
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Step 2 (T2-state): In T2, 8085 places data into the data bus and sends WR signal low to write into the addressed
memory location.
Step 3 (T3-state): During T3, WR signal goes high, which disables the memory device and terminates the write
operation.
Fig (a): Memory READ Machine Cycle Fig (a): Memory WRITE Machine Cycle
I/O READ & WRITE Cycle
The I/O read and I/O write machine cycle is similar to Memory READ and Memory WRITE machine cycles
respectively. The only difference is that IO/M signal is high during I/O read and Write machine cycles. The high
IO/M signal indicates that it is an I/O operation. Figure below shows the diagram of I/O read and I/O write cycles
respectively.
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Fig (a): I/O read Machine Cycle Fig (b): I/O write Machine Cycle
I/O INTERFACING
The I/O devices such as keyboard and display devices are the communication path for the Microprocessor to
communicate with outside world. Data can enter or transfer in serial mode or parallel mode. For the
communication of Microprocessor and I/O device a circuit is required which is knows as interfacing circuit. The
design of interfacing circuit depends upon instructions to be used for data transfer. There are two schemes for I/O
interfacing, they are 1. I/O mapped I/O & 2. Memory mapped I/O scheme.
I/O MAPPED I/O
Some CPUs provide one or more control lines (for example, IO/ M line for 8085), the status of which indicates
either memory or I/O operation. When the status of IO/ M line is high, it indicates I/O operation and when low, it
points to memory operation. Thus, in this case, the same address may be assigned to either memory or an I/O
device depending on the status of IO/M line.
The above scheme is referred to as I/O mapped I/O scheme. Here two separate address spaces exist—one space is
meant exclusively for memory operations and the other for I/O operations. Usually, the space earmarked for I/O is
8
much smaller than memory space. I/O mapped I/O is also known as standard I/O. A maximum of 2 = 256 I/O’s
can be addressed in this mode, because in this mode a 1-byte address is specified.
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MEMORY MAPPED I/O
In this scheme, there is only one address space. This address space is allocated to both memory and I/O devices.
Some addresses are assigned to memories and some to I/O devices. The address for I/O devices is different from
the addresses which have been assigned to memories. An I/O device is also treated as a memory location. In this
scheme one address is assigned to each memory location and one address is assigned to each I/O device.
In this scheme, all data transfer instructions of the microprocessor can be used for transferring data from and to
either memory or I/O devices. For example, MOV D,M instruction would transfer one byte of data from a memory
location or an input device to the register D, depending on whether the address in the H-L register pair is assigned
to a memory location or to an input device. If H-L contains address of a memory location, data will be transferred
from that memory location to register D, while if H-L pair contains the address of an input device, data will be
transferred from that input device to register D.
This scheme is suitable for small systems. In this scheme, IO/ M signal is not used to distinguish between memory
and I/O devices. An I/O device is interfaced in the same manner as a memory device .
COMPARISON BETWEEN MEMORY MAPPED I/O AND I/O MAPPED I/O
Interfacing: The objective of interfacing an output device is to get information or a result out of the processor
and to display it; similarly the input device is interfaced to get information into the processor. To do that three
common steps are undertaken.
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1. Decode the address bus to generate a unique pulse corresponding to the device address on the bus; this is
called I/O address pulse.
2. Combine (AND) the device address pulse with the control signal to generate a device select (I/O select) pulse
that is generated only when both signals are applied.
3. Use the I/O select pulse to active the interfacing device (I/O ports)
The diagram below illustrates the steps:
The address lines A7 – A0 are connected to a decoder which will generate a unique pulse corresponding to each
address on the address lines. This pulse is combined with the control signal to generate a device select pulse
which is used to enable an output latch or an input buffer.
Interfacing output display: The figure below shows an output interfacing circuit for LED display
Here:
 The address bus A7 – A0 is decoded by using an 8 input NAND gate.
 The output of the NAND gate goes low only when the address line carries the address FF H.
 The output of the NAND gate combines with the microprocessor control signal IOW in a NOR gate
(connected as a negative AND). The output of NOR gate (74LS02) goes high to generate on I/O select pulse
when both inputs are low (or both signals are asserted).
 Meanwhile the contents of the accumulator have been put on the data bus.
 The I/O select pulse is used to activate the latch and data are latched and displayed on the diodes.(LEDs)
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Interfacing an Input device (DIP switches): The figure below shows an input interfacing circuit for DIP
switches.
Here:
 The address bus A7 – A0 is decoded using a decoder.
 The output of the decoder (O4) goes low only when the address line carries the address 84H.
 The output of the decoder combines with the μP control signal IOR in a negative NAND gate. The output of
this gate goes low to generate an I/O select pulse when both inputs are low.
 The I/O select pulse is used to activate the buffer and the data from the DIP switches (F8H) is put on the
data.
UNIQUE & NON-UNIQUE ADRESS DECODING
If only a portion of the addressable space is going to be implemented there are two basic address decoding
strategies they are as follows:
1. UNIQUE (or Full) address decoding
 All the address lines are used to specify a memory location
 Each physical memory location is identified by a unique address
2. Non-UNIQUE (or Partial) address decoding
 Since not all the address space is implemented, only a subset of the address lines are needed to point to
the physical memory locations
 Each physical memory location is identified by several possible addresses (using all combinations of the
address lines that were not used)
MEMORY STRUCTURE
A memory is a device that stores information in electrical, magnetic or optical form. A μC based system, which
operates on digital logic, holds binary information. Semiconductor memories are used in μC based system.
Semiconductor memories have become very popular and widely used because of their high reliability, low cost,
high speed and ease with which memory size can be expanded. It can be categorized into two ways:
 Primary memory or main memory or working memory.
 Secondary memory or auxiliary memory or mass storage.
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RAM and ROM comprise the primary memory while magnetic tapes, magnetic disks, floppy disks or compact disks
(CDs) are examples of secondary memory. Difference between the two types of memories are given below,
Primary Memory:
It is the storage area where all programs are executed. The microprocessor can directly access only those items
that are stored in the primary memory. Hence, all programs and data must be within the primary memory prior to
execution. Usually, the size of the primary memory is much larger than that of processor memory and its
operating speed is much slower than processor’s registers. Primary memories can be divided into two main
groups:
1. Read only memory (ROM)
2. Random Access memory. (RAM)
Random Access memory OR Read/Write memory:

It is a volatile memory and is used in store programs and datas for immediate use of the processor. Data can be
readily written into and read from a RAM at any selected address in any sequence. Two types of read/write
memories are available:
 Static RAM
 Dynamic RAM
Comparison of SRAM and DRAM
SRAM DRAM
It stands for static RAM It stands for Dynamic RAM
This memory is made up of flip-flops and bits are This memory is made up of MOS transistor gates and
stored in the form of voltage. stores bits as charge.
It has low density. It has high density.
It has high speed. It has low speed.
It is more expensive. It is less expensive.
It consumes less power. It consumes more power.
Does not need to be refreshed. As the data is stored in the form of charge, it leaks, so
memory has to be refreshed.
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Read only memory (ROM):

ROM is a non volatile memory and can be read only. It is used to store data and programs that are not to be
altered. ROM is constructed using diodes. Among other things ROM is needed for storing an initial program called
boot strap loader. The bootstrap loader is a program whose function is to start the computer software operating
when power is turned on. Since RAM is volatile, its contents are destroyed when power is turned off. The contents
of ROM remain unaltered after power is turned off and on again. The startup of a computer consists of turning the
power on and starting the execution of an initial program. Thus when power is turned on, the hardware of the
computer sets the program counter to the first address of the bootstrap loader. The bootstrap program loads a
portion of the operation of the operating system from disk to main memory and control is then transferred to the
operating system, which prepares the computer for general use. There are five types of ROM, they are discussed
below.
Masked ROM: In this ROM, a bit pattern is permanently stored. Memory manufactures are generally equipped to
do this.
PROM (Programmable ROM): This memory has nichrome or polysilicon wires arranged in a matrix. These wires
can be functionally viewed as diode or fuse. This memory can be programmed by the user with a special PROM
programmer that selectively burns the fuses (applying high current) according to the bit patters to be stored. The
process is known as ‘burning the PROM’, and the information stored is permanent.
EPROM (Erasable PROM): EPROM uses MOSFETS. Data is stored with PROM programmer. Later data can be
erased with ultraviolet light. The effect is to wipe out the stored contents. In other word, the EPROM is ultraviolet-
light-erasable and electrically programmable. Once the chip is programmed the window is covered with opaque
tape to avoid accidental erasing.
EEPROM (Electrically erasable PROM): This is nonvolatile like EPROM but does not require U-V rays to be erased.
It can be completely erased or have certain byes changed, using electrical pulses. Writing to EEPROM is slower
than writing to RAM, so it cannot be used in high speed circuits.
FLASH MEMORY: This is a modified EEPROM. The difference is the erasure procedure. EEPROM can be erased
at a register level, but flash memory must be erased either in its entirety or at the sector (block) level.
MEMORY INTERFACING
To communicate with the memory Microprocessor selects the chips, identifies the register and then read from or
writes into the register. For this purpose following are the requirement for memory chip.
1. A memory chip requires address line to identify a memory register.
2. A memory chip requires a chip select signal (CS) to enable the chip.
3. Address lines connected to CS selects the chip & address lines connected to address lines of memory chip
selects the register.
4. Two control signals RD & WR are required. RD enables the output buffer while WR enables to input buffer.
INTERNAL STRUCTURE OF MEMORY:

The internal structure of a 8 × 8 memory is shown below. Every memory unit has the similar types of structure.
Internally a memory consists of address decoder, input buffer, output buffer, registers, address lines, data lines,
RD, WR, CS control lines as shown in the figure below.
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The number of address lines will be determined by

the memory capacity. The number of data lines will
be determined by memory size. For example for
memory capacity 1k× 8 will have 10 address lines
and data lines. 2k × 4 chip will have 11 address lines
and 4 data lines. For 2n k × m memory capacity the
number of address lines = n and number of data
lines = m.
Let’s consider the 8 × 8 memory device with 8
registers, a 3 to 8 decoder, an input buffer and an
output buffer. The device will have 3 address lines
and eight data lines. It will also have control lines RD,
WR and CS.
 To write an 8 bit word the μp places the
register address on the three address line e.g. to
write in the register 7, μp places 111 on the address
lines.
 The decoder decodes the address and selects
the register 7.
 Then the μp places the data on the data bus and sends the active low WR control signal.
 The control signal enables the input buffer and data are placed in the selected register.
 To read from this memory, the process is similar to that of write operation except that output buffer is
enabled with RD active low signal.
 The remaining address lines of the μp address bus are used to select the chip (CS).
INTERFACING RAM
To interface RAM chip following steps should be taken into

consideration
1. 8085 places a 16-bit address on an address bus & with this address
only one register must be selected. For RAM chip only 11 lines are
required to identify 2048 registers. So, address lines A0-A10 are
connected to the memory chip.
2. The remaining address lines A11-A15 should be decoded to generate a
chip select signal CS.
3. In order to read from memory, MEMR signal will be generated & in
order to write into memory, MEMW signal will be generated to enable
the appropriate buffer.
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Address Decoding for RAM chips: Address decoding of RAM can be achieved in two ways, they are by using
decoders and by using NAND gate, both type of decoding are given below.
1. By using 3:8 Decoder
For interfacing the chip with 8085 μp we just need and additional 3 to 8 decoder to select the chip. The register
inside the chip can be identified by the internal address decoder and input or output buffers can be enabled by
the control signals RD or WR.
The memory chip 2048 × 8 requires 11 address lines to identify the 2048 register. Therefore the lower address
lines A10 – A0 form the μP are connected to the chip. The remaining address line (A15 – A11) should be decoded to
generate a chip select (CS) signal unique for that chip.
The remaining five lines are connected to the decoder (3 to 8 decoder) as shown is the figure above.
 The decoder is enabled by IO / M signal is addition to address lines A15 and A14
 The output O1 of the decoder is connected to CS of the memory chip.
 The input line lines to the decoder are A15, A12, and A11. These activate the output O1 to select the
memory chip.
 Thus to select the memory chip we must have the output O1 to selected by the 3 to 8 decoder, which
means we need A13 = 0, A12 = 0, A11 = 1
 Also to enable the 3 to 8 decoder we need IO / M low and A14 = 0 , A15 = 1
Thus the chip is selected by ‘10001’ at lines A15 – A11 of the address bus. And hence the range of address for the
memory chip would be
10001 00000000000 = 8800 H
10001 11111111111 = 8FFF H
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2. By using NAND gate
In this case, the higher address lines A15 – A11 are

connected to the NAND gate for decoding and
lower address lines A0-A10 are connected to
memory chip.
INTERFACING ROM
To interface RAM chip following steps should be taken into consideration
1.8085 places a 16-bit address on an address bus & with this address only
one register must be selected. For ROM chip only 12 lines are required to
identify 4096 registers. So, address lines A0-A11 are connected to the
memory chip.
2. The remaining address lines A12-A15 should be decoded to generate a
chip select signal CS.
3. In order to read from memory, MEMR signal will be generated to enable
the appropriate buffer.
Address Decoding for ROM chips: Address decoding of ROM can also be achieved in two ways, they are by using
decoders and by using NAND gate same as for RAM, both type of decoding are given below.
1. By using 3:8 Decoder
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Similarly the ROM can be interfaced with 8085. The only difference would be, there would be no WR lines
connection, as this memory is not used for write operation. The interfacing is as shown above.
2. By using NAND gate
DMA (Direct Memory Access)
Instruction set of a processor provides for data transfer between processor registers and memory or I/O device.
Thus when data transfer between memory and an I/O device is needed, it is done in two steps, from memory to
accumulator of processor and then to I/O device or reverse. This slows down data transfer. DMA mode is
introduced to overcome this.
In DMA mode, straight data exchange takes place between memory and I/O device bypassing the processor. This
is done with the help of a DMA controller. In DMA mode, the DMA controller acts as a ‘Master’ and the
processor as a ‘Slave’. This is a process where data is transferred between two peripherals directly without the
involvement of the microprocessor. This process employs the HOLD & HLDA pin on the microprocessor.
Steps involved in DMA transfer scheme are as follows

1. The external DMA controller sends a high signal on the HOLD pin to the microprocessor.
2. The microprocessor completes the current operation and sends a signal on HLDA and stops using the buses.
3. DMA controller takes control of buses and transfers the data.
4. Once the DMA controller finishes its task, it turns off the HOLD signal and the microprocessor takes back
control of the buses.
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UNIT 5
8085 INTERRUPTS
INTERRUPT
An interrupt is a signal that an external device or peripheral board sends to the central processor in order to request
attention. In response to an interrupt, the processor stops what it is currently doing and executes an Interrupt
Service Subroutine (ISS). When the execution of the ISS is terminated, the original process may resume its previous
operation.
The interrupt is initiated by an external device and is asynchronous, meaning that it can be initiated at any time
without reference to system clock. However, the response to an interrupt request is directed or controlled by the
microprocessor.
Types of interrupt:
There are three major types of interrupts that cause a break in the normal execution of a program. They can be
classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts.
External interrupts: External interrupts are initiated via the microprocessor’s interrupt pins by external devices
such I/O devices, timing device, circuit monitoring the power supply etc. Causes of these interrupts may be; I/O
device requesting transfer of data, I/O device finished transfer of data, or power failure. External interrupts can be
further divided into two types:
1. Maskable interrupt.
2. Non-maskable interrupt.
Maskable interrupt: A maskable interrupt is one which can be enabled or disabled by executing instructions such as
EI (enable interrupts) and DI (Disable interrupt). If the microprocessor’s “interrupt enable flip flop” is disabled, it
ignores a maskable interrupt. In 8085, the 1 byte instruction EI sets the interrupt enable flip flop and enables the
interrupt process. Similarly the 1 byte instruction DI resets the interrupt enable flip flop and disables the interrupt
process. Non maskable interrupts are recognized by the processor when the interrupt is disabled.
Non maskable interrupt: This type of interrupt cannot be enabled or disabled by instructions. It has higher priority
over the maskable interrupt. This means that if both the maskable and non maskable interrupts are activated at the
same time, then the processor will service the non-maskable interrupt first. In 8085 TRAP is an example of non
maskable interrupt.
Internal interrupts: Internal interrupt arise from illegal or erroneous use of an instruction or data. Cause of this
interrupt may be: register overflow, attempt to divide by zero, an invalid operation code, stack overflow etc. These
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error conditions usually occur as a result of premature termination of the instruction execution. These are even
termed as exceptions.
Software interrupts: External and internal interrupts are initiated from signal that occurs in the hardware of the
CPU whereas software interrupt is initiated by executing an instruction. Software interrupt is a special call
instruction that behaves like an interrupt rather than a subroutine call. It can be used by the programmer to initiate
an interrupt procedure at any desired point in the program. In 8085 the instruction like RST0, RST1, RST2, RST3 etc.
causes a software interrupt.
Interrupt process:
The 8085 interrupt process is controlled by interrupt enable flip-flop which is internal to the processor and can be
set or reset by using software instructions. If the flip-flop is enabled and I/P to the interrupt signal INTR goes high
the microprocessor is interrupted.
The steps involved in interrupt process are as follows:
1 The I/O unit issues an interrupt signal to the processor. An interrupt signal from I/O is the request for exchange
of data with the processor.
2 When INTR signal goes high, processor finishes execution of the current instruction, disable the interrupt enable
flip-flop before responding to the interrupt and sends INTA signal. The processor cannot accept any interrupt
request until the flip-flop is enable again.
3 The processor now begins to transfer the control to the routine which serves the interrupt request from the
device. This routine is called Interrupt Service Subroutine (ISS) and it resides at a specified memory location. For
this process, the status of the processor, which contained by the program status word (PSW) and the location of
the next instruction to be executed which is contained by the program counter (PC), these all are pushed onto
the stack.
4 The processor then loads the program counter with the entry location of the interrupt service routine that will
respond to this interrupt. Once the program counter has been loaded, the control is transferred to the interrupt
handler program.
5 The fundamental requirement of the ISS is that it should begin by saving the contents of all the registers on the
stack (as state of the main program should be safe).
6 When interrupt processing is complete the saved register’s value (of the main program) are retrieved from the
stack and restored to the register.
7 The final function is to restore the PSW and program counter values from the stack. As a result the next
instruction to be executed will be from the previously interrupted main program.
Interrupts of 8085: The 8085 has five interrupts which are listed below according to their priority.
i. TRAP
ii. RST 7.5
iii. RST 6.5
iv. RST 5.5
v. INTR
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INTR:
This interrupt is maskable. It can be enabled by instruction EI and can be disabled by instruction DI. The INTR
interrupt requires external hardware to transfer program sequence to specific CALL locations. There are 8 numbers
of CALL-Locations for INTR interrupt. The hardware circuit generates RST codes for this purpose and places that on
the data bus externally.
The signal INTA is used to insert a Restart (RST) instruction, (it saves the memory address of the next instruction to
the stack. The program is transferred to the call location.). The RST instruction and their call locations are:
Instruction Hex-code Call location
RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038
Vectored Interrupts
Four interrupts except INTR are vectored interrupts, since these four interrupts TRAP, RST 7.5, 6.5,5.5 are
automatically vectored (transferred) to specific locations on without any external hardware. They do not require
INTA signal or an input port; the necessary hardware is already implemented inside the 8085. These interrupts and
their call locations are:
INTERRUPT CALL LOCATION
TRAP 0024 H
RST 7.5 003 CH
RST 6.5 0034 H
RST 5.5 002C H
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The TRAP has the highest, followed by RST 7.5, 6.5, 5.5 and INTR. Figure below shows the schematic diagram of
8085 interrupts.
TRAP:
It is a non maskable & highest priority interrupt signal. It cannot be enabled or disabled. When this interrupt is
triggered the program control is transferred to the location 0024 H without any external hardware or the interrupt
enable instruction. TRAP is generally used for such critical events as power failure and emergency shut off.
RST 7.5, 6.5, 5.5:

These interrupts are maskable and are enabled by software using instructions EI and SIM (set interrupt mask). The
execution of the instruction SIM enables/disables the interrupts according to the bit pattern of the accumulator.
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This is 1 byte instruction & can be used for three different functions:
1. This instruction reads the content of the accumulator and depending upon the contents it enables or
disables the interrupts.
2. The 2nd function is to set mask for RST 7.5, 6.6 and 5.5 interrupts.
3. To implement serial I/O.
RST 7.5
This can be triggered with the short pulse. The request is stored internally by the D flip-flop until it is cleared by
reset or by bit D4 .
RST 6.5, 5.5:
These are level sensitive, which means they should be kept HIGH until the Microprocessor recognizes these
interrupts. If the processor does not recognize these interrupts immediately, their triggering level should be held by
external hardware.
Programmed I/O
In this scheme data transfer from I/O to CPU or vice versa, under the control of programs which resides in memory.
These programs are executed by CPU. When I/O device is ready to transfer data, processor executes the program to
transfer data. This scheme is used when small amount of data is transferred.
Interrupt Driven I/O
Microprocessor initiates I/O devices to get ready and then it executes its main program instead of remaining in a
program loop to check the status of the I/O device. When I/O device becomes ready it sends a high signal to
processor through interrupt line. On receiving the interrupt request, the microprocessor completes the current
instruction and then attains I/O devices. It saves the contents of program counter on stack and then executes a n ISS
which transfers data to/from I/O device. After completion of transfer, processor returns back to main program. It is
used for slow I/O devices.
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UNIT 6
INTRODUCTION TO GENERAL PURPOSE
PROGRAMMABLE PERIPHERAL DEVICES
8255 PROGRAMMABLE PERIPHERAL INTERFACE (PPI)
A programmable peripheral interface is a multiport device. The port may be programmed in a variety of ways as
required by the programmer. The device is very useful for interfacing peripheral devices. It has three 8- bit ports,
namely port A, port B and port C. The port C has been further divided into two of 4-bit ports, and port C upper and
port C lower. Thus a total of 4 ports are available, two 8-bit ports and two 4-bit ports. Each port can be programmed
either as an i/p port or an o/p port.
Architecture of INTEL 8255
INTEL 8255 is a 40 pin IC which operates on 5V supply. The pins for various ports are as follows
1.PA0 – PA7 - 8 pins of port A 2.PB0 – PB7 - 8 pins of port B

3.PC0 – PC3 - 4 pins of port Clower 4. PC4 – PC7 - 4 pins of port Cupper.
The important control signals for 8255 are as follows:
(CS): This is Chip Select signal. A LOW signal on this input pin enables the communication between the 8255A &
CPU.
(RD): when this Read signal is LOW it enables the 8255A to send the data or status information to the data bus of
CPU. In essence, it allows the CPU to READ from the input port of 8255A.
(WR): When this Write signal is LOW on the input pin it enables the CPU to write data or control words into the
output port of 8255.

(A0 and A1): These are Port Select 0 and Port Select 1 input signal. These Input signals, in conjunction with the RD
and WR Input controls the selection of one of the three ports or the control word registers. They are normally
connected least significant bits of the address bus (A0 and A1).
Operating modes of 8255:

8255 has 3 modes of operation which are selected by software.
Mode 0 - Simple input/output
Mode 1 – Strobed input/output
Mode 2 – Bidirectional port.
Mode 0: In this mode of operation, a port can be operated as a simple o/p or i/p port. Each of the four ports of
8255 can be programmed to be either an i/p or o/p port.
Mode 1: Mode 1 is strobed input/output mode of operation. The port A and port B both are designed to operate in
this mode of operation. When port A and port B are programmed in mode 1, six pins of port C are used for their
control. PC0, PC1 and PC2 are used for control of port B which can be used as input or output port. If the port A is
operated as an input port then PC3, PC4, and PC5 are used for its control. The remaining pins of port C, i.e PC6 and
PC7 can be used as either input or output. When port A is operated as an output port, pins PC3, PC6 and PC7 are
used for its control. The pins PC4 and PC5 can be used either as input or output.
Mode 2: Mode 2 is strobed bidirectional mode of operation. In this mode port A can be programmed to operate as
a bidirectional port. The mode 2 operation is only for port A. When port A is programmed in mode 2, the port B can
be used in either mode 1 or mode 0. For mode 2 operation PC3 to PC7 are used for the control of port A.
CONTROL WORD
A port can be programmed to be an input or output port. For programming the ports of 8255 ,a control word is
formed. This control word is written into control word register of 8255. The control word bit can be 0 or 1. If the bit
is 1, then the port will be input port & if the bit is 0, then the port will be output port. The control word register
format is shown in the figure below.
The detailed description of the bits of the control word is as follows:
1.BIT 0: It is for Port Clower. If 0, Port Clower is output port. If 1, Port Clower is input port.
2.BIT 1: It is for Port B. If 0, port B is output port. If 1, port B is input port.
3.BIT 2: It is for the selection of the mode for the Port B. If 0, Port B operates in Mode 0. If 1, B operates in Mode 1.
4.BIT 3: It is for Port Cupper. If 0, Port Cupper is output port. If 1, Port Cupper is input port.
5.BIT 4: It is for Port A. If 0, port A is output port. If 1, port A is input port.
6.BIT 5 & BIT 6: These bits are to define the operating mode of the port A. For the various modes of Port A these bits
are defined as follows:
Mode of Port A Bit no. 6 Bit no. 5
Mode 0 0 0
Mode 1 0 1
Mode 2 1 0 or 1

7.BIT 7: It is set to 1, if Port A, B, & C are defined as input or output port. It is set to 0, if the individual pins of the
Port c are to be set or reset.
8254(8253) PROGRAMMABLE COUNTER/INTERVAL TIMER
The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer
system design. It is used for the timing and counting functions such as, BCD/binary counting, generation of accurate
time delay, generation of square wave of required frequency etc. INTEL 8253 & 8254 are programmable interval
timer.8253 is compatible with 8085 Microprocessor while 8254 is compatible with 8085, 8086 & 8088
Microprocessors. The 8254 is a superset of the 8253.
It is a 24 pins IC which operates at 5v supply. It provides three independent 16-bit counters, each capable of
handling clock inputs up to 10 MHz. It consists of six counter modes and all modes are software programmable. The
pin description of 8253 is as follows:
A0-A1: These are connected to address bus & used to select one of the three counters.
CLK0, CLK1, CLK2: These are clocks for counter0, counter1 & counter 2 respectively.
GATE0, GATE1 & GATE2: These are input gate terminal of counter0, counter1 & counter2 respectively.
OUT0, OUT1 & OUT2: These are the output terminals of counter 0, counter 1 & counter 2 respectively.

8253 also contains a data bus buffer which is of 8-bits & used to interface 8253 to the system bus via data lines. It
also contains read/write logic which takes input from system bus & generates control signals for operation of 8253.
The control word register and counters are selected according to the signals on lines A0 and A1.
Control Word Register : This register is accessed when lines A0 and A1 are at logic 1. It is used to write a command
word which specifies the counter to be used (binary or BCD), its mode, and either a read or write operation.
SC (select Counter) RW (Read/Write)

SCO SC1 FUNCTION RW1 RW0 OPERATION
0 0 Select Counter 0 0 0 Counter Latch Command
0 1 Select Counter 1 0 1 Read/Write least significant byte only
1 0 Select Counter 2 1 0 Read/Write most significant byte only
1 1 Read-Back Command 1 1 Read/Write least significant byte first,
(see Read Operations then most significant byte
M (Mode) BCD
M2 M1 M0 MODE SELECTION 0 Binary Counter 16-
0 0 0 MODE0 bits
0 0 1 MODE1 1 Binary Coded Decimal
X 1 0 MODE2 (BCD) Counter
X 1 1 MODE3
1 0 0 MODE4
1 0 1 MODE5

Operating modes of 8253:
1.MODE 0: INTERRUPT ON TERMINAL COUNT

Mode 0 is used for generation of accurate time delay under software control. This mode is set by loading the
control word into control word register. In Mode 0 operation the output will be initially low after the mode set
operation. After the count is loaded into the selected count Register the output will remain low and the counter will
count. 3) When the terminal count is reached (i.e. count reaches zero) the output will go high and remain high until
the selected count is reloaded. Gate = 1 enables counting. Gate = 0 disables counting. Gate has no effect on OUT.
2. MODE 1: PROGRAMMABLE ONE-SHOT

The output will be initially high. The output will go low on the CLK pulse following the rising edge at the gate input.
The output will go high on the terminal count and remain high until the next rising edge at the gate input. The one
shot is re-triggerable, hence the output will remain low for the full count after any rising edge of the gate input.
3. MODE 2: Rate generator

The output will be initially high. The output will go low for one clock pulse before the terminal count. The output
then goes high, the counter reloads the initial count and the process is repeated. The period from one output pulse
to the next equals the number of input counts in the count register. If Gate = 1 it enables a counting otherwise it
disables counting (Gate = 0 ). If Gate goes low during an low output pulse, output is set immediately high. A trigger
reloads the count and the normal sequence is repeated.

4. MODE 3: Square Wave Rate Generator

a) Initially output is high.
b) For even count, counter is decremented by 2 on the falling edge of each clock pulse. When the counter reaches
terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole
process is repeated.
c) If the count is odd and the output is high the first clock pulse (after the count is loaded) decrements the count by
1. Subsequent clock pulses decrement the clock by 2. After timeout, the output goes low and the full count is
reloaded. The first clock pulse (following the reload) decrements the count by 3 and subsequent clock pulse
decrement the count by two. Then the whole process is repeated. In this way, if the count is odd, the output will be
high for (n+1)/2 counts and low for (n-1)/2 counts.
d) If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while output is low, output is set high
immediately. After this, When Gate goes high, the counter is loaded with the initial count on the next clock pulse
and the sequence is repeated.
5. MODE 4: Software Triggered Strobe

The output will be initially high. The output will go low for one CLK pulse after the terminal count (TC). If Gate is one
the counting is enabled otherwise it is disabled. The Gate has no effect on the output.
6. MODE 5: Hardware triggered strobe (Retriggerable)

The output will be initially high. The counting is triggered by the rising edge of the Gate. The output will go low for
one CLK pulse after the terminal count (TC). If the triggering occurs on the Gate input during the counting, the initial
count is loaded on the next CLK pulse and the counting will be continued until the terminal count is reached.

8259 PROGRAMMABLE INTERRUPT CONTROLLER
It is used when several I/O devices transfer data using interrupt & they are connected to some interrupt line of
Microprocessor. INTEL 8259 is a single chip programmable interrupt controller. It is compatible with 8085, 8086 &
8088 Microprocessors. It is a 28 pin IC which uses NMOS technology. It requires 5v supply to operate.
Architecture of INTEL 8259
The detailed pin description of INTEL 8259 is given below.
CS (Chip select): A LOW signal on this pin indicates that chip has been selected.
WR (Write): If WR signal is LOW then INTEL 8259 will be enable to accept command word from CPU.
RD (Read): A LOW signal on this pin enable a 8259 to send status signal on data bus to CPU.
D7-D0 (Data lines): It is bidirectional data bus. Control, status & interrupt vector information are transferred via this
bus.
CAS0-CAS2: These are cascaded lines, which are used when more than one 8259 IC are to be connected.
SP/EN (Slave Program/Enable): It is related to cascade control. It is used to differentiate between master and slave
controller.
INT (Interrupt): this signal is used to interrupt CPU.
INTA (Interrupt Acknowledgement): Microprocessor acknowledges the requested interrupt through this pin.
IR0-IR7 (Interrupt Request): I/O devices send interrupt request through these lines.

A0 (Address Line): It is in conjunction with RD, WR & CS. INTEL 8259 uses it to interrupt command words the CPU
writes & the status which CPU wants to read.
OPERATION OF 8259
Eight I/O devices can be connected to 8259 through IR0-IR7 lines. One or more I/O devices can send interrupt
request at the same time to the interrupt controller. Depending upon the priority of interrupt the request of I/O
device which has highest priority is sent to the Microprocessor on INT line. In return Microprocessor sends an
acknowledgement signal via INTA line. On receipt of INTA signal all the interrupts of lower priority are discarded.
And the address of the interrupt service subroutine (ISS) for the concerned I/O device is sent by 8259.
If there are more than eight devices to transfer data using interrupt then two 8259 chips can be connected in series,
such connection is known as cascading. The 8259 IC which is connected to the processor is known as Master & the
IC which is connected to the master is known as Slave.
INTERNAL REGISTERS OF 8259
1.Interrupt Request Register (IRR): It stores the interrupt request & keeps information about all the interrupt.
2.Interrupt Service Register (ISR): The information of the interrupt which is being serviced is stored in ISR.
3.Interrupt Mask Register (IMR): It contains a specific bit for each interrupt line. It is used to disable or enable an
interrupt.
Intel 8251 UNIVERSAL SYNCHRONOUS ASYNCHROUNOUS RECEIVER TRANSMITTER (USART)
INTEL 8251 is used for serial data transmission. It is also known as Programmable Communication Interface. It can
be interfaced with 8085, 8086 & 8088 Microprocessors. It can transmit or receive serial data. It accepts the data in
parallel format from Microprocessor and converts into serial data for transmission. It also receives serial data &
converts that in parallel form & send to CPU.
Architecture of Intel 8251

Detailed pin description of Intel 8251 is as follows:

C/D (Control/Data): when this signal is low, data is transmitted from data bus. When it is high control signal is
transmitted.
DSR: Data Set Ready
DTR: Data Terminal Ready
CTS (Clear to Send): A low signal on this pin enables 8251 to transmit serial data.
RTS: Request To Send
TxD: Line for serial data transmission.
TxRDY: When the transmitter is ready this signal will be HIGH. Or else LOW.
TxE: Transmitter empty.
TxC: Transmitter clock. It controls rate of data transmission.
RxD: line for receiving data.
RxRDY: Receiver Ready.
RxC: It controls the rate at which character are received.
OPERATION OF INTEL 8251
A high signal on TxRDY line informs CPU that transmitter is ready to accept data. After receiving data from CPU, this
line becomes low. 8251 sends serial data on TxD line when CTS is low & transmitter is enabled serial data are
received on RxD line when RxRDY is low. After receiving data 8251 makes RxRDY high & informs CPU that is ready to
send data.
There are four modem control signals, they are: DSR, DTR, RTS & CTS. These are connected to corresponding lines of
MODEM. 8251 sends DTR signal to MODEM in order to indicate that it is ready to send data. When MODEM &
USART both are ready for data transmission the 8251 sends a low RTS signal to start the data transmission.
MODEM sends the acknowledgement of this request by making CTS low which will enable transmission logic of
8251.

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INRODUCTION TO MICROPROCESSOR Prepared by: Er.

MICROPROCESSOR: - The microprocessor is a programmable device having computing and

1.2 History of Microprocessor

8008- Introduced in 1972, 8-bit μp (Microprocessor), 40 pin

8080 - Introduced in 1973, 8-bit μp.

80486 - Introduced in 1989, 32-bit μp with 4 GB memory addressing capability. It consists of

Pentium - Introduced in 1993, 32-bit up with 4 GB of memory addressing capacity consists of

1.4 Typical Block diagram of Microprocessor

DEX program, MMP 2|Page

Fig: - Typical block diagram of Microprocessor

Register array: This area of microprocessor consists of various register identified by B, C, D, E, H

1.5 Typical block diagram of Microcontroller

A microcontroller is an entire computer on a single chip. A microcontroller consists of

Fig: typical block diagram of Microcontroller

DEX program, MMP 3|Page

1.6 General architecture of Microcomputer

Microcomputer: A small computer that contains microprocessor is called microcomputer. They

DEX program, MMP 4|Page

1.7 Programming Languages

Demerits of machine language programs are:

Merits of assembly language are:

DEX program, MMP 5|Page

Merits of High-Level languages are:

Demerits of High-level languages are:

• Since the 8085 is an 8-bit device it can have up to 28 or 256 instructions.

1.9 Introduction to Simple As Possible (SAP) computers

DEX program, MMP 6|Page

 Control Unit: It consists of five components which are illustrated below.

DEX program, MMP 7|Page

Controller-sequencer: It generates the control signal in order to control the operation of

 ALU: It also consists of five components which are illustrated below.

Accumulator: it is a buffer register that stores intermediate results during execution of an

Adder/Subtractor: It performs addition and subtraction using 2’s complement method.

Register B: it is another buffer register which is used in arithmetic opertions.

Instruction Operation comments

DEX program, MMP 8|Page

Fig: SAP 2 Architecture

DEX program, MMP 9|Page

Controller-Sequencer: it generates control words to control the operation of a computer.

1. Memory Reference instructions: It is an instruction which uses memory during

 LDA example: LDA 6285H

 STA example: SAT 6284H

 MVI example: MVI 32H

 MOV example: MOV A, B

 ADD example: ADD B

 SUB example: SUB C

 INR example: INR B

 DCR example: DCR C

 JMP example: JMP 3000H

 JNZ example: JNZ 3001H

 JM example: JM 3002H; jump if sign flag is set to 1.

 CALL example: CALL 6000H

 RET ;return instruction

 CMA, ANA, ORA, XRA, ANI, ORI, XRI

5. Other Instructions: NOP, HLT, IN, OUT

DEX program, MMP 11 | P a g e

MICROPROCESSOR ARCHITECTURE AND THE INSTRUCTION SET

Internal Architecture of 8085:

Timing and control unit

a. General purpose register:

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DEX program, MMP 2|Page

b. Special purpose registers: