Unit-3

1. Draw the internal architecture of 8255 PPI and explain its

operation
The 8255A is a general purpose programmable I/O device designed to transfer the data from I/O to
interrupt I/O under certain conditions as required. It can be used with almost any microprocessor. It
consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per the
requirement.
Architecture of 8255:
The parallel input-output port chip 8255 is also called as programmable peripheral input- output port. The
Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability microprocessors.
It has 24 input/output lines which may be individually programmed in two groups of twelve lines each, or
three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of these
two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines
or a 4-bit port.
Thus Group A contains an 8-bit port A along with a 4-bit port C upper. The port A lines are identified by
symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, Group B contains an 8-bit
port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and port
C lower can be used in combination as an 8-bit port C. Both the port C are assigned the same address.
Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these
ports can function independently either as input or as output ports. This can be achieved by programming
the bits of an internal register of 8255 called as control word register (CWR). This buffer receives or
transmits data upon the execution of input or output instructions by the microprocessor. The control
words or status information is also transferred through the buffer.

The two address lines, along with CS signal, determine the selection of a particular port or control
register. This is explained below:
Control Word Register (CWR): The control word format, when 8255 is operated in I/O mode, is shown
below: For 8255 PPI to be operated in I/O mode, D7 bit must be 1. The three ports are clubbed into two
groups A and B. Group A consists of Port A and CU. Port A can be operated in any of the modes 0, 1 or
2. Group B consists of Port B and CL. Here Port B can be operated in either mode 0 or 1.

Operational Modes: PPI 8255 can operate in three modes. (a) Mode 0 (b) Mode 1 and (c) Mode 2. Apart
from the three, there is another mode called BSR mode (Bit Set / Reset mode). These are I/O operations
and selected only if D7 bit of the control word register is put at 1. The three operating modes of 8255 are
distinguished in the following manner:
Mode 0: This is a basic or simple input/output mode, whose features are:
• Outputs are latched.
• Inputs are not latched.
• All ports (A, B, CU, CL) can be programmed in either input or output mode.
• Ports don’t have handshake or interrupt capability.
• Sixteen possible input/output configurations are possible.
• When unconditional or non-handshaking I/O is required, mode 0 is chosen.
Mode 1: In this mode, input or outputting of data is carried out by taking the help of handshaking signals,
also known as strobe signals. The basic features of this mode are:
• Ports A and B can function as 8-bit I/O ports, taking the help of pins of Port C.
• I/Ps and I/Ps are latched.
• Interrupt logic is supported.

Handshake signals are exchanged between CPU and peripheral prior to data transfer.
• In this mode, Port C is called status port.
• There are two groups in this mode group A and group B. They can be configured separately. Each
group consists of an 8-bit port and a 4-bit port. This 4-bit port is used for handshaking in each group.
Mode 2: In this mode, Port A can be set up for bidirectional data transfer using handshake signals from
Port C. Port B can be set up either in mode 0 or mode 1.

2. Explain the interfacing memory with neat block diagram.

Basic Concepts in Memory Interfacing: For interfacing memory devices to microprocessor
8086/88 following important points are to be kept in mind.
1. Microprocessor 8086/88 can access 1Mbytes memory since address bus is 20-bit. But it is not
always necessary to use full 1Mbytes address space. The total memory size depends upon the
application.
2. Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a data
memory. When both, EPROM and RAM are used, the total address space 1Mbytes is shared by
them.
3. The individual capacities of program memory and data memory depend on the application.
4. It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and
multiple RAMs as per the requirement of application.
5.We can place EPROM/RAM anywhere in full 1Mbytes address space. But program memory
(EPROM) should be located at last memory page so that the starting address FFFFOH will lie
within the program memory range. To provide facility to set addresses in the interrupt vector
table we must provide RAM at page 0 of memory. So that the interrupt vector table lie with the
read/write memory range.
6. It is not always necessary to locate EPROM and RAM in consecutive memory addresses.
However, it is advised to do that.
7. While interfacing memory to 8086 we have to provide odd and even banks of memory. Even
bank is selected when A0 = 0 and odd bank is selected when BHE = 0. Odd and even banks are
not required for interfacing memory to 8086.
• Select the chip
• Identify the register
• Enable the appropriate buffer.
 3. With neat block diagram explain the 8251 and its operating
modes.
The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial
data communication.
It supports the serial transmission of data.
It is packed in a 28 pin DIP.
Architecture:

• The functional block diagram of 825 1A consists five sections.

They are:
Read/Write control logic
• The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according
to the control word written into its control register.
• It monitors the data flow.
• This section has three registers and they are control register, status register and data buffer.
• The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.
• When C/D(low) is high, the control register is selected for writing control word or reading status word.
• When C/D(low) is low, the data buffer is selected for read/write operation.
• When the reset is high, it forces 8251A into the idle mode.
• The clock input is necessary for 8251A for communication with CPU and this clock does not control either the
serial transmission or the reception rate.
Transmitter
• The transmitter section accepts parallel data from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another
register called output register to convert the parallel data into serial bits.
• When output register is empty, the data is transferred from buffer to output register. Now the processor can
again load another data in buffer register
• If buffer register is empty, then TxRDY is goes to high.
• If output register is empty then TxEMPTY goes to high.
• The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.
• The clock frequency can be 1,16 or 64 times the baud rate.
Receiver
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits are received by the USART.
• During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.
• During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.
Modem control
 • The TTL logic levels of the serial data lines and the control signals necessary for serial transmission and
reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type
connector.
• In 8251A the transmission and reception baud rates can be different or same.
• The device which requires serial communication with processor can be connected to this 9-pin D-type connector
using 9-core cable
• The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data
transfer scheme between processor and 8251
4. Draw the interacting diagram of A/D convertor with 8086
microprocessor and explain its operation.
A/D AND D/A CONVERTERS
ADC 0808/0809: The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive
approximation converters. It is fastest technique. The conversion delay is 100 μs at a clock frequency of
640 kHz, which is quite low as compared to other converters.
This converter internally has a 3:8 analog multiplexer, so that at a time 8 different analog inputs can be
connected to the chips. Out of these 8 inputs only one can be selected for conversion by using 3 address
lines A, B, C. The CPU may drive these lines using output port lines in case of multichannel applications.
In case of single input applications these may be hardwired to select the proper input.

Example: Interface ADC 0808 with 8086 using 8255 ports. Use Port A of 8255 for transferring digital
data output of ADC to the CPU & Port C for control signals. Assume that an analog input is present at
I/P2 of the ADC and a clock input of suitable frequency is available for ADC. Draw the schematic &
timing diagram of different signals of ADC0808.
Solution:
• The analog input I/P2 is used & therefore address pins A, B, C should be 0,1,0 respectively to select
I/P2.
• The OE (Out put latch Enable) & ALE pins are already kept at +5v to select the ADC and enable the
outputs.
• Port C upper acts as the input port to receive the EOC signal while Port C lower acts as the output port
to send SOC to ADC.
• Port A acts as a 8-bit input data port to receive the digital data output from the ADC.
8255 Control Word:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0 = 98H
Program:
MOV AL,98H ; Initialize 8255, send AL to control word (CWR)
OUT CWR, AL
MOV AL, 02H ;Select I/P2 as analog I/P
OUT Port B, AL ;Port B as output
MOV AL, 00H ; Give start of conversion pulse to the ADC
OUT Port C, AL
MOV AL, 01H
OUT Port C, AL
MOV AL, 00H
OUT Port C, AL
WAIT: IN AL, Port C ; check for EOC by reading Port C upper & rotating
RCL ; through carry.
JNC WAIT
IN AL, Port A ; if EOC, read digital equivalent in AC
HLT ; stop.
5. Explain the concept of methods of serial communication with
example

• Serial data communication uses two methods, asynchronous and synchronous. The synchronous method
transfers a block of data (characters) at a time, while the asynchronous method transfers a single byte at a time.

• In data transmission if the data can be transmitted and received, it is a duplex transmission. This is in contrast
to simplex transmissions such as with printers, in which the computer only sends data. Duplex transmissions can
be half or full duplex, depending on whether or not the data transfer can be simultaneous. If data is transmitted
one way at a time, it is referred to as half duplex. If the data