Professional Documents
Culture Documents
University of Belgrade
School of Electrical Engineering
Department of Computer Science
Authors:
Goran Timotic gogi@beotel.yu
Gvozden Marinkovic mgvozden@eunet.yu
Prof. Dr. Veljko Milutinovic vm@etf.bg.ac.yu
PIC - Introduction
Microchip is the Embedded Control Solutions Company
The company’s focus is on products that meet the needs of the
embedded control market
Some of the benefits for the customer include:
– Quick time to market
– Allows code changes to product, during production run
– No Non-Recurring Engineering (NRE) charges for Mask Revisions
– Ability to easily serialize the product
– Ability to store calibration data, without additional hardware
– Better able to maximize PICmicro MCU inventory
– Less risk, since the same device is used for development as well as
for production.
2/60
PIC - Introduction
PICmicro devices are grouped by the size of
their Instruction Word
The three current PICmicro families are:
– Base-Line: 12-bit Instruction Word length
– Mid-Range: 14-bit Instruction Word length
– High-End: 16-bit Instruction Word length
3/60
PIC - Introduction
PIC12 Family
PIC12C5XX Family - 8-Pin, 8-Bit CMOS Microcontrollers
PIC12CE5XX Family - 8-Pin, 8-Bit CMOS Microcontrollers with
EEPROM Data Memory
PIC12C67X Family - 8-Pin, 8-Bit CMOS Microcontrollers with A/D
Converter
PIC12CE67X Family - 8-Pin, 8-Bit CMOS Microcontrollers with A/D
Converter and EEPROM Data Memory
4/60
PIC - Introduction
PIC16 Family
PIC16C5X Family & PIC16HV540 - EPROM/ROM-Based 8-Bit CMOS Microcontroller Series
PIC16C55X Family EPROM-Based 8-Bit CMOS Microcontrollers
PIC16C6X Family 8-Bit CMOS Microcontrollers
PIC16X62X Family 18-Pin EPROM-Based 8-Bit CMOS Microcontrollers
PIC16CE62X Family 8-Bit CMOS Microcontrollers with Analog Comparators and EEPROM
Data Memory
PIC16C7X Family 8-Bit CMOS Microcontrollers with A/D Converter
PIC16C7XX Family 8-Bit CMOS Microcontrollers with A/D Converter for USB, PS/2 and
Serial Device Applications
PIC16C9XX Family 8-Bit CMOS Microcontrollers with LCD Driver
5/60
PIC - Introduction
PIC17 Family
PIC17C4X Family - High-Performance 8-Bit CMOS EPROM/ROM
Microcontrollers
PIC17C7XX Family - High-Performance 8-Bit CMOS EPROM
Microcontrollers
6/60
PIC - Introduction
The high performance of the PICmicro™ devices can
be attributed to a number of architectural features
commonly found in RISC microprocessors:
– Harvard architecture
– Long Word Instructions
– Single Word Instructions
– Single Cycle Instructions
– Instruction Pipelining
– Reduced Instruction Set
– Register File Architecture
– Orthogonal (Symmetric) Instructions
7/60
PIC - Architecture Overview
13 D a ta B u s 8
EPROM P ro g ra m C o u n te r
P ro g ra m RAM
M e m o ry G e n e ra l
8 L e v e l S ta c k F ile R e g is te r s
u p to P u r p o s e I/O
(1 3 -b it) u p to
8K x 14
368 x 8
14 P ro g ra m B u s RAM Addr 9
In s t r u c t io n r e g Addr M UX
7 D ir e c t A d d r In d ir e c t
8 Addr
F S R re g
8
S T A T U S reg
In s t r u c t i o n
Decode & P o w e r-u p T im e r 3
C o n tro l
O s c illa to r S ta r t- u p M UX
T im e r
P o w e r-o n R e s e t
T im in g
G e n e ra tio n
ALU
W a tc h d o g T im e r 8
In t e r n a l
B ro w n -o u t R e s e t
R C c lo c k W re g
P e r ip h e r a l M o d u le s
8/60
PIC - Oscillator
The internal oscillator circuit is used to generate the device clock
Four device clock periods generate one internal
instruction clock (TCY) cycle
There are up to eight different modes,
which the oscillator may have:
– LP Low Frequency (Power) Crystal
– XT Crystal/Resonator
– HS High Speed Crystal/Resonator
– RC External Resistor/Capacitor (same as EXTRC with CLKOUT)
– EXTRC External Resistor/Capacitor
– EXTRC External Resistor/Capacitor with CLKOUT
– INTRC Internal 4 MHz Resistor/Capacitor
– INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT
9/60
PIC - Reset
The reset logic is used to place the device into a known state
The source of the reset can be determined
by using the device status bits
Most registers are unaffected by a reset, their status is unknown
on POR and unchanged by all other resets
The other registers are forced to a “reset state” on Power-on
Reset, MCLR, WDT reset, Brown-out Reset, Parity Error Reset,
and on MCLR reset during SLEEP
While the PICmicro™ is in a reset state, the internal phase clock
is held at Q1 (beginning of an instruction cycle)
10/60
PIC - Reset 2
Devices differentiate between various kinds of reset:
– Power-on Reset (POR) - pulse is generated on-chip when V DD
rise is detected
– MCLR reset during normal operation
– MCLR reset during SLEEP
– WDT reset during normal operation
– Brown-out Reset (BOR) - places the device into reset when
the device voltage falls below a trip point (BV DD)
– Parity Error Reset (PER)
11/60
PIC - Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles
(Q1, Q2, Q3, and Q4)
Fetch takes one instruction cycle while decode
and execute takes another instruction cycle
Due to Pipelining, each instruction effectively
executes in one cycle
If an instruction causes the program counter to change (e.g. GOTO)
then an extra cycle is required to complete the instruction
12/60
PIC - Instruction Pipeline Flow
13/60
PIC - Central Processing Unit (CPU)
CPU is responsible for:
– fetching the correct instruction for execution
– decoding that instruction
– executing that instruction
Sometimes works in conjunction with the ALU to complete the
execution of the instruction (in arithmetic and logical operations)
The CPU controls the program memory address bus, the data
memory address bus, and accesses to the stack
14/60
PIC - Instruction Clock
Each instruction cycle (TCY) is comprised of four Q cycles (Q1-Q4)
The Q cycles provide the timing/designation for the Decode, Read,
Process Data, Write, etc., of each instruction cycle
The four Q cycles that make up an instruction cycle (TCY)
can be generalized as:
– Q1: Instruction Decode Cycle or forced No operation
– Q2: Instruction Read Data Cycle or No operation
– Q3: Process the Data
– Q4: Instruction Write Data Cycle or No operation
15/60
PIC - Arithmetic Logical Unit (ALU)
PICmicro MCUs contain an 8-bit ALU and an 8-bit working register
The ALU is a general purpose arithmetic and logical unit
ALU performs arithmetic and Boolean functions between
the data in the working register and any register file
The ALU is 8-bits wide and is capable of addition,
subtraction, shift and logical operations
– In two-operand instructions
• one operand is the working register (W register)
• the other operand is a file register or an immediate constant
– In single operand instructions,
• the operand is either the W register or a file register
16/60
PIC - STATUS Register
The STATUS register contains the arithmetic status of the ALU,
the RESET status and the bank select bits for data memory
17/60
PIC - OPTION_REG Register
Readable and writable register which contains various control
bits to configure the TMR0/WDT prescaler, the external INT
Interrupt, TMR0, and the weak pull-ups on PORTB
18/60
PIC - PCON Register
The Power Control (PCON) register contains flag bit(s),
that together with the TO and PD bits, allows the user to
differentiate between the device resets
19/60
PIC - Memory Organization
There are two memory blocks
– Program memory
– Data memory
Each block has its own bus, so that access to each block
can occur during the same oscillator cycle
The data memory can further be broken down into General
Purpose RAM and the Special Func-tion Registers (SFRs)
20/60
PIC - Program Memory Organization
PCLATH
S ta c k L e v e l 1
S ta c k L e v e l 8
R e s e t V e c to r 0000h
2K
In t e r r u p t V e c t o r 0004h
4K 0005h
O n -c h ip P r o g r a m
6K M e m o ry (P a g e 0 )
07FFh
8K 0800h
O n -c h ip P r o g r a m
M e m o ry (P a g e 1 )
0FFFh
1000h
O n -c h ip P r o g r a m
M e m o ry (P a g e 2 )
17FFh
1800h
O n -c h ip P r o g r a m
M e m o ry (P a g e 3 )
1FFFh 21/60
PIC - Program Memory Organization
Mid-Range MCU devices have a 13-bit program counter capable of
addressing an 8K x 14 program memory space
The width of the program memory bus (instruction word) is 14-bits
Since all instructions are a single word, a device with an 8K x 14
program memory has space for 8K of instructions
This program memory space is divided
into four pages of 2K words each
To jump between the program memory pages, the high bits
of the Program Counter (PC) must be modified.
This is done by writing the desired value into a SFR called
PCLATH (ProgramCounter Latch High)
22/60
PIC - Program Memory Organization
Reset Vector - on any device, a reset forces
the Program Counter (PC) to address 0h
Interrupt Vector - when an interrupt is acknowledged
the PC is forced to address 0004h
Calibration Information - some devices have calibration
information stored in their program memory.
This information is programmed by Microchip when the device is
under final test
Computed GOTO - accomplished by adding an offset
to the program counter (ADDWF PCL)
23/60
PIC - Program Memory Organization
Program Counter (PC) - specifies the address of the instruction to
fetch for execution
– The low byte is called the PCL register. This
register is readable and writable
– The high byte is called the PCH register. This register contains the
PC<12:8> bits and is not directly readable or writable. All updates to
the PCH register go through the PCLATH register
Stack - 8-level deep x 13-bit wide hardware stack
– allows a combination of up to 8 program calls and interrupts to occur
– contains the return address from this branch in program execution
24/60
PIC - Program Memory Organization
Program Memory Paging
25/60
PIC - Data Memory Organization
Data memory is made up of the Special Function Registers (SFR)
area, and the General Purpose Registers (GPR) area
General Purpose Registers (GPR)
– GPRs are the general area for data storage and scratch pad operations
– We refer to this area as the Common RAM
Special Function Registers (SFR)
– The SFRs are used by the CPU and Peripheral Modules for controlling
the desired operation of the device.
– These registers are implemented as static RAM
26/60
PIC - Data EEPROM
The EEPROM data memory is readable and writable
during normal operation (full VDD range)
A byte write automatically erases the location
and writes the new data (erase before write)
This memory is not directly mapped in the register file space
It is indirectly addressed through the Special Function Registers
There are four SFRs used to read and write this memory
– EECON1
– EECON2 (not a physically implemented register)
– EEDATA - holds the 8-bit data for read/write
– EEADR - holds the address of the EEPROM location being accessed
27/60
PIC - Interrupts
One interrupt source for each peripheral module
Some modules may generate multiple interrupts
(such as the USART module)
There is a minimum of one register used in the control
and status of the interrupts (INTCON)
If the device has peripheral interrupts, then it will have registers to
enable the peripheral interrupts and registers to hold the interrupt
flag bits. Depending on the device, the registers are:
– PIE1
– PIR1
– PIE2
– PIR2
28/60
PIC - Interrupts
The current interrupts are:
– INT Pin Interrupt (external interrupt)
– TMR0 Overflow Interrupt
– PORTB Change Interrupt (pins RB7:RB4)
– Comparator Change Interrupt
– Parallel Slave Port Interrupt
– USART Interrupts
– Receive Interrupt
– Transmit Interrupt
– A/D Conversion Complete Interrupt
– LCD Interrupt.
– Data EEPROM Write Complete Interrupt
– Timer1 Overflow Interrupt
– Timer2 Overflow Interrupt
– CCP Interrupt
– SSP Interrupt
29/60
PIC - Interrupts
Control Registers
– INTCON Register
– PIE Register(s)
– PIR Register(s)
30/60
PIC - Interrupts
INTCON Register - readable and writable register,
which contains various enable and flag bits
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
31/60
PIC - Interrupts
PIE Register(s) - Peripheral Interrupt Enable register(s)
(the number of PIE registers depends on the number
of peripheral interrupt sources)
32/60
PIC - Interrupts
RCIE: USART Receive Interrupt Enable bit
TXIE: USART Transmit Interrupt Enable bit
ADIE: A/D Converter Interrupt Enable bit
ADCIE: Slope A/D Converter comparator Trip Interrupt Enable bit
OVFIE: Slope A/D TMR Overflow Interrupt Enable bit
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
EEIE: EE Write Complete Interrupt Enable bit
LCDIE: LCD Interrupt Enable bit
CMIE: Comparator Interrupt Enable bit
33/60
PIC - Interrupts
PIR Register(s) - Peripheral Interrupt Flag registers contain the
individual flag bits for the peripheral interrupts
34/60
PIC - Interrupts
ADIF: A/D Converter Interrupt Flag bit
ADCIF: Slope A/D Converter Comparator Trip Interrupt Flag bit
OVFIF: Slope A/D TMR Overflow Interrupt Flag bit
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
EEIF: EE Write Complete Interrupt Flag bit
LCDIF: LCD Interrupt Flag bit
CMIF: Comparator Interrupt Flag bit
35/60
PIC - Interrupts
Interrupt Latency
– Interrupt latency is defined as the time from the interrupt event (the
interrupt flag bit gets set) to the time that the instruction at address
0004h starts execution (when that interrupt is enabled)
– For synchronous interrupts (typically internal), the latency is 3T CY
– For asynchronous interrupts (typically external), the interrupt latency
will be 3 - 3.75TCY
Context Saving During Interrupts
– During an interrupt, only the return PC value is saved on the stack
– Typically, users may wish to save key registers during an interrupt e.g.
W register and STATUS register.
This has to be implemented in software
36/60
PIC - I/O
General purpose I/O pins can be considered
the simplest of peripherals
They allow the PICmicro™ to monitor and control other devices
To add flexibility and functionality to a device, some pins are
multiplexed with an alternate function(s)
37/60
PIC - I/O Descriptions
38/60
PIC - I/O Descriptions
Pin Name Description
OSC1 Oscillator crystal input or external clock source input
OSC2 Oscillator crystal output
PBTN Input with weak pull-up resistor
PSP0..PSP7 Parallel Slave Port for interfacing to a microprocessor port
RA0..RA5 PORTA is a bi-directional I/O port
RB0..RB7 PORTB is a bi-directional I/O port
RC0..RC7 PORTC is a bi-directional I/O port
RD Read control for parallel slave port
RD0..RD7 PORTD is a bi-directional I/O port
RE0..RE7 PORTE is a bi-directional I/O port
REFA, REFB Programmable reference A (B) output
RF0..RF7 PORTF is a digital input or LCD Segment Driver Port
RG0..RG7 PORTG is a digital input or LCD Segment Driver Port
RX USART Asynchronous Receive
SCL Synchronous serial clock input/output for I 2C mode.
SCLA, SCLB Synchronous serial clock for I 2C interface.
SDA I2C ™ Data I/O
39/60
PIC - I/O Descriptions
Pin Name Description
SDAA, SDAB Synchronous serial data I/O for I 2 C interface
SCK Synchronous serial clock input/output for SPI mode
SDI SPI Data In
SDO SPI Data Out (SPI mode)
SS SPI Slave Select input
SEG00..SEG31 LCD Segment Driver00 through Driver31
SUM AN1 summing junction output
T0CKI Timer0 external clock input
T1CKI Timer1 external clock input
T1OSO Timer1 oscillator output
T1OSI Timer1 oscillator input
TX USART Asynchronous Transmit
VLCD1...VLCD3 LCD Voltage
VLCDADJ LCD Voltage Generation
VREF Analog High Voltage Reference input.
VREG Output to control the gate of an external N-FET for voltage regulation
VSS Ground reference for logic and I/O pins
VDD Positive supply for logic and I/O pins
WR Write control for parallel slave port
40/60
PIC - Parallel Slave Port (PSP)
Some devices have an 8-bit wide Parallel Slave Port (PSP)
This port is multiplexed onto one of the devices I/O ports
The PORT operates as an 8-bit wide Parallel Slave Port, or
microprocessor port, when the PSPMODE control bit is set
(in this mode, the input buffers are TTL)
41/60
PIC - Timer0
The Timer0 module has the following features:
– 8-bit timer/counter
– Readable and writable
– 8-bit software programmable prescaler
– Clock source selectable to be external or internal
– Interrupt on overflow from FFh to 00h
– Edge select for external clock
42/60
PIC - Timer1
The Timer1 module is a 16-bit timer/counter
It consists of two 8-bit registers (TMR1H and TMR1L),
which are readable and writable
Timer1 can operate in one of three modes:
– As a synchronous timer
– As a synchronous counter
– As an asynchronous counter
43/60
PIC - Timer2
Timer2 is an 8-bit timer with
– Prescaler
– Postscaler
– Period register
Using the prescaler and postscaler at their maximum settings,
the overflow time is the same as a 16-bit timer
44/60
PIC - Capture/Compare/PWM
Each CCP (Capture/Compare/PWM) module contains a 16-bit
register which can operate in three modes:
– As a 16-bit capture register
– As a 16-bit compare register
– As a 10-bit PWM master/slave Duty Cycle register
The CCP modules are identical in operation,
with the exception of the operation of the special event trigger
45/60
PIC - Synchronous Serial Port (SSP)
The Synchronous Serial Port (SSP) module is a
serial interface useful for communicating with other
peripherals or microcontroller devices
These peripheral devices may be serial EEPROMs,
shift registers, display drivers, A/D converters, etc.
The SSP module can operate in one of two modes:
– Serial Peripheral Interface (SPI™)
– Inter-Integrated Circuit (I2C™)
• Slave mode
• I/O slope control, and Start and Stop bit detection to ease software
implementation of Master and Multi-master modes
46/60
PIC - Synchronous Serial Port (SSP)
Serial Peripheral Interface (SPI™)
– Allows 8-bits of data to be synchronously transmitted
and received simultaneously
– All four modes of SPI are supported, as well as Microwire™
(sample edge) when the SPI is in the master mode
– To accomplish communication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
47/60
PIC - Synchronous Serial Port (SSP)
Inter-Integrated Circuit (I2C™)
– The SSP module in I2C mode fully implements all slave functions,
except general call support
– Provides interrupts on start and stop bits in hardware to facilitate
software implementations of the master functions
– Implements the standard mode specifications
as well as 7-bit and 10-bit addressing
48/60
PIC - USART
The Universal Synchronous Asynchronous Receiver Transmitter
(USART) module is one of the two serial I/O modules
(other is the SSP module)
The USART can be configured in the following modes:
– Asynchronous (full duplex)
• CRT terminals
• personal computers
– Synchronous - Master (half duplex)
• A/D or D/A integrated circuits
• Serial EEPROMs etc.
– Synchronous - Slave (half duplex)
49/60
PIC - A/D Converter
The A/D allows conversion of an analog input signal
to a corresponding 8-bit digital number
The output of the sample and hold is the input into the converter,
which generates the result via successive approximation
The A/D converter has a unique feature of being able to operate
while the device is in SLEEP mode
The A/D module has three registers:
– A/D Result Register (ADRES)
– A/D Control Register0 (ADCON0) - controls the operation
of the A/D module
– A/D Control Register1 (ADCON1) - configures the functions
of the port pins
50/60
PIC - LCD
The LCD module generates the timing control to drive a static or
multiplexed LCD panel, with support for up to 32 segments
multiplexed with up to four commons
The interface to the module consists of three control registers
used to define the timing requirements of the LCD panel
– LCDCON
– LCDSE
– LCDPS
Up to 16 LCD data registers (LCD00-LCD15) that represent the
array of the pixel data
51/60
PIC - Watch Dog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator
which does not require any external components
The Watchdog Timer (WDT) is enabled/disabled by a device
configuration bit. If the WDT is enabled, software execution
may not disable this function
During normal operation, a WDT time-out generates a device RESET
If the device is in SLEEP mode, a WDT time-out causes the device
to wake-up and continue with normal operation, this is known as a
WDT wake-up
The WDT can be permanently disabled by clearing the WDTE con-
figuration bit
52/60
PIC - Device Configuration Bits
The device configuration bits allow each user to customize certain
aspects of the device to the needs of the application
When the device powers up, the state of these bits determines the
modes that the device uses
These bits are mapped in program memory location 2007h
This location is not accessible during normal device operation
(can be accessed only during programming mode)
53/60
PIC - Voltage Reference
The Voltage Reference is a 16-tap resistor ladder network that
provides a selectable voltage reference
The resistor ladder is segmented to provide two ranges of VREF
values and has a power-down function to conserve power when
the reference is not being used
54/60
PIC - Clock/Instruction Cycle
The clock input (from OSC1) is internally divided by four to
generate four non-overlapping quadrature clocks, namely Q1, Q2,
Q3, and Q4
Internally, the program counter (PC) is incremented every Q1, and
the instruction is fetched from the program memory and latched
into the instruction register in Q4
The instruction is decoded and executed during the following Q1
through Q4
55/60
PIC - Clock/Instruction Cycle
Q 1 Q 2 Q 3 Q 4 Q 1 Q 2 Q 3 Q 4 Q 1 Q 2 Q 3 Q 4
O SC1
Q 1
Q 2
Q 3
Q 4
PC
O S C 2 /C L K O U T
F e t c h IN S T ( P C )
E x e c u t e IN S T ( P C - 1 ) F e t c h IN S T ( P C + 1 )
E x e c u t e IN S T ( P C ) F e t c h IN S T ( P C + 2 )
E x e c u t e IN S T ( P C + 1 )
56/60
PIC - Instruction Format
Byte-oriented file register operations
13 8 7 6 0
OPCODE d f (FILE #)
60/60