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INSTRUCTION EXECUTION IN RISC MACHINES

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Instruction execution can be divided into five phases. These are
Phase- I: INSTRUCTION FETCH (IF)
II: INSTRUCTION DECODE & OPERAND FETCH (ID)
III: EXECUTION (EX)
IV: MEMORY OPERATION (MEM)
V: WRITE BACK (WB)

In the following discussions, we use the DLX instruction set

which is very similar to the MIPS instruction set.
We used a register transfer notation to describe what happens in
each phase of instruction execution. Control
unit is responsible for generating the necessary control signals at
various phases in instruction execution. The control unit of a typical
RISC processor is implemented in hardware (hard-wired control unit
design).

Phase- I: INSTRUCTION FETCH (IF)

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In this phase, the instruction to be executed next is fetched from
memory using PC (program counter) as the address of the memory location.
Corresponding location in the (instruction) memory is accessed and is
assigned to the instruction register (IR).
IR <-- Mem[PC];
Next, the program counter is incremented to point to the next
instruction. This is done by adding 4 to the current program counter
(Each instruction in DLX/MIPS architecture is 4 bytes long)
The new value of PC is stored in the NPC register.
NPC <-- PC + 4 ;
Schematic diagram of the processor path is given in Fig 1.

Phase- II: INSTRUCTION DECODE & OPERAND FETCH (ID)

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Once the Instruction Register is loaded with the instruction, decoding
of the that instruction along with operand fetching starts.
Depending upon the instruction format (R, I or J), opcode along with
the function-code fields are used to decode the instruction.
Simultaneously the two source operands are fetched using the
Rs1 and Rs2 field of the instruction. The fetched operands are
stored in two internal register A and B. As operand fetch takes
place even before the instruction decoding, fetching operand
values into A and B registers take place for all three instruction
forms (R, I and J) even though some instructions may have have one
or zero source operands! Simultaneous register fetch is possible
due to the fixed field decoding (source operand fields are always at
the position in all instruction formats).
Thus,
A <-- Rs1; B <- Rs2;
Example of R-Format instructions :
add R1,R2,R3 (in R-format)
__ A <-- Rs1
| /
Rd <-- Rs1 func Rs2 <== |ALU --- B <-- Rs2
|

Here, func may be any arithmetic operation (e.g.. add, sub, mult etc.)
where R1 is the destination reg. and R2,R3 are the source operands of the
instruction (meaning R1 <- R2+R3 ).
Example of I-format instructions:
add R1,R2,#8 Rs1 is R2, Rd is R1; the immediate constant
(8 in this case ) is stored in the
offset filed (LS 16bit of I-format)
beqz R1,loop (conditional branch instruction)
(Rs1 is R1 and Rs2 and Rd fields are unused.)
offset (to the instruction labelled loop)
from the current PC (actually PC+4) is
stored in the offset filed (LS 16bit of
I-format)
ld R2,8[R3] (Rs1 is R3 and Rd is R2; Rs2 is unused;
displacement (8 in this case) is stored
in the offset filed (LS 16bit of I-format
instruction)
st -16[R2],R1 (Rs1 is R2 and Rs2 is R1 ; Rd is unused)
displacement (-16 in this case) is in the
offset filed.
To get the immediate constant or displacement or offset from the
I-format instruction, the Imm (internal) register gets the
32-bit sign extended value of the offset field value.
Imm <-- SignExt(LS 16-bit of IR)

Phase- III: EXECUTION (EX)

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In this phase,
(IIIa) ARITHMETIC INSTRUCTIONS are executed as follows. The operands
(A and B register) for R-format and (A and Imm) for I-format are
sent to the ALU with the appropriate control signal for performing
the arithmetic operation (see Fig. 1). The control signals for the ALU
and the MUX used to choose the second operand (between B and Imm, in this
case) are derived by the control unit using the opcode and function code
fields of the instruction in IR. Thus,
ALU_out <-- A (+) B (for instruction in R-format)
 ALUo_ut <-- A (+) Imm (for instruction in I-format)
On the other hand,
(IIIb) for DATA TRANSFER INSTRUCTIONS, only computing the effective
address of the memory location is done in the EX phase.
For example, in case of a LOAD instruction,
Ld R2, 8(R1)
the decode and operand fetch phase has fetched the source register (R1)
in A and the displace (8 in this case)) has been sign extended in
Imm register. Hence the effective memory address is

ALU_out <-- A + Imm (in this case ALU_out is called

effective memory address )
And
(IIIc) for CONTROL INSTRUCTIONS (branching (by PC relative address),
the branch target address is calculated by adding the offset (given in the
offset field of the instruction, loaded and sign extended in the Decode
phase in the Imm register, to the Next Program Counter (NPC) value.
That is,
ALU_out <-- NPC + Imm
For this, the first input operand is NPC which is Multiplexed with
operand from the A register. (see Figure 1).
Further the Cond register is set based on the condition (source register
value equal to zero or not equal to zero) specified in the instruction.
That is
Cond <-- A (eq/neq) 0
For ALU and Load/Store instruction. the Cond register can be reset to 0.
Cond <-- 0
For unconditional branch instructions (Jump Instrn.) the target address
is specified as a 26-bit constant in the instruction (J-Format). For this
instruction, the new PC value is obtained by concatenating the MS 4 bits
of the current PC value, with 26-bit addr. specified in the instruction,
and "00". Since all instructions in the DLX/MIPS architecture are 4
bytes wide, all instructions start at word boundary (address divisible
by 4), and hence the LS 2-bits of PC will always be 00.
PC <-- PC_(31-28) || 26-bit addr || 00
[Q:] How is PC is updated for JR (Jump Register) and JLR instruction?
Also, how is the link register updated in JL/JLR instruction?
Phase- IV: MEMORY OPERATION (MO)
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The memory phase is important fro Load/Store instructions only.
For load instructions, the memory location whose effective address
was calculated in the EX phase is fetched. That is,
LDR <--- Mem[ALU_out]
For store instructions, the memory location whose effective address
was calculated in the EX phase is written with the second source
operand (which is fetched in B register).. That is,
 Mem[ALU_out] = B;
Phase- V: WRITE BACK (WB) / (RESULT WRITE)
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In this phase, for ALU and Load instructions, the result value is written in
the destination register. For branch instruction, PC is loaded with
the branch target address (calculated in the EX phase) or NPC depending
whether or not the condition specified in conditional branch instruction is
true.
For ALU instruction,
Rd <-- ALU_out
for Ld instruction
Rd <-- LDR
Hence LDR and ALU_out are multiplexed in the WB stage as shown in Figure 1.
Note that PC has to be set for branch instructions either to NPC or to
branch target address, and to NPC for all other instruction.
For uniform implementation of this, the Cond register

For branch instruction,

PC <--- NPC if Cond == 0
PC <--- ALU_out if Cond == 1
This is achieved by multiplexing NPC and ALU_out and controlling the
MUX output through the Cond register (as shown in Figure 1).
Note, for unconditional branches (Jumps), Cond must be set to 1 to effect
the branch. For non-branch instructions, Cond is set to 0 in the EX phase
and this ensures that PC gets NPC.

Typically each phase of instruction execution is completed within

one clock cycle. The clock synchronizes all activities of the processor
and the events/actions of the processor are triggered at the rising/falling
edge of the clock.