Professional Documents
Culture Documents
Data Sheet
64/80/100-Pin,
16-Bit Flash Microcontrollers
with USB On-The-Go (OTG)
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Remappable Peripherals
Memory (Bytes)
Comparators
UART w/IrDA®
PMP/PSP
Capture Input
USBOTG
Timers 16-Bit
Program
PWM Output
Remappable
CTMU
JTAG
Compare/
I2C™
Pins
Device
Pins
SPI
VBUSST/VCMPST1/CN68/RF0
VCPCON/RP24/CN50/RD1
RP25/PMWR/CN13/RD4
RP20/PMRD/CN14/RD5
RP22/PMBE/CN52/RD3
DPH/RP23/CN51/RD2
VCMPST2/CN69/RF1
C3INA/CN16/RD7
C3INB/CN15/RD6
PMD4/CN62/RE4
PMD3/CN61/RE3
PMD2/CN60/RE2
PMD1/CN59/RE1
PMD0/CN58/RE0
VCAP/VDDCORE
ENVREG
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SOSCO/T1CK/C3INC/RPI37/
1 48 CN0/RC14
PMD5/CN63/RE5
47 SOSCI/C3IND/CN1/RC13
SCL3/PMD6/CN64/RE6 2
46 DMH/RP11/INT0/CN49/RD0
SDA3/PMD7/CN65/RE7 3
C1IND/RP21/PMA5/CN8/RG6 4 45 RP12/PMCS1/CN56/RD11
C1INC/RP26/PMA4/CN9/RG7 5 44 SCL1/RP3/PMCS2/CN55/RD10
C2IND/RP19/PMA3/CN10/RG8 6 43 DPLN/SDA1/RP4/CN54/RD9
PIC24FJ64GB106 42 RTCC/DMLN/RP2/CN53/RD8
MCLR 7
RP27/PMA2/C2INC/CN11/RG9 8
PIC24FJ128GB106 41 VSS
VSS 9 PIC24FJ192GB106 40 OSCO/CLKO/CN22/RC15
VDD 10 PIC24FJ256GB106 39 OSCI/CLKI/CN23/RC12
PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 11 38 VDD
PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 12 37 D+/RG2
AN3/C2INA/VPIO/CN5/RB3 13 36 D-/RG3
AN2/C2INB/VMIO/RP13/CN4/RB2 14 35 VUSB
PGEC1/AN1/VREF-/RP1/CN3/RB1 15 34 VBUS
PGED1/AN0/VREF+/RP0/PMA6/CN2/RB0 16 33 RP16/USBID/CN71/RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AN15/RP29/REFO/PMA0/CN12/RB15
TDI/AN13/PMA10/CTED1/CN31/RB13
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
AN8/RP8/CN26/RB8
AN9/RP9/PMA7/CN27/RB9
TMS/CVREF/AN10/PMA13/CN28/RB10
TCK/AN12/PMA11/CTED2/CN30/RB12
TDO/AN11/PMA12/CN29/RB11
AN14/CTPLS/RP14/PMA1/CN32/RB14
SDA2/RP10/PMA9/CN17/RF4
SCL2/RP17/PMA8/CN18/RF5
AVSS
VSS
AVDD
VDD
VBUSST/VCMPST1/CN68/RF0
VCPCON/RP24/CN50/RD1
RP25/PMWR/CN13/RD4
RP20/PMRD/CN14/RD5
RP22/PMBE/CN52/RD3
DPH/RP23/CN51/RD2
VCMPST2/CN69/RF1
RPI42/CN57/RD12
C3INA/CN16/RD7
C3INB/CN15/RD6
PMD4/CN62/RE4
PMD3/CN61/RE3
PMD2/CN60/RE2
PMD1/CN59/RE1
PMD0/CN58/RE0
VCAP/VDDCORE
CN19/RD13
CN77/RG0
CN78/RG1
ENVREG
65
64
63
62
61
75
74
73
72
71
70
69
68
67
66
80
79
78
77
76
60 SOSCO/T1CK/C3INC/RPI37/CN0/RC14
PMD5/CN63/RE5 1
59 SOSCI/C3IND/CN1/RC13
SCL3/PMD6/CN64/RE6 2
58 DMH/RP11/INT0/CN49/RD0
SDA3/PMD7/CN65/RE7 3
RPI38/CN45/RC1 57 RP12/PMCS1/CN56/RD11
4
RPI40/CN47/RC3 56 SCL1/RP3/PMCS2/CN55/RD10
5
PMA5/RP21/C1IND/CN8/RG6 6 55 SDA1/DPLN/RP4/CN54/RD9
C1INC/RP26/PMA4/CN9/RG7 7 54 DMLN/RTCC/RP2/CN53/RD8
C2IND/RP19/PMA3/CN10/RG8 8 53 SDA2/RPI35/CN44/RA15
PIC24FJ64GB108 52 SCL2/RPI36/CN43/RA14
MCLR 9
C2INC/RP27/PMA2/CN11/RG9 10
PIC24FJ128GB108 51 VSS
VSS 11 PIC24FJ192GB108 50 OSCO/CLKO/CN22/RC15
VDD 12 PIC24FJ256GB108 49 OSCI/CLKI/CN23/RC12
TMS/RPI33/CN66/RE8 48 VDD
13
TDO/RPI34/CN67/RE9 14 47 D+/RG2
PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 15 46 D-/RG3
PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 16 45 VUSB
AN3/C2INA/VPIO/CN5/RB3 17 44 VBUS
AN2/C2INB/VMIO/RP13/CN4/RB2 18 43 RP15/CN74/RF8
PGEC1/AN1/RP1/CN3/RB1 19 42 RP30/CN70/RF2
PGED1/AN0/RP0/CN2/RB0 20 41 RP16/USBID/CN71/RF3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RP5/CN21/RD15
AVDD
VDD
PGED2/AN7/RP7/RCV/CN25/RB7
Vss
AN11/PMA12/CN29/RB11
AN15/REFO/RP29/PMA0/ACN12/RB15
PGEC2/AN6/RP6/CN24/RB6
AN8/RP8/CN26/RB8
AN9/RP9/CN27/RB9
AN10/CVREF/PMA13/CN28/RB10
TCK/AN12/PMA11/CTED2/CN30/RB12
TDI/AN13/PMA10/CTED1/CN31/RB13
RP10/PMA9/CN17/RF4
RP17/PMA8/CN18/RF5
RPI43/CN20/RD14
VREF-/PMA7/CN41/RA9
VREF+/PMA6/CN42/RA10
AN14/CTPLS/RP14/PMA1/CN32/RB14
AVSS
VBUSST/VCMPST1/CN68/RF0
VCPCON/RP24/CN50/RD1
RP25/PMWR/CN13/RD4
RP20/PMRD/CN14/RD5
RP22/PMBE/CN52/RD3
DPH/RP23/CN51/RD2
VCMPST2/CN69/RF1
RPI42/CN57/RD12
C3INA/CN16/RD7
C3INB/CN15/RD6
PMD4/CN62/RE4
PMD3/CN61/RE3
PMD2/CN60/RE2
PMD1/CN59/RE1
PMD0/CN58/RE0
VCAP/VDDCORE
CN80/RG13
CN79/RG12
CN81/RG14
CN19/RD13
CN77/RG0
CN78/RG1
CN40/RA7
CN39/RA6
ENVREG
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75 VSS
CN82/RG15 1
SOSCO/T1CK/C3INC/RPI37/
VDD 2 74 CN0/RC14
PMD5/CN63/RE5 3 73 SOSCI/C3IND/CN1/RC13
SCL3/PMD6/CN64/RE6 4 72 DMH/RP11/INT0/CN49/RD0
SDA3/PMD7/CN65/RE7 5 71 RP12/PMCS1/CN56/RD11
RPI38/CN45/RC1 6 70 RP3/PMCS2/CN55/RD10
RPI39/CN46/RC2 7 69 DPLN/RP4/CN54/RD9
RPI40/CN47/RC3 8 68 DMLN/RTCC/RP2/CN53/RD8
RPI41/CN48/RC4 9 67 SDA1/RPI35/CN44/RA15
C1IND/RP21/PMA5/CN8/RG6 10 66 SCL1/RPI36/CN43/RA14
C1INC/RP26/PMA4/CN9/RG7 11 PIC24FJ64GB110 65 VSS
OSCO/CLKO/CN22/RC15
C2IND/RP19/PMA3/CN10/RG8 12 PIC24FJ128GB110 64
MCLR 13 63 OSCI/CLKI/CN23/RC12
PIC24FJ192GB110
C2INC/RP27/PMA2/CN11/RG9 14 62 VDD
VSS 15
PIC24FJ256GB110 61 TDO/CN38/RA5
VDD 16 60 TDI/CN37/RA4
TMS/CN33/RA0 17 59 SDA2/CN36/RA3
RPI33/CN66/RE8 18 58 SCL2/CN35/RA2
RPI34/CN67/RE9 19 57 D+/RG2
PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 20 56 D-/RG3
PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 21 55 VUSB
AN3/C2INA/VPIO/CN5/RB3 22 54 VBUS
AN2/C2INB/VMIO/RP13/CN4/RB2 23 53 RP15/CN74/RF8
PGEC1/AN1/RP1/CN3/RB1 24 52 RP30/CN70/RF2
PGED1/AN0/RP0/CN2/RB0 25 51 RP16/USBID/CN71/RF3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VSS
VDD
VDD
AN14/CTPLS/RP14/PMA1/CN32/RB14
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
VREF-/PMA7/CN41/RA9
VREF+/PMA6/CN42/RA10
AN8/RP8/CN26/RB8
AN9/RP9/CN27/RB9
TCK/CN34/RA1
RP31/CN76/RF13
RPI32/CN75/RF12
AN12/PMA11/CTED2/CN30/RB12
AN13/PMA10/CTED1/CN31/RB13
AN15/REFO/RP29/PMA0/CN12/RB15
RPI43/CN20/RD14
RP5/CN21/RD15
RP10/PMA9/CN17/RF4
RP17/PMA8/CN18/RF5
AN10/CVREF/PMA13/CN28/RB10
AVDD
AVSS
AN11/PMA12/CN29/RB11
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
EA MUX 16
Address Bus
Literal Data
24 16 16
PORTD(1)
Inst Register
Instruction
Decode & PORTE(1)
Control
Divide
Control Signals Support (10 I/O)
OSCO/CLKO 16 x 16
OSCI/CLKI W Reg Array
17x17
Timing Power-up Multiplier
Generation Timer
Oscillator
FRC/LPRC Start-up Timer
REFO PORTF(1)
Oscillators 16-Bit ALU
Power-on
Reset (9 I/O)
16
Precision
Band Gap Watchdog
Reference Timer
ENVREG BOR and
Voltage
Regulator LVD(2)
PORTG(1)
(12 I/O)
VDDCORE/VCAP VDD, VSS MCLR
10-Bit
Timer1 Timer2/3(3) Timer4/5(3) RTCC Comparators(3) USB OTG
ADC
PMP/PSP
Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: These peripheral I/Os are only accessible through remappable pins.
PMA4 5 7 11 O —
PMA5 4 6 10 O —
PMA6 16 24 29 O —
PMA7 22 23 28 O —
PMA8 32 40 50 O —
PMA9 31 39 49 O —
PMA10 28 34 42 O —
PMA11 27 33 41 O —
PMA12 24 30 35 O —
PMA13 23 29 34 O —
PMCS1 45 57 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15.
PMCS2 44 56 70 O ST Parallel Master Port Chip Select 2 Strobe/Address Bit 14.
PMBE 51 63 78 O — Parallel Master Port Byte Enable Strobe.
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C™ = I2C/SMBus input buffer
PMD0 60 76 93 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
PMD1 61 77 94 I/O ST/TTL Address/Data (Multiplexed Master modes).
VDD
VSS
R1 (1) (1)
16-bit microcontrollers requires attention to a minimal R2
set of device pin connections before proceeding with (EN/DIS)VREG
MCLR
development. VCAP/VDDCORE
C1
The following pins must always be connected: C7
PIC24FXXXX
• All VDD and VSS pins
VDD
(see Section 2.2 “Power Supply Pins”) VSS
C6(2) C3(2)
• All AVDD and AVSS pins, regardless of whether or VSS
VDD
not the analog device features are used
AVDD
AVSS
VDD
VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
C5(2) C4(2)
• ENVREG/DISVREG and VCAP/VDDCORE pins
(PIC24FJ devices only)
(see Section 2.4 “Voltage Regulator Pins
Key (all values are recommendations):
(ENVREG/DISVREG and VCAP/VDDCORE)”)
C1 through C6: 0.1 F, 20V ceramic
These pins must also be connected if they are being
C7: 10 F, 6.3V or greater, tantalum or ceramic
used in the end application:
R1: 10 kΩ
• PGECx/PGEDx pins used for In-Circuit Serial
R2: 100Ω to 470Ω
Programming™ (ICSP™) and debugging purposes
Note 1: See Section 2.4 “Voltage Regulator Pins
(see Section 2.5 “ICSP Pins”)
(ENVREG/DISVREG and VCAP/VDDCORE)”
• OSCI and OSCO pins when an external oscillator for explanation of ENVREG/DISVREG pin
source is used connections.
(see Section 2.6 “External Oscillator Pins”) 2: The example shown is for a PIC24F device
Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
• VREF+/VREF- pins used when external voltage adjust the number of decoupling capacitors
reference for analog modules is implemented appropriately.
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
ESR ()
family) must always be connected directly to either a 0.1
similar noise).
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
C2
Application Notes, available at the corporate web site
Oscillator
(www.microchip.com): GND Crystal
• AN826, “Crystal Oscillator Basics and Crystal C1
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design” OSCI
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
DEVICE PINS
Data Bus
Interrupt
Controller
16
8 16 16
Data Latch
23
PCH PCL Data RAM 16
23
Program Counter
Stack Loop Address
Control Control Latch
Logic Logic
23 16
RAGU
Address Latch WAGU
Program Memory
Control Signals
to Various Blocks Hardware
Multiplier 16 x 16
W Register Array
Divide
Support 16
16-Bit ALU
16
To Peripheral Modules
W9
W10
W11
W12
W13
W14 Frame Pointer
W15 Stack Pointer 0
7 0
Table Memory Page
TBLPAG
Address Register
7 0
Program Space Visibility
PSVPAG Page Address Register
15 0
Repeat Loop Counter
RCOUNT
Register
15 SRH SRL 0
IPL
— — — — — — — DC
2 1 0 RA N OV Z C
ALU STATUS Register (SR)
15 0
— — — — — — — — — — — — IPL3 PSV — — CPU Control Register (CORCON)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
3.3 Arithmetic Logic Unit (ALU) The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
The PIC24F ALU is 16 bits wide and is capable of addi- dedicated hardware multiplier and support hardware
tion, subtraction, bit shifts and logic operations. Unless for 16-bit divisor division.
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the 3.3.1 MULTIPLIER
ALU may affect the values of the Carry (C), Zero (Z),
The ALU contains a high-speed, 17-bit x 17-bit
Negative (N), Overflow (OV) and Digit Carry (DC)
multiplier. It supports unsigned, signed or mixed sign
Status bits in the SR register. The C and DC Status bits
operation in several multiplication modes:
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations. 1. 16-bit x 16-bit signed
The ALU can perform 8-bit or 16-bit operations, 2. 16-bit x 16-bit unsigned
depending on the mode of the instruction that is used. 3. 16-bit signed x 5-bit (literal) unsigned
Data for the ALU operation can come from the W 4. 16-bit unsigned x 16-bit unsigned
register array, or data memory, depending on the 5. 16-bit unsigned x 5-bit (literal) unsigned
addressing mode of the instruction. Likewise, output
6. 16-bit unsigned x 16-bit signed
data from the ALU can be written to the W register array
or a data memory location. 7. 8-bit unsigned x 8-bit unsigned
TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Instruction Description
ASR Arithmetic shift right source register by one or more bits.
SL Shift left source register by one or more bits.
LSR Logical shift right source register by one or more bits.
FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES
7FFFFFh
800000h
F7FFFEh
F80000h
Device Config Registers Device Config Registers Device Config Registers Device Config Registers
F8000Eh
F80010h
FEFFFEh
FF0000h
DEVID (2) DEVID (2) DEVID (2) DEVID (2)
FFFFFFh
FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES
MSB LSB
Address MSB LSB Address
0001h 0000h SFR
SFR Space
07FFh 07FEh Space
Near
0801h 0800h Data Space
1FFFh 1FFEh
2001h 2000h
Implemented Data RAM
Data RAM
47FFh 47FEh
4801h 4800h
Unimplemented
Read as ‘0’
7FFFh 7FFFh
8001h 8000h
Program Space
Visibility Area
FFFFh FFFEh
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
PIC24FJ256GB110 FAMILY
WREG13 001A Working Register 13 0000
WREG14 001C Working Register 14 0000
WREG15 001E Working Register 15 0800
SPLIM 0020 Stack Pointer Limit Value Register xxxx
PCL 002E Program Counter Low Word Register 0000
PCH 0030 — — — — — — — — Program Counter Register High Byte 0000
TBLPAG 0032 — — — — — — — — Table Memory Page Address Register 0000
PSVPAG 0034 — — — — — — — — Program Space Visibility Page Address Register 0000
RCOUNT 0036 Repeat Loop Counter Register xxxx
SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 — — — — — — — — — — — — IPL3 PSV — — 0000
DISICNT 0052 — — Disable Interrupts Counter Register xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS39897C-page 43
TABLE 4-4: ICN REGISTER MAP
DS39897C-page 44
PIC24FJ256GB110 FAMILY
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
CNPD1 0054 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CN7PDE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE 0000
CNPD2 0056 CN31PDE CN30PDE CN29PDE CN28PDE CN27PDE CN26PDE CN25PDE CN24PDE CN23PDE CN22PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN18PDE CN17PDE CN16PDE 0000
CNPD3 0058 CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2) CN32PDE 0000
CNPD4 005A CN63PDE CN62PDE CN61PDE CN60PDE CN59PDE CN58PDE CN57PDE(1) CN56PDE CN55PDE CN54PDE CN53PDE CN52PDE CN51PDE CN50PDE CN49PDE CN48PDE(2) 0000
CNPD5 005C CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1) — — CN71PDE CN70PDE(1) CN69PDE CN68PDE CN67PDE(1) CN66PDE(1) CN65PDE CN64PDE 0000
(2)
CNPD6 005E — — — — — — — — — — — — — CN82PDE(2) CN81PDE(2) CN80PDE(2) 0000
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 CN31IE CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE(1) CN20IE(1) CN19IE(1) CN18IE CN17IE CN16IE 0000
CNEN3 0064 CN47IE(1) CN46IE(2) CN45IE(1) CN44IE(1) CN43IE(1) CN42IE(1) CN41IE(1) CN40IE(2) CN39IE(2) CN38IE(2) CN37IE(2) CN36IE(2) CN35IE(2) CN34IE(2) CN33IE(2) CN32IE 0000
CNEN4 0066 CN63IE CN62IE CN61IE CN60IE CN59IE CN58IE CN57IE(1) CN56IE CN55IE CN54IE CN53IE CN52IE CN51IE CN50IE CN49IE CN48IE(2) 0000
CNEN5 0068 CN79IE(2) CN78IE(1) CN77IE(1) CN76IE(2) CN75IE(2) CN74IE(1) — — CN71IE CN70IE(1) CN69IE CN68IE CN67IE(1) CN66IE(1) CN65IE CN64IE 0000
CNEN6(2) 006A — — — — — — — — — — — — — CN82IE(2) CN81IE(2) CN80IE(2) 0000
CNPU1 006C CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006E CN31PUE CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN17PUE CN16PUE 0000
CNPU3 0070 CN47PUE(1) CN46PUE(2) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2) CN32PUE 0000
CNPU4 0072 CN63PUE CN62PUE CN61PUE CN60PUE CN59PUE CN58PUE CN57PUE(1) CN56PUE CN55PUE CN54PUE CN53PUE CN52PUE CN51PUE CN50PUE CN49PUE CN48PUE(2) 0000
CNPU5 0074 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1) — — CN71PUE CN70PUE(1) CN69PUE CN68PUE CN67PUE(1) CN66PUE(1) CN65PUE CN64PUE 0000
CNPU6(2) 0076 — — — — — — — — — — — — — CN82PUE(2) CN81PUE(2) CN80PUE(2) 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Unimplemented on 64-pin devices; read as ‘0’.
2: Unimplemented on 64-pin and 80-pin devices; read as ‘0’.
2009 Microchip Technology Inc.
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP
2009 Microchip Technology Inc.
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
PIC24FJ256GB110 FAMILY
IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444
IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440
IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444
IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044
IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 4444
IPC5 00AE — IC8IP2 IC8IP1 IC8IP0 — IC7IP2 IC7IP1 IC7IP0 — — — — — INT1IP2 INT1IP1 INT1IP0 4404
IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440
IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444
IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 0044
IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 4440
IPC10 00B8 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 4444
IPC11 00BA — — — — — — — — — PMPIP2 PMPIP1 PMPIP0 — OC8IP2 OC8IP1 OC8IP0 0044
IPC12 00BC — — — — — MI2C2P2 MI2C2P1 MI2C2P0 — SI2C2P2 SI2C2P1 SI2C2P0 — — — — 0440
IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440
IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400
IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440
IPC18 00C8 — — — — — — — — — — — — — LVDIP2 LVDIP1 LVDIP0 0004
IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040
IPC20 00CC — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — 4440
DS39897C-page 45
IPC21 00CE — U4ERIP2 U4ERIP1 U4ERIP0 — USB1IP2 USB1IP1 USB1IP0 — MI2C3P2 MI2C3P1 MI2C3P0 — SI2C3P2 SI2C3P1 SI2C3P0 4444
IPC22 00D0 — SPI3IP2 SPI3IP1 SPI3IP0 — SPF3IP2 SPF3IP1 SPF3IP0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 4444
IPC23 00D2 — — — — — — — — — IC9IP2 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 0044
INTTREG 00E0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6: TIMER REGISTER MAP
DS39897C-page 46
PIC24FJ256GB110 FAMILY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC1BUF 0144 Input Capture 1 Buffer Register 0000
IC1TMR 0146 Timer Value 1 Register xxxx
IC2CON1 0148 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC2BUF 014C Input Capture 2 Buffer Register 0000
IC2TMR 014E Timer Value 2 Register xxxx
IC3CON1 0150 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC3CON2 0152 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC3BUF 0154 Input Capture 3 Buffer Register 0000
IC3TMR 0156 Timer Value 3 Register xxxx
IC4CON1 0158 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
PIC24FJ256GB110 FAMILY
IC4BUF 015C Input Capture 4 Buffer Register 0000
IC4TMR 015E Timer Value 4 Register xxxx
IC5CON1 0160 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC5CON2 0162 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC5BUF 0164 Input Capture 5 Buffer Register 0000
IC5TMR 0166 Timer Value 5 Register xxxx
IC6CON1 0168 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC6CON2 016A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC6BUF 016C Input Capture 6 Buffer Register 0000
IC6TMR 016E Timer Value 6 Register xxxx
IC7CON1 0170 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC7CON2 0172 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC7BUF 0174 Input Capture 7 Buffer Register 0000
IC7TMR 0176 Timer Value 7 Register xxxx
IC8CON1 0178 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC8CON2 017A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC8BUF 017C Input Capture 8 Buffer Register 0000
IC8TMR 017E Timer Value 8 Register xxxx
IC9CON1 0180 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
DS39897C-page 47
IC9CON2 0182 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC9BUF 0184 Input Capture 9 Buffer Register 0000
IC9TMR 0186 Timer Value 9 Register xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8: OUTPUT COMPARE REGISTER MAP
DS39897C-page 48
PIC24FJ256GB110 FAMILY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC1RS 0194 Output Compare 1 Secondary Register 0000
OC1R 0196 Output Compare 1 Register 0000
OC1TMR 0198 Timer Value 1 Register xxxx
OC2CON1 019A — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC2CON2 019C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC2RS 019E Output Compare 2 Secondary Register 0000
OC2R 01A0 Output Compare 2 Register 0000
OC2TMR 01A2 Timer Value 2 Register xxxx
OC3CON1 01A4 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC3CON2 01A6 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC3RS 01A8 Output Compare 3 Secondary Register 0000
OC3R 01AA Output Compare 3 Register 0000
OC3TMR 01AC Timer Value 3 Register xxxx
OC4CON1 01AE — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC4CON2 01B0 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC4RS 01B2 Output Compare 4 Secondary Register 0000
OC4R 01B4 Output Compare 4 Register 0000
OC4TMR 01B6 Timer Value 4 Register xxxx
OC5CON1 01B8 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC5CON2 01BA FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC5RS 01BC Output Compare 5 Secondary Register 0000
OC5R 01BE Output Compare 5 Register 0000
OC5TMR 01C0 Timer Value 5 Register xxxx
OC6CON1 01C2 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC6CON2 01C4 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC6RS 01C6 Output Compare 6 Secondary Register 0000
OC6R 01C8 Output Compare 6 Register
2009 Microchip Technology Inc.
0000
OC6TMR 01CA Timer Value 6 Register xxxx
OC7CON1 01CC — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC7CON2 01CE FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC7RS 01D0 Output Compare 7 Secondary Register 0000
OC7R 01D2 Output Compare 7 Register 0000
OC7TMR 01D4 Timer Value 7 Register xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8: OUTPUT COMPARE REGISTER MAP (CONTINUED)
2009 Microchip Technology Inc.
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
OC8CON1 01D6 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC8RS 01DA Output Compare 8 Secondary Register 0000
OC8R 01DC Output Compare 8 Register 0000
OC8TMR 01DE Timer Value 8 Register xxxx
OC9CON1 01E0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000
OC9CON2 01E2 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC9RS 01E4 Output Compare 9 Secondary Register 0000
OC9R 01E6 Output Compare 9 Register 0000
OC9TMR 01E8 Timer Value 9 Register xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ256GB110 FAMILY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
I2C3CON 0276 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C3STAT 0278 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
I2C3ADD 027A — — — — — — Address Register 0000
I2C3MSK 027C — — — — — — Address Mask Register 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10: UART REGISTER MAPS
DS39897C-page 50
PIC24FJ256GB110 FAMILY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — Transmit Register xxxx
U1RXREG 0226 — — — — — — — Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler Register 0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — Transmit Register xxxx
U2RXREG 0236 — — — — — — — Receive Register 0000
U2BRG 0238 Baud Rate Generator Prescaler Register 0000
U3MODE 0250 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U3STA 0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U3TXREG 0254 — — — — — — — Transmit Register xxxx
U3RXREG 0256 — — — — — — — Receive Register 0000
U3BRG 0258 Baud Rate Generator Prescaler Register 0000
U4MODE 02B0 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U4STA 02B2 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U4TXREG 02B4 — — — — — — — Transmit Register xxxx
U4RXREG 02B6 — — — — — — — Receive Register 0000
U4BRG 02B8 Baud Rate Generator Prescaler Register 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000
2009 Microchip Technology Inc.
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7(2) Bit 6(2) Bit 5(2) Bit 4(2) Bit 3(2) Bit2(2) Bit 1(2) Bit 0(2)
Name Resets
TRISA 02C0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 36FF
PORTA 02C2 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx
LATA 02C4 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
ODCA 02C6 ODA15 ODA14 — — — ODA10 ODA9 — ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: PORTA and all associated bits are unimplemented on 64-pin devices and read as ‘0’. Bits are available on 80-pin and 100-pin devices only, unless otherwise noted.
2: Bits are implemented on 100-pin devices only; otherwise read as ‘0’.
PIC24FJ256GB110 FAMILY
ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000
Legend: Reset values are shown in hexadecimal.
TRISC 02D0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F01E
PORTC 02D2 RC15(3,4) RC14 RC13 RC12(3) — — — — — — — RC4 RC3 RC2 RC1 — xxxx
LATC 02D4 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx
ODCC 02D6 ODC15 ODC14 ODC13 ODC12 — — — — — — — ODC4 ODC3 ODC2 ODC1 — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: Bits are unimplemented on 64-pin and 80-pin devices; read as ‘0’.
2: Bits are unimplemented on 64-pin devices; read as ‘0’.
3: RC12 and RC15 are only available when the Primary Oscillator is disabled or when EC mode is selected (POSCMD<1:0> Configuration bits = 11 or 00); otherwise read as ‘0’.
4: RC15 is only available when the POSCMD<1:0> Configuration bits = 11 or 00 and the OSCIOFN Configuration bit = 1.
TRISD 02D8 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF
PORTD 02DA RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
LATD 02DC LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
ODCD 02DE ODD15 ODD14 ODD13 ODD12 ODD11 ODD10 ODD9 ODD8 ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: Bits are unimplemented on 64-pin devices; read as ‘0’.
DS39897C-page 52
PIC24FJ256GB110 FAMILY
TABLE 4-16: PORTE REGISTER MAP
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 8(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TRISE 02E0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF
PORTE 02E2 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
LATE 02E4 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
ODCE 02E6 — — — — — — ODE9 ODE8 ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 ODE0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: Bits are unimplemented on 64-pin devices; read as ‘0’.
TRISF 02E8 — — TRISF13 TRISF12 — — — — — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF
PORTF 02EA — — RF13 RF12 — — — — — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx
LATF 02EC — — LATF13 LATF12 — — — — — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx
ODCF 02EE — — ODF13 ODF12 — — — — — — ODF5 ODF4 ODF3 ODF2 ODF1 ODF0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: Bits are unimplemented on 64-pin and 80-pin devices; read as ‘0’.
2: Bits are unimplemented on 64-pin devices; read as ‘0’.
TRISG 02F0 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF
PORTG 02F2 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx
LATG 02F4 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx
ODCG 02F6 ODG15 ODG14 ODG13 ODG12 — — ODG9 ODG8 ODG7 ODG6 — — ODG3 ODG2 ODG1 ODG0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: Bits unimplemented on 64-pin and 80-pin devices; read as ‘0’.
2: Bits unimplemented on 64-pin devices; read as ‘0’.
2009 Microchip Technology Inc.
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
PIC24FJ256GB110 FAMILY
ADC1BUFE 031C ADC Data Buffer 14 xxxx
ADC1BUFF 031E ADC Data Buffer 15 xxxx
AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000
AD1CON2 0322 VCFG2 VCFG1 VCFG0 r — CSCNA — — BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000
AD1CON3 0324 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
AD1CHS 0328 CH0NB — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1PCFGH 032A — — — — — — — — — — — — — — PCFG17 PCFG16 0000
AD1PCFGL 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
Legend: — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal.
CTMUCON 033C CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000
CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS39897C-page 53
TABLE 4-22: USB OTG REGISTER MAP
DS39897C-page 54
PIC24FJ256GB110 FAMILY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
U1OTGIR 0480 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000
U1OTGIE 0482 — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000
U1OTGSTAT 0484 — — — — — — — — ID — LSTATE — SESVD SESEND — VBUSVD 0000
U1OTGCON 0486 — — — — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000
U1PWRC 0488 — — — — — — — — UACTPND — — USLPGRD — — USUSPND USBPWR 0000
U1IR 048A(1) — — — — — — — — STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF 0000
— — — — — — — — STALLIF ATTACHIF(1) RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF(1) 0000
(1)
U1IE 048C — — — — — — — — STALLIE — RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE 0000
— — — — — — — — STALLIE ATTACHIE(1) RESUMEIE IDLEIE TRNIE SOFIE UERRIE DETACHIE(1) 0000
U1EIR 048E(1) — — — — — — — — BTSEF — DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0000
— — — — — — — — BTSEF — DMAEF BTOEF DFN8EF CRC16EF EOFEF(1) PIDEF 0000
U1EIE 0490(1) — — — — — — — — BTSEE — DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0000
— — — — — — — — BTSEE — DMAEE BTOEE DFN8EE CRC16EE EOFEE(1) PIDEE 0000
U1STAT 0492 — — — — — — — — ENDPT3 ENDPT2 ENDPT1 ENDPT0 DIR PPBI — — 0000
U1CON 0494(1) — — — — — — — — — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN 0000
— — — — — — — — JSTATE(1) SE0 TOKBUSY RESET HOSTEN RESUME PPBRST SOFEN(1) 0000
U1ADDR 0496 — — — — — — — — LSPDEN(1) USB Device Address (DEVADDR) Register 0000
U1BDTP1 0498 — — — — — — — — Buffer Descriptor Table Base Address Register — 0000
U1FRML 049A — — — — — — — — Frame Count Register Low Byte 0000
U1FRMH 049C — — — — — — — — Frame Count Register High Byte 0000
U1TOK(2) 049E — — — — — — — — PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0 0000
U1SOF(2) 04A0 — — — — — — — — Start-Of-Frame Count Register 0000
U1CNFG1 04A6 — — — — — — — — UTEYE UOEMON — USBSIDL — — PPB1 PPB0 0000
U1CNFG2 04A8 — — — — — — — — — — — PUVBUS EXTI2CEN UVBUSDIS UVCMPDIS UTRDIS 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Alternate register or bit definitions when the module is operating in Host mode.
2: This register is available in Host mode only.
2009 Microchip Technology Inc.
TABLE 4-22: USB OTG REGISTER MAP (CONTINUED)
2009 Microchip Technology Inc.
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
U1EP0 04AA — — — — — — — — LSPD(1) RETRYDIS(1) — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP1 04AC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP2 04AE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP3 04B0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP4 04B2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP5 04B4 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP6 04B6 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP7 04B8 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP8 04BA — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP9 04BC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP10 04BE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP11 04C0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP12 04C2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP13 04C4 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1EP14 04C6 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
PIC24FJ256GB110 FAMILY
U1EP15 04C8 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
U1PWMRRS 04CC USB Power Supply PWM Duty Cycle Register USB Power Supply PWM Period Register 0000
U1PWMCON 04CE PWMEN — — — — — PWMPOL CNTEN — — — — — — — — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Alternate register or bit definitions when the module is operating in Host mode.
2: This register is available in Host mode only.
PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 0000
PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000
PMADDR 0604 CS2 CS1 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0000
PMDOUT1 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000
PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000
PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000
PMDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000
PMAEN 060C PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000
DS39897C-page 55
PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
DS39897C-page 56
PIC24FJ256GB110 FAMILY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
CMSTAT 0630 CMIDL — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT 0000
CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000
CM1CON 0634 CEN COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM2CON 0636 CEN COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
CM3CON 0638 CEN COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0040
CRCXOR 0642 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 — 0000
CRCDAT 0644 CRC Data Input Register 0000
CRCWDAT 0646 CRC Result Register 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-27: PERIPHERAL PIN SELECT REGISTER MAP
2009 Microchip Technology Inc.
File All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
PIC24FJ256GB110 FAMILY
RPINR20 06A8 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 3F3F
RPINR21 06AA — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 3F3F
RPINR22 06AC — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 3F3F
RPINR23 06AE — — — — — — — — — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 003F
RPINR27 06B6 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 3F3F
RPINR28 06B8 — — SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 — — SDI3R5 SDI3R4 SDI3R3 SDI3R2 SDI3R1 SDI3R0 3F3F
RPINR29 06BA — — — — — — — — — — SS3R5 SS3R4 SS3R3 SS3R2 SS3R1 SS3R0 003F
RPOR0 06C0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000
RPOR1 06C2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000
RPOR2 06C4 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000
RPOR3 06C6 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000
RPOR4 06C8 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000
RPOR5 06CA — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000
RPOR6 06CC — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000
RPOR7 06CE — — RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000
RPOR8 06D0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 0000
RPOR9 06D2 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 0000
RPOR10 06D4 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000
RPOR11 06D6 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 0000
DS39897C-page 57
RPOR12 06D8 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 0000
RPOR13 06DA — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 0000
RPOR14 06DC — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 0000
RPOR15 06DE — — RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2) — — RP30R5 RP30R4 RP30R3 RP30R2 RP30R1 RP30R0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Bits are unimplemented on 64-pin devices; read as ‘0’.
2: Bits are unimplemented on 64-pin and 80-pin devices; read as ‘0’.
TABLE 4-28: SYSTEM REGISTER MAP
DS39897C-page 58
PIC24FJ256GB110 FAMILY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
RCON 0740 TRAPR IOPUWR — — — — CM PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN Note 2
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 CPDIV1 CPDIV0 — — — — — — 0100
OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000
REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The Reset value of the RCON register is dependent on the type of Reset event. See Section 6.0 “Resets” for more information.
2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 8.0 “Oscillator Configuration” for more information.
NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY 0766 — — — — — — — — NVMKEY Register<7:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD 0000
PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCMD — — — U3MD I2C3MD I2C2MD — 0000
PMD4 0776 — — — — — — — — — UPWMMD U4MD — REFOMD CTMUMD LVDMD USB1MD 0000
PMD5 0778 — — — — — — — IC9MD — — — — — — — OC9MD 0000
PMD6 077A — — — — — — — — — — — — — — — SPI3MD 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
4.2.5 SOFTWARE STACK 4.3 Interfacing Program and Data
In addition to its use as a working register, the W15 Memory Spaces
register in PIC24F devices is also used as a Software The PIC24F architecture uses a 24-bit wide program
Stack Pointer. The pointer always points to the first space and 16-bit wide data space. The architecture is
available free word and grows from lower to higher also a modified Harvard scheme, meaning that data
addresses. It pre-decrements for stack pops and can also be present in the program space. To use this
post-increments for stack pushes, as shown in data successfully, it must be accessed in a way that
Figure 4-4. Note that for a PC push during any CALL preserves the alignment of information in both spaces.
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear. Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
Note: A PC push during exception processing accessed during operation:
will concatenate the SRL register to the
• Using table instructions to access individual bytes
MSB of the PC prior to the push.
or words anywhere in the program space
The Stack Pointer Limit Value register (SPLIM), associ- • Remapping a portion of the program space into
ated with the Stack Pointer, sets an upper address the data space (program space visibility)
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM<0> is Table instructions allow an application to read or write
forced to ‘0’ because all stack operations must be to small areas of the program memory. This makes the
word-aligned. Whenever an EA is generated using method ideal for accessing data tables that need to be
W15 as a source or destination pointer, the resulting updated from time to time. It also allows access to all
address is compared with the value in SPLIM. If the bytes of the program word. The remapping method
contents of the Stack Pointer (W15) and the SPLIM reg- allows an application to access a large block of data on
ister are equal, and a push operation is performed, a a read-only basis, which is ideal for look ups from a
stack error trap will not occur. The stack error trap will large table of static data. It can only access the least
occur on a subsequent push operation. Thus, for significant word of the program word.
example, if it is desirable to cause a stack error trap
4.3.1 ADDRESSING PROGRAM SPACE
when the stack grows beyond address 2000h in RAM,
initialize the SPLIM with the value, 1FFEh. Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
Similarly, a Stack Pointer underflow (stack error) trap is
needed to create a 23-bit or 24-bit program address
generated when the Stack Pointer address is found to
from 16-bit data registers. The solution depends on the
be less than 0800h. This prevents the stack from
interface method to be used.
interfering with the Special Function Register (SFR)
space. For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
A write to the SPLIM register should not be immediately
region within the program space. This is concatenated
followed by an indirect read operation using W15.
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit of
FIGURE 4-4: CALL STACK FRAME TBLPAG is used to determine if the operation occurs in
0000h the user memory (TBLPAG<7> = 0) or the configuration
15 0
memory (TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility Page Address register (PSVPAG) is used to
Stack Grows Towards
Higher Address
23 Bits
EA 1/0
8 Bits 16 Bits
24 Bits
Select
1 EA 0
Program Space Visibility(1)
(Remapping)
0 PSVPAG
8 Bits 15 Bits
23 Bits
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of
data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the
configuration memory space.
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
PSV Area
...while the lower 15
bits of the EA specify
an exact address
FFFFh within the PSV area.
This corresponds
exactly to the same
lower 15 bits of the
actual program space
800000h
address.
24 Bits
Using
Program 0 Program Counter 0
Counter
Working Reg EA
User/Configuration Byte
Space Select 24-Bit EA Select
#define NUM_INSTRUCTION_PER_ROW 64
unsigned int offset;
unsigned int i;
unsigned long progAddr = 0xXXXXXX; // Address of row to write
unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write
MOV #LOW_WORD, W2 ;
MOV #HIGH_BYTE, W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
Brown-out BOR
Reset
Trap Conflict
Illegal Opcode
Configuration Mismatch
Uninitialized W Register
Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.
7.3 Interrupt Control and Status The INTTREG register contains the associated inter-
Registers rupt vector number and the new CPU interrupt priority
level, which are latched into the Vector Number
The PIC24FJ256GB110 family of devices implements (VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit
a total of 37 registers for the interrupt controller: fields in the INTTREG register. The new interrupt
• INTCON1 priority level is the priority of the pending interrupt.
• INTCON2 The interrupt sources are assigned to the IFSx, IECx
• IFS0 through IFS5 and IPCx registers in the order of their vector numbers,
as shown in Table 7-2. For example, the INT0 (External
• IEC0 through IEC5
Interrupt 0) is shown as having a vector number and a
• IPC0 through IPC23 (except IPC14 and IPC17) natural order priority of 0. Thus, the INT0IF status bit is
• INTTREG found in IFS0<0>, the INT0IE enable bit in IEC0<0>
Global interrupt control functions are controlled from and the INT0IP<2:0> priority bits in the first position of
INTCON1 and INTCON2. INTCON1 contains the Inter- IPC0 (IPC0<2:0>).
rupt Nesting Disable (NSTDIS) bit, as well as the Although they are not specifically part of the interrupt
control and status flags for the processor trap sources. control hardware, two of the CPU Control registers con-
The INTCON2 register controls the external interrupt tain bits that control interrupt functionality. The ALU
request signal behavior and the use of the Alternate STATUS register (SR) contains the IPL<2:0> bits
Interrupt Vector Table. (SR<7:5>). These indicate the current CPU interrupt
The IFSx registers maintain all of the interrupt request priority level. The user may change the current CPU
flags. Each source of interrupt has a status bit which is priority level by writing to the IPL bits.
set by the respective peripherals, or an external signal, The CORCON register contains the IPL3 bit, which
and is cleared via software. together with IPL<2:0>, indicates the current CPU
The IECx registers maintain all of the interrupt enable priority level. IPL3 is a read-only bit so that trap events
bits. These control bits are used to individually enable cannot be masked by the user software.
interrupts from the peripherals or external signals. All interrupt registers are described in Register 7-1
The IPCx registers are used to set the interrupt priority through Register 7-39, in the following pages.
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn
pin. See Section 10.4 “Peripheral Pin Select” for more information.
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn
pin. See Section 10.4 “Peripheral Pin Select” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn
pin. See Section 10.4 “Peripheral Pin Select” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC24FJ256GB110 Family
REFO
PLLDIV<2:0> CPDIV<1:0>
8 MHz
Postscaler
CLKDIV<10:8> FRC
CLKO
Postscaler
CPU
LPRC LPRC
Oscillator 31 kHz (nominal)
SOSCEN
Enable
SOSCI Oscillator Clock Control Logic
Fail-Safe
Clock
Monitor
WDT, PWRT
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL clock mode is selected.
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL clock mode is selected.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
2: This setting is not allowed while the USB module is enabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range, and may not be monotonic.
PLLDIV<2:0>
48 MHz Clock
FNOSC<2:0> 12 for USB Module
111 PLLDIS
Input from 10 2
110
POSC 6
Prescaler
101
5 4 MHz 96 MHz
PLL
100
Input from 4
FRC 011 PLL 8
3 11
010 PLL Output
Prescaler
(4 MHz or 2 32 MHz 4
8 MHz) 001 10 for System Clock
1
PLL
000 3 2 01
1
00
CPDIV<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIO Module 1
Output Data
Read TRIS 0
WR TRIS CK
TRIS Latch
D Q
WR LAT +
CK
WR PORT
Data Latch
Read LAT
Input Data
Read PORT
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TCKPS<1:0>
SOSCO/ TON 2
1x
T1CK
Gate Prescaler
SOSCEN Sync 01 1, 8, 64, 256
SOSCI
TCY 00
TGATE
TGATE TCS
1 Q D
Set T1IF
0 Q CK
0
Reset
TMR1
1 Sync
Comparator TSYNC
Equal
PR1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
TCKPS<1:0>
T2CK TON 2
1x
(T4CK)
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
TGATE TGATE(2)
TCS(2)
1 Q D
Set T3IF (T5IF)
Q CK
0
PR3 PR2
(PR5) (PR4)
MSB LSB
TMR3 TMR2
Sync
Reset (TMR5) (TMR4)
16
(1)
Read TMR2 (TMR4)
Write TMR2 (TMR4)(1)
16
TMR3HLD 16
(TMR5HLD)
Data Bus<15:0>
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
3: The ADC Event Trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode.
TCKPS<1:0>
TON 2
T2CK 1x
(T4CK)
Gate Prescaler
Sync 01 1, 8, 64, 256
TGATE 00
TCY TCS(1)
1 Q D TGATE(1)
Set T2IF (T4IF) Q CK
0
Reset
TMR2 (TMR4) Sync
Comparator
Equal
PR2 (PR4)
Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
TCKPS<1:0>
T3CK TON 2
Sync 1x
(T5CK)
Prescaler
01 1, 8, 64, 256
TGATE 00
TCY TCS(1)
1 Q D TGATE(1)
Set T3IF (T5IF) Q CK
0
Reset
TMR3 (TMR5)
PR3 (PR5)
Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
2: The ADC Event Trigger is available only on Timer3.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see
Section 10.4 “Peripheral Pin Select”.
3: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral
Pin Select” for more information.
3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
ICTSEL<2:0>
Clock Increment 16
IC Clock Select ICxTMR 4-Level FIFO Buffer
Sources 16
Trigger and
Sync Logic 16
Reset
Trigger and ICxBUF
Sync Sources
SYNCSEL<4:0>
TRIGGER
ICOV, ICBNE System Bus
Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select”.
Note 1: Use these inputs as trigger sources only and never as sync sources.
OCMx
OCxCON1 OCINV
OCTRIS
OCTSELx
OCxCON2 FLTOUT
SYNCSELx
FLTTRIEN
TRIGSTAT
FLTMD
TRIGMODE
ENFLT0
OCTRIG OCxR OCFLT0
OCx Interrupt
Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
OCxCON1
OCMx
OCxCON2 OCINV
OCTSELx OCTRIS
SYNCSELx OCxR FLTOUT
TRIGSTAT FLTTRIEN
TRIGMODE FLTMD
OCTRIG Rollover/Reset ENFLT0
OCFLT0
OCxR buffer
OCx Pin
Comparator Match
Clock Increment
OC Clock Event
Select
Sources
OCxTMR OC Output and
Rollover Fault Logic
Reset
Comparator OCFA/OCFB
Match Event Match
Trigger and Event
Trigger and
Sync Sources Sync Logic
OCxRS buffer
Rollover/Reset
OCxRS
OCx Interrupt
Reset
Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
log10 (F PWM
FCY
)
• (Timer Prescale Value)
bits
Maximum PWM Resolution (bits) =
log10(2)
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz
Timer Prescaler Ratio 8 1 1 1 1 1 1
Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz
Timer Prescaler Ratio 8 1 1 1 1 1 1
Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select”.
2: OCFA pin controls the OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and
OCxRS are double-buffered only in PWM modes.
Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent
SYNCSEL setting.
2: Use these inputs as trigger sources only and never as sync sources.
Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent
SYNCSEL setting.
2: Use these inputs as trigger sources only and never as sync sources.
Transfer Transfer
SPIxBUF
16
Internal Data Bus
Transfer Transfer
SPIxBUF
16
Internal Data Bus
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4
“Peripheral Pin Select” for more information.
Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4
“Peripheral Pin Select” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
Select” for more information.
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
Select” for more information.
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select”
for more information.
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
Select” for more information.
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin
Select” for more information.
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select”
for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
SDOx SDIx
Serial Clock
SCKx SCKx SPIx Buffer
SPIx Buffer
(SPIxBUF)(2) (SPIxBUF)(2)
SSx(1)
PROCESSOR 1 (SPI Enhanced Buffer Master) PROCESSOR 2 (SPI Enhanced Buffer Slave)
SDOx SDIx
SSx(1) SSx(1)
PIC24F PROCESSOR 2
(SPI Master, Frame Master)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
PIC24F PROCESSOR 2
(SPI Master, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
PIC24F PROCESSOR 2
(SPI Slave, Frame Master)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync.
Pulse
PIC24F PROCESSOR 2
(SPI Slave, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSB
I2CxMSK
Write Read
I2CxADD
Read
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
Write
Read
TCY/2
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D/A P S R/W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
IrDA®
Note: The UART inputs and outputs must all be assigned to available RPn pins before use. Please see
Section 10.4 “Peripheral Pin Select” for more information.
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select” for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select” for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin.
See Section 10.4 “Peripheral Pin Select” for more information.
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin.
See Section 10.4 “Peripheral Pin Select” for more information.
Full-Speed Pull-up
Host Pull-down 48 MHz USB Clock
D+(1)
Registers
Transceiver and
Control
Interface
D-(1)
Host Pull-down
USBID(1) USB
SIE
VMIO(1)
VPIO(1)
DMH(1)
DMLN(1)
DPLN(1)
RCV(1)
System
USBOEN(1)
RAM
VBUSON(1)
SRP Charge
USB
VBUS Voltage
Comparators
SRP Discharge
USB 3.3V
VUSB Regulator
Transceiver Power 3.3V
VCMPST1(1)
VCMPST2(1)
VBUSST(1) VBUS
Boost
Assist
VCPCON(1)
Note 1: Pins are multiplexed with digital I/O and other device features.
VSS
1.5 k
D+
D-
FIGURE 18-4: SELF-POWER ONLY
Many USB applications will likely have several different VSELF VDD
sets of power requirements and configuration. The ~3.3V
most common power modes encountered are:
VUSB
• Bus Power Only,
• Self-Power Only and 100 k VSS
• Dual Power with Self-Power Dominance.
Bus Power Only mode (Figure 18-3) is effectively the
simplest method. All power for the application is drawn
from the USB.
FIGURE 18-5: DUAL POWER EXAMPLE
To meet the inrush current requirements of the USB 2.0
Specification, the total effective capacitance appearing 100 k
Attach Sense
across VBUS and ground must be no more than 10 F. VBUS
In the USB Suspend mode, devices must consume no 3.3V
VBUS VDD
more than 2.5 mA from the 5V VBUS line of the USB ~5V
cable. During the USB Suspend mode, the D+ or D- Low IQ
pull-up resistor must remain active, which will consume Regulator
VUSB
some of the allowed suspend current. 100 k
In Self-Power Only mode (Figure 18-4), the USB VSELF VSS
~3.3V
application provides its own power, with very little
power being pulled from the USB. Note that an attach
indication is added to indicate when the USB has been
connected and the host is actively powering VBUS.
0.1 µF,
2 k 3.3V
150 µF
A/D pin
Micro A/B 2 k
Connector
VBUS VBUS
D+ D+
D- D-
ID ID
GND VSS
Micro A/B
Connector 4.7 µF 40 k
VBUS VBUS
D+ D+
D- D-
ID ID
GND VSS
Legend: VUSB – Voltage applied to the VUSB pin in volts (3.0V to 3.6V).
PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC® microcontroller that are a value
of ‘0’.
PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic.
LCABLE – Length (in meters) of the USB cable. The USB 2.0 Specification requires that full-speed
applications use cables no longer than 5m.
IPULLUP – Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB
cable.
EP15 Tx Odd
EP15 Tx Odd Descriptor
Descriptor
Mode 3
Mode 0 Mode 1 Mode 2
Endpoint (Ping-Pong on all other EPs,
(No Ping-Pong) (Ping-Pong on EP0 Out) (Ping-Pong on all EPs)
except EP0)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
ATTACHIF
ATTACHIE
RESUMEIF
RESUMEIE
IDLEIF
IDLEIE
TRNIF
TRNIE
Second Level (USB Error) Interrupts
SOFIF
SOFIE
BTSEF
BTSEE URSTIF (DETACHIF) Set USB1IF
DMAEF URSTIE (DETACHIE)
DMAEE
BTOEF
BTOEE (UERRIF)
DFN8EF UERRIE
DFN8EE
IDIF
CRC16EF
IDIE
CRC16EE
T1MSECIF
CRC5EF (EOFEF) TIMSECIE
CRC5EE (EOFEE)
LSTATEIF
PIDEF
LSTATEIE
PIDEE
ACTVIF
ACTVIE
SESVDIF
SESVDIE
SESENDIF
SESENDIE
VBUSVDIF
VBUSVDIE
Top Level (USB OTG) Interrupts
Control Transfer(1)
1 ms Frame
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical
control transfers will spread across multiple frames.
18.4 Device Mode Operation 5. Enable the USB module by setting the USBEN
bit (U1CON<0>).
The following section describes how to perform a com-
6. Set the OTGEN bit (U1OTGCON<2>) to enable
mon Device mode task. In Device mode, USB transfers
OTG operation.
are performed at the transfer level. The USB module
automatically performs the status phase of the transfer. 7. Enable the endpoint zero buffer to receive the
first setup packet by setting the EPRXEN and
18.4.1 ENABLING DEVICE MODE EPHSHK bits for Endpoint 0 (U1EP0<3,0> = 1).
8. Power up the USB module by setting the
1. Reset the Ping-Pong Buffer Pointers by setting,
USBPWR bit (U1PWRC<0>).
then clearing, the Ping-Pong Buffer Reset bit
PPBRST (U1CON<1>). 9. Enable the D+ pull-up resistor to signal an attach
by setting DPPULUP (U1OTGCON<7>).
2. Disable all interrupts (U1IE and U1EIE = 00h).
3. Clear any existing interrupt flags by writing FFh
to U1IR and U1EIR.
4. Verify that VBUS is present (non OTG devices
only).
REGISTER 18-3: U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R-0, HSC U-0 R-0, HSC U-0 R-0, HSC R-0, HSC U-0 R-0, HSC
ID — LSTATE — SESVD SESEND — VBUSVD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These bits are only used in Host mode; do not use in Device mode.
Note 1: Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON<3,0> and U1OTGCON<2>)
are all cleared.
R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC U-0 U-0
ENDPT3 ENDPT2 ENDPT1 ENDPT0 DIR PPBI(1) — —
bit 7 bit 0
Note 1: This bit is only valid for endpoints with available EVEN and ODD BD registers.
R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Host mode only. In Device mode, this bit is unimplemented and read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: All other combinations are reserved and are not to be used.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Never change these bits while the USBPWR bit is set (U1PWRC<0> = 1).
REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits
are always unimplemented and read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Address Bus
Data Bus
Control Lines
PMA<0>
PIC24F PMALL
Parallel Master Port
PMA<1>
PMALH
Up to 16-Bit Address
PMA<13:2> EEPROM
PMA<14>
PMCS1
PMA<15>
PMCS2
PMBE
FIFO
PMRD Microcontroller LCD
PMRD/PMWR
Buffer
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
8-Bit Data
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These bits have no effect when their corresponding pins are used as address lines.
Note 1: These bits have no effect when their corresponding pins are used as address lines.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The WAITB and WAITE bits are ignored whenever WAITM<3:0> = 0000.
2: A single-cycle delay is required between consecutive read and/or write operations.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>)) bit must also be set.
Address Bus
Master PIC24F Slave
Data Bus
PMD<7:0> PMD<7:0> Control Lines
PMCS1 PMCS1
PMRD PMRD
PMWR PMWR
Address Bus
Data Bus
Control Lines
PIC24F PMA<13:0>
PMD<7:0>
PMCS1
PMCS2
Address Bus
PMRD Data Bus
PMWR Control Lines
PIC24F PMA<13:8>
PMD<7:0>
PMA<7:0>
PMCS1
PMALL Multiplexed
Data and
PMRD Address Bus
Control Lines
PMWR
FIGURE 19-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, TWO CHIP SELECTS)
PMD<7:0>
PIC24F PMA<13:8>
PMCS1
PMCS2
PMALL
PMALH Multiplexed
Data and
PMRD Address Bus
PMWR Control Lines
FIGURE 19-10: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)
PMD<7:0> D<7:0>
PMCS1 CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines
FIGURE 19-11: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)
PMD<7:0> D<7:0>
PMBE A0
PMCS1 CE
Address Bus
PMRD OE
Data Bus
PMWR WR
Control Lines
ALMTHDY
Compare Registers ALRMVAL ALWDHR
with Masks
ALMINSEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC Pin
RTCOE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>)) bit must also be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CRCDAT
CRCWDAT
CRCWDAT
Read/Write Bus
Shift Buffer
Data Bit 0 Bit 1 Bit 2 Bit n(2)
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial length n is determined by ([PLEN<3:0>] + 1)
21.1 User Interface To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
21.1.1 DATA INTERFACE allowed to run until the CRCMPT bit is set.
To start serial shifting, a ‘1’ must be written to the Also, to get the correct CRC reading, it will be
CRCGO bit. necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
The module incorporates a FIFO that is 8 deep when
PLEN (CRCCON<3:0>) > 7, and 16 deep, otherwise. If a word is written when the CRCFUL bit is set, the
The data for which the CRC is to be calculated must VWORD Pointer will roll over to 0. The hardware will
first be written into the FIFO. The smallest data element then behave as if the FIFO is empty. However, the con-
that can be written into the FIFO is one byte. For dition to generate an interrupt will not be met; therefore,
example, if PLEN = 5, then the size of the data is no interrupt will be generated (See Section 21.1.2
PLEN + 1 = 6. When loading data, the two MSbs of the “Interrupt Operation”).
data byte are ignored. At least one instruction cycle must pass after a write to
Once data is written into the CRCWDAT MSb (as CRCWDAT before a read of the VWORD bits is done.
defined by PLEN), the value of VWORD
(CRCCON<12:8>) increments by one. When 21.1.2 INTERRUPT OPERATION
CRCGO = 1 and VWORD > 0, a word of data to be When the VWORD<4:0> bits make a transition from a
shifted is moved from the FIFO into the shift engine. value of ‘1’ to ‘0’, an interrupt will be generated. Note
When the data word moves from the FIFO to the shift that the CRC calculation is not complete at this point;
engine, VWORD decrements by one. The serial shifter an additional time of (PLEN + 1)/2 clock cycles is
continues to receive data from the FIFO, shifting until required before the output can be read.
the VWORD reaches 0. The last bit of data will be
shifted through the CRC module (PLEN + 1)/2 clock 21.2 Operation in Power-Saving Modes
cycles after VWORD reaches 0. This is when the
module is completed with the CRC calculation. 21.2.1 SLEEP MODE
Therefore, for a given value of PLEN, it will take If Sleep mode is entered while the module is operating,
(PLEN + 1)/2 * VWORD number of clock cycles to the module will be suspended in its current state until
complete the CRC calculations. clock execution resumes.
When VWORD reaches 8 (or 16), the CRCFUL bit will
be set. When VWORD reaches 0, the CRCMPT bit will 21.2.2 IDLE MODE
be set. To continue full module operation in Idle mode, the
To continually feed data into the CRC engine, the rec- CSIDL bit must be cleared prior to entry into the mode.
ommended mode of operation is to initially “prime” the If CSIDL = 1, the module will behave the same way as
FIFO with a sufficient number of words so no interrupt it does in Sleep mode; pending interrupt events will be
is generated before the next word can be written. Once passed on, even though the module clocks are not
that is done, start the CRC by setting the CRCGO bit to available.
‘1’. From that point onward, the VWORD bits should be
polled. If they read less than 8 or 16, another word can
be written into the FIFO.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
VREF+ VR-
VREF-
Comparator
VINH
VR- VR+
AN0 S/H DAC
VINL
AN1
AN2
10-Bit SAR Conversion Logic
VINH
AN3
AN4
MUX A
Data Formatting
AN5
AN6
VINL
AN7 ADC1BUF0:
ADC1BUFF
AN8
AN9 AD1CON1
AD1CON2
AN10
AD1CON3
AN11 AD1CHS
VINH
MUX B
AD1PCFGL
AN12
AD1PCFGH
AN13 AD1CSSL
VINL
AN14
AN15
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/W-0, HCS
SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE
bit 7 bit 0
Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the
conversion values from the buffer before disabling the module.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1)
10001 = Channel 0 positive input is internal band gap reference (VBG)(2)
10000 = Channel 0 positive input is VBG/2(2)
01111 = Channel 0 positive input is AN15
01110 = Channel 0 positive input is AN14
01101 = Channel 0 positive input is AN13
01100 = Channel 0 positive input is AN12
01011 = Channel 0 positive input is AN11
01010 = Channel 0 positive input is AN10
01001 = Channel 0 positive input is AN9
01000 = Channel 0 positive input is AN8
00111 = Channel 0 positive input is AN7
00110 = Channel 0 positive input is AN6
00101 = Channel 0 positive input is AN5
00100 = Channel 0 positive input is AN4
00011 = Channel 0 positive input is AN3
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 6-5 Unimplemented: Read as ‘0’
bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits
Implemented combinations are identical to those for CHOSB<4:0> (above).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TAD
ADCS = –1
TCY
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
VDD
RIC 250 Sampling RSS 5 k(Typical)
Switch
VT = 0.6V
Rs ANx RSS
CHOLD
VA CPIN ILEAKAGE = DAC capacitance
6-11 pF VT = 0.6V 500 nA = 4.4 pF (Typical)
(Typical)
VSS
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k.
(VINH – VINL)
VR+ – VR-
VR+
VR-
0
1024
1024
1024
Voltage Level
VR- +
VR- +
VR- +
EVPOL<1:0>
CCH<1:0>
CREF
Trigger/Interrupt CEVT
CPOL Logic COE
VIN-
VIN+ C1
CXINB
Input C1OUT
Pin
CXINC Select COUT
Logic
CXIND
EVPOL<1:0>
VBG/2
Trigger/Interrupt CEVT
CPOL Logic COE
VIN-
VIN+ C2
C2OUT
Pin
COUT
EVPOL<1:0>
CXINA
Trigger/Interrupt CEVT
CVREF
CPOL Logic COE
VIN-
VIN+ C3
C3OUT
Pin
COUT
COE
VIN-
VIN+ Cx
Off (Read as ‘0’) CxOUT
Pin
Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare
CEN = 1, CREF = 0, CCH<1:0> = 00 CEN = 1, CREF = 0, CCH<1:0> = 01
COE COE
VIN- VIN-
CXINB CXINC
VIN+ Cx VIN+ Cx
CXINA CxOUT CXINA CxOUT
Pin Pin
Comparator CxIND > CxINA Compare Comparator VBG > CxINA Compare
CEN = 1, CREF = 0, CCH<1:0> = 10 CEN = 1, CREF = 0, CCH<1:0> = 11
COE COE
VIN- VIN-
CXIND VBG/2
VIN+ Cx VIN+ Cx
CXINA CxOUT CXINA CxOUT
Pin Pin
Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare
CEN = 1, CREF = 1, CCH<1:0> = 00 CEN = 1, CREF = 1, CCH<1:0> = 01
COE COE
VIN- VIN-
CXINB CXINC
VIN+ Cx VIN+ Cx
CVREF CxOUT CVREF CxOUT
Pin Pin
Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare
CEN = 1, CREF = 1, CCH<1:0> = 10 CEN = 1, CREF = 1, CCH<1:0> = 11
COE COE
VIN- VIN-
CXIND VBG/2
VIN+ Cx VIN+ Cx
CVREF CxOUT CVREF CxOUT
Pin Pin
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CVRSS = 1
VREF+
AVDD
CVRSS = 0 8R
CVR<3:0>
CVREN R
R
16-to-1 MUX
16 Steps
CVREF
R
R
R
CVRR 8R
CVRSS = 1
VREF-
CVRSS = 0
AVSS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC24F Device
Timer1
CTMU
EDG1 Current Source
EDG2
Output Pulse
A/D Converter
ANx
ANY
CAPP RPR
PIC24F Device
CTMU
CTEDG1 EDG1
Current Source
CTEDG2 EDG2
Output Pulse
A/D Converter
ANx
CAD
RPR
PIC24F Device
CTMU
CTEDG1 EDG1 CTPLS
Current Source
Comparator
C2INB
C2
CDELAY CVREF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If TGEN = 1, the CTEDGx inputs and CTPLS outputs must be assigned to available RPn pins before use.
See Section 10.4 “Peripheral Pin Select” for more information.
Note 1: If TGEN = 1, the CTEDGx inputs and CTPLS outputs must be assigned to available RPn pins before use.
See Section 10.4 “Peripheral Pin Select” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be
modified while programming the device through the JTAG interface.
Note 1: The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be
modified while programming the device through the JTAG interface.
Legend:
R = Readable bit PO = Program-once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
U U R R R R R R
— — FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2
bit 15 bit 8
R R R R R R R R
FAMID1 FAMID0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 7 bit 0
U U U U U U U R
— — — — — — — MAJRV2
bit 15 bit 8
R R U U U R R R
MAJRV1 MAJRV0 — — — DOT2 DOT1 DOT0
bit 7 bit 0
FWPSA WDTPS<3:0>
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
3.00V
2.75V 2.75V
Voltage (VDDCORE)(1)
2.50V PIC24FJXXXGB1XX
2.25V 2.25V
2.00V
16 MHz 32 MHz
Frequency
For frequencies between 16 MHz and 32 MHz, FMAX = (64 MHz/V) * (VDDCORE – 2V) + 16 MHz.
Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCOREVDD3.6V.
Param
Symbol Characteristics Min Typ Max Units Comments
No.
VRGOUT Regulator Output Voltage — 2.5 — V
VBG Internal Band Gap Reference — 1.2 — V
CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm
recommended; < 5 Ohm required.
TVREG Regulator Start-up Time
— 10 — s PMSLP = 1, or any POR or BOR
— 190 — s Wake for sleep when PMSLP = 0
TBG Band Gap Reference Start-up — — 1 ms
Time
Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSCO
VSS
15 pF for OSCO output
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSCI
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS40 OS41
Param
Characteristic Min Typ Max Units Conditions
No.
F20 FRC Accuracy@ 8 MHz(1) -2 — 2 % +25°C, 3.0V VDD 3.6V
-5 — 5 % -40°C TA +85°C,
3.0V VDD 3.6V
F21 LPRC Accuracy @ 31 kHz(2) -20 — 20 % -40°C TA +85°C,
3.0V VDD 3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
2: Change of LPRC frequency as VDD changes.
I/O Pin
(Input)
DI35
DI40
XXXXXXXXXX PIC24FJ256
XXXXXXXXXX GB106-I/
XXXXXXXXXX PT e3
YYWWNNN 0920017
XXXXXXXXXXX PIC24FJ256G
XXXXXXXXXXX B106-I/M4 e3
XXXXXXXXXXX 0910017
YYWWNNN
XXXXXXXXXXXX PIC24FJ256GB
XXXXXXXXXXXX 108-I/PT e3
YYWWNNN 0920017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXXXXXXXX PIC24FJ256GB
XXXXXXXXXXXX 110-I/PT e3
YYWWNNN 0920017
XXXXXXXXXXXX PIC24FJ256GB
XXXXXXXXXXXX 110-I/PF e3
YYWWNNN 0920017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
03/26/09