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The I2C Bus Specifications

The I2C Bus Specifications

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THE I
2
C-BUS SPECIFICATIONVERSION 2.1 JANUARY 2000
document order number: 9398 393 40011
 
2
Philips Semiconductors
The I
2
C-bus specification
CONTENTS
1PREFACE. . . . . . . . . . . . . . . . . . . . . . . . . . .31.1Version 1.0 - 1992. . . . . . . . . . . . . . . . . . . . 31.2Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . . 31.3Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . . 31.4Purchase of Philips I
2
C-bus components . . 32THE I
2
C-BUS BENEFITS DESIGNERSAND MANUFACTURERS. . . . . . . . . . . . . . .42.1Designer benefits . . . . . . . . . . . . . . . . . . . . 42.2Manufacturer benefits. . . . . . . . . . . . . . . . . 63INTRODUCTION TO THE I
2
C-BUSSPECIFICATION . . . . . . . . . . . . . . . . . . . . .64THE I
2
C-BUS CONCEPT . . . . . . . . . . . . . . .65GENERAL CHARACTERISTICS . . . . . . . . .86BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .86.1Data validity . . . . . . . . . . . . . . . . . . . . . . . . 86.2START and STOP conditions. . . . . . . . . . . 97TRANSFERRING DATA. . . . . . . . . . . . . . .107.1Byte format . . . . . . . . . . . . . . . . . . . . . . . . 107.2Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 108ARBITRATION AND CLOCKGENERATION . . . . . . . . . . . . . . . . . . . . . .118.1Synchronization . . . . . . . . . . . . . . . . . . . . 118.2Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 128.3Use of the clock synchronizingmechanism as a handshake. . . . . . . . . . . 139FORMATS WITH 7-BIT ADDRESSES. . . .13107-BIT ADDRESSING . . . . . . . . . . . . . . . . .1510.1Definition of bits in the first byte . . . . . . . . 1510.1.1General call address. . . . . . . . . . . . . . . . . 1610.1.2START byte . . . . . . . . . . . . . . . . . . . . . . . 1710.1.3CBUS compatibility. . . . . . . . . . . . . . . . . . 1811EXTENSIONS TO THE STANDARD-MODE I
2
C-BUS SPECIFICATION . . . . . . .1912FAST-MODE. . . . . . . . . . . . . . . . . . . . . . . .1913Hs-MODE . . . . . . . . . . . . . . . . . . . . . . . . . .2013.1High speed transfer. . . . . . . . . . . . . . . . . . 2013.2Serial data transfer format in Hs-mode. . . 2113.3Switching from F/S- to Hs-mode andback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313.4Hs-mode devices at lower speed modes. . 2413.5Mixed speed modes on one serial bussystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413.5.1F/S-mode transfer in a mixed-speed bussystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513.5.2Hs-mode transfer in a mixed-speed bussystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513.5.3Timing requirements for the bridge in amixed-speed bus system. . . . . . . . . . . . . . 271410-BIT ADDRESSING. . . . . . . . . . . . . . . . 2714.1Definition of bits in the first two bytes. . . . . 2714.2Formats with 10-bit addresses. . . . . . . . . . 2714.3General call address and start byte with10-bit addressing. . . . . . . . . . . . . . . . . . . . 3015ELECTRICAL SPECIFICATIONSAND TIMING FOR I/O STAGESAND BUS LINES. . . . . . . . . . . . . . . . . . . . 3015.1Standard- and Fast-mode devices. . . . . . . 3015.2Hs-mode devices. . . . . . . . . . . . . . . . . . . . 3416ELECTRICAL CONNECTIONS OFI
2
C-BUS DEVICES TO THE BUS LINES . 3716.1Maximum and minimum values ofresistors R
p
and R
s
for Standard-modeI
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 3917APPLICATION INFORMATION. . . . . . . . . 4117.1Slope-controlled output stages ofFast-mode I
2
C-bus devices. . . . . . . . . . . . 4117.2Switched pull-up circuit for Fast-modeI
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 4117.3Wiring pattern of the bus lines. . . . . . . . . . 4217.4Maximum and minimum values ofresistors R
p
and R
s
for Fast-modeI
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 4217.5Maximum and minimum values ofresistors R
p
and R
s
for Hs-modeI
2
C-bus devices . . . . . . . . . . . . . . . . . . . . . 4218BI-DIRECTIONAL LEVEL SHIFTERFOR F/S-MODE I
2
C-BUS SYSTEMS . . . . 4218.1Connecting devices with differentlogic levels. . . . . . . . . . . . . . . . . . . . . . . . . 4318.1.1Operation of the level shifter . . . . . . . . . . . 4419DEVELOPMENT TOOLS AVAILABLEFROM PHILIPS. . . . . . . . . . . . . . . . . . . . . 4520SUPPORT LITERATURE . . . . . . . . . . . . . 46
 
3Philips Semiconductors
The I
2
C-bus specification
1PREFACE1.1Version 1.0 - 1992
This version of the 1992 I
2
C-bus specification includes thefollowing modifications:
Programming of a slave address by software has beenomitted. The realization of this feature is rathercomplicated and has not been used.
The “low-speed mode” has been omitted. This mode is,in fact, a subset of the total I
2
C-bus specification andneed not be specified explicitly.
The Fast-mode is added. This allows a fourfold increaseof the bit rate up to 400kbit/s. Fast-mode devices aredownwards compatible i.e. they can be used in a 0 to100kbit/s I
2
C-bus system.
10-bit addressing is added. This allows 1024 additionalslave addresses.
Slope control and input filtering for Fast-mode devices isspecified to improve the EMC behaviour.NOTE: Neither the 100kbit/s I
2
C-bus system nor the100kbit/s devices have been changed.
1.2Version 2.0 - 1998
The I
2
C-bus has become a de facto world standard that isnow implemented in over 1000 different ICs and licensedto more than 50 companies. Many of today’s applications,however, require higher bus speeds and lower supplyvoltages. This updated version of the I
2
C-bus specificationmeets those requirements and includes the followingmodifications:
The High-speed mode (Hs-mode) is added. This allowsan increase in the bit rate up to 3.4Mbit/s. Hs-modedevices can be mixed with Fast- and Standard-modedevices on the one I
2
C-bus system with bit rates from 0to 3.4Mbit/s.
The low output level and hysteresis of devices with asupply voltage of 2V and below has been adapted tomeet the required noise margins and to remaincompatible with higher supply voltage devices.
The 0.6V at 6mA requirement for the output stages ofFast-mode devices has been omitted.
The fixed input levels for new devices are replaced bybus voltage-related levels.
Application information for bi-directional level shifter isadded.
1.3Version 2.1 - 2000
Version 2.1 of the I
2
C-bus specification includes thefollowing minor modifications:
After a repeated START condition in Hs-mode, it ispossible to stretch the clock signal SCLH (seeSection13.2 and Figs22, 25 and 32).
Some timing parameters in Hs-mode have been relaxed(see Tables6 and 7).
1.4Purchase of Philips I
2
C-bus components
Purchase of Philips I
2
C components conveys a license under the Philips’ I
2
C patent to use thecomponents in the I
2
C system provided the system conforms to the I
2
C specification defined byPhilips.

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