Philips Ftv1.9de - Training Manual

Colour Television Chassis
FTV1.9DE
AA
CL 965320690-163.eps
020999
Contents Page
1 Introduction 2
2 Mechanical instructions 5
3. Blockdiagram 11
4 Service modes 12
5 Preconditioner 26
6 VsVa supply 38
7 Audio Video control 54
8 PDP- Limesco 68
9 Audio amplifier 80
10 LED panel 81
11 Switch panel 82
12 YUV / YC input 83
©
Copyright reserved 1999 Philips Consumer Electronics B.V. Eindhoven, The
Netherlands. All rights reserved. No part of this publication may be reproduced,
stored in a retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by JvR 9969 Service PaCE Printed in The Netherlands Subject to modification 5 3122 785 10036
2 1. Introduction FTV1.9DE Display Box
1. Introduction
CONFIGURATIONS
TV-CONFIGURATION
R, G, B, HS, VS
RECEIVER BOX DISPLAY BOX

CONFIG_IDENT
DIS_RC_5
µP UART µP
MONITOR-CONFIGURATION
R, G, B, H, V
PERSONAL COMPUTER DISPLAY BOX
CONFIG_IDENT
µP DDC µP
CL 96532069_002.eps
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The successor of the FTV1.5 is the FTV1.9, which had to be

cheaper,and had to make as much as possible "re-use" of
PWB's from the FTV1.5.
Personal notes
It is built around an E-Box (= Receiver Box) and a 42" Monitor

(= Display Box). Within the Monitor a Fujitsu Plasma Display
panel - version 5 - is used.
For the FTV1.9, the Monitor can be used in two applications.

• Stand-alone configuration, monitor is connected to a PC or
a laptop
• TV configuration, where the monitor is connected to the E-
box.
The Monitor is a separate device, which can also be sold and

serviced separately.
The monitor, as a stand-alone unit, can be serviced by using a
test pattern coming from the PDP-LIMESCO panel on the
monitor itself or via a PC/laptop by using ComPair via the
ComPair connector.
FTV1.9 Family has been set up for Europe, USA, Asian and
LATAM markets.
The Europe type consisting of 1 version, having no diversity.
FTV1.9DE Display Box 1. Introduction 3
1.1 Description of used panels
VS/VA Supply
PDP Discharge
Audio Amplifier
PDP Limesco
Pre-conditioner
AV Control YUV/YC Input
CL 96532069_131.EPS
120899
The panels are:

1. VsVa supply. At this panel all the supply voltages will be
generated for the display itself, the electronics of the display
Personal notes
and our PCB's. This panel contains also the fan control and
the protection circuits.
2. PDP Discharge Panel. Temporarily used in the DEM-
models of the FTV1.9. In the final models this panel is either
going to be integrated into the VsVa panel or is going to be
re-designed as a separate new panel. The function of this
panel is to discharge the big capacitor of the Vs-supply and
the Va-supply (minor reason). If these capacitors are not
discharged it can take up to 60 seconds before the set re-
starts after turning it OFF and ON again.
3. Audio amplifier. This panel is almost the same as the GFL
audio amplifier. Some small changes have been made like
other plugs, deleting a switch and external speaker
connectors and an adaptation of the outlines, just to mount
the panel at the backside of the Monitor.
4. Preconditioner. At this panel the mains input and mains
output (to connect the E-Box) is located. After the mains
input, the mains filter is placed. The panel contains also the
preconditioner. This is an auto voltage function from 95V ...
264VAC in to 380VDC out and the standby supply for the
µP and the NVM.
5. AV Control. At this panel the VGA, audio and control (UART
or DDC) signals enter the Monitor. These signals will be
buffered and are available at the output of this panel for
feedthrough (except the control signals). The same signals
will be fed to the Audio part (including an (optional) audio
4 1. Introduction FTV1.9DE Display Box
delay to correct the timing between video and audio) and to

the video control IC to control the RGB signals. Also the µP
for the panel control in the Monitor is located on this board.
Personal notes
The audio filters for the high and low/medium signals are
also located on the AV Control board.
6. PDP LIMESCO. This panel converts the analogue video
after gamma correction to a digital video signal, which is
connected to the PDP itself. The OSD generator is located
at the PDP LIMESCO, close to the LIMESCO IC for the
insertion of digital OSD information. The LIMESCO IC is
responsible for the scaling of the signals of the various
standard TV standards, VGA formats at this board. The H
and V position is corrected by an EPLD.
7. YUV YC input panel. This board gives the possibility to
attach several video formats to the stand-alone display. It
also has one stereo audio connection.
• Video input signals:
– YUV on three CINCHES (Y, Cb, Cr).
– YC on Hosiden connector (SVHS).
– CVBS on CINCH.
– CVBS on BNC.
• Audio input signals:
– L and R on 2 CINCHES.
• Output signal (AV Control):
– RBG-signal.
– H-sync and Vsync signal.
– L and R audio signal.
8. LED Display panel. At this panel, the LED's and the IR-
Receiver is located.
9. Switch Display panel. At this panel, the low power mains
switch is located. With this switch a relay is controlled to
switch ON and OFF the monitor
FTV1.9DE Display Box 2. Mechanical instructions 5
2.1 Introduction:
There are pre-defined service positions for the following panels: VS/VA SUPPLY panel.
2. Mechanical instructions2.1 Introduction:
1. VS/VA SUPPLY panel.

2. PDP DISCHARGE panel.
3. AUDIO AMPLIFIER panel. VS/VA Supply
4. PRE-CONDITIONER panel.
5. AV CONTROL panel.
6. PDP LIMESCO panel.
7. YUV/YC INPUT panel.
8. LED DISPLAY panel.
9. SWITCH DISPLAY panel.
Before these panels can be accessed, the rear cover has to be
removed:
FD07
1 4
2
2
CL 96532069_132.EPS
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1
Figure 2-3
CL 96532069_130.EPS
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1. Disconnect Fan Supply cable from connector FD07 in the
upper left corner [1].
2. Remove the 7 fixation screws of the panel [2].
Figure 2-1
3. Place panel on the 2 hinges, which are located near the
right corners of the panel [3].
1. Place the Display Box in the service stand via 2 reinforced 4. Use the mechanical service part (extension cable
cushions (order code: 3122 126 30181). assembly, 12NC: 3122 785 90006) to extend the Fan
2. Remove the 9 fixation screws of the rear cover. Supply cable [4].
3. Remove the rear cover (during removal push it slightly 5. The copper side is now accessible from the left.
upwards).
PDP DISCHARGE panel.
As in the FTV 1.5, this panel must be exchanged completely if

VS/VA Supply defective.
PDP Discharge
Audio Amplifier
PDP Limesco
Pre-conditioner
AV Control YUV/YC Input
CL 96532069_131.EPS
120899
Figure 2-2
1. All panels are now accessible.

6 2. Mechanical instructions FTV1.9DE Display Box
2.1 Introduction:
AUDIO AMPLIFIER panel. PRECONDITIONER panel.
Audio Amplifier Pre-conditioner
3 22 5
1 5
1
4
2
CL 96532069_135.EPS
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3
2 CL 96532069_134.EPS
Figure 2-5
120899
1. Disconnect the 2 grounding wires from the shielding plate
Figure 2-4 by pressing the small lever on the connector while pulling
[1].
1. Some testpoints are accessible at the B-side [1]. 2. Remove the 2 ferrite ring cores from their fixations [2].
2. If this is not sufficient, remove the 3 fixation screws of the 3. Remove the 5 fixation screws of the panel [3].
panel [2]. 4. Place panel on the 2 hinges, which are located, near the left
3. Panel now can be hinged on the left side to access the A- corners of the panel [4].
side (soldering side) [3]. 5. Reconnect grounding wires to the extra connectors on the
shielding plate at the left side [5].
6. The copperside becomes accessible now from the right
side.
AUDIO VIDEO CONTROL panel.
AV Control
CL 96532069_136.EPS
120899
Figure 2-6
2.1 Introduction:
This panel has no service position for accessing the A-side, YUV/YC INPUT panel.
however all service test points are accessible at the B-side (see
Service Manual).
In case some components must be (de)soldered, all fixation YUV/YC Input
screws (6 for the panel, 5 at the metal connector plate) and all
cables must be removed to access the A-side.
PDP LIMESCO panel.
PDP Limesco
SVHS BNC
2
2
1
1 CL 96532069_138.EPS
120899
1
1
2 Figure 2-8
1
This panel has no pre-defined service position. For access of
CL 96532069_137.EPS the A-side, the panel has to be removed:
120899
1. Remove the 4 screws at the metal connector plate [1].
Figure 2-7 3. Panel can be removed now to access the A-side [3].
All SMC's are located on the B-side, so all testpoints are LED DISPLAY panel.
accessible. In case some components must be (de)soldered,
the hinge construction can be used to access the A-side.
2. Panel can now be hinged to access soldering side [2].
CL 96532069_139.EPS
1 120899
Figure 2-9
2.1 Introduction:
1. Remove 2 x 2 screws at the sides and 4 screws at the

bottom of the front cover [1].
2. Remove the front cover (it hinges at the top). During
Personal notes
removal unplug the cable of the LED DISPLAY panel at the
SWITCH DISPLAY panel (connector SD11) [2].
CL 96532069_140.EPS
120899
Figure 2-10
1. The LED DISPLAY panel can be removed now by

unscrewing 1 fixation screw [3].
SWITCH DISPLAY panel.
1. Remove front cover (for a description see Chapter 2.1.8

'LED DISPLAY panel').
CL 96532069_141.EPS
120899
Figure 2-11
1. The SWITCH DISPLAY panel can be removed now by

unscrewing 3 fixation screws [3].
2.2 Exchanging parts
Some parts of the FTV1.9 Display Box must be exchanged if

defective:
1. GLASS PLATE.
2. LOUDSPEAKER.
3. PLASMA DISPLAY PANEL [PDP].
3
Exchanging of the GLASS PLATE.
4
1. First unplug (remove Mains and VGA cable) the Display 3
Box .
'LED DISPLAY panel'). 4
3
CL 96532069_143.EPS
120899
2 Figure 2-13
1. The LOUDSPEAKER can now be removed by

disconnecting its cable and removing the 4 fixation screws
at the top and bottom of the speakerbox. Be sure to remove
the correct screws, otherwise the speaker system will be
damaged (it is an airtight system).
Exchanging of the PDP.

5
3 4 1. First unplug (remove Mains and VGA cable) the Display
Box.
2. Place the rear side of the Display Box on a foam cushion (be
CL 96532069_142.EPS
120899 sure the metal rear cover is mounted in order to prevent
damaging of the electronic panels).
Figure 2-12
LED DISPLAY panel).
4. Now the GLASS PLATE can be removed by unscrewing all
1. Now the GLASS PLATE can be removed by unscrewing all
screws and removing all glass clips (for a description see
screws [3] and removing all glass clips [4].
Chapter 2.2.1. 'Exchanging of the GLASS PLATE').
Exchanging of a LOUDSPEAKER.
1. First unplug (remove Mains and VGA cable) the Display

Box.
'LED DISPLAY panel').
CL 96532069_144.EPS
120899
Figure 2-14
1. Remove all copper EMC SHIELDING springs mounted

around the display [6].
2. Now flip the complete Display Box and place it with the
Personal notes
Plasma Display down on a foam cushion. Be 100 % sure a
large foam cushion is placed underneath the PDP, as it will
drop about 10 mm after removing its fixation screws ! !
3. Disassemble metal rear cover (for a description see
Chapter 1.1 'Introduction').
PDP Discharge
PDP Limesco
FOA
M CU
SHIO
N
1
FD173 FD171
4
2
5
3 PD3
3
CL 96532069_145.EPS
CN24 CN23 120899
Figure 2-15
1. Disconnect the following cables:

– Cables coming from connectors CN23 and CN24 of the
PDP DISPLAY panel [3] (for easiest access lift the PDP
DISCHARGE panel from its fixations [2]).
– Flat cable on connector PD3 of the PDP LIMESCO
panel [4]. Also remove the ferrite 'flat cable shield'
completely by unlocking its fixations [5].
1
1
2 1
2 1
3
2
2
CL 96532069_146.EPS
120899
Figure 2-16
1. Now remove the 8 large screws which hold the PDP:

– 4 screws are located at the top: they also hold the
aluminium wall mount [1].
– The other 4 are located at the bottom: the 2 outer screws
are hidden behind panels. Therefor unscrew the VS/VA
SUPPLY and the PDP-LIMESCO panel (grey panels)
[2].
2. Lift encasing from PDP and replace PDP [3].
FTV1.9DE Display Box 3. Block diagram 11
For the block diagram see Service Manual chapter 6.

3. Block diagram
The power is supplied by the VsVa supply (which is an LLC

converter). The Pre-conditioner delivers the input voltage of
Personal notes
380 V.
The output voltages of the VsVa supply are:

• Va: 55 V + 5 * Vra (Vra varies between 0 and 2 V).
• Vs: 165 V + 10 * Vrs (Vrs varies between 0 and 2 V).
• +5 V, 8.6 V and the +/- V_audio.
The controls located on the µP panel, which is a panel on the

AV Control panel, are activated by the keyboard on the Front I/
O and RC5 signals from the remote control receiver on the LED
panel.
Audio signals coming from the YUV Y/C panel or from the AV
Control are selected and processed at IC7940 (TDA9860). The
outcoming L/R signals are filtered (HPF) and corrected for low
frequency by the DBE-circuit, before they are fed to the Audio
amplifier.
CVBS signals (BNC connector or CINCH) at the YUV Y/C panel
are first passed through a comb-filter IC7012. The output
signals (Y and C) of IC7012 and the Y/C signal from the SVHS
connector are selected by IC7010. The output Y/C are fed to
YUV/RGB matrix IC7013 (TDA8854).
The YUV signals (CINCH) are processed separately in a RGB
matrix and transferred to IC7013. The selected RGB_YC output
signals from IC7013 are fed to the AV Control panel.
RGB signals coming from the Receiver Box or PC, the normal
RGB_VGA or separate RGB_YC signals are selected by the
source select switch (IC7360). The output signals are fed to the
video control IC7300. The RGB output signals from IC7300 are
buffered and transferred to the PDP LIMESCO panel. Here the
signals are prepared and processed (gamma correction;
filtered; digitised by an ADC), buffered and fed to the display.
OSD-signals are added on the display via the PDP LIMESCO
IC.
RGB_VGA input signal are buffered and passed through to the
VGA-out connector.
12 4. Service modes FTV1.9DE Display Box
For the FTV1.9, the Monitor can be used in two applications.

4. Service modes
• A stand-alone configuration, a separate device which can

also be sold and serviced separately.
Personal notes
• TV configuration, where the monitor is combined with the E-
box.
The monitor, as a stand-alone unit, can be serviced by using a

test pattern coming from the PDP-LIMESCO panel on the rear
of the monitor itself or via a PC/laptop by using ComPair via the
ComPair connector.
In this chapter the following paragraphs are included:

1. Test points
2. Dealer Service Tool (DST)
3. Service Modes
4. Error code buffer and error codes
5. The "blinking LED" procedure
6. Fault-finding tips
7. ComPair
FTV1.9DE Display Box 4. Service modes 13
4.1 Test points
The FTV1.9 chassis is equipped with test points in the service

4.1 Test points
printing. These test points are referring to the functional blocks:

• A1-A2-A3, etc.: Test points for the Audio amplifier (A)
Personal notes
• C1-C2-C3, etc.: Test points for the AV control circuit (AVC)
• FD1-FD2-FD3, etc.: Test points for the VsVa supply (FD1-
FD2) and the PDP discharge panel
• L1-L2-L3, etc.: Test points for the PDP LIMESCO (PD1-
PD9)
• PR1-PR2-PR3, etc.: Test points for the Pre-conditioner
(PR1-PR3)
• Y1-Y2-Y3, etc: Test points for the Y/C YUV monitor panel
(UY1-YC4)
Measurements are performed under the following conditions:

Video: colour bar signal; Audio: 3 kHz left, 1 kHz right
4.2 Dealer Service Tool (DST)
For easy installation and diagnosis the dealer service tool

4.2 Dealer Service Tool (DST)
(DST) RC7150 can be used. When there is no picture (to

access the error code buffer via the OSD), DST can enable the
Personal notes
functionality of displaying the contents of the entire error code
buffer via the blinking LED procedure, see also paragraph 5.5.
The ordering number of the DST (RC7150) is 4822 218 21232.
Installation features for the dealer
The dealer can use the RC7150 for programming the TV-set
with pre-sets. 10 Different program tables can be programmed
into the DST via a GFL TV-set (downloading from the GFL to
the DST; see GFL service manuals) or by the DST-I (DST
interface; ordering code 4822 218 21277). For explanation of
the installation features of the DST, the directions for use of the
DST are recommended (For the FTV1.9 chassis, download
code 4 should be used).
Diagnose features for service
FTV1.9 sets can be put in two service modes via the RC7150.
These are the Service Default Mode (SDM) and the Service
Alignment Mode (SAM).
4.3 Service Modes
Below described sequence is only valid for the "Monitor Only Service Alignment Mode (SAM)
4.3 Service Modes
Configuration". When a Receiver box is connected to the

Display Box (TV Configuration), please check chapter 4 in the The purpose of the SAM is to align and or adjust settings.
Training Manual of the Receiver Box. For recognition of the SAM, "SAM" is displayed at the top of the
right side of the screen
Service Default Mode (SDM) Entering the SAM-menu:
• By pressing the "ALIGN" button on the RC7150 Dealer
The purpose of the SDM is: Service Tool
• Provide a situation with predefined settings to get the same • Standard RC sequence 062596 followed by the "OSD"
measurements as in this manual. button.
• Access to the error buffer via the blinking LED procedure. • By short-circuiting the SAM pin on the µP panel (Caution:
• Inspect the error buffer. override of software protections ! ! )
• Possibility to overrule software protections via the service
pins (caution: override of software protections! ). In the SAM the following information is displayed on the screen:
--------------------------------------------------
Entering the SDM: F19DBC X.Y_12345 SAM
• By transmitting the "DEFAULT" command with the RC7150 ERROR## ## ## ## ##
Dealer Service Tool (this works both while the set is in WHITE POINT
normal operation mode or in the SAM). PDP TEST PATTERN [ON/OFF]
• By pressing on a standard RC the following sequence 0, 6, STORE
2, 5, 9, 6 followed by the "MENU" key. RESET ERROR BUFFER
• By short-circuiting the SDM pin on the µP panel. --------------------------------------------------
In the SDM the following information is displayed on the screen:
-------------------------------------------------------------- The menus and submenus
F19DBC X.Y_12345 (1) LLLL (2) SDM (3)
ERR 02 01 14 ## ## ## ## ## ## ## White point
-------------------------------------------------------------- The white point sub menu contains the following items:
Explanation notes/references: • RED
(1) Software identification of the main micro controller (F19DBC • GREEN
X.Y_12345) • BLUE
• F19D is the chassis name for FTV1.9 display • COLOUR TEMPERATURE
• B is the region identification
• C is the language cluster PDP Test pattern
• X = (main version number) By selecting this item, all OSD disappears from the screen. The
• Y = (subversion number) screen now changes from light grey to dark grey in a slow
• ##### are 5 digits of the Serial number regular rhythm. One can so easily check if all pixels of the
(2) "LLLL" Normal display operation in hours monitor are correct.
(3) "SDM" To indicate that the TV set is in the service default
mode Store
(4) "ERR 02 01 14 ## ## ## ## ## ## ##" This line shows the The change values are stored in the NVM.
contents of the error buffer (max. 10 errors). The last error that
occurred is displayed at the most left position. When less then Reset Error Buffer
10 errors have occurred the rest of the line is empty. When the This option will reset the error buffer.
errorlist is empty " No errors" is displayed. No duplicate errors.
Exit the SAM:
Exit the SDM:
Push the "Standby" button on the Remote Control.
Push the "Standby" button on the Remote Control.
SAM menu control:
The SDM sets the following pre-defined conditions:
Menu items can be selected with the "UP" or "DOWN" key.
• Volume level is set to 25% (of the maximum volume level).
Entry into the selected items (sub menus) is done by the "LEFT"
• Linear Audio and Video settings are set to 50%.
or "RIGHT" key. The selected item will be highlighted.
• Colour temperature is set to normal.
With the same "LEFT/RIGHT" keys, it is possible to increase/
decrease the value of the selected item.
The following functions are "overruled" in SDM since they
Return to the former screen by pushing the "MENU" button. The
interfere with diagnosing/repairing a set
item values are stored in NVM if the sub menu is left.
• Video blanking.
• Slow demute.
• Anti-ageing.
• Automatic switch to "Standby" when H- and/or V-sync
signals are lost.
All other controls operate normally.
4.3 Service Modes
Customer Service Mode (CSM) Display

Personal notes
FTV1.9 monitors are equipped with the "Customer Service
Mode" (CSM). CSM is a special service mode that can be
activated and de-activated by the customer, upon request of
the service technician/dealer during a telephone conversation
in order to identify the status of the set. This CSM is a 'read only'
mode, therefore modifications in this mode are not possible.
Entering the Customer Service Mode.

• By pressing on RC03333/01 the following sequence :
Picture, sound, cursor up, cursor down, cursor left, cursor
right followed by the button (MUTE)
Exit the Customer Service Mode.

• pressing the "MENU" or any key on the Remote Control
handset (except "P+" or "P-")
• switching off the TV set with the mains switch.
All settings that were changed at activation of CSM are set back
to the initial values
The Customer Service Mode information screen
The following information is displayed on screen:

--------------------------------------------------
CUSTOMER SERVICE MENU
• Software version F19DBC X.Y_#####)
• Code 1: contains the last 5 error codes
• Code 2: contains the first 5 error codes with the last
received error at the most left-hand side.
• Service unfriendly modes
--------------------------------------------------
4.4 Error code buffer and error-codes
4.4 Error code buffer and error-codes
Error-nr Type of Error Possible defect/cause

1 +5V +5V pin at uP is low.
2 8V6 8V6 pin at uP is low
3 Fan_prot Gives an indication that 1 or more FAN(s) does not function, or that 1 or
more fan control circuits is defect
4 Over-temp_prot Temperature at the heatsink of the VsVa supply or the Preconditioner is
too high
5 DC_prot Audio-amplifier IC, its supply or the Audio amplifier is defect
6 Over_voltage_prot Vs or Va supply voltage is too high
7 Vrr Powersupply of the display is not correct. Ignorance of the signal during
startup by the software.
8 Power_OKE Power supply or modules that uses this voltage. If this signal is NOT
activated means that all supply voltages are available (exception Audio
supply )
9 Blocked NVM IIC bus NVM IIC bus is not correct
10 Blocked slow IIC bus Slow IIC bus is not correct
11 TDA9860 No acknowledge of Audio controller
12 TDA4885 No acknowledge of Video controller
13 MC141585 No acknowledge of OSD Generator
14 uPD93687GD-LBD No acknowledge of Limesco
15 PCF8574AT No acknowledge of I/O Expander
16 NVM No acknowledge of NVM
17 Communication Fault in the communication
ch5-table1-mon.eps
Figure 1 : Error-code list of the D-box 041099
The error code buffer contains all errors detected since the last
time the buffer was erased. The buffer is written from left to
right.
Personal notes
In case of non-intermittent faults, clear the error buffer before
starting the repair to prevent that "old" error codes are present.
If possible check the entire content of the error buffers. In some
situations an error code is only the RESULT of another error
code (and not the actual cause).
Note: a fault in the protection detection circuitry can also lead to
a protection
The error code buffer will be cleared in the following cases:

• exiting SDM or SAM with the "Standby" command on the
remote control
• transmitting the commands "DIAGNOSE-9-9-OK" with the
DST.
The error buffer is not reset by leaving SDM or SAM with the
mains switch.
Examples:
ERROR: 0 0 0 0 0 : No errors detected
ERROR: 6 0 0 0 0 : Error code 6 is the last and only detected
error
ERROR: 5 6 0 0 0 : Error code 6 was first detected and error
code 5 is the last detected (newest) error
4.5 The "blinking LED" procedure
The contents of the error buffer can also be made visible

4.5 The "blinking LED" procedure
through the "blinking LED" procedure. This is especially useful

when there is no picture.
Personal notes
There are two methods:

• When the SDM is entered, the LED will blink the contents of
the error-buffer. Error-codes = 10 are shown as followed. A
long blink of 1second which is an indication of the decimal
digit, followed by a pause, followed by n short blinks. When
all the error-codes are displayed, the sequence is finished
with a led display of about 3 seconds. The sequence starts
again.
• With the DST all error codes in the error buffer can be made
visible. Transmit the command: "DIAGNOSE x OK" where x
is the position in the error buffer to be made visible x ranges
from 1, (the last (actual) error) to 10 (the first error). The
LED will operate in the same way as in the previous point,
but now for the error code on position x.
Example:
Error code position 1 2 3 4 5
Error buffer: 12 9 5 0 0
• after entering SDM: 1 long blink of 1 sec. + 2 short blinks -
pause - 9 short blinks - pause - 5 short blinks - pause -
long blink of 3 sec. --etc.
• after transmitting "DIAGNOSE- 1- OK" with the DST: 1 long
blink 2 short blinks - pause - 1 long blink + 2 short blinks -
etc.
• after transmitting "DIAGNOSE- 2- OK" with the DST: blink
(9x) - pause - blink (9x) - etc.
• after transmitting "DIAGNOSE- 3- OK" with the DST: blink
(5x) - pause - blink (5x) - etc.
• after transmitting "DIAGNOSE- 4- OK" with the DST:
nothing happens
4.6 Protections
All protections are handled by the hardware. The SW will only

4.6 Protections
monitor the hardware to generate error codes for the service.

The hardware switches to protection when one of the following
Personal notes
protections becomes active: FAN_PROT,
OVER_TEMP_PROT, DC_PROT, OVER_VOLTAGE_PROT
and Vrr.
When 1 of these protections occur, the HW will switch the set
to STANDBY.
The error must be read out by the microprocessor and the error
code must be generated. The microprocessor keeps the set in
STANDBY and starts the blinking red led. It is not allowed to
start up as long as the protections are present.
For the error code generation, the following levels of the A/D
converter are defined:
Input voltage at A/D converter [V]: Sort protection:

< 0.300 V No protection
0.3 < V < 1.875 FAN_PROT
1.875 < V < 2.813 OVER_VOLTAGE_PROT
2.813 < V < 3.75 OVER_TEMP_PROT
3.75 < V < 4.688 DC_PROT
DISPLAY SUPPLY MODULE
LLC Converter
Vs
OVP
SENSE
380 VDC
Error Vrs
LLC Control Amp.
Delay Vrr
Voc
Vs Va ok Vrr to µP
POWER OK POWER OK
17V
TEMP
ptc Speed Control Fans (1-5)
ptc
ptc
Protection FAN
FAN PROT
Circuit PROTECTION PROT-FAN (1-5)

Fan
Vs OVP Va OVP Protect
DC PROT (Audio)
AND -1 STBY
17V DC_DC
+5V
Converter
LLC Converter 5V OVP Vcc
+8V6
+/- V Audio
Va
OVP
SENSE
Error
Vra
LLC Control Amp.
5VSTBY-SWITCHED TO µP
On/Off
Switch
5VSTBY
CL 96532069_112.eps
240899
4.6 Protections
POWER_OKE
Personal notes
For ease of start-up and fault diagnosis a POWER_OKE signal
is generated. The signal is high when the voltages that are
sensed are in the right level. This signal is mixed with signals
derived from Vs and the Va. The POWER_OKE signal will be
high when simultaneously:
5V = 5V
17V >12.8V
Vs >135V
Va > 45V
In all other cases the output is low.
4.6 Protections
5VSTBY-SWITCHED VA 5VSTBY-SWITCHED VS
5VSTBY-SWITCHED
VCC 3033 3036

3035
3135 3136 3384
3058
7371 SUPPLY-ON 7016
VDD 3133 7341
[PR3] 7113 3385
7012
7301
7302 7112
7370 3137 3034 2037 3037
2134 3134 7114
+5V 3394 FD1
[C-14]
3138 2132 2135 AA
7013
2038
3386 3038 2032

CONNECTOR
FD06-12
3323
5VSTBY-SWITCHED
CONNECTOR PROT-FAN 1-6

5VSTBY-SWITCHED
D09
5 4 17V
7340 7321
TEMP
17V
3331
7337
DC
3332 3380
7331 6371
7314 7315
3 8 3339
7330-A 7316-7321
2 7332
4
5VSTBY-SWITCHED
3333
3039 3139
PROTS
7003 7103
7338
PROTECTION-STATUS
7333
7339 7103
3379 3378 3011 3111
7101-PIN10
CL 96532058_086.eps
7001-PIN10
280999
Protection structure
Personal notes
The protection structure of the FTV1.9 D-box is shown at figure
above.
The FTV1.9 monitor has one microprocessor, which is situated
on the AV-control panel and is supplied by the 5V standby-
supply. The microprocessor is even active when the set is
switched to standby. The microprocessor controls the "supply-
on" line which switches first relay 5680 and then relay 5690.
In de standby-mode or the protection-mode the "supply-on" line
is "low" and both both relays are switched off. The
preconditioner is disconnected from the mains.
The potections of the FTV1.9 monitor can be divided into 5

subgroups:
– Fan_prot
– Over_temp_prot
– DC_prot
– Over_voltage_prot
– Vrr
For the Fan-, Over_temp, DC and the Over_voltage protections

the signals for the µP are latching, using the 5Vstby_switched
for powering the circuits permanently. The µP has sufficient
time for diagnosis and for storing the error-codes in the NVM.
Vrr, which is an indication of the powersupply of the display is
correct, is directly fed to the µP.
4.6 Protections
Signal line "PROTECTION STATUS" and errorcodes Connecting PROTS to ground, will start a current flow through
opto-coupler diode 7103 and the opto-coupler transistor
When one of the protection mechanism is triggered, the connects supply voltage Vcc2 to the fault input ( pin 10 ) of IC
5Vstby-switched is connected via a saturated transistor and a 7101. When the voltage at pin 10 exceeds 1.0V, IC7101 stops
pre-defined resistor to signal line "protection status", which is oscillating. The Va-supply stops functioning.
connected to the µP. To continue the signal flow, go to the right upper corner of
Signal line "protection status" is connected to ground via schematic FD2. Connecting PROTS to ground also results in a
resistor R3378 and 3379. For each seperate fault condition current flow through the opto-coupler diode of 7003. The opto-
mechanism we get a pre-defined voltage at the µΠ. coupler transistor connects supply voltage Vcc1 to the fault
This results in the following table input ( pin 10 ) of IC 7001. When the voltage at pin 10 exceeds
1.0V, IC7001 stops oscillating. The Vs-supply stops
functioning.
Protection- Series Voltage at "protection- Error-
mode resistor status" line code
Vs and Va protection
None ----- < 0.3V none Va protection

Fan_prot 1KΩ 0.30V < Vprot < 1.90V 3 When this protection is activated, the Va- and Vs power supply
Vs or 470Ω 1.90V < Vprot < 2.80V 4
are shut down. The set is switched to the standby mode and
Va_prot error-code 4 is stored in the NVM.
When the Va-supply exceeds the 68V, regulator 7112 is
Temp_prot 220Ω 2.80V < Vprot < 3.75V 5
triggered and will switch on T7113. Capacitor 2132 is charged
DC-prot 68Ω 3.75V < Vprot < 4.7V 6 via the 5Vstby-switched and will trigger thyristor 7114, which
Vrr ------ ------ 7 will switch on T7341. The voltage "protection status" is now
determined by the voltage dividing of R3386 and resistor
Protection signal Vrr coming from the PDP, to indicate that the R3378 and 3379. ( neglect the Vce of 0.2V of T7341 ). See
powersupply is ok or not ok ( "1" or "0" ) is directly connected schematic FD2.
to the µP. Error-code 7 is stored in the NVM and the set is The presence of the voltage at "protection status" line will
switched to standby. eventually reset the VsVa-supply. For more info see
When one of the protections is activated, the power supplies of subparagraph - Reset of the VsVa-supply.
the Vs and Va are shut down and the set is switched to standby.
Vs protection
Fan protection When this protection is activated, the Vs power supply is shut
down. The set is switched to the standby mode and error-code
When this protection is activated, the Va- and Vs power supply 4 is stored in the NVM.
are shut down. The set is switched to the standby mode and When the Vs supply exceeds the 198V, regulator 7012 is
error-code 3 is stored in the NVM. triggered and will switch on T7016. Capacitor 2032 is charged
The fan voltage is powered by 17V, but clamped to 12V to via the 5Vstby-switched and will trigger thyristor 7013. Thyristor
prevent damage. In order to be able to verify whether the fans 7013 is fired and connects signal Aa to ground. To follow the
are running, a fault detection circuit is implemented for each of signal flow, go to the right upper corner of schematic FD1.
the 6 fans. A running fan gives pulses in the same speed as the When signal Aa is shorted to ground, T7341 is switched on. The
rotation of the blades. The circuit uses these pulses to trigger voltage "protection status" is now determined by the voltage
the discharge of an elcap. The elcap is continuously charged dividing of R3386 and resistor R3378 and 3379. ( neglect the
through a resistor. Vce of 0.2V of T7341 ). See schematic FD2.
The presence of the voltage at "protection status" line will
Example : Capacitor C2319 is charged through R3356 and at eventually reset the VsVa-supply. For more info see
every pulse discharged by T7322. When fan 6 is blocked, subparagraph - Reset of the VsVa-supply.
C2314 is charged via D6326 en triggers thyristor 7315,
because C2319 is no longer discharged via T7322. The current Temperature Protection
now flows from the 5Vstby-switched via resistor 3383 and 3325
driving transistor T7321 into saturation. The voltage "protection When this protection is activated, the Va- and Vs power supply
status" is now determined by the voltage dividing of R3323 and are shut down. The set is switched to the standby mode and
resistor R3378 and 3379. ( neglect the Vce of 0.2V of T7321. ). error-code 5 is stored in the NVM.
When the temperture of the heatsink on the Preconditioner
Reset of the VsVa-supply. panel or on one of the 2 heatsink on the VsVa panel exceeds
Transistor T7339 is shorted now by the presence of the the 110°C, the PTC resistance increases drastically. The
"protection status" signal. T7339 connects resistor R3376 and voltage at pin 3 of IC7330 will drop and the output of 7330 will
R3389 to ground, switching on T7338. Thyristor 7333 is now do the same. The current flow through opto-coupler diode 7331
triggered, shorting signal PROTS to ground. To follow the results also in a current flow through the opto-coupler transistor
signal flow, go to the right upper corner of schematic FD1. and will trigger thyristor 7332. The fired thyristor switches
transistor 7337 on. The voltage "protection status" is now
4.6 Protections
determined by the voltage dividing of R3339 and resistor

R3378 and 3379. ( neglect the Vce of 0.2V of T7337 ).
Personal notes
eventually reset the VsVa-supply. For more info see
subparagraph - Reset of the VsVa-supply.
DC Protection - Audio Amplifier
When this protection is activated, the Va- and Vs power supply

are shut down. The set is switched to the standby mode and
error-code 6 is stored in the NVM.
In case of a fault in the Audio amplifier or when a DC voltage
appears on the speaker output, a signal called DCPROT is
generated. See schematic FD2 - F7. In case of a fault, thyristor
7314 is triggered and switches on T7340. The voltage
"protection status" is now determined by the voltage dividing of
R3380 and resistor R3378 and 3379. ( neglect the Vce of 0.2V
of T7340 ).
eventually reset the VsVa-supply. For more info see
subparagraph - Reset of the VsVa-supply.
Vrr - PDP supplies
Vrr is a logical signal ( "high" in normal circumstances ) that

comes from the PDP. It's purpose is to trigger the switch off of
the Pre-conditioner supply in case Vrr becomes "low" , to trigger
the shutdown of the VsVa supply and to initialise that error-
code 7 is stored in the NVM.
When signal Vrr becomes "low", see FD1 - F13, the output of
IC7301-B becomes "high". This results in two actions.
It will trigger thyristor 7302 and short signal PROTS to ground.
This results eventually in a reset of the VsVa supply.
Switching on T7371, which again switches on T7370 via the
5Vstby-switched supply. Signal-line "supply-on" is now
grounded. This results in switching off relay 5680 and 5690,
disconnecting the mains from the pre-conditioner. The standby
supply( 5Vstby-switdhed ) is still functional.
4.7 Alignments
4.7 Alignments
Electrical Alignments Personal notes

Pre-conditioner +5Vstby (PR3)
Connect a voltmeter to capacitor C2510 (PR2). With the aid of
R3504 adjust the voltage to 5.2 V +/- 50 mV.
Va-supply (Addressing of the PDP - FD1)

De-activated the PDP.
Connect a voltmeter to capacitor C2120 (FD1). With the aid of
R3126 adjust the voltage to 55 V +/- 0.5 V.
Vs-supply (Sustain pulses - FD2)

De-activated the PDP.
Connect a voltmeter to capacitor C2020 (FD2). With the aid of
R3026 adjust the voltage to 165 V +/- 0.5 V.
Software Alignments
See chapter 4.3.2. "Service Alignment Mode (SAM)".

26 5. Preconditioner FTV1.9DE Display Box
5.1 Caution
When repairing the Preconditioner supply the hidden mains-

5. Preconditioner5.1Caution
switch must be used to disconnect the monitor from the mains.

The pre-conditioner and the VsVa supply remains under
Personal notes
tension if the mains-cable is still connected to the mains socket
and the mains switch is NOT pressed.
FTV1.9DE Display Box 5. Preconditioner 27
5.2 Introduction
5.2 Introduction
MAINS IN
MAINS FILTER PRECONDITIONER 380V
TEMP
+12VSB PRECON
Filtered Mains
Voltage +5VSTBY
+5VSTBY Switched
STANDBY SUPPLY
SUPPLY ON
POR
CL 96532069_119.eps
300999
The preconditioner module is designed for the FTV 1.9. It is the

interface between the mains input and the VsVa panel of the
monitor.
Personal notes
The advantage of a preconditioner in this application is:

• reduction of mains harmonics to legal limits
• lower mains current for the same output power.
• regulated output for the mains isolated power supplies
following the preconditioner module.
The preconditioner consists of 3 functional sub-modules.

1. Mains filter
2. Main supply
3. Stand-by supply
5.3 General description.
CL 96532069_085.eps
300999
5.3 General description.
The mains is fed through the mainsfilter to reduce common-

and differential noise.
Personal notes
The mains switch - 1004, is added to disconnect the mains
input from the pre-conditioner. This ON/OFF relay has to be
switched manually, while the other relay is controlled by the
SUPPLY ON signal. This signal is low if the standby signal is
high, or one of the protections is activated.
The standby supply is a separate power supply to reduce power

consumption of the Flat TV set in standby mode. The bridge
rectifier rectifies the mains voltage and is applied to a
differential mode filter- 5605 for EMI requirements and then to
the preconditioner.
The preconditioner has an output voltage of 380V, controlled by

the PCF controller (MC3336P) which is independent of the
mains input. The output voltage of 380V is delivered to the Vs-
and Va supply.
A PTC is connected to the heatsink of the MOSFET, which puts

the set in protection, by activating an Opamp on the VsVa
panel, when the temperature exceeds a safety limit.
5.4 Mainsfilter
5.4 Mainsfilter
MAINS FILTER
1402 I200 3404

F204 DSP 220R
F208
F209
1401 2404 2406
AC inlet F207
PR1 47p 47p
I201 1400 I202 I203
0314
1 LIVE_IN F200 1004 5401 5402
4 2 1 5400 2 4 CU28D3 3 4 CU28D33
2407
RES
2322595
GROUND_IN
2400
470n
3400
2401
220n
3401
V
1M
3 1
3 NEUTRAL_IN
3 4 I204 2 1 I205 2 1
F211 PR30
PR31
PR2
RES
2405
470p
470p
2402
2403
F210
3402
4M7
F212
F202
F201
I206 GNDEARTH2
GNDEARTH2 GNDEARTH2
F203 PR3
3403
4M7
GNDEARTH2
CL 96532069_113.eps
110899
The AC power is fed to the mainsfilter (0314). A mains switch

has been added to switch off the mains while repairing the set.
The first filter around coil 5400 is to differential mode filter to
Personal notes
reduce H.F. noise produced by the FTV.
A second filter around coil 5401 is a common mode filter to
reduce noise from the VS/VA supply and the preconditioner
itself. Together with capacitors 2400 en 2401, coil 5401 works
as a lowpass filter.
A second common mode filter is made around coil 5402 and
capacitor 2407.
Resistor 3400 is a high energy VDR. The advantage of this
VDR is that it can handle 380VAC without risk of fire. The mains
filters are damped by a spark gap / resistor combination to
prevent damage in the mains isolated power supplies of the
monitor. Ground leads of the AC inlet and outlet are filtered with
a toroid inductor. This is needed to fulfil EMC regulations
without the need of a special and expensive filtered mains cord.
Resistor 3401 discharges the X capacitors after the mains is
disconnected.
5.5 Standby supply
5.5 Standby supply
STANDBY SUPPLY
6503
BYD33D
4u7
2505
2506
100p 5500
CE165T
PR6 1 9
GNDHOT1 2507
3508
2 8 PR8
100p
3 6504
RES
3 7
2501
DF06M 1R +12VSB
2503
22u
4 6 BYD33D
4u7
6500
2508
1 2
5 PR10
RES
2500
1500 4 PR9
PR7 6505
+5VSTB
1m
3506 BYV27-200
GNDHOT1 2509
2510
10R
100p
3501
470R
7500
3502
33K
+5VSTBY_SWITCHED TOP 210
BZT03-C
9667
6501
7501
3505
5 SOURCE CONTROL 4
4K7
TCDT1102G
9520
6 N/C N/C 3 3500
2511
1
33n
3520
3521
39K
1K
7 N/C N/C 2 470R
BZT03-C
9668
3
6502
100n 2504
47u
7520 8 DRAIN CONTROL 1 TL431CLP
MC34064P2 7502
3503
2513
3K9
1 7521
RESET_ IN
9521
BC547B 2
GNDHOT1
3504
1K
2520
+5VSTBY
GNDHOT1
GND
CL 96532069_087.eps
300999
The standby supply is a separate power supply to reduce power

consumption of the Flat TV set in standby mode. It has 2 mains
isolated outputs:
Personal notes
• +5VSTBY for the microprocessor of the monitor and to
power the ON/OFF relay in the preconditioner.
• +12VSB to power the inrush relay of the preconditioner.
The AC input is applied through fuse 1500, rectified by bridge

6500 and smoothed by capacitor C2503.
The stand by supply is build around the TOP Switch TOP210.
The frequency is fixed to 100 kHz. The voltage is controlled by
regulating the input current at pin 4 of the TOPSWITCH via the
opto-coupler transistor 7501. More current means a smaller
duty cycle.
The 5VSTBY can be adjusted by resistor 3504.
If the 5VSTBY increases, pin 3 of 7502 also increases. The
current through the opto-coupler diode 7502 will increases and
so the current through the optocoupler transistor 7502. An
increase of the input current at pin 4 of the 7500 will decrease
the duty cycle. As a result the 5VSTBY will decrease again.
Diodes 6501 en 6502 are added to protect the input of the
TOPSWITCH against mains spikes.
5.6 POR circuit
5.6 POR circuit
+5VSTBY
>4.5V
time
POR
time
>100ms
CL 96532069_150.eps
250899
POR will go low if the 5V-STBY is out of specification. The POR

signal resets the processor (and if needed other small signal
circuits) on the AV Control Board.
Personal notes
The POR circuit is build around IC7520 (MC34064P). When
starting the set the POR follows the 5VSTBY. Transistor 7521
is switched on with a certain delay defined by R3520 and
C2520, and signal POR is grounded.
When the 5VSTBY drops below 4.59V pin 1 7520 becomes
low, transistor 7521 is switched OFF and the POR changes
from "0" into "1". The microprocessor at the AV control will put
the set to STANDBY.
6605
1N5406 6611 PR12 PR09
3 5605 4 0310-1
BYV29F-500 1
6606 380V
14
15
16
12
13
2611
5612
1 CU20 2
1N5406
FTV1.9DE Display Box
100MHZ
3600 3601 1n5
7610
5610
CE423D
+t +t STY34NB50
1
6
2
2
4
10R 10R 6608 3610
3n3
2610
2615
330u
2616
330u
2
1n
2600
G4W G4W 1N4148 3R3
3602 BC369
1u
1u
1u
1u
2 4 4 2 4 1 PR13
2605
2604
2606
2607
6600 7608
t 1R
3
6609
B57464 HOT_GROUND
0R1
0R1
0R1
0R1
BZT03-C
3613
3614
3615
3616
1n
1 3 3 1 3 GBU8
2601
PR14
4
6 5 5 6 1N4148 TEMP_PREC_A
3608
0315 0316
12R
6663
3663 2663 6661
5680 5690 HEATSINK HEATSINK 1 3
1R 100u BYD33D
1 2 3 4 5 1 2 3 4 5 2 7660
Vref
1K
L7815
3653
+t
1K
9606
3606
3668
2664
100u
6660
Vref
BYD33D
5
TEMP_PREC_B
SIG1 SIG3
Vref
10K
7650
3654
6665
6654
1M
MC33368
1N4148
3652
BYV10-40
2656 PR15
1M3
3650
BC557B 1 VREF LINE 16
100n SIG2
7654
2 RD NC1 15
2652
3641
10K
2u2
7641
3665
NC2
47u
3 VFB 14
2654
2665 470R BC337-25
PR16
4 COMP FC 13 SIG3
1u 2655 PR17 470p
5 MULT VCC 12
SIG2 6641 6642
SIG1
6 CS GATE 11
6662
2662
470u
res
10K
10n
1N4148 BYV10-40
3651
2651
6651
7 ZC PGND 10
BYV10-40
6640
10K
3667
2608
100p
5. Preconditioner
8 AGND LEB 9
BYV10-40 3642
PRECONDITIONER
3666 100R
100R
1n
+12VSB 7640
2653
2640
470p
RES BSN304
3670
750K
2
2666
100p
6652
6664
RES
+5VSTBY_SWITCHED
BYV10-40
BYV10-40
1 3
10K
3684
3640
2683
100u
470R
6681
6691
BYD33D
BYD33D
3683 BC557B
10K 7684
10K
3671
6680
6690
BYD33D
BYD33D
7681 3682
4K7
STD17N06
3685
2 10K
3680 1 PR18
4K7 3
7690
BC547B
10K
10K
3681
3690
040899
CL 96532069_088.eps
33
5.7 The preconditioner
The input voltage of the preconditioner is universal, between 95 Voltage regulation

V and 264 V.
The output is 380 Vdc (370 V - 390 V) to the Vs/Va module with The output voltage (380 V) is divided by R3670 and R3671 and
a maximum output power of 500 W (long-term average), and a connected to pin 3 7650. A change of the load will adjust the
peak value of max. 1000 W during 1 minute. duty cycle of the gate pulse at pin 11 of the supply IC to
The preconditioner does not provide mains isolation. maintain the output voltage constant at 380 V. There is no need
to adjust the output voltage by means of a potentiometer.
Starting up.
Current-protection.
The microprocessor controls the double pole by means of
signal SUPPLY ON. This signal switches indirect relay 5680 via The current through the FET flows also through the resistors
MOSFET 7681 and so enables the use of a small low voltage 3613, 3614, 3615 and 3616. The voltage across these resistors
switch. are fed to pin 6 of IC7650. If the current becomes too high, then
To protect rectifier 6600 and relay 5680 the inrush current is the preconditioner will turn off. A filter consisting of C2666 and
limited to maximum 20 A by charging capacitors 2605,2606 and R3666 avoid an unnecessary protection due to spikes.
2607 through 2 serial PTC's. C2665 and R3665 on pin 13 determine the maximum osc.
After approx. 0.5 sec relay 5690 is activated. This relay frequency.
connects an NTC in parallel with the PTC. The advantage of
using an NTC is the fact that the resistance varies with current Temperature protection.
and hence mains voltage. At high mains voltage, the current is
lower for the same power. PTC 3606is connected to the same heatsink as MOSFET 7610.
Two clamp diodes 6605 and 6606 charge output capacitors If the temp of this heatsink exceeds a safety limit the resistance
C2615 and 2616 to the peak voltage of the mains input. During of PTC 3606 will increase dramatically. This increase will
normal operation both diodes are blocked because of the trigger an Opamp on the VsVa panel and this will switch the set
output voltage of 380 Vdc, and will only conduct if there is a to standby. This is done by resetting control IC7001 and IC7101
mains spike or an output dip. of the VsVa supply.
Capacitor 2615 and 2616 deliver via R3668 the start-up voltage The module is designed to operate at an ambient temperature
at pin 16 of IC7650. After the start-up cyclus, IC7650 is supplied from 0° to 45°C and with forced air-cooling. For detailed info
via auxiliary winding 1-2. Capacitor C2663 is charged during about the temperature protection, see chapter 4.6. of the TM
the cycle that MOSFET 7610 conducts. While MOSFET 7610 Monitor.
is switched off, capacitor transfers its energy via D6661 to the
input of stabiliser IC7660. The output voltage of IC7660 is 15 V
and is fed via D6665 to supply-pin 12 of IC7650.
The slow start function is realised by the circuit consisting of
transistor 7654, D6654, R3654 and C2654.
Preconditioner-circuit
The supply IC generates pulses at pin 11 of IC7650, referred to

as SIG2. Because these pulses aren't small enough, a circuit
around transistor 7640 and 7641 has been implemented. The
duration of the square wave is decreased by 500 nsec.
Components R3640 and C2640 set this value.
A current sense coil has been used to switch ON the MOSFET
when there is no energy left in the transformer. This information
is fed to the controller IC7650 pin 7. In this way the dissipation
is very low combined with a low EMI.
The rectified mains input is connected to pin 5 of IC7650 via
voltage divider R3650 and R3651. This voltage is proportional
with the mains input and is used to change the duty cycle of the
gate-pulses at pin 11.
The MOSFET is switched OFF at very high current, up to 30 A.
To reduce dissipation, this is done with high speed. Turn off
driver T7608 has been added to accomplish this.
When there is an error in the supply the supply-IC would like to
restart. To prevent this hiccup a RESTART DELAY is build in
around pin 2 7650. The delay is set by R3652 and C2625 and
can be adjusted up to a few seconds.
Resistor 3401 discharges the X capacitors after the mains is
disconnected. This is needed to fulfil safety regulations.
ûs sin ωst
0 π/2 π
ωst
CL 96532069_151.eps
250899
Application
Personal notes
The European Law describes a reduction of Mains harmonics
for apparatus with a power consumption above 75W. Only the
ground harmonics are responsible for the power transfer. The
power factor should be close to 1.
The solution is the Pre-conditioner.
The advantages of a pre-conditioner compared to a mains input

filter are:
• Stable output voltage
• Small
• Low weight
• Power factor close to 1
Out of the three basic switch mode power circuits, the

upconverter was used as pre-conditioner. In the FTV1.9 an
upconverter is used with discontinuous current. The switching
frequency of the converter will be chosen much higher than the
mains frequency (50 - 60 Hz). It is then possible to consider the
supply to be constant during every high frequency period and
the envelop of all voltage steps during the low frequency period
approximates a half sine wave, as given in figure 7. We shall
consider only one half period, in which the voltage is a sinus
wave-form
Every step gives a current pulse of which the amplitude is
determined by the requirement that the low frequency
component pulses have the shape of a half sine wave. Figure
8 shows an example.
is (ωst)
0 π/2 π
ωst
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The smooth waveform between the peaks in figure 8 can be

considered as the mains input current after filtering of the high
frequencies. A small low pass filter will be necessary to fulfil the
Personal notes
interference requirements
Figure 9 shows the basic circuit definition for the up-converter.
Ls
is2
+ uLs - is1
S2
+ +
Us S1 Us
- -
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Two current values have been introduced, Is1 being the current
when S1 is conducting and Is2 when the diode start conducting.
The up-converter as used in the FTV1.9 is used as a semi-
Personal notes
discontinuous mode. The MOSFET is switched on when the
energy in the transformer is totally transferred to the secondary
side. The circuit can be split up in 2 modes
Mode 1: MOSFET is conducting - Increase of the current during
ton
Ul = Us = Ls * dI/ dt(Us = input voltage = Vmains rectified)
dI = (Us * ton) / Ls
Mode 2: Diode is conducting - Decrease of the current to zero
during toff
Ul = (Uc - Us) * dI / dt(Uc = output voltage = 380 Vdc)
dI =((Uc - Us) * toff) / Ls
During its normal operation the current increase equals the
current decrease.
dI (mode 1) = dI (mode 2)
ton = called the duty cycle (d)
ton + toff = t = switching period
In both equations we find the term Ls, which can be eliminated
when solving the equation.
Us * ton = (Uc - Us) * toff
Us * (ton + toff) = Uc * toff

Uc = (Us * t) / toff
Uc = Us / (1 - d)
The output voltage of the preconditioner equals the input
voltage when the MOSFET is continuous switched OFF, and
increases while the MOSFET is switched ON.
38 6. VsVa supply FTV1.9DE Display Box
6.1 General
6. VsVa supply6.1General
GENERAL
380V
SUPPLIES Vs Va 5V2
5 Vstby-sw Vrs Vra
PDP
PRE- Vrr
CONDITIONER 5 Vstby
Supply on
TEMP
POR
PROTECTIONS
5 Vstby-sw
5 Vstby
POR
1)
STBY FAN-SUPPLY
SND-ENABLE PROT-FAN
V+
SND- DC V-
ENABLE PROD 5 VSTBY-SW
AV- 8V6 5V2 AUDIO

CONTROL AMPLIFIER
FANS
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The supply delivers the power for the display of the FTV1.9, The Va supply
which includes the power for the PDP itself, the PDP LIMESCO The Va voltage is used to supply the power for driving the
panel, the AV controller and the audio power amplifiers, but not addressing electrodes of the PDP.
the standby voltage. The value of Va is also depending on a reference voltage (Vra)
coming from the PDP.
Block-diagram Va = 55V + 5 * Vra(Vra varies between 0 and 2 V).
The Va supply also delivers several other voltages like ;
Both Va and Vs supply circuits are based upon the LLC • + 5 V for PDP , PDP interface panel
converter technology as used • + 8V6 : for AV controller and video controller
in the power supply for MG 98 TOP. • +Vsnd : pos. supply for audio amplifier (+19 V)
The supply consists of four parts: • - Vsnd : neg. supply for audio amplifier (-19 V)
SUPPLY-ON signal : indicates if supplies have to switched on ;
The Vs voltage this signal is
Is used to supply the power of the sustain pulses, which controlled by the protection circuit and the standby signal.
generate the light in the PDP.
The voltage is set by a reference DC voltage (Vrs), coming from The FAN Supply :
the PDP. Provides power for the cooling fans ; controlled by fan speed
Vs = 165 V + 10 * Vrs (Vrs varies between 0 and 2 V). control circuit
Protection-circuitry :
Consists out of an O(ver)V(oltage)P(rotection) , Temperature
protection , Fan potections,
DC protection (Audio Ampl.) and UVLO (input undervoltage
protection).
FTV1.9DE Display Box 6. VsVa supply 39
6.2 The Resonant Power Supply
RESONANCE SUPPLY
+300v
POWER
BLOCK
T1 7005
6007 3014
DRIVER
T2
7006
6008 3017
FEEDBACK
VCC VAUX
FASE
FAULT INPUT SENSING
CONTROL-IC
CONTROLLER
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Block diagram resonance supply Principle
The start-up voltage for the IC is derived from one phase, the The LLC supply is a serial resonance power supply.
IC starts to oscillate and alternately T1 and T2 are driven into The coil, resistor and capacitor form a trap at the resonance
conduction with a dead time in between. frequency Fr. The impedance is frequency dependent. The
This effects that via the resonance circuit and the MOSFETS smallest impedance is at the resonance frequency, at the right
energy is stored into the transformer. side of Fr is the inductive part and the left side capacitive. In
The secondary voltages are rectified and smoothed, these principle the resonance supply could operate at the left side or
secondary voltages is via a voltage divider fed to the the right side of the curve, but the supply works only in the right
optocoupler that influences the oscillator frequency of the part since higher frequencies causes minor losses.
control-IC and stabilises the secondary voltages. If the current The stabilisation is realised by regulating the frequency as
becomes too high then the supply is switched of via the fault function of the mains voltage, the load is stabilised by
input of the control-IC. influencing the series-loop.
The higher the frequency the lower the output power.
Advantages and disadvantages.
Advantages: In practice two methods can be used:
• High efficiency (more then 90%, other supplies 75%). • Method 1: transformer + series coil (Lr ext) + capacitor (Cr).
• Less radiation. This has the advantage of a better optimisation, since the
• Cheaper: two MOSFETS of 400 V are cheaper than one value of series coil can be selected individually and the
MOSFET of 600 V. power-losses are distributed among 2 components. The
• Simpler transformer construction. disadvantage is the size/price of the transformer plus coil.
Disadvantages: • Method 2: transformer with bad 'induction factor' + capacitor
• Very low power stand-by impossible. (Cr). This has the advantage of a smaller/cheaper
• Realisation + stabilisation more complex. transformer, but the disadvantage of a limited Lr and
• Optimising is limited at this moment because of the temperature rise due to dissipation
availability of IC and transformer. Method 2 is realised because this is the cheaper version.
where Lr: leakage induction
Lh: magnetic induction
The coil Lr is the self-induction measured with short-circuited

secondary winding (=leakage-induction); thus the worse the
coupling factor of the transformer the bigger Lr.
Personal notes
The coil Lh is the total inductance of the primary winding minus
Lr.
6.3 Resonant mode controller-IC MC34067
MC34067 Representative Block Diagram

VCC
15
50k 7.0k
Enable / 7.0k Vref
UVLO Adjust 5.1V Vref
9 Reference 5
VCC UVLO
50k 8.0V Vref UVLO
Vref 4.2/4.0V
D1
Q1
Q2
1 Output A
Oscillator Steering 14
R3003 Flip-Flop Power Ground
Q 13
C2004 2
IOSC T
4.9V/3.6V RQ
One-Shot RC
R3004 16 One±Shot
C2005 Oscillator Output B
Control Current 4.9V/3.6V 12
3.1V
3
IOSO R3005
Error Amp R
Clamp Q Fault Input
Error Amp Output 6 S 10
8
Noninverting Input Fault 1.0V
9.0µA Latch
Inverting Input
7 Error Amp
Soft-Start
11
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As control-IC the MC34067P is used for the following reasons : The minimum frequency is reached when Iosc current is zero;
• zero voltage switching C2004 then discharges only via the resistor R3003.
• variable frequency oscillator (above 1 MHz)
• precision one shot timer for the dead time The one-shot timer
• 5 V reference output
• double high current totem-pole output The one-shot timer was developed in order to deactivate both
• soft-start outputs simultaneously and provides a dead time so that one
• wideband error amplifier output will be high.
• fault input (protection) The one-shot capacity (C2005) is first charged by Q1.
The one-shot period begins when the oscillator comparator is
The oscillator switched off by Q1.
The one-shot capacity is discharged via the parallel resistance
The Oscillator circuit is build around the internal OP- (R3004); if this voltage gets lower than the lower threshold of
comparator with 2 threshold-voltages; 4.9 and 3.6 V. C2004 is 3.6 V the comparator will be high and controls the flip-flop,
first charged via transistor Q1. If the voltage across C2004 is which makes one of both outputs high.
more then 4.9 V then the output of the upper of the oscillator If Q1 is reconducted through the oscillator comparator (for the
comparator becomes low, the NOR-port output will be high and oscillator) the one-shot capacitor is recharged.
Q1 will be blocked because the base will be shortened by Q2.
C2004 will be discharged via the resistors R3003 and the Fault detector input
oscillator control current (Iosc). If the voltage across C2004 is
below the lower threshold of 3.6 V, transistor Q1 is conducting At pin 10 there is a fault detector input. If this voltage reaches 1
and the capacitor is charged again. The oscillation frequency is V then the output of the op-amp is high and both drive outputs
modulated by the oscillator control current. are switched off.
The discharge current increases when pin3 MC34067 is loaded In addition, the output of OR3 will be high via the fault latch. The
even more; thus the lower the voltage on pin3 MC34067 the output of OR3 drives Q1 so the oscillator- and the one-shot-
higher the oscillator control current and the higher the capacitor remain charged.
frequency. The maximum frequency is reached when the Via OR3 the soft-start capacitor is discharged.
output of the error amp is minimal (0.1 V). Thus R3005
determines the max freq.
Soft start Protection against overcurrent and overvoltage
Due to the soft-start circuit the oscillator starts with maximum The voltage at R3021 is a criterion for the current, which flows
frequency. through the primary.
The low voltage on the soft-start capacitor (C2008) is buffered Via C2015 and D6010 the negative information is clamped at -
and keeps the error amp. output low (Iosc = max > Fosc = max). 0.6 V.
The capacity is charged with a current of 9 µA, the output of the The total amplitude is rectified via D6009 and C2010 and via
buffer gets high and the error amp. input takes charge of the R3020 and TS7009 supplied to the fault input (pin 10) of the
oscillator control current. controller.
When the fault input is higher than 1 V the protection is
Practical diagram activated (= overcurrent-protection).
The voltage V at R3010 is the take-over winding voltage; this
The start voltage of the IC is tapped from one phase and led to voltage is also supplied to pin 10 of the controller via a voltage
pin15 of the IC. divider R3010/R3011 (= overvoltage protection).
The supply IC begins to oscillate, the voltage on pin 15 is taken
over by the transfer winding (pin 1 & 2 transformer). Since the Soft start overcurrent protection
transformer has a bad coupling factor the transfer winding is
tangled in the secondary, though with a triple isolated wire If short-term overcurrent peaks occur the frequency is adapted.
(TRISO). The voltage at R3021 is clamped at -0.6 V via C2015 and
Via R3026 the Vs can be adjusted and stabilised. Via the D6010.
alignment/stabilisation for Vs the output voltages are also The total amplitude is rectified via D6011 and C2008 and
stabilised. supplied to the "capacitive" thyristor T7017/18 via R3012.
The Vs is fed via a voltage divider to IC 7110 When the voltage at the emitter of T7017 gets higher than 5 V,
If the voltage at pin3 IC7110 is higher than 2.5 V a current will the soft-start capacitor is discharged, and the frequency
flow from cathode to anode. This current flows also through the increases as a result of which the Vs drop.
secondary of the optocoupler. If this voltage remains 5 V the supply is interrupted (hick-up).
The voltage at pin7 of the MC34067 determines the output This circuit is adjusted in a way that the voltage does not drop
frequency, the higher this voltage, the higher the output- too much if a flash occurs.
frequency. That results that in case of increasing Vbat the
voltage of pin7 increases; the frequency increases and Vs
decreases.
When the output voltage rises, the voltage at the reference IC
7110 also rises, which causes the current through the diode of
the opto-coupler to rise. The transistor of the opto-coupler
conducts more, as a result of which the voltage at pin 7
MC34067 increases.
The output voltage of the error amplifier gets lower, and the
current through R3005 increases.
Driver stage
The two secondary windings of the driver transformer are

wound in opposite directions and control the two switching
MOSFET's.
The primary winding of the driver transformer is alternately
controlled by the two totem-pole outputs of the controller.
Cross-conduction of both MOSFET's is prevented by the dead
time.
The gate of each MOSFET is controlled via the resistors 3014/
3017 and via the diodes 6007/6008; the transistors 7007/7008
discharge the gate faster by switching off. The diodes at the
basis-emitter of 7007/7008 prevent the zener-effect of these
transistors. The zener diodes at the gate-source of 7005/7006
are for ESD.
C2011 and C2014 form the capacity for the series resonant
circuit.
6.4 Voltage/current waveforms of the resonance-circuit
Vi
S1
D1
Lr
Br1
S2 Lp
+
D2 Cs
Cr
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The total switching time can be distributed over 12 phases with

different current paths.
Only 4 phases are discussed to simplify the explanation.
In the 4 phases we have 3 different positions of the switches.
1. Switch S1 is closed, Switch S2 is open
2. Switch S1 is open, Switch S2 is open ( Dead time )
3. Switch S1 is open, Switch S2 is closed
Phase 1:
s1 closed, s2 open
The gate of MOSFET 1 is positive which causes S1 to be
closed.
The input voltage Vi of 380 VDC provides a current flow through
S1 and the series circuit.
At the same time a current flows through the bridge rectifier in
the secondary winding which charges capacitor Cs.
The current through Lr starts negative, but it is increasing to
change polarity
Capacitor Cr is charged sinusoidal, while the voltage at Lr drops
which makes the current drop.
Vi
S1
D1
Lr
Br1
2
S2 Cp Lp
1 +
D2 Cs
Cr
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Phase 2:
S1 open, S2 open (dead time)
Both MOSFET's are not conductive.
Personal notes
The current through the coils wants to continue. The capacity
Cp releases its load to the series circuit, and the voltage at Cr
continues to rise. (Cp is the sum of several parasitic capacities).
The voltage at the drain of MOSFET 2 drops because Cp is
discharged at this moment. This causes a voltage inversion
across Lr and Lp. The secondary winding begins to feed back,
charging capacitor Cs.
The voltage becomes negative, and diode D2 start to conduct.
The secondary bridge remains conductive.
Vi
S1
D1
Lr
Br1
S2 Lp
+
D2 Cs
Cr
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Phase 3:
S1 open, S2 closed
The gate of MOSFET 2 is becoming high. The current through
Personal notes
D2 is taken over by MOSFET 2. The switching losses are
neglectible, due to the fact that the voltage across the switch is
now approx. 1V.
The current through Lr starts negative, but is increasing to
change polarity. A current flows through MOSFET 2 and the
series circuit. The bridge remains conductive but its current
gets zero because of the decreasing voltage across Lp. This is
caused by the discharge of capacitor Cr. The voltage at
capacitor Cr is decreasing sinusoidal and so is the voltage
across Lp and Lr.
Vi
S1
Cp 1
D1
2
Lr
Br1
S2 Lp
+
D2 Cs
Cr
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Phase 4:
S1 open, S2 open ( Dead time )
Both MOSFET's are not conductive.
Personal notes
The current through the coils wants to continue. The capacity
Cp releases its load to the series circuit, and the voltage at Cr
continues to fall. (Cp is the sum of several parasitic capacities).
The voltage at the drain of MOSFET 2 increases because Cp is
discharged at this moment ( Cp was charged to 380V ). This
causes a voltage inversion across Lr and Lp. The secondary
winding begins to feed back, charging capacitor Cs.
The voltage becomes higher than 380V , and diode D1 start to
conduct. The secondary bridge remains conductive.
6.5 Vs Supply
6.5 Vs Supply
Vs SUPPLY
Vs
Vs
OUT GND
HF- CONTROL
BRIDGE CIRCUIT
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Control is done in the usual way by a TL431 at the secondary

side. Vrs is mixed into the feedback voltage using an additional
TL431 (7011 at schematic FD2). Vrs , a signal coming from the
Personal notes
display, influences the output of the Vs supply. The output
voltage of the Vs supply varies between 165V when Vrs is 0V
and 185V when Vrs is 2V.
Accurate Overvoltage Protection is added, using a TL431
(7012) as reference/comparator and an additional optocoupler
(7003) that acts on the fault input pin 10 of the MC34067P. See
also TM Monitor at Ch4.6 - Protections.
6.6 Va supply
6.6 Va supply
Va SUPPLY
V+
AUDIO GND
Audio
N.C.
SUPPLY V-
Va
Va
OUT
8V6
STAB.
5V2
HF- CONTROL
BRIDGE CIRCUIT
GND
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For this supply the same design philosophy as for the Vs supply
has been adopted. Main difference is the switching frequency,
which is between 50 and 73 kHz (depending on actual output
Personal notes
voltage).
Vra is mixed into the feedback voltage using an additional
TL431 (7111 at schematic FD1). Vra , a signal coming from the
display, influences the output of the Va supply. The output
voltage of the Va supply varies between 55V when Vra is 0V
and 65V when Vra is 2V.
Accurate Overvoltage Protection is added, using a TL431
(7112) as reference/comparator and an additional optocoupler
(7103) that acts on the fault input pin 10 of the MC34067P. See
also TM Monitor at Ch4.6 - Protections.
6.6 Va supply
Audio Supply
Personal notes
It is a floating symmetrical supply for the Audio Power Amplifier.
Due to the fact that this voltage is tightly coupled to the Va
voltage, this voltage varies considerable, between 15.0 V (full
load, Va = 55 V) and 20 V (no load, Va = 65 V).
The Audio ground can be connected to the normal secondary
ground (ground B in the diagram) with a capacitor and a resistor
in parallel, to have the possibilities to suppress spurious
oscillations.
17V supply
The second output voltage serves as power supply for the 5 V

down converter, supply for the Fans and several other auxiliary
circuits. Also this voltage varies with Va, and the levels are
identical to the Audio supply voltage. (This output is called 17 V
on the circuit diagrams.)
6.7 The 5 V down converter.
6.7 The 5 V down converter.
5V DOWN CONVERTER
5207
2201
5201
1m
GNDB
3206
CU20v *3u3 7203
L4940
4K7
7201
3201
15K
1
4
2
5
10
13
1K 3393
2209 100n
L4977A 9 13 4 6
3099
2202
1R
VI
SYNC
RESO
BTS
2212
100u
2213
100u
15
VST
2u2 3 7 6204
GNDB RESI OUT
2u2
2210
14 BYD33D GNDB
1n
VREF
5206
ROSC
COSC
3211
100K
RESD
83R
FDBI
GND
FRC
2203
SST
2223
100n
BZX55-C6V2
GNDB GNDB
3202
10K
1103
PBYR745F
5202
2211
6205
1m
12 5 8 10 1 2 11
2320 1n 6203
10u
4A *
3205
3212 10K
MP
1N4148
GNDB BC557B
3214
470K
39K 2n2
2208
6207
7372
15R
3213
2205
3204
10K
2u2
GNDB
2204
5208
100u
100u GNDB
2224
100n
3215 BC547B
7205
BT151X-500R
10K BC557B
390p
2207
7204
2n7
2206
3216 3217
7202
10K 10K
2214
100n
100R
3207
3203
1K
GNDB
CL 96532069_079.eps
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The required 5 V for the AV control and the PDP is made out of The coil 5201 of this down-converter has an auxiliary winding.
the 17 V. The topology is a down converter in the continuous This voltage is rectified and the resulting voltage is added to the
current mode. Control and switch are incorporated in IC 7201, 5 V output voltage. Due to variations of the 5 V load this voltage
which is the L4977A. is not stabilised sufficiently. So a linear voltage regulator (7203)
is added. To achieve the highest efficiency it is a low drop
It has all functionality on board, like: version, that directly delivers 8.5 V (type number L4940-8V5).
• Over Current Protection (at 9 A typ.)
• Reference voltage,
• Programmable slow start,
• Programmable oscillator,
• Bootstrap diode,
• Reset input
This input also serves as an indication that both the input

voltage and the output voltage of the converter are within the
specified range. By consequence the IC gives an indication
whether to power source is OK or not.
The L4977A lacks one protection against short circuit of the
switch inside the IC. If that happens, the output voltage
becomes equal to the input voltage. In order to prevent that, a
voltage higher than 5.8 V (typ.) is detected via 6205 and
thyristor 7202 is fired. This thyristor will cause a fuse to blow,
and the outputs of the converter will drop to zero, thus
preventing the circuits that are supplied by this converter to be
damaged.
6.8 Vrr delay.
Vrr is a logical signal ("high" in normal circumstances) that

6.8 Vrr delay.
comes from the PDP. Its purpose is to activate the switch- off of
the supplies in case Vrr becomes "low"
Personal notes
Vrr is "0" during start-up. So an additional circuit, around 7301,
has been designed to prevent the "0" of Vrr to influence the
behaviour of the supplies during approx. 3 seconds.
The Vrr signal is directly fed through to the µP for fault
diagnostics.
6.9 Fan control.
In the monitor 6 fans are implemented. In order to decrease the

6.9 Fan control.
fan noise as far as possible the fan speed is controlled

according to air temperature.
Personal notes
A NTC temperature sensor senses the temperature of the
incoming air (Tair). Based on this temperature, the fan speed is
controlled by controlling the voltage across the fans. The fans
are 12 V types, which can also run on lower voltage (though
that is not specified in the specification of the fans). The lowest
speed is at a fan voltage of 5 V, the highest at 12 V. The sensing
circuit, built around a LM358 Opamp, is designed in such a way,
that at air temperature up to 25 degree C. the fan voltage is 5
V. Above that temperature the fan voltage rises linearly with
temperature, and reaches it maximum of 12 V at Tair = 45
degree C. The fan control circuit is powered from the 17V.
Because of the fact that this voltage is varying, a special circuit
is designed. The fan voltage is clamped to 12 V, in order to
prevent damage to the fans.
In order to be able to verify whether the fans are running or not,

a fault detection circuit is implemented for each fan individually.
Two types of fault detection are supported. The simplest way of
detection is a logical signal that is low when everything is OK
and high when a fault occurs. The other way is that a running
fan gives pulses in the same speed as the rotation of the blades
of the fan. In that case a detection has to be made whether
there are pulses or not. In the circuit that is detected using
detection of the rising edge of the pulse. The rising edge
triggers the discharge of an elcap (C2306). The elcap in turn is
charged through a resistor. When for a longer time no pulses
appear, the voltage across the elcap rises above a critical level,
and the protection is activated (via D6323). The actual circuit
implemented is for a fan with pulses (e.g. SUNON), but
provision has been made for adaptation to the other protection
philosophy, by just omitting most of the components and adding
a bridge wire (the PCB is prepared). The time constant is
chosen such that at start-up no problems occur, while a fault is
detected well within one second.
6.10 UVLO-protection.
6.10 UVLO-protection.
Under Voltage Lockout Circuit
6026
380 Vcc2
1004 5003 13
* 1N4148
12
T 2A/250V 6025 150u
2001
47u
1N4148 * 3059 3001
* 6 16
3062
47K
22K FD46 22K
*
220R
3060
3063
2M2
GNDA 4 15
7014
BC547B
3002 6002 6001 5004 1N4148 * 14
*
6024
22R BYD33D BYV27-200 6u8 6030
1
11
*
2003
2002
2
47u
1m
BZX55-C6V2 7015
56K
GNDA 10
3061
BC547B
GNDA 9
GNDA GNDA
GNDA GNDA
5002
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General: The Protections are described at Chapter 4.6 of this

Training Manual : Protections.
Personal notes
Both Vs and Va supplies have an OverVoltageProtection
(OVP). They are very accurate and use a separate voltage
sensing circuit around additional TL431's. When activated a
small thyristor is fired, and this in turn controls an optocoupler.
The receiving side of the optocoupler is connected to the fault-
input pin of the MC34067 control IC's at the primary side. The
optocoupler and the thyristor are fed by the 5V standby-
switched. By consequence they are latching, preventing the
supplies to hickup.
Under voltage lockout circuit
In order to prevent an uncontrolled hick-up after switching off

the monitor, and/or putting it into standby, an Under Voltage
Lockout circuit is implemented, that prevents the functioning of
the control IC by diverting the starting current (Vcc ) to ground
when the input voltage is below approx. 200V. In this way the
supply voltage of the IC will be below it's own UVLO. The
detection is done with the circuit around T7014 and T7015.
7.
54
Audio video control
VGA-OUTPUT
15 poles
RGB_IN_VGA RGB_LT_VGA RGB OUT (3*)
RGB
HS_SYNC (5*) VGA_INPUT HS_SYNC (5*) 2X
15 poles BUFFER
VS_SYNC VS_SYNC
CONFIG_IDENT AVC36
Loop through H_SYNC_OUT (2*)
AVC32 VGA Output
FBOX_MODE_INPUT BUFFER
VGA Input V_SYNC_OUT to external
from UART_OUT/DDC (2*) HS_SYNC_BUFF (2*)
monitor
E-box or PC
DIS-RC5 FBOX_MODE_OUTPUT
BUFFER RGB_VGA (3*)
+5V_STBY_SWITCHED
CONNECTOR VIDEO CONTROL
CONTROL
5 poles
BLOCK 5 poles
AVC05 AVC01
to +5V to RGB_VGA
Vs/Va to PDP RGB (3*) 23 poles
CONFIG_IDENT RGB_YC VIDEO BUFFER
supply Limesco
CONTROL
FBOX_MODE
+5V _INPUT RGB_BLACK_FEED (3*)
13 poles
8V6
UART_OUT/DDC UART_OUT AVC02
CONTRAST to PDP
STANDBY DDC/SDA
INPUT/OUTPUT_CLAMP (2*) Limesco
SND_ENABLE H, V_SYNC SDA, SCL (2*)
Monitor muP panel _BUFF (2*)
AVC04
to +5Vstby muP H, V (2*)
P87C695 H, V_YC
Vs/Va
UART_IN/DDC
supply POR SDA,SCL (2*)
DDC/SCL VGA_YC_MODE
PROTECTION_STATUS
EBOX_PRESENT
POK
+5Vstby_switched DIS_RC5 AUDIO DELAY AUDIO CONTROL AUDIO FILTERING
9 poles L_HIGH 7 poles

+5Vstby_switched L_AUDIO_YC HPF
MAIN
3 poles L_BYPASS
DIS_RC5 DIS_RC5 SCART L
AVC89
L L_MID_LOW To audio
POK L (optionally) DBE LPF
AVC10 LED_GREEN POK DELAY AUX amplifier
L_
to DELAY
SND_ENABLE
7. Audio video control
LED AUDIO
LED_RED
panel DEMUTE SDA_NVM (2*) CONTROL
SCL_NVM R_ R_HIGH
AUDIO/VIDEO CONTROL
display +5V +5V 1/2 AVC35 R

R HPF
SDA, SCL (optionally) DELAY AUX
SND_ENABLE DELAY
R
+5Vstby
Service R_BYPASS R_MID_LOW
AUDIO INPUT SCART DBE LPF
3 poles
MAIN
AVC34 SDA, SCL (2*) R_AUDIO_YC
service REQUEST
NVM
CLOCK (3*) 3 poles
15 poles SDA, SCL (2*) DATA L L
SDA, 1/2 AVC35
AUDIO
SCL (2*) R R Audio
MUTE
RGB_YC Output
AVC12
H,V_YC
to YUV
connector
panel L_YC
SND_ENABLE
R_YC
110899
CL 96532069_054.eps
(*)= NUMBERS OF WIRES
FTV1.9DE Display Box
FTV1.9DE Display Box 7. Audio video control 55
The Audio Video Control board provides the interface of the

Display Box for Audio, Video and Control signals.
At this panel the Audio, Video and Control (UART or DDC)
Personal notes
signals enter the Monitor.
These signals will be buffered and are available at the output of
this panel for feedthrough (except the control signals).
The same signals will be fed to the Audio part (including an
optional audio delay to correct the timing between video and
audio) and to the video control IC to control the RGB signals.
Also the µP for the panel control in the Monitor is located on this
board.
The audio filters for the high and low/medium signals are also
located on the AVC board.
The AVC interfaces the following signals:
Internal:
• RGB/SYNC signals to/from PDP LIMESCO panel.
• RGB/SYNC/Audio signals from YUV/YC Input panel.
• Control signals (for power supply) from/to VS/VA SUPPLY
panel.
• Audio signals to audio amplifier.
External:
• RGB/SYNC/UART/CONFIG_IDENT and RC-5 in case of a
Receiver Box via sub_D connector.
• RGB/SYNC/DDC in case of a Personal Computer via
sub_D connector.
• RGB/SYNC loop-through via sub_D connector (e.g. for
additional Display).
• Audio in L and R via CINCH connector.
• Audio loop-through L and R via CINCH connector.
The AVC board has no predefined service position, as it is

surrounded by other panels and it cannot be hinged due to the
fact that the connectors are located all over the panel.
Development made, for that reason, all service testpoints
available at the B-side (reflow side).
As the component placing is very dense, service printing was
very difficult to realise. Therefore the testpoint overview of this
panel, which can be found in the Service Manual, is of utmost
importance in order to service this panel.
56 7. Audio video control FTV1.9DE Display Box
7.1 Audio signal processing
The audio part is divided into several sections.

1. An (optional) audio delay to correct the timing between

video and audio.
Personal notes
2. Audio control for the source selection and volume function.
3. Filters to split the audio signals in high and medium/low
frequencies and Dynamic Bass Enhancement (DBE).
4. Audio mute.
The output signals are fed to the audio amplifier.
Audio delay (optional)
To compensate for 'lip sync error' (the difference in time

between the aural and visual perceptions), audio delay was
designed in during initial development.
The L/R audio input signals are delayed digitally by two IC's
(7910 & 7920), which are controlled by a special M(itsubishi)-
bus connected to the µP.
Because the FTV 1.9 has no PALPLUS, so less delay in the
video signal, this feature was not necessary. That is why it was
made optional (it is disabled by using jumpers 4930 and 4931).
AUDIO CONTROL
AVC35
L_AUDIO
L_AUDIO_OUT
AUDIO
R_AUDIO MUTE
R_AUDIO_OUT
TDA9860
7940 26 7 20 13 22 21 19 25 17 16
4930 2915 L R
28 MAD SDA SCL 31
L
headphone
470n
AUX channel IIC - BUS
2935 volume CONTROL
30 R
2
4931
470n
INPUT SELECTOR
2948 1
L
470n (RES)
SCART
2949
32 R
470n (RES)
2950 3 R
L
L 18 L_AUDIO
470n STEREO
MAIN L
2951
5 R
SPATIAL
BALANCE
VOLUME
STEREO
TREBLE
470n
BASS
TO FILTER
PSEUDO
6 REFERENCE STEREO
VOLTAGE 15 R_AUDIO
R FORCED
MONO
4 8 24 9 23 10 29 27 11 12 14
3981 3983
3K9 3K9
3982 3984
8K2 8K2
2982 2984
10µ 10µ CL 96532069_043.eps
110899
Audio control
Personal notes
The audio input signals at CINCH connector AVC35 are directly
fed to the audio control IC.
The L/R_AUDIO_YC (at internal connector AVC12) signals
coming from the YUV/YC Input panel are fed to this IC as well.
This audio control IC, which is I2C controlled, consists of:

• an input selector for the direct L/R signals or the delayed L/
R signals (optional),
• a L/R constant level signal to the audio output (CINCH
connector AVC35),
• a volume control (tone control optional or via E-box) with L/
R_AUDIO output.
The undelayed L/R_AUDIO signals (variable level) are fed to
audio filtering part.
HPF
+4VA
+8VA
3236
7250-A AVC89
3 8
LM833N
3205 L_HIGH
2236
1 To audio
15p
2203 3237 amplifier
2 100R
L_AUDIO
(from audio control) 10n 3K9 4
3238
33K
2238
47p
CL 96532069_044.eps
140799
Filters, DBE
Personal notes
The audio signals are filtered before the amplifier. There are
some reasons for doing this:
• it is now easy to do active filtering and
• at less costs (no expensive coils and capacitors).
L/R_HIGH:
For L and R separately a High Pass Filter (IC7250A & B) is
processing L_HIGH and R_HIGH.
The f-3dB for this filter is determined by R3237 and C2203 (for
the Left channel).
The output signal of this HPF is fed to the audio amplifier board
via connector AVC89.
For the Right channel the circuit is identical.
LPF & DBE
+4VA
3200
39K
From +8VA
Audio
control 2200 2201 3 7200-A +8VA AVC89
8
L_AUDIO LM833N
680n 680n 3202 7200-B
2202
1 5 8
15p
LM833N
3213 1K 3205 L_MID_LOW
2205
2 7 To audio
15p
4 amplifier
390R 6 100R
2204
100n
3212 3201 4
2207
10u
1K 1K 3207 3206
2231
1K 1K
+8VA 47p
2212
10u
2234
2237
10u
47p
3211
4K7
6200 2215
3209 3208
100K BAS216 4K7 2u2
BAS216
3210
330K
3242
2206
6208
10K
7202
2u2
BC847B
7203
BC847B
CL 96532069_045.eps
240899
L/R_MID_LOW and DBE:

A Dynamic Bass Enhancement (DBE) circuit, with opamp
LM833 and Low Pass Filter, processes the signals
Personal notes
L_MID_LOW and R_MID_LOW:
The audio signal coming from the TDA9860 enters a bandpass
filter (T-filter), consisting of C2200, C2201 and R3211 in series
with R3210, which is tuned at a frequency of 65Hz (the
resonance frequency of the speaker).
The Q-factor of this filter can be influenced by chancing the R-
value. Low R means low Q, high R means high Q-factor.
In this circuit, the R-value can be influenced by steering
transistor T7203.
The output signal of IC7200A is fed to a LPF (IC7200B) with a
fixed f-3dB via R3202 and C2204.
The output signal of this filter is then fed to the AUDIO
AMPLIFIER board via connector AVC89 but also to a feed back
loop. Here the signal is rectified by D6200 & D6208, then
integrated by a RC network (load via R3208/C2206, unload via
R3209/C2206) and finally fed to T7202.
When the signal amplitude is high enough, this transistor drives
'diode' T7203 and thereby regulates the R-value of the T-filter
by shorting R3210. This results in a low Q-factor, so a flat
response around 65Hz.
DBE frequency characteristic
MAG
HPF
DBE
LPF
10 100 1000 10000 Hz 100K

65Hz
CL 96532069_001.eps
110899
However with low signal amplitudes, where you need DBE,

T7203 is not activated, resulting in a high R-value (R3211 +
R3210) and so a high Q-factor. The filter will now enhance the
Personal notes
signal around 65Hz. So in this way the low frequencies are
dynamically controlled.
From R_AUDIO
AUDIO MUTE
Audio
L_AUDIO
Control
100K
3968
7968
BSH103 AVC35
6967 3953 6 0335-B
BAS216 150R
4
R_AUDIO_OUT
6951 6950
6969 5 L_AUDIO_OUT
BZX284-C33 BZX284-C33
BAS216
BSH103
100K
3966
7969
+5Vstby
100K
3970 7972
BSH103
100R
3967
6970 3958
BAS216 150R
6960
BC857B
BZX284-C33
7965
6968
6961
BAS216
BSH103 BZX284-C33
7971
100K
3978
SOUND ENABLE
CL 96532069_046.eps
110899
Audio mute
Personal notes
The display can go from STANDBY MODE to ON and vice
versa (TV-Configuration version). In order to avoid audible plop
in the left and right CINCH output signals, an audio mute circuit
has been implemented. The audio mute circuit is controlled by
the POWER_OK (POK) signal.
When the set will be switched ON, first all the power supply
voltages become available. After this, the POK signal will
become active, and the audio signal will be de-muted.
While the POK signal is not available, the audio will be muted
by the SOUND_ENABLE signal, which again is controlled by
the DEMUTE signal of the µP.
For the actual mute circuit, use has been made of MOSFET's
to handle the rather large signal amplitudes of 2Veff.
Also when there are no sync pulses available, the audio must
be muted. When these pulses become available again, the de-
mute sequence will be as follows:
de-mute the audio amplifier by the mute pin,
5. de-mute the audio processor by the SOUND_ENABLE
signal and
6. then increase the volume stepwise to the last status value.
7.2 Video signal processing
RGB CONTROL
[to PDP-LIMESCO]
AVC02
10 CONTRAST
7300 LIM
GM1 GM2 GM3
SDA SCL
TDA4885 17 12 13 14
data
[from MONITOR uP]
VGA_YC_MODE
6-BIT 6-BIT
I2C-BUS MODULATION
DAC DAC
8-BIT 8-BIT 8-BIT CHANNEL 3 22
DAC DAC DAC REFERENCE N.C.
REGISTER 4-BIT BLANKING CHANNEL 2 27
[VGA IN] LIMITING DAC FPOL REFERENCE N.C.
6-BIT 6-BIT 6-BIT
AVC32 FPOL DAC DAC DAC CHANNEL 1 32
7360 DISV POLARITY REFERENCE N.C.
DISO SWITCH VP1
29
R_VGA 3 PEDST
1 4 R 6 INPUT- CONTRAST
signal path 1
GAIN
5 CLAMPING 30 VO1
BLANKING
CLIPPING BRIGHTNESS
2 R_VIDEO
OSD- PEDESTAL 28 FB1
CONTRAST BLANKING
31
1 R_BLACK_FEED
VP2
G_VGA 1 G PEDST
24
2 15 8 INPUT- CONTRAST
signal path 2
GAIN
2 CLAMPING 25 VO2
BLANKING
BRIGHTNESS PEDESTAL
5 G_VIDEO
CLIPPING
OSD-
BLANKING 23 FB2
G_BLACK_FEED
CONTRAST 4
26
19 VP3
B_VGA 13 PEDST
3 14 B 10 INPUT- CONTRAST
signal path 3
GAIN
12 CLAMPING 20 VO3
BLANKING
CLIPPING
OSD-
BRIGHTNESS PEDESTAL
8 B_VIDEO
CONTRAST 18 FB3
blanking
BLANKING
7 B_BLACK_FEED
21
HS_SYNC input clamping

PEDST
13
VS_SYNC fast blanking SUPPLY
14 OSD-INPUT DISO INPUT CLAMPING
VERTICAL BLANKING
DISV
BLANKING
OUTPUT CLAMPING
TDA4885
[from YUV- 1 2 3 4 7
VP
9
GND
YC-INPUT] FBL OSD1 OSD2 OSD3 5 11
CLI HFB OUTPUT
AVC12 15
CLAMP
R_YC 1 7370 INPUT
G_YC 3 16
2 CLAMP
B_YC 5 15 H
5 18 H
HS_YC 8
1 V
VS_YC 9 4 20
3 V
CL 96532069_047.eps
240899
The video part is divided into the following sections which will Feedback signals
each be described below:
1. Source selection The video control IC, is provided with a black level feedback via
2. Feedback signals signal RGB_BLACK_FEED coming from the gamma amplifier
3. Signal loopthrough on the PDP Limesco panel. This to ensure proper DC-coupling
The output signals are fed to the PDP Limesco panel between the two panels.
Furthermore there is a CONTRAST control feedback from the
Source selection PDP LIMESCO, which controls the Peak White Limiter.
Also an INPUT and OUTPUT CLAMP pulse is required. These
Incoming signals, from Receiver Box or PC, are entering the are also generated by the PDP LIMESCO.
Display Box via a sub_D connector (AVC32).
The RGB signals R/G/B_IN_VGA are fed to a source select
switch (IC7360), which selects the
normal RGB_VGA or a separate RGB_YC signal, coming from
the YUV YC INPUT panel.
The source select output signals are fed to the high bandwidth
(35MHz bandwidth @ -3dB) video control IC (IC7300) with I2C
control.
The RGB output signals from this IC are buffered via discrete
transistors and fed to connector AVC02 which is connected to
the PDP LIMESCO panel.
The belonging sync pulses, HS_SYNC and VS_SYNC, are
buffered via two Schmitt triggers, after which they are fed to a
source select switch (IC7370) as well, which selects the HS/
VS_SYNC_BUFF or the HV_YC signals coming from the
additional YUV/YC Input panel.
RGB BUFFER
8V6
3810
4R7
+8VC
330R
100K
3812
3811
2811
470u
2810
22n
2812 BC557B
R_LT_VGA
7810
7811 AVC36
10u
BC847B
3814 3813 R_OUT
VGA Output
150R 75R
150R
3816
3815
22K
CL 96532069_048.eps
110899
Signal loopthrough
Personal notes
The same RGB_IN_VGA signals are directed via the RGB
buffers (with two times amplification and 75 Ohm output
impedance) to the VGA OUT connector (AVC36).
The belonging sync pulses HS_SYNC and VS_SYNC are
buffered as well via two Schmitt triggers in series and fed to the
same sub_D connector.
7.3 Control signal processing
TV CONFIGURATION
VGA_IN
AVC32
CONFIG_IDENT
µP
UART_OUT UART_IN
DDC/SDA
UART_IN/DIS_RC5
UART_IN
LED PANEL DDC/SDL
AVC10
DIS_RC5 EBOX_PRESENT
CL 96532069_003.eps
240899
The circuit consists of the Monitor Microprocessor panel, on • Monitor only configuration: a PC connected to the Display
which the µP P87C695 is located and a Non Volatile Memory Box.
(NVM), to control the AV-Control and the PDP LIMESCO
panels via I2C (internal). When there is no valid response on the CONFIG_IDENT pulse,
the µP will select the DDC_IN/OUT bus (via EBOX_PRESENT)
The control part is divided into the following sections which will for communication with the µP (in the Personal Computer).
each be described below: The DDC protocol is based on the I2C protocol.
1. Configurations The DIS_RC5 signal is now routed directly to the µP of the
2. Monitor µP panel Monitor.
3. Non Volatile Memory (EAROM)
4. Mode detection
Configurations
There are 2 configurations possible:

• TV configuration: a Receiver Box connected to the Display
Box.
Communication between the 2 microprocessors, is based on

UART and not on I2C. This has been done to handle the VGA-
cable length of (max ) 15 m.
Via the CONFIG_IDENT pulse (3 level handshaking), which
must be generated every 500 ms, the µP in the Display Box
detects the presence of the Receiver Box. When there is a valid
response, the UART_IN/OUT bus is selected via the
EBOX_PRESENT signal. Now the Receiver Box will tell the
Monitor the corresponding video mode via UART.
At the same time the DIS_RC5 signal is routed to the VGA
connector in order to control the µP in the Receiver Box.
Monitor µP panel Non Volatile Memory
The initially chosen µP, the P87C380 had, during design Following data is stored in the NVM:
progress, not enough memory capacity. Therefor a new µP was
necessary. This new processor could not be placed on the AV
Control board without the need for an (expensive) PWB Group Attributes
change. Therefor it was decided to develop an 'add on' PWB for
Audio Volume
this new microprocessor (P87C695).
Mute
This µP works on 3.3 Volt, so an extra power supply IC has
been added on this board. Delay
Also a better accessible SERVICE MODE connector has been Video Contrast
added (due to this extra PWB, this connector was not longer Brightness
accessible on the AV control board. See also chapter 7.4). Decoder Hue
Decoder Saturation
µP input signals: Decoder contrast
• DEMUTE : signal for triggering the audio Decoder brightness
mute circuit. Decoder peaking
• CONFIG_IDENT : detects if a Receiver Box is
H shift
connected.
V shift
• FAN_PROT : becomes active if one of the fans
White point R
is malfunctioning.
• POWER_OK : becomes active if all power White point G
supply voltages are available. White point B
• POR : Power On Reset pulse. To be Decoder white point R
sure the µP starts from an initialised status. Decoder white point G
• PRotection_STATUS : combined signal for detecting Decoder white point B
several protections. Black point R
• STANDBY : controls the power supply in case Black point G
of malfunctioning. Black point B
• UART-IN : communication bus between
Colour temperature
Receiver and Display box.
Aspect ratio
• VRR :feedback signal if PDP is
Video format
switched on.
Last colour system
µP output signals: Anti ageing H position VGA
• EBOX_PRESENT :becomes active when a Receiver Anti ageing H position
Box (E-box) is connected. Anti ageing V position
• I2C bus(ses) : for NVM, local. General Operation hours
• LED green : status signalling. Error codes
• LED red : status signalling. Service default mode
• UART_OUT : communication bus between Last Source
Receiver and Display box.
• VGA_YC mode : becomes active when a PC is Mode detection
connected.
• WRite COntrol : for NVM control. The VGA input related sync pulses HS_SYNC/VS_SYNC are
buffered and fed to the µP for mode detection.
Some µP I/O pins are used to control the correct start up Mode detection is done based on H/V frequencies and
procedure: POK, VRR, STANDBY, SOUND_ENABLE, and one polarities.
combined PROTECTION_STATUS pin for For the E-box mode, the FBX- or the HDIO mode (USA only),
OVER_TEMP_PROT, FAN_PROT and DC_PROT. an UART command will be send from the Receiver Box to the
Monitor. However when 2 Monitors are connected in
loopthrough, the 2nd one must detect these modes by itself:
• FBX mode can be detected by fv=60Hz, fh=32kHz, negative
H-sync (see TM AV Buffer) and positive V-sync,
• HDIO mode can be detected by the fact that the signal is
interlaced.
When there is no sync input, a free-running H and V frequency
mode is available: 32kHz and 60Hz. This is necessary to
reduce the frame flicker, to generate a stable OSD and for test
picture generation.
7.4 Service
7.4 Service
ComPair
TOPVIEW B-SIDE
AVC39 AVC39
5 4 5 4
6 3 6 3
7 2 7 2
8 1 8 1
DEFAULT ComPair
CL 96532069_005.eps
240899
ComPair
Personal notes
For service purposes (ComPair) there is an I2C control
connector AVC34, to be used in combination with a hardware
switch (jumper setting on connector AVC39) to connect this
'normal slow' I2C bus with the 'NVM' I2C bus.
This is done to be able to read/write in the NVM.
For detailed information on Error codes etc. see chapter
PROTECTIONS.
Entering ComPair mode:

1. Switch Display 'OFF'.
2. Disconnect Receiver Box if connected.
3. Connect ComPair cable with connector AVC34.
4. Remove default jumpers on connector AVC39 and re-
connect pins 1 with 2 and 3 with 4.
5. Switch Display 'ON'
Leaving ComPair mode:

1. Switch Display 'OFF'
2. Remove ComPair configuration jumpers: replace default
jumpers (pin 2 with 7 and pin 3 with 6 of AVC39).
3. Remove ComPair cable
4. Switch Display 'ON'
7.4 Service
SDM / SAM
TOPVIEW B-SIDE
MUP37
5 4
6 3 SAM
7 2 SDM
8 1
CL 96532069_009.eps
240899
SAM/SDM
Personal notes
In Monitor only configuration, the display can be set to Service
Default Mode (SDM) or Service Alignment Mode (SAM) by
short-circuiting the relevant pins of connector MUP37 on the
Monitor µP panel, or by RC5 (via the DST).
SDM: short-circuit pins 2 and 7.
SAM: short-circuit pins 3 and 6.
68 8. PDP LIMESCO FTV1.9DE Display Box
8. PDP LIMESCO8.1Functional Block Description
PDP LIMESCO PANEL
EPLD
contrast (via Limesco) filter
black feedback(3)
R,G,B (a)(6) Gamma

23 poles
PD02 R,G,B(a)
H/V
ok(4)
Underflow/
H/V polarity LPF ADC level
change to
positive 5V
(EPLD)
A/D PLLA:
TDA8714/6 74HCT9046
I2C(3) 5V
R,G,B(d) pix
3.3V pix clock
divide
Limesco
I/O expander Freerun uPD93687G
for mode info clock 4MHz. D-LBD
pix clock
(CKD)
R,G,B(d)
pix
divide
OSD CKD
MC141585
H/V/Nblank
5V PLLD : 74HCT9046
H/V-protection
(EPLD)
FLEX6k
5V
H/V/Nblank
3V
5V(*2) 5V to 3V
connector
PD01 R,G,B(d)
GND (*2)
Hirose 68 poles PDP connector PD03
CL 96532069_111.eps
270799
FTV1.9DE Display Box 8. PDP LIMESCO 69
8.1 Functional Block Description
The PDP LIMESCO board has to do the following tasks:

• Anti gamma correction.
• Digitising the RGB signals.
Personal notes
• Converting different standards to the format required for the
Plasma Display Panel (PDP).
• Add OSD information to VGA signals.
This is done in different steps, which will be described below.
The RGB signals, coming from the AV-Control board, enter the
PDP LIMESCO board through connector PD02. They are fed to
the gamma correction circuit, which corrects the gamma for the
linear plasma display (i.s.o. the non linear CRT).
Then the signal passes a Low Pass Filter, which obscures
some effects produced by digitising the signal.
The signals are digitised by the 8 bit ADC's (Analogue to Digital
Converters).
Now the different standards that can be sent to the LIMESCO
have to be converted to a format the PDP can understand. This
happens inside the LIMESCO.
The LIMESCO gives the 3 Colours, in digital format, that are
ready to be processed by the PDP.
Around these main blocks, several signals, components are

required to make the whole thing work:
• Black feedback signals for the 3 colours in order to stabilise
the input black level coming from the AV Control board.
• Underflow monitoring to adjust the black reference level of
the ADC's.
• Overflow monitoring to reduce the contrast of the video
control on the AV Control board.
• 2 PLL'S: one for input clocking and one for output clocking.
• A 4 MHz clock intended for display protection purposes
inside the EPLD and as a freerun clock for the LIMESCO.
• An OSD generator: because the monitor can be used as a
stand-alone monitor, the OSD has to be generated inside
the screen and the E-box OSD generator cannot be used
for this.
• I/O expander for video mode selection, bug fix, 4:3 or 16:9
selection.
• An EPLD (Erasable Programmable Logic Device): for
various reasons (protection, adjustment of sync signals,...).
• Transistors 7365, 7364 and 7363 were added, see FD1,
between the IC bus connections of the LIMESCO panel.
When the set is put in Standby, the LIMESCO-IC has no
supply. This would cause the IC bus to be drawn to ground
potential resulting in an error.
8.2 Block Diagram of the PDP Limesco
GAMMA CIRCUIT
+5Va
+5Va
+5Va
7118-C
L23 74HCT4053D 16
680R
3137
3139 Vdd
5 Y0 S 9
+5Vc 2R2 7120

3 Y1 Z 4 BC847B
2116
470u
2115
220n
2114
220n
3138
2111
100n
Vss Vee E
12K
8 7 6
3100
100R
2102 3126
3122
10p
1K
BF824 3p9 1M
100R
180R
3102
3112
3116
3118
3119
3410
2100
2101
10K
2K2
68p
1K
1K
7101
BF824
BF824 BC847B
7116
BF824
L29 7112 LOW PASS FILTER
7108
BC847B
BF824 3120 5100 5105
7110
7100 BC857B
3101
2K2
7115 150R 0u68 0u47

L30
7109
3125
2104
4K7
6p8
3146
3147
3121
3123
2120
2107
2105
2121
33p
18p
39p
4p7
1M
1M
1K
1K
3106 3111 2103 7111
BF824
22R 22R 15p
330R
3113
3115
22K
3144
470R
3110
7127
4K7 BC847B
270R
3444
3145 7128
+5Va
+5Va
4K7 BC847B
3128
7124 2K2
BC858B 7117-B
8
TS922 5
+5Va
3127 7
3129
2117
220n
5K6
7118-B
+5Va
7121-D 1K 6
74HCT4053D 16
2018
74HCT04D 4
1n
14 Vdd
9 8 2 Y0 S 10
L34
7 2106 3124 1 Y1 Z 15
100n 1K8 Vss Vee E
3458
4K7
8 7 6
+5Va
7102
BC847B 7104
BC847B 14
3141 3108 2 1
120R 3K3
7 7121-A
74HCT04D
330R
3105
3107
2122
2K7
68p
CL 96532069_094.eps
041099
Figure 8-1 CL96532069_094.eps
Gamma Correction (See diagrams PD2, PD3, PD4 of

Service Manual)
Personal notes
Unlike a CRT, a plasma display has a linear 'light output versus
input voltage' characteristic.
Because all the input signals are gamma corrected for use with
a CRT, we have to make an anti gamma amplification to make
the input signal linear again with the light output.
As an example we take the RED Video signal path.
Two resistors mainly determine the gamma of this circuit:
R3106 and R3111.
The RED signal flow is as follows:

1. R-Video signal enters at T7102.
2. Amplification by T7109 and T7110.
3. Buffers T7111 and T7115.
4. Then it passes the low pass filter
5. Amplification by T7116
6. Entry in ADC
Noise Insertion
Personal notes
Because of the limited number of grey levels that can be
displayed, dithering is done. This happens with a certain
algorithm (Floyd-Steinberg) which produces a time stable
pattern. This is visual very annoying. To obscure this effect,
some noise is added to the signal, so that the regularity is out
of the pattern (every field will have another pattern). This makes
it less visible. The amount of noise is smaller than 1 LSB.
The noise signal is generated in the EPLD and added in the
gamma amplifiers.
Low Pass Filter
This filter serves as an anti-aliasing filter to obtain optimal

picture sharpness. For the high-resolution modes, a higher
sample frequency is used. When we use a lower sample
frequency, we have to limit the bandwidth to avoid aliasing
problems when digitising the signal.
Therefore, in an earlier design phase, a switchable filter was
used with two possible cut-off frequencies: 13 and 22 MHz.
The components that form this anti-aliasing filter are L5100 and
L5105 together with C2104, C2120 and C2121 for the higher
frequency of 22MHz.
The switching is done by the EPLD via signal lines 7350_P112
and 7350_P15, depending on the detected standard.
In the final version of the FTV1.9 however, the decision was
made to use a filter with a fixed cut-off frequency of 18 MHz.
AVC Limesco (PD)

R digital R
R
video controller 30 gamma circuit ADC Limesco
TDA4885 2
G
25 adj gain underflow
ampl (internal) red
B
via 7117-B 2 3x8 bits
20
clamp
VRB PWL
1
opamp
7117-A 2 2
17 31
(lim) R-black-feed
(every field) 1
noise underflow
red
3 H-white
1 2 2
(every field)
H-black-loop EPLD
(every line)
clamp
output dither
(peak white limiting)
contrast
1 Black level adj
at inputside 3131
2 Black level adj 2
at outputside
CL 96532069_166.eps
3 Aplification adjustments 011099
Stabilisations This inserts a measuring pulse in the gamma amplifier and

sets the feedback loop around OpAmp 7117-B on
Three automatic adjustments are performed in the gamma (integration). This will adjust the gain to keep the output of
corrector: the adjustment pulse constant.
1. Black level adjustment at the input side. Working with a
CRT, the GFL has a built-in cutoff stabilisation. The same
principle is used here: the offset of the amplifier is adjusted
so that the feedback voltage during the measuring pulses
remains constant (R_BLACK_FEED for red). This is done
once every field.
2. Black level adjustment at the output side. This makes sure
that the black level (measured between every line)
corresponds with the 'zero' of the ADC (TDA8714T/6).
Every line, the H_BLACK_LOOP signal from the EPLD
becomes active. Then the underflow bit is used to adjust the
ADC offset. When the underflow (pin 11) is low, VRB (pin 4)
will increase because of the integrator (around OpAmp
7117-A) until the VRB level is higher than the black level.
Then the underflow output will go high, which causes VRB
to decrease slowly. Thus, the VRB level will follow the black
level. However, if we didn't take precautions, this loop could
produce oscillations because the adjustment is yet too hard.
To soften this up, an OUTPUT DITHER signal is added.
This makes the output of the OpAmp increase or decrease
less fast so that the underflow bit changes less frequently.
Normally the variation of VRB is a couple of tenths of a Volt.
3. Amplification adjustment. Because of spread and
temperature influence, the gain of the gamma amplifier may
vary. Every field, the EPLD, will toggle the H_WHITE signal.
AD CONVERTERS
PD1/PD7
L24
5102
+5Vb 5101
6u8
6u8 +5Vd
2113
220n
L25
3439
10R
3143
2112
220n
1K
L26
7123
TDA8714T/6 7 16 18 22
+5Va
+5Va
VCCA CLK VCCD CEn

3134 D7 12
12K L27 D6 13
+5Va
+5Va
+5Va
9 VRT CLOCK DRIVER D5 14
2110
2373
220n
7118-A
3411
L28 D4 15
1K
16 74HCT4053D 220n TTL
3136 3 7117-A 8 VI AD LATCHES D3 23
Vdd 8 OUTPUTS
11 S Y0 12 TS922 CONVERTER
6K8 1 3403 7122 L32 D2 24
3130 3133 1K2 BC847B
14 Z Y1 13 2 4 VRB D1 1
4K7 3K3 4 OVERFLOW
680R
3406
E Vee Vss D0 2
3135
UNDERFLOW
2108
100p
22R
6 7 8
100R
3117
L33 LATCH VCCO1 19
2109
3131
VCCO2 21
10K
47n OGND AGND DGND O|UF 11 L31

NC TTL OUTPUT
3447
2K2
20 6 17 3 5 10
CL 96532069_095.eps
270799
AD Converters
Personal notes
3 ADC's (TDA8714T/6) are used to digitise the RGB signals.
On pin 8 the signals enter the converter. 256 levels are possible
(8 bits) between the VRB (pin 4) and the VRT (pin 9) level. The
input clock is connected to pin 16.
The converter produces an under/overflow bit. It is used in 2

ways:
• Black level reference setting (see before).
• Peak White Limiting: When the incoming signal for the ADC
becomes too high, the over-/underflow bit is set. To
distinguish whether it is over- or underflow, this bit can be
'AND-ed' with the most significant bit. When this outcome is
true, we have an overflow. This is done for every colour and
afterwards, the three signals are 'OR-ed'. This result is used
to reduce the contrast in the video controller on the AV
board. Signals UNDERFLOW_RED,
UNDERFLOW_GREEN, UNDERFLOW_BLUE are led to
the LIMESCO, which performs the AND - OR operation.
The outcome of this is led to the EPLD, which generates the
signal 'CONTRAST' to reduce the contrast.
8.3 Line Memory Scan Converter ( Limesco ) and OSD
PIXEL FORMAT
852
480
CL 96532069_096.eps
040899
LIMESCO Pixel Format

Personal notes
The PDP does not accept horizontal line sync frequencies
above 35.7 kHz or vertical sync frequencies > 72 Hz. Therefore,
to display these standards anyway, we convert them to a fixed
format acceptable for the PDP.
In the FTV1.5 we were more restricted concerning the amount
of displayable standards.
In the FTV1.9 the number of standards that can be displayed
has increased through the use of the LIMESCO ( item 7320 ).
This IC maps different VGA standards (like VGA, SVGA, and
XGA) to the standard of the PDP, which is 852x480 pixels.
However, we are still bound to standards with a field frequency
between 48 and 72 Hz.
The LIMESCO expects 8 bit values for R,G,B and horizontal
and vertical sync signals. The 3 colours are supplied through
buffers. The sync signals come from the EPLD.
At the output, the 3 colours are provided as 8 bit digital signals,
with the correct timings for the PDP.
The horizontal and vertical sync for the PDP are first passed to
the EPLD, which performs some adjustments to them because
they are not always according to the spec of the PDP.
OSD GENERATOR
L63
5323
100MHZ uPD93687GD-LBD
+5Vd
GND23
GND22
LR7
LR6
LR5
3393
10K +3V3a
L66 1
VDD0
2372
2353
220n
10u
L67 2
LG0
L68 3
LG1
L69 4
7327 LG2
MC141585 4 9 11 3418 L70 5
LG3
3371 7 SDA VDD1 VDD2 VDD3 100K 6
LG4
100R 8 SCL I 2 C DATA RCVR L71 7
3372 GND1
6 RESET_ L72 8
COLOUR DECODER
100R RESET SYSTEM LOGIC LG5
FBKG 12 L73 9
10 VSYNC_ LG6
VERTIC CTRL B 13 L74 10
3 NC LG7
G 14 L75 11
2 PIX-IN LB0
HORIZONTAL R 15 12
5 HSYNC_ LB1
CONTROL
L76 13
VSS1 VSS2 GND2
1 16 L77 14
LB2
L78 15
LB3
L79 16
LB4
L80 17
LB5
L81 18
LB6
19
LB7
20
+3V3a VDD1
2334 21
GND3
220n 22
CKS
23
GND4
24
OFR
25
OFG
26
OFB
27
PWL
28
HPLLA
29
L64 HCMPA
30
5325 VGA
CST
31
100MHZ GND5
7352
+5Vd
7353
2355
220n
32
74LVU04D14 CKA
4M
VCC 33
3390 1A 1Y L65 HEXT
1 2
34
1M 2A 2Y 4 REFCLK
3
35
3A 3Y 6 FREERUN
5
36
4A 4Y 8 HBLKA
9
37
5A 5Y10 HCLMPA
11
38
6A 6Y12 VSYNC
13
3391
BC847B 39
1K
GND HSYNC
7360 7361
7 40
BC847B +3V3a VDD2
2335
220n
3377
3378
10K
1K
CL 96532069_097.eps
040899
OSD Generator
Personal notes
Also, the RGB signals from the OSD generator ( 7327 ) are fed
to the LIMESCO ( 7320 ) to be mixed with the output signals.
Synchronisation and reference clock
IC7353 (74LVU04D) is used for 2 functions:

1. A free running 4 MHz, back-up clock that serves as a time
reference. A 4 MHz crystal is connected at pin 1 of IC 7353.
This signal is inverted twice and led to pin 34 of the
LIMESCO. This time reference clocks two counters: one for
field protection and one for line protection. When horizontal
or vertical frequencies are too fast or too slow, the EPLD will
construct a new sync. This sync-pulse is asynchronous with
respect to the incoming synchronisation signals. The image
will therefore not be stable.
2. Synchronisation of the input clock and the output clock.
During MODE change the input-clock is shorted to the out-
put clock, which both work at a different frequency, by
transistor 7360 and 7361. If this is not done it could be
possible due to bug in the LIMESCO, that the addressing of
the internal registers goes wrong.
8.4 PLL
8.4 PLL
PLL
L90
5306
100MHZ
+5Va
3321
3323
3324
22R
22R
18K
2322
220n
L91
BC857B
7315 5314
+3V3
7311 16 3322 L92 100MHZ
74HCT9046AD
220R 7319
2333
220n
VCC 7312
3 2 L93 PMBF170 BC857B
COMPI PC1O|PCPO
2326
150p
14 13
SIGI PC2O
6
C1A PLL
470R
3320
L94
7 14 14
C1B 2327 1 2 5315
1 2
11 +3V3
R1 7313-A 7314-A 100MHZ
3361
68p
2324
7
47n
1M
74LVCU04D 74LVCU04D 7
12 10
3326
R2 DEMO
2370
220n
1M
15 4 14 14
RB VCOO 3 4 3 4
330n
2303
330n
2304
9
VCOI 7313-B 7314-B
3318
56K
7 74LVCU04D 7 7330
5 74LVCU04D
INH 74LVU04D 14
GND 14 14 VCC
5 6 5 6 1A 1Y 2
1
1 8 7313-C 7314-C 2A 2Y
7 74LVCU04D 7 3 4
2329
74LVCU04D
2328
2330
8p2
8p2
8p2
3A 3Y 6
7362 5 3330
BC847B 14 14 4A
9 8 9 8 9
4Y 8
47R
7313-D 7314-D 5A 5Y10
74LVCU04D 7 74LVCU04D 7 11
6A 6Y12
13
14 14
11 10 11 10 GND
7
7313-E 7314-E
7 74LVCU04D 7
74LVCU04D
14 14
13 12 13 12
7313-F 7314-F
74LVCU04D 7 74LVCU04D 7
PHASE DETECTER VCO BUFFER INVERTER
CL 96532069_098.eps
240899
For the pixel clocks, 2 PLL's are used. The PLL around 7311
used as an example, consists of :
• a phase detector (inside 7311 )
Personal notes
• a loop filter (resistor and 2 capacitors)
• a Voltage controlled oscillator (ring oscillator around 7313)
• a divider (inside the LIMESCO)
It is important that the PLL has little jitter (phase noise).

Otherwise this would reduce the sharpness of the picture.
Critical components for the jitter are the VCO and the phase
detector.
Therefore we do not use item 7311 on its own (it contains also
a VCO), but we use the phase detector from it and build a VCO
around 3 MOSFET inverters ( 7313 ).
The current consumption of the inverters is proportional to the
oscillation frequency. Therefore we convert the voltage of the
phase detector to a current with a MOSFET and a PNP current
mirror.
A capacitor of 150pF is added to provide the switching
transients of the inverters.
8.5 LOGIC CONTROL AND I/O
EPLD
L99
+5Vd
100MHZ
7307
EPC1441 23 27 5327
2358
220n
2 VCC1 VCC2 31
DCLK DATA 7357
10 EPC1441
CS_ 32 8 1
7 VCC1 DATA
30
OE 29 7 2
VCC2 DCLK
1 28
NC 6 3
3 26
CASC_ OE
4 25
5 4 5329
5 24
GND CS_
6 6u8
8 NC +5Vd 7350
9 EPF6016 144 143
GND 2360
11 13 14 15 16 17 18 19 20 21 22 12 220n 1
2
7355-A L102
N74F574D 3
20 5326
1 VCC 4
EN 100MHZ
+5Vd
11 GND 220n 5
C1 10 3392
1K
L103 2377 6
2 19 3367 L104 7
1D
47R L105 8
20 9
1 VCC
EN 10
11 GND 7355-B
C1 10 N74F574D 11
L106
12
3 18 3368
1D 13
47R
14
20
1 VCC 15
EN
DCLK 11 GND 7355-C 16
C1 10 N74F574D
L107 17
EPLD-7350
4 17 3369 18
1D
47R 19
20
7351
PCF8574AT 21
13 INT_ 22
1 A0 INTERRUPT 23
LP FILTER
LOGIC
2 A1 L108 24
3 A2 P0 4 L109 25
SCL 3386 14 SCL P1 5 L110 L116 26

2
100R INPUT I C BUS
SDA P2 6 L111 L117 27
FILTER CONTROL
SDA 3387 15 P3 7 L112 28
100R SHIFT 8 BIT I/O
L118 REGISTER PORTS
P4 9 L113 29
5331 16 VDD POWER-ON P5 10 30
3451
100MHZ RESET
1K
+5Vd P6 11 31
3416
8 VSS P7 12
2356
220n
32
+5Vd
1K
L114
33
L115
+5Vd
CL 96532069_099.eps
270799
8.5 LOGIC CONTROL AND I/O
EPLD IO EXPANDER
A FLEX6016 EPLD ( 7350 ) is used for different functions to A PCF8574AT is used to decode information on the video-
improve performance, correct timings, ...: mode.
• Protect the frequency of the Hsync and Vsync : The meaning of the bits is as follows :
• The spec of the PDP indicates an absolute maximum of P0 : aspect ratio : is used to adjust the sync in 4:3 modes.
35.7kHz for the horizontal sync and 72Hz for the vertical 4:3 ==> 0
sync. For reason of protection, the EPLD will construct a 16:9 ==> 1
sync signal within specification of the PDP when Hsync or P1 : video mode bit
Vsync is to low or high. The image will then not be P2 : video mode bit
synchronised with respect to the incoming sync signals, and P3 : video mode bit
therefore not stable. P4 : video mode bit
• Ensure valid timing for horizontal , vertical sync signals and P5 : CKD bit : is used for a bugfix of the LIMESCO. Before
N-blank signals coming from the LIMESCO. These signals changing registers DIV or FIL in the LIMESCO, this bit should
are not always according to spec, so the EPLD corrects be pulled low. Afterwards, it must be set high again.
that. P6 : Undefined
• Positioning of H-sync for 16:9 modes. P7 : Undefined
• When the LIMESCO grabs only 640 pixels, these pixels
could be used to construct a 4:3 image, if sidepanels were The video mode bits ( P1 - P4 ) are encoded as shown in table
added. The LIMESCO cannot produce the correct timing for below :
this event. Therefore, the LIMESCO is forced to produce
900 pixels at the output side, and told that 260 pixels are
Mode name Resolution P4 P3 P2 P1
flyback. The LIMESCO will then fill the flyback with the
colour that is set inside certain registers. What the EPLD VGA350 640 * 350 0 0 0 0
has to do is to move the Nblank to the correct position so VGA400 640 * 400 0 0 0 1
that part of the flyback is used as if it were active data. VGA480 630 * 480 0 0 1 0
• Noise generation for the gamma amplifiers. By means of
MACVGA 640 * 480 0 0 1 1
two linear feedback shift registers, the EPLD produces
random noise. This noise is added in the gamma amplifiers SVGA 56Hz 800 * 600 0 1 0 0
to obscure stable dither patterns and to improve grey scale SVGA60Hz 800 * 600 0 1 0 1
tracking. XGA 56Hz 1024 * 768 0 1 1 0
• Generation of clamping and measurement pulses for black,
white and cut-off measurements. XGA 60Hz 1024 * 786 0 1 1 1
• Pulses to activate the feedback loops for input clamping, FBX 840 * 480 1 0 0 0
output clamping and gain adjustment are generated in the HDIO 1920 * 1080 1 0 0 1
EPLD. Input clamping is adjusted once a frame, output
clamping every line, and the gain once a frame (and takes This information is used by the EPLD.
3 line-times).
• VCR behaviour improvement. The Vsync signal coming out
of the feature box during feature box modes is not what it
should be. Especially during VCR feature modes this can
cause the PDP to flicker annoyingly. In the EPLD, the Vsync
signal is sent through a low pass filter to reduce that
problem.
• OSD clock generator and positioning. The sync pulses and
a pixel clock is generated for the OSD generator
(MC141585DW). To make the position of the OSD
independent from the video mode, these pulses have to be
changed. This is done by the EPLD.
• LIMESCO bug : during conversion modes, there will be a
phase jump at the end of a field. This disturbs the output
PLL, which in turn disturbs the LIMESCO, resulting in a
shifted picture. To prevent this, the output PLL loop is
opened for a few lines during vertical flyback.
80 9. Audio amplifier FTV1.9DE Display Box
9. Audio amplifier
AUDIO AMPLIFIER
CL 96532069_089.eps
260799
Compared to the FTV1.5, the audio amplifier module has been

moved from the E-box to the Monitor.
The module is derived from the GFL-ECO-amplifier module.
Personal notes
The actual panel contains only two amplifier-IC's, a mute and a
protection circuit.
The audio input signals L_HIGH, L_MID LOW, R_HIGH AND
R_MID LOW originate from the AV control panel.
The source for the amplifier can be the audio signals from the
SSP (regulation and signal switching), or the sound circuit in the
Monitor.
The supply voltage of the output amplifiers is symmetrical (+16
V and -16 V). Therefore the outputs from the amplifiers are
connected directly to the loudspeakers and as a result during
normal operation the signal contains no DC components.
If a DC-voltage exists on one of the outputs of the amplifier IC's
(e.g. an IC is faulty) as a result the DC_PROT line becomes
high and causes the VsVa supply to switch off the supply
voltages.
This protection can be overruled by unplugging connector A20.
The sound can be muted in various ways in the output

amplifiers:
• When the supply voltages becomes less than +/- 6 V the IC
will automatically interrupt its non-inverting input. The IC
therefore automatically suppresses unwanted signals when
switching on or off.
• The mute can also be activated externally (active = low) via
the SND_ENABLE line originated by the microprocessor at
the AV control panel.
FTV1.9DE Display Box 10. LED panel 81
10. LED panel
START-UP CIRCUIT
3 fold
AV15 LE15
JST B03B-EDM-WH JST B03B-EDM-WH
FRONT I/O LED PANEL
E-BOX (partial)
CL 96532069_157.eps
250899
The LED Panel Display contains a red and green bi-colour LED
to indicate the state of the monitor, a RC5 remote control
receiver and some additional required discrete electronic
Personal notes
components.
The bi-colour LED is used to indicate the state of the monitor.
The colours of the LED are red or green, and orange when both
red and green is on.
The remote control receiver enables one-way interaction
between the user and monitor by infrared RC5 signals.
The switch panel is interconnected between the LED Panel and
the AV Control Panel.
Figure below shows the functional block diagram of the LED
Panel Display.
The LED is activated by two logic input signals 'GREEN_LED'
and 'RED_LED', coming from the AV Control Panel. Both
signals must be low active what should be implemented in
software. The logic signals are converted to steady currents to
enable the LED to emit light. When both red and green light
(=orange light) is desired, the total LED current will be twice
every single colour current.
The RC5 receiver is used for reception of IR remote control
signals. The received signal is led to the Monitor
microcontroller.
82 11. Switch panel FTV1.9DE Display Box
11. Switch panel
START-SWITCH PANEL DISPLAYUP CIRCUIT
Soft Switch
1
+5VSTBY_SWITCHED +5VSTBY SWITCHED
2
+5VSTBY_SWITCED_RELAIS
3
+5VSTBY
4
GND GND
5
DIS_RC5 DIS_RC5
6
LED Green LED Green
7
LED Red LED Red
CL 96532069_159.eps
250899
The Switch Panel Display contains a soft-switch to turn the

monitor ON and OFF and two connectors. One connector is
going to the LED Panel Display, the other one to the AV Control
Personal notes
panel.
The Monitor can be turned ON and OFF by using the soft-
switch, which interrupts the +5V-Standby line.
Figure below shows the functional block diagram of the Switch
Panel Display.
The soft-switch is a 'low power_dual pole_two position' switch
which interrupts the power line '+5V STBY' into
'+5VSTBY_SWITCHED' and
'+5VSTBY_SWITCHED_RELAIS'.
A dual pole switch is used so the relays inside the monitor
cannot get unwanted supply from other parts of the Monitor
electronics.
FTV1.9DE Display Box 12. YUV / YC input 83
12. YUV / YC input
START-UP CIRCUIT
YUV / YC Input
YUV / YC
YUV / YC / CVBS / LR
Input Panel
R
GB I2C
HV +5V / +8V
+L
R
VGA Input
AV-Control PDP Limesco
RGBHV+LR RGBHV RGBHV PDP
Panel Panel
CL 96532069_160.eps
250899
The YUV / YC Input panel can be present in the display cabinet

of the FTV 1.9 Eco. This board gives the possibility to attach
several video formats to the stand-alone display. It also has one
Personal notes
stereo audio connection.
The input video signals are:

• YUV on CINCH (Y, Cb, Cr)
• YC on Hosiden connector (SVHS)
• CVBS on CINCH
• CVBS on BNC
The input audio signals are:

• Left and Right audio on CINCH.
The board is designed to handle 1fh video-input signals. The

output signals of the board (RGBHV+LR) go to the AV-Control
panel that controls (among other things) the inputs of the
display. From the AV-Control the signals go to the PDP
LIMESCO panel which processes the video and uses line
doubling to display the 1fh signal on the 2fh display.
Figure 1 shows schematically how the panel is a part of the
Monitor. It is placed on the back of the display with the
possibility to connect the plugs from the outside world. From
there on the signals (RGBHV+LR) go via the AV-Control board
to the PDP LIMESCO which processes the signals for the PDP
itself.
84 12. YUV / YC input FTV1.9DE Display Box
12.1 Circuit description
YS-Video
CS-video
CVBS1 Ycombed P6
CVBS2 Combfilter Ccombed (YC_switch)
Switch
P0
(CF_Input select)
P1 / P2 P3 Yswitched Cswitched
(CF_Sys1 / CF_Sys2) (CF_Bypass)
Ycomponent
Y Y,Cb,Cr to R
Cb RGB G
Cr matrix B
Hsync /
Sandcastle / H
RGB blanking
Hout SCin RGB- R G B (in) Y/CVBS(ext) Y C R

blanking G
Yout
Uout B
Vout Bimos
Vin TDA8854
Uin SDSC vert. Sawtooth V
Yin A L
P0 P1 P2 P3 P4 P5 P6 P4 Crystal-
(Crystal select) Select
SCL
SDA I/O expander
L L
R audio R
CL 96532069_161.eps
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FTV1.9DE Display Box 12. YUV / YC input 85
In the block diagram of Figure 2, a simplified view is given to COMB FILTER TDA9181
explain the functionality of the board.
The heart of the board is a TDA8854: the BIMOS one chip TV. The comb filter is used to separate luminance (Y) and
The main function of this IC is to convert YC into RGB signals chrominance (C) signals out of a CVBS video signal. The
and it also gives the possibility to adjust the video, like TDA9181 is chosen because of its following properties:
saturation, contrast and peaking. • Multi-standard.
The Y/C input is via a switch (YC-switch) connected to the • Good quality Y / C separation.
TDA8854. A 2D-comb filter TDA9181 processes the two CVBS • Input switch for two CVBS inputs.
input signals and converts them to Y and C components. Then • Alignment free.
via the mentioned switch the signals are led to the TDA8854. • Almost no external components needed.
The colour difference signals YUV (component video) are
converted to RGB video by a discrete circuit. These RGB YUV COMPONENT VIDEO (Y,CB,CR) TO RGB MATRIX
signals are led into the TDA8854 as well.
The H and V synchronisation signals are derived from the Y The Y, Cb, Cr to RGB matrix converts YUV component video
output of the TDA8854. Also here the sync is removed from this (Y, Cb, Cr) to RGB video. The RGB signals will be connected
Y output and led back to the IC. This is done because the to the TDA8854. The Y signal is also directly connected to the
LIMESCO uses the time during the sync pulse to adjust its TDA8854 for synchronisation.
black level.
The Y, Cr, Cb signals are NOT directly connected to the Y, U,
The panel is designed with 2 or 3 quartz crystals to enable V inputs of the TDA8854 because:
global use of the display. Systems that are implemented are the • The signals Y, Cb, Cr are not the same as Y, U, V of the
following. TDA8854, so a conversion should always be made.
• PAL / SECAM (Crystal frequency: 4.433619 • An extra three-fold switch would be necessary to switch
MHz) between YUV out of the TDA8854 and the converted Y, Cb,
• NTSC (Crystal frequency: 3.579545 Cr signals.
MHz)
• PAL M (Crystal frequency: 3.575611 Used is the NTSC standard: 0.714 Vb-w (0.714V video +
MHz) 0.286V sync = 1Vpp)
Left and Right audio is not processed on the panel and led Input signals (YUV):
immediately from the CINCH input connectors to the AV- • Y = 0.7 Vb-w
Control Panel. • U = Cb
• V = Cr
TDA8854 BIMOS TV PROCESSOR
Output signals (RGB):
The TDA8854 BIMOS TV Processor is chosen for this panel • R = Y + 1.402 * Cr
because of the following properties: • G = Y + 0.714 * Cr - 0.337 * Cb
• Y / C input. • B = Y + 1.772 * Cb
• Y input is also usable for CVBS (SECAM).
• RGB input. CRYSTAL SELECTION
• RGB output.
• Multi-standard. The board contains 3 crystals to be able to handle PAL, NTSC
• I2C controllable. and PAL M colour standards.
• Small package (QFP64). Normally the TDA8854 can handle only one or two crystals.
With some additional electronics three crystals can be
The TDA8854 also processes the video attributes like: attached. On one pin of the TDA8854 two crystals are
• Brightness range 0..63 connected and one of them can be selected with control line P4:
• White point CRYSTAL_SELECT.
• Peaking In the NVM of the Monitor the last detected system per source
• Saturation range 0..63 will be memorised. This will increase the speed of the
• Contrast range 0..63 recognition of the colour system when a certain source is
• Hue (NTSC only) range 0..63 selected. If the colour system is not recognised the TDA8854
will search in 'own intelligence'-mode for the appropriate
system. In a three-crystal version the CRYSTAL_SELECT line
must be altered if none of the first two crystals is the right one.
86 12. YUV / YC input FTV1.9DE Display Box
IO EXPANDER
Function Schematics Function P7 P6 P5 P4 P3 P2 P1 P0

block name
YC or YC switch YC 0
CVBS 1/2 CVBS 1/2 1
inout switch
Crystal select XTAL_sel PAL + SECAM + 1
NTSC
PAL + SECAM + 0
PAL M
Comb filter CF_Bypass SECAM 1 X X
CF_SYS1 (No combing)
CF_SYS2 NTSC 0 0 1
PAL 0 1 0
PAL M 0 0 0
CVBS input CF_inpsel CVBS 1 (cinch) 1
CVBS 2 (BNC) 0
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IO EXPANDER - PCF8574AT
Personal notes
The user controls the display with a remote control and toggles
manually through the source loop. The IO Expander is
addressed via the I2C bus with signals coming from the
microprocessor. The IO expander controls the settings of the
comb filter, the YC switch and the crystal selection.
The table below gives a description of the output lines P0-
P7and their function.
The signals to control the comb-filter (TDA9181) are:
CF_BYPASS, CF_SYS1 AND CF_SYS2 , which select the
SECAM, NTSC or PAL system.
The signal to select the YC input or the CVBS-1 or -2 input is
YC_SWITCH. This signal is the select-input for IC7010 that
selects either the YC-signal of the Hosiden SVHS or the YC
combed output signal from the TDA9181. The selection
between CVBS 1 (CINCH) or 2 (BNC) is done by switch-signal
CF_INPSEL.
Switch signal XTAL_SEL selects one of the crystals, which are
connected to pin 51 of the BIMOS.

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Colour Television Chassis

RECEIVER BOX DISPLAY BOX

The successor of the FTV1.5 is the FTV1.9, which had to be

It is built around an E-Box (= Receiver Box) and a 42" Monitor

For the FTV1.9, the Monitor can be used in two applications.

The Monitor is a separate device, which can also be sold and

The panels are:

delay to correct the timing between video and audio) and to

1. VS/VA SUPPLY panel.

As in the FTV 1.5, this panel must be exchanged completely if

1. All panels are now accessible.

AUDIO AMPLIFIER panel. PRECONDITIONER panel.

Audio Amplifier Pre-conditioner

AUDIO VIDEO CONTROL panel.

PDP LIMESCO panel.

1. Remove 2 x 2 screws at the sides and 4 screws at the

1. The LED DISPLAY panel can be removed now by

SWITCH DISPLAY panel.

1. Remove front cover (for a description see Chapter 2.1.8

1. The SWITCH DISPLAY panel can be removed now by

Some parts of the FTV1.9 Display Box must be exchanged if

1. The LOUDSPEAKER can now be removed by

Exchanging of the PDP.

1. First unplug (remove Mains and VGA cable) the Display

1. Remove all copper EMC SHIELDING springs mounted

1. Disconnect the following cables:

1. Now remove the 8 large screws which hold the PDP:

For the block diagram see Service Manual chapter 6.

The power is supplied by the VsVa supply (which is an LLC

The output voltages of the VsVa supply are:

The controls located on the µP panel, which is a panel on the

For the FTV1.9, the Monitor can be used in two applications.

• A stand-alone configuration, a separate device which can

The monitor, as a stand-alone unit, can be serviced by using a

In this chapter the following paragraphs are included:

The FTV1.9 chassis is equipped with test points in the service

printing. These test points are referring to the functional blocks:

Measurements are performed under the following conditions:

For easy installation and diagnosis the dealer service tool

(DST) RC7150 can be used. When there is no picture (to

Installation features for the dealer

Diagnose features for service

Configuration". When a Receiver box is connected to the

Customer Service Mode (CSM) Display

Entering the Customer Service Mode.

Exit the Customer Service Mode.

The Customer Service Mode information screen

The following information is displayed on screen:

Error-nr Type of Error Possible defect/cause

The error code buffer will be cleared in the following cases:

The contents of the error buffer can also be made visible

through the "blinking LED" procedure. This is especially useful

There are two methods:

All protections are handled by the hardware. The SW will only

monitor the hardware to generate error codes for the service.

Input voltage at A/D converter [V]: Sort protection:

DISPLAY SUPPLY MODULE

Circuit PROTECTION PROT-FAN (1-5)

VCC 3033 3036

3386 3038 2032

CONNECTOR PROT-FAN 1-6

3379 3378 3011 3111