Hi All,

I am working on implementation of Verilog code for Bidirectional Data Buffer.

Bi-Directional Data Buffer:

---------------------------
Inputs dir - Direction control; Low for Write and High for Read
      en - Bi-directional Buffer enable
Two In/Out port data_in and data_out.

My Code:
-------

`ifndef Tristate                  //n-bit declaration for Tristate variable

`define Tristate(n) {n{1'bz}}
`endif
`define datawidth 2

module bi_dir_xceiver (data_in, data_out,rst, en, dir);

   inout [`datawidth-1:0]data_in;
   inout [`datawidth-1:0]data_out;
   input en;
   input dir;
   input rst;  
      
   reg [`datawidth-1:0]data_tmp;
  
   assign data_in  = ((dir) & (!en)) ? data_tmp : data_in;
   assign data_out= ((!dir) & (!en)) ? data_tmp : data_out;
   
   always@(en or rst or data_in or data_out or dir)
  
    if(!rst)
     begin
      data_tmp=`Tristate(`datawidth);
     end
   else
     begin
      if(!en)
       begin
          if(!dir)
            begin
              data_tmp = data_in;
            end
          else
            begin              
              data_tmp = data_out;
            end
        end
      end
 endmodule    

This code is got complied and simulation i am facing following problem:

The first execution in the simulation is working fine.

i.e., if i place a data on data_in with dir=0 and en=0.
I am getting data at the data_out. if change the dir=1
and place a data in data_out, there is no change in data_in.

if i do the simulation in opposite manner,

i.e., if i place a data on data_out with dir=1 and en=0.
I am getting data at the data_in. if change the dir=0
and place a data in data_in, there is no change in data_out.

After successful first execution, there is no change in the data transfer

What could be the problem?

Pls suggest your solution and suggestion.

Thanks & Regards,

Arun Kumar P N

Posted by: arunKumarpn     9/11/2009 1:16:06 PM

Comments Posted:2       Questions Posted:1

Hi All,

Please give your suggestion reg. my above specified problem.

I am expecting your replies.

Thanks & regards,

Arun Kumar P N

Posted by: arunKumarpn     9/10/2009 10:33:12 AM

Comments Posted:2       Questions Posted:1Accepted Answer
Hi All,

I have modified my code as follows:

`ifndef Tristate                  //n-bit declaration for Tristate variable

`define Tristate(n) {n{1'bz}}
`endif
`define datawidth 16

module bi_dir_jump (data_in, data_out, en, dir);

   inout [`datawidth-1:0]data_in;
   inout [`datawidth-1:0]data_out;
   input en;
   input dir;
    
   reg [`datawidth-1:0]data_in_tmp;
   reg [`datawidth-1:0]data_out_tmp;
  
   assign data_in = data_in_tmp;
   assign data_out= data_out_tmp;
   
   always@(en or data_in or data_out or dir)
   begin    
      if(!en)
       begin
          if(!dir)
            begin
              data_in_tmp = data_in;
              data_out_tmp = data_in_tmp;
            end
          else
            begin
              data_out_tmp = data_out;              
              data_in_tmp = data_out_tmp;
            end
      end
   end
endmodule

Still i am facing the same problem as descriped in my previous post!!!

Regards,

Arun Kumar