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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 40, NO. 4, JULY/AUGUST 2004

Harmonic Analysis and Improvement of a New Solid-State Fault Current Limiter

M. M. R. Ahmed, Member, IEEE, Ghanim A. Putrus, Li Ran, Member, IEEE, and Lejun Xiao
AbstractThis paper presents a harmonic study on a newly developed solid-state fault current limiter. Using this device, the supply voltage sag is reduced when a short-circuit fault occurs on a cable feeder in the downstream network, hence improving the power quality. The device will eventually isolate the faulted part from the healthy network. Harmonics caused by the fault current limiter are analyzed and a method is proposed to prevent undesirable harmonic interactions. Analytical and experimental results are compared with existing regulations. It is verified that, with precautions, the operation of the solid-state fault current limiter will not cause problems to either the supply network or the loads. Index TermsFault current limiters, harmonics, power quality and switched-mode power supply (SMPS).

Fig. 1.

Construction of FCLID.

I. INTRODUCTION AULT CURRENT limiters are being developed to improve the performance of distribution networks. Advantages of using a fault current limiter include reduced fault level of the supply and smaller voltage sag during a short-circuit fault. These will avoid upgrading switchgears during system expansion and improve the power quality delivered to customers. Previous studies have proposed designs with impedance insertion, switched using semiconductor devices [1], [2]. Superconducting fault current limiters are also being developed [3], [4]. A shortcoming with previous fault current limiters using impedance insertion is that the limited fault current varies with the supply system condition and fault location. In addition, operation time is limited due to power dissipation in the impedance, which is usually very resistive. For such reasons, a new solid-state fault current limiter was proposed [5] and more recently developed. The semiconductor devices in the proposed fault current limiter are controlled in a repetitive switching pattern during operation so that the fault current is always limited to a predetermined level. A side effect
Paper ICPSD-01-D5, presented at the 2001 IEEE Rural Electric Power Conference, Little Rock, AR, April 29May 2, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Rural Electric Power Committee of the IEEE Industry Applications Society. Manuscript submitted for review May 15, 2001 and released for publication April 12, 2004. The work of M. M. R. Ahmed was supported by Northern Electric Distribution Ltd., U.K., and the Egyptian Government through a scholarship to study at Northumbria University. M. M. R. Ahmed is with the Industrial Education College, Cairo, Egypt (e-mail: mohamedra62@yahoo.co.uk) G. A. Putrus is with the School of Engineering and Technology, Northumbria University, Newcastle upon Tyne NE1 8ST, U.K. (e-mail: ghanim.putrus@unn.ac.uk) L. Ran is with the School of Engineering, University of Durham, Durham DH1 3LE, U.K. (e-mail: li.ran@durham.ac.uk) L. Xiao is with the School of Engineering, University of Salford, Manchester M45 7FN, U.K. (e-mail: l.xiao@salford.ac.uk) Digital Object Identifier 10.1109/TIA.2004.830774

of the repetitive switching of the semiconductor devices is that harmonics are generated. This paper considers the harmonic characteristics, and the effects on supply system and loads near the fault current limiter. This paper first outlines the construction and operation of the new solid-state fault current limiter. Its features are summarized. The mechanism of harmonic generation is then analyzed and a MATLAB/SIMULINK model proposed to predict the harmonic level. The calculated harmonics are checked against IEEE standard 5191992 [6] and the U.K. standard G5/3 [7], regarding short-duration harmonics. A control method is proposed to improve the harmonic signature. Laboratory experiments are performed to verify the harmonic calculation and the control method. Tests are also carried out to investigate the risk and solutions regarding harmonic resonance with power factor correction capacitors in the network or cable capacitance. The effect on sensitive loads such as switched-mode power supplies (SMPSs) in the customer loads is also investigated. II. FAULT CURRENT LIMITING AND INTERRUPTING DEVICE (FCLID) The solid-state fault current limiter concerned in this study is actually an FCLID. Fig. 1 shows the configuration of a singlephase FCLID. It consists of a high-speed bidirectional switch realized using power semiconductor devices such as insulated gate bipolar transistor (IGBT), a varistor (nonlinear resistor), and a snubber circuit, all connected in parallel. In operation without a fault, the semiconductor devices are constantly gated on. Alternatively, the whole FCLID can be bypassed using a circuit breaker to avoid losses. The bypass circuit breaker is opened when the FCLID is required to operate. Considering that a short-circuit fault occurs on the load side, a semiconductor device will initially conduct the fault current. The switch is turned off when the fault current reaches a preset which should be within the interrupting capability value of the semi-conductor device. The fault current is, thus, diverted to the varistor. The clamping voltage of the varistor is set to be higher than the peak supply voltage. Therefore, the current in

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Fig. 2. FCLID incorporated in a typical distribution network.

Fig. 4. Spectrum of FCLID current.

Fig. 3. Current through FCLID.

the faulted circuit starts to decrease. The varistor voltage remains almost constant as long as it is conducting. The semiconductor device is turned on again to reestablish the current as it . Switching logic is the same reduces to a preset low value for both positive and negative half cycles of the fault current and the operation is maintained for a specified period of time which is useful to collect information about the fault location and to coordinate protection relays [8]. If the fault persists, the semiconductor devices are turned off permanently, after a certain time, and the fault current is completely interrupted. To illustrate the above operating principle, a simulation model is established using MATLAB/SIMULINK for the single-phase 230-V system shown in Fig. 2 [9]. It is assumed that the pre-fault load current is less than 40 A. Without the fault current limiter, the prospective peak short-circuit current at the busbar of Load 4 is 1 kA. The value changes to 2, 3, and 4 kA if the fault location is at Load 3, Load 2, and Load 1, respectively. Busbar A is the point of common coupling (PCC) with other cable feeders. For the case of a fault at Load 4, the maximum through current, which is potentially 1 kA without the FCLID, is limited by A. Fig. 3 shows the curthe fault current limiter to is set to 0 A (practirent through the fault current limiter. cally the small leakage current of the varistor) in this case. The simulation is performed for three half cycles only. As will be shown later, the corresponding laboratory model of the FCLID is able to operate for about 1 s. The features of the proposed FCLID can be summarized as follows. 1) The limited fault current is independent of the supply system condition and fault location. The maximum, min-

imum, and average values of the current are all determined by the controller. 2) The current-limiting function is achieved via the insertion of the varistor. Power dissipation in the varistor may be carefully dealt with such that the FCLID can operate for a considerable period of time. A method was developed to provide equal current sharing between parallel varistors [10]. 3) The rate of change of the current depends on the total series inductance in the circuit, the supply system condition, and fault location. Therefore, these will affect the switching frequency of semiconductor devices in the FCLID. 4) The varistor presents its clamping voltage when conducting but the supply source voltage is time variant. Therefore, the switching rate is not constant even within a half cycle. While the proposed FCLID provides some very desirable characteristics, it is also clear from the above that the FCLID will exhibit some special harmonic characteristics which should be carefully analyzed. III. HARMONIC CALCULATION AND IMPROVEMENT Fig. 4 shows the frequency spectrum of the current waveform shown in Fig. 3. In deriving the spectrum, the current was sampled for one fundamental cycle and Fourier analysis was then applied to the sample. It is observed that the harmonics originate from two distinct mechanisms: the harmonics around the average switching frequency of the semiconductor devices in the FCLID, and the lower order harmonics due to the constant and modulation control. The latter have similar distribution to the harmonics in a square wave [11]. Referring to Fig. 2, the simulated voltage waveforms across the FCLID and at the PCC (A) are shown in Fig. 5. During operation, the FCLID alternatively presents the clamping voltage of the varistor (varistor conducting) and about 0 V (switch turned on) in series in the power circuit. The voltage across the FCLID (upper trace) is, therefore, very distorted. As for the voltage at the PCC, the harmonics in the FCLID voltage are divided between source impedance and the impedance from the PCC to

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Fig. 5.

Voltage across FCLID and at PCC.

Fig. 7. Spectrum of FCLID current with I min = 50 A.

and system fault level should be considered. The harmonics in the FCLID current are of higher frequency and can be more easily absorbed using a passive filter at the PCC. The voltage at the PCC will also be slightly improved. IV. STANDARDS REGARDING SHORT-DURATION HARMONICS There are two main recognized standards dealing with the short-duration harmonic as their main goal. These are: IEEE Standard 5191992, which states that for short-duration harmonics Devices such as a thyristor-controlled drive applied to a rolling mill generate short duration harmonic currents as the material passes through the mill. Generation of intermittent harmonics and the resulting voltage stress on the capacitors, the transformers, and other apparatus is sometimes more tolerable than the stress caused by the constant generation of harmonics. [6]. Engineering Recommendation G5/3, which states that short duration transients are tolerable provided the current bursts and related voltage distortions are of an intermittent nature, e.g., the burst duration does not exceed 2 seconds and the interval between bursts is not less than 30 seconds. The principal concern is to prevent damage to other plant such as capacitors. Provided that the fundamental voltage at the metering point does not exceed the nominal supply voltage plus 6 per cent, there should be no risk of damage. [7]. Operation of the fault current limiter is a rare event as compared to a rolling mill drive. Its duration is usually less than 2 s. According to the above standards, the harmonics produced by the fault current limiter may not be a problem. This is particularly the case if the harmonics are reduced using the modulation control. However, the risk of damage to the FCLID and other equipment must be prevented. Therefore, it is important to investigate the possibility of harmonic resonance with the supply network and loads connected to the PCC. V. CONSIDERATION OF HARMONIC RESONANCE It has been shown that during the operation of the FCLID, rich harmonics over a quite wide spectrum band are produced. The

Fig. 6.

FCLID current with I min = 50 A.

the fault. Therefore, as long as the FCLID is installed close to a strong supply and the fault location is sufficiently far from the FCLID, the voltage at the PCC before the fault current limiter will be close to a sine wave. For this reason, an extra inductor may be integrated in the fault current limiter, or protective measures are taken in the controller so that the FCLID does not respond when the fault is very near to it. Other feeders connected to the PCC will be subjected to the voltage waveform shown in Fig. 5. Little voltage sag may be present during the fault. Also, the voltage will be more distorted for a fault closer to the fault current limiter. Additionally, the harmonic current shown in Fig. 3 must be absorbed by the supply system. It is, therefore, advisable to improve the harmonic characteristics of the fault current limiter. A method to reduce the harmonic content in the current during the operation of the fault current limiter is to modify the switching strategy. Instead of turning on the switches when the current reduces to 0 A, the semiconductor devices can be turned on at a higher current level. Fig. 6 shows the simulated current A. Its spectrum is shown in Fig. 7. waveform with is to reIt is observed that the effect of increasing duce the bandwidth of the limited fault current. This will increase switching frequency. Therefore, device switching loss

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Fig. 8. Harmonic current flow.

worst case is that some harmonics could coincide with the natural frequencies of the circuit formed by power factor correction capacitor at the PCC and the supply system impedance in the upstream. If this happens, the harmonics injected into the supply system will be amplified and overvoltage/overcurrent may cause damage to the plant. To analyze the situation, harmonic current flow analysis for the distribution network shown in Fig. 2 has been carried out. A simple equivalent circuit of the network is shown in Fig. 8, where the FCLID is assumed to be a source of harmonic current . The current at any harmonic frequency divides between the shunt capacitor and supply as

Fig. 9.

Resonant peak with different capacitance.

where is the harmonic current generated, is the harmonic is the harcurrent that flows into the supply system, and monic current that flows into the capacitor. Then,
Fig. 10. Resonance frequency versus cable length.

(1) (2) where and are the impedances of the supply system and capacitor, respectively, at the frequency examined. Harmonic resonance corresponds to the case when the inductive reactance of the supply equals the capacitive reactance of and will be greater than . Analthe capacitor. Both ysis is performed for different values of the capacitance and is plotted in Fig. 9 for a system fault level. The ratio system fault level of 1 kA. The shunt capacitance is varied from 1 to 10 mF and the resonant peak is captured for each capacitance value. It is clear that the switching frequency should avoid the range from 200 to 800 Hz. If the switching frequency of the and FCLID is increased above 800 Hz by setting proper , there will be no risk of parallel resonance. It is worth pointing out that this is the worst case where power-factor-correction capacitors are connected directly at the PCC of the FCLID, point A in Fig. 2. Normally, when capacitors are connected in the distribution network, the PCC will be at a higher voltage level. The cable capacitance and inductance could also introduce a resonant mode. For the 230-V single-phase circuit, the cable capacitance is about 1 F/km and inductance is about 230 H/km. Fig. 10 shows the relationship between the resonance frequency and cable length. The supply fault current level is assumed to be 1 kA. It is clear that for cables shorter than 5 km, which is usually the case, there is no risk of resonance as long as the switching frequency of the FCLID is under 2 kHz. Too high a switching frequency should also be avoided from the device point of view to prevent excessive switching losses. VI. EXPERIMENTAL RESULTS An experiment was set up for the network shown in Fig. 2, where the line current and voltage as well as the current in other load connected at the PCC were recorded. Fig. 11 shows a cycle set to 120 A and set to 50 A. of the line current with Its spectrum is shown in Fig. 12. Good agreement is observed with previous simulation results. Earlier analysis and conclusions based on computer simulation are, therefore, validated. VII. EFFECT OF FCLID ON SMPS Typical loads that are most sensitive to the distorted waveforms produced by the FCLID are domestic and commercial electronic equipment such as a personal computer (PC) and television (TV). Such equipment normally includes SMPS. As shown in Fig. 13, the SMPS derives its power from the utility supply via a diode rectifier with a capacitively smoothed dc link.

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Fig. 11.

Measured FCLID current waveform (I

= 1 kA).

Fig. 14.

Input current to SMPS.

Fig. 12.

Spectrum of measured FCLID current. Fig. 15. PC current with a remote fault.

Fig. 13.

SMPS.

The input current is usually discontinuous as shown in Fig. 14. It is useful to consider the effects of the proposed FCLID on such load when connected to the PCC in the distribution network. A main concern is that the FCLID may affect the operation of the SMPS due to the high rate of change of voltage when the semiconductor device in the FCLID is turned off and the clamping voltage of the varistor appears across the FCLID. Test has been performed for a case when the short-circuit fault is far from the FCLID. The prospective fault current is 1 kA. A PC is connected in front of the FCLID. Figs. 15 and 16 show the PC

Fig. 16.

PC voltage with a remote fault.

current and voltage waveforms. For a fault close to the FCLID, the corresponding waveforms are shown in Figs. 17 and 18.

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AHMED et al.: HARMONIC ANALYSIS AND IMPROVEMENT OF A NEW SOLID-STATE FAULT CURRENT LIMITER

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Fig. 17.

PC current with fault close to FCLID.

Fig. 19.

Simulated PC current.

Fig. 20. Fig. 18. PC voltage with fault close to FCLID.

Simulated PC voltage.

It is shown that the high applied at the input of the SMPS will be seen by the dc-link capacitor, causing input current spikes. The spikes are higher when the fault is close to the fault current limiter and, hence, the PCC. The current spikes may exceed the fuse rating of the SMPS and cause fuse fatigue. Fig. 17 shows the moment when the PC fuse blew at 220 ms after the fault current limiter started operating. The second problem which may arise, particularly when the fault is close to the FCLID, is that more zero-crossing points are introduced in the voltage waveform. This may affect the operation of equipment that is phase locked to the sinusoidal supply voltage. A simulation model is used to recreate the situation shown in Figs. 17 and 18. The results are given in Figs. 19 and 20. Similar signatures can be observed between the simulation and experiment if the measured waveforms are zoomed in. As a solution to the above problem, a small inductor of 100 H may be inserted in series with the FCLID. The simulation results for this case are shown in Figs. 21 and 22. The rating and the required duration of of the inductor depends on FCLID operation. Referring to the analysis about harmonics in

Fig. 21.

PC current with series inductor.

Section III, it is generally advisable to include a series inductor with the FCLID proposed.

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Fig. 22.

PC voltage with series inductor.

VIII. CONCLUSION This paper has investigated the problems associated with harmonic generation in a new solid-state FCLID. Simulation and test were performed regarding the application of the FCLID in a typical 230-V single-phase distribution network. Factors affecting the harmonic characteristics were identified. The risk of harmonic resonance and adverse effect on sensitive loads such as SMPSs were assessed. Remedy actions were recommended. The results obtained from simulation and the experimental test show the following. 1) Operation of the proposed FCLID will produce harmonic current into the supply system which can be reduced by . increasing 2) The short-duration harmonics produced by the FCLID comply with the harmonics standards (IEEE 5191992 and G5/3). 3) Proper measures can be taken to avoid the risk of harmonic resonance between the cable or power-factor-correction capacitance, and the supply network inductance. Insertion of a small series inductor will attenuate the undesirable effects on sensitive loads such as SMPS. The voltage waveform at the PCC is also improved. 4) Provided that a detailed system study is carried out, the major problems regarding harmonics in the proposed FCLID are generally solvable. ACKNOWLEDGMENT The authors would like to thank Northern Electric Distribution Ltd., U.K., and the Regional Center for Electronic Technology (ReCET), U.K., for their support to and advice on this work. This paper describes part of a development work, the results of which have been submitted in a patent application. REFERENCES
[1] R. K. Smith, P. G. Slade, and H. Mehta, Solid-state distribution current limiter and circuit-breaker application requirements and control strategies, IEEE Trans. Power Delivery, vol. 8, pp. 11551164, July 1993.

[2] T. Ueda, M. Morita, and H. Arita, Solid-state current limiter for power distribution system, IEEE Trans. Power Delivery, vol. 8, pp. 17961801, Oct. 1993. [3] A. J. Power, An overview of transmission fault current limiter, in IEE Colloq. Fault Current LimiterA Look at Tomorrow, June 1995, Dig. 1995/026, pp. 1/11/5. [4] L. Salasoo, Comparison of superconducting fault limiter concepts in electric utility applications, IEEE Trans. Appl. Superconduct., vol. 5, pp. 10791082, June 1995. [5] G. A. Putrus, N. Jenkins, and C. B. Cooper, A static fault current limiting and interrupting device, in IEE Colloq. Fault Current LimiterA Look at Tomorrow, June 1995, Dig. 1995/026, pp. 5/15/6. [6] IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems, ANSI/IEEE Std. 519-1992. [7] Limits for Harmonics in the United Kingdom Electricity Supply System, Engineering Recommendation G5/3, 1979. [8] M. M. R. Ahmed and G. Putrus, Investigation into custom power technology, in Proc. UPEC99, 1999, pp. 519522. [9] M. M. R. Ahmed, Report on development of a solid-state FCLID, School Eng. Technol., Univ. Northumbria, Newcastle upon Tyne, U.K., 1999. [10] G. A. Putrus, M. M. R. Ahmed, and L. Ran, Improving current sharing between parallel varistors, in Proc. IEEE ISIE01, Pusan, Korea, June 2001, pp. 13241327. [11] J. Arrillaga, D. A. Bradley, and P. S. Bodger, Power System Harmonics. New York: Wiley, 1985.

M. M. R. Ahmed (M00) was born in Cairo, Egypt, in 1967. He received the B.Sc.E.E. degree from Helowan University, Helowan, Egypt, in 1989, the M.Sc. degree in electrical engineering from Cairo University, Cairo, Egypt, in 1994, and the Ph.D. degree from Northumbria University, Newcastle upon Tyne, U.K., in 2002. He was a Lecturer at the National Civil Aviation Training Institute, Cairo, Egypt, from 1990 to 1991, followed by four years as an Administrate and Teacher at the Industrial Education College, Cairo, Egypt. From 1993 to 1996, he was with the Abha Technical College, Abha, Saudi Arabia, as a Teacher. He is currently a Lecturer with the Faculty of Industrial Education, Industrial Education College. His research areas are in power electronics, microcomputer control, dc motor drives, power systems, and power quality. Dr. Ahmed has reviewed papers for several IEEE conferences.

Ghanim A. Putrus was born in Mosul, Iraq, in 1955. He received the Ph.D. degree from the University of Manchester Institute of Science and Technology (UMIST), Manchester, U.K. He joined Northumbria University, Newcastle upon Tyne, U.K., as a Senior Lecturer in Power System Engineering in January 1995, after working for six years at UMIST. Since moving to Northumbria, he has provided consultancy to several companies, including Northern Electric Distribution Ltd., VATECH Reyroll, and National Grid Company (NGC). He has over 20 years of research experience in electrical power engineering and has authored over 35 publications in journals and conference proceedings. His main research interests are the application of power electronics in power systems, in particular, FACTS, custom power technology, and active control of power distribution networks. Dr. Putrus was a Member of the 19992000 Professional Group P7 of the Institution of Electrical Engineers, U.K. (IEE). He is still regularly involved in IEE professional activities such as organizing lectures and refereeing papers.

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Li Ran (M98) was born in Sichuan, China, in 1963. He received the Ph.D. degree in power engineering from Chongqing University, Chongqing, China, in 1989. He then became a Lecturer at Chongqing University. Between 19921999, he was a Research Fellow at the Universities of Aberdeen, Aberdeen, U.K., Nottingham, Nottingham, U.K., and Heriot-Watt, Edinburgh, U.K., where he was involved in research on marine and offshore electrical systems, and industrial drives. Between 19992003, he was a Lecturer in Power Electronics at Northumbria University, Newcastle upon Tyne, U.K. He joined the University of Durham, Durham, U.K., in 2003. His present research interests include the control and grid integration of offshore renewable energy systems. Dr. Ran received a Stanley Gray AwardOffshore Technology from the Institute of Marine Engineers in 1999 for his work on the interconnection of offshore oil platforms.

Lejun Xiao was born in Hunan, China, in 1963. He received the B.Eng. and M.Eng degrees from Xian Jiaotong University, Xian, China, in 1983 and 1986, respectively, and the Ph.D. degree from the University of Bradford, Bradford, U.K., in 2000. He was an Associate Professor at Hunan University, Changsha, China, before joining the University of Strathclyde, Glasgow, U.K., as an Academic Visitor in 1995. Between 20002001, he was a Senior Research Assistant at Northumbria University, Newcastle upon Tyne, U.K. He is currently a Research Fellow at the University of Salford, Manchester, U.K. His main research interests are in power electronics, power systems, electromagnetism, room acoustics, and controller design and DSP implementation.

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