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Table Of Contents

1 Introduction
1.1 Foundations of 100 Hz technology
1.1.1 Prerequisites for 100 Hz
1.1.2 100 Hz display modes
1.1.3 Mode AABB
1.1.4 Mode ABAB
1.1.5 Mode AA’B’B
1.1.6 Mode AA*BB*
2 Basic board
2.1 Standby power supply
2.1.1 Standby power supply circuit
2.2 Blocking oscillator type power supply
2.2.1 Primary side
2.2.2 Start-up
2.2.3 Normal and control operation
2.2.4 Protective operation
2.2.5 Power Factor Control
2.2.6 Secondary side
2.2.7 Voltage stabilisation
2.2.8 Voltage increase
2.2.9 Servicing information
2.3.1 Horizontal driver
2.4 Horizontal output stage
2.4.1 High voltage production
2.4.2 Horizontal- offset deflector
2.5 East/west correction
2.5.1 Circuit
2.6 Vertical output stage
Vertical output stage
2.6.1 Flyback generator
2.6.2 Vertical protection circuits
2.7 Beam current limitation
Beam current limitation
2.7.1 Overbeam current fuse
2.7.2 HFLB protective circuit
2.8 Speed modulator
2.8.1 General
2.8.2 Switching of the speed modulator
2.9 Colour stages
2.9.1 Cut off control
2.9.2 Switch off flash suppression
2.10 Rotation panel
2.10.1 Raster correction
Switch off flash suppression
2.10.2 Circuit
2.11 NF output stages
3 Receiver components
3.1 HF/IF unit
3.1.1 HF/IF components
3.2 DVB Board
3.2.1 Overview
3.3.2 DVB/TV features
3.3.3 Architecture
3.4 Components
3.4.1 Satellite front end
3.4.2 Functional distribution
3.4.3 Tuner
3.4.5 LNC supply
4 Signal board
4.1 Device control
4.1.1 The infrared sensor
4.1.2 Infrared receiver
4.1.3 The SDA 6000 central control unit
4.1.4 Reset
4.1.5 Creation of cycle frequency
4.1.6 Operational commands
4.1.7 LED display
4.1.8 ON/OFF function
4.1.9 Protective circuit
4.1.10 AV operation
4.2 Bus systems in Q 2500 chassis
4.2.1 I²C bus systems
4.2.2 IC 24C64 memory
4.2.3 EPROM M 27 C 322
4.2.4 SRAM
4.2.5 Search functions
4.2.6 Storage
4.2.7 Programme recall
4.2.8 System clock
4.2.9 Control of signal processing
4.2.10 Service mode
4.2.11 Video text
4.2.12 Picture signal processing
4.2.14 Signal path
4.2.15 IC functions
4.3 VPC 3230
4.3.1 Input interface
4.3.2 20.25 MHz clock generator
4.3.3 Comb filter
4.3.4 Multi-standard colour decoder
4.3.6 Output format conversion
4.3.7 Synchronisation block
4.3.8 I²C bus interface
4.4 Half picture memory SAA4955HL
4.4.1 Storage space
4.4.3 Half picture memory 2 and 3
4.4.4 Control pulses
4.5.2 Line interpolation
4.5.3 Movement detector
4.5.4 Memory control
4.6 SAA 4979 (BESIC)
4.6.1 Chroma branch
4.6.2 Band width doubling
4.6.3 Colour flank sharpening
4.6.4 Y signal path
4.6.5 Microprocessor interface
4.6.6 Control of the 100 Hz processing (Display)
4.7.2 Control stages
4.8 Picture in picture
5 Audio signal processing
5.2.9 Sound setting
5.2.11 DAC
5.2.12 Headphone branch
5.2.13 Interface branch
5.2.14 Deadline volume
5.2.15 Mute circuit
5.2.16 Headphone amplifier
5.3 AC3 module (Dolby Digital)
5.3.2 AC 3 signal processing
5.3.3 AC 3 IC functions
6 Interface switching
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Q2500 Engl Uebersetzung

Q2500 Engl Uebersetzung

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Published by Liisel Laks

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Published by: Liisel Laks on Oct 22, 2011
Copyright:Attribution Non-commercial

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10/22/2011

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