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Lab 3

Lab 3

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Published by acormier

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Published by: acormier on Nov 14, 2008
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12/28/2012

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RSTCLKD1XX00Falling000Falling11
1 -Flip Flop Truth Table
Lab 3 Page 1
 
Transistor Level DiagramThe last gate was sized to drive the output load (100fF) reasonably well.
2 -Flip Flop Schematic
Lab 3 Page 2
 
This waveform shows the output only changing state on the negative edge of the CLK at which point theinput is sampled and reflected in the output.The waveform also shows the minimum setup time => .2ns
3 -Flip Flop HSpice
Lab 3 Page 3

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