1 - Flip Flop Truth Table

RST CLK D Q
1 X X 0
0 Falling 0 0
0 Falling 1 1

Lab 3 Page 1
2 - Flip Flop Schematic

Transistor Level Diagram

The last gate was sized to drive the output load (100fF) reasonably well.

Lab 3 Page 2
3 - Flip Flop HSpice

This waveform shows the output only changing state on the negative edge of the CLK at which point the
input is sampled and reflected in the output.

The waveform also shows the minimum setup time => .2ns

Lab 3 Page 3
4 - Truth Table of Shifter

Q =D << M

Lab 3 Page 4
5 - Shifter Schematic

Lab 3 Page 5
6 - Shifter Logic Output

Lab 3 Page 6
7 - Shifter with Flip-Flops

Lab 3 Page 7
8 - Clock Estimation

For the last lab, we saw that through 3 stages of MUX's the total propagation delay was around 2ns.

Since we now have the setup time for the flip flops to worry about which was calculated to be
around .2ns, and we also have a clock skew to worry about, I estimate that I'll practically be able to
reach a 3ns propagation delay through the 8 bit shifter which will come out to 1/3ns -> 330 Mhz

Lab 3 Page 8
9 - Shifter with Flip Flop Simulation

A simulation showing the correct operation of the 8 bit shifter with flip flops.

Now showing the 8bit shifter under high speed failing to operate 100% correctly.

Lab 3 Page 9
Lab 3 Page 10
10 - Layout

Lab 3 Page 11