LABORATORY 3 – COMBINATIONAL & SEQUENTIAL CIRCUIT

LABORATORY 3
COMBINATIONAL & SEQUENTIAL CIRCUIT
OBJECTIVES
No. Objectives Requirements
1 Design a combinational circuit (a 1-bit Full ▪ Complete schematic and
Adder). transient simulation.
2 Design a sequential circuit (a PRBS – Pseudo ▪ Measure some timing
Random Binary Sequence – generator). parameters and power
consumption.
▪ Define speed/clock speed of
your design.

EXPERIMENT 1

Objective: Known how to design a basic combinational circuit.

Requirement: Students implement some topology of 1-bit Full Adder.

Instruction:

➢ In this section, students have a chance to review 1-bit Full Adder (FA). Moreover, FA
will be observed in another aspect – topology. First, let’s overview the truth table of this
component.

Figure 1 Block diagram of FA.

𝐴 𝐵 𝐶𝑖𝑛 𝑆 𝐶𝑜𝑢𝑡 Carry Status
0 0 0 0 0 Delete
0 0 1 1 0 Delete
0 1 0 1 0 Propagate
0 1 1 0 1 Propagate
1 0 0 1 0 Propagate
1 0 1 0 1 Propagate
1 1 0 0 1 Generate
1 1 1 1 1 Generate

Table 1 Truth table of 1-bit Full Adder.

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′ ′
𝑆 = 𝐴′ 𝐵′ 𝐶𝑖𝑛 + 𝐴′ 𝐵𝐶𝑖𝑛 + 𝐴𝐵′ 𝐶𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛 = 𝐴⨁𝐵⨁𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶𝑖𝑛 + 𝐵𝐶𝑖𝑛 = (𝐴 + 𝐵)𝐶𝑖𝑛 + 𝐴𝐵

Figure 2 Logic circuit of FA.

➢ Observe the last column of 1-bit FA truth table – “Carry Status” column – there are
three keywords you need to take care: delete, propagate, and generate. These are analyzed as
follows:
o Generate: concept even if 𝐶𝑖𝑛 = 0, 𝐶𝑜𝑢𝑡 = 1
▪ 𝐺𝑒𝑛𝑒𝑟𝑎𝑡𝑒 ≡ 𝐺 = 𝐴𝐵
o Delete: concept even if 𝐶𝑖𝑛 = 1, 𝐶𝑜𝑢𝑡 = 0
▪ 𝐷𝑒𝑙𝑒𝑡𝑒 ≡ 𝐴′𝐵′
o Propagate: even does not generate if 𝐶𝑖𝑛 = 1, 𝐶𝑜𝑢𝑡 = 1
▪ 𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑒 ≡ 𝑃 = 𝐴′ 𝐵 + 𝐴𝐵′ = 𝐴⨁𝐵

These keywords can be used to implement Carry Look Ahead Adder to improve critical path in
Ripple Carry Adder.

➢ When students count the number of transistors used in Figure 2, they find that it
amounts to 46 transistors. This indicates that the area of this topology is large, so solutions to
reduce the number of transistors are needed.
➢ First, student can use the Boolean function to implement (compound gate). However,
the equation describing sum output exists in another form:
o 𝑆 = 𝐴𝐵𝐶 + 𝐶𝑜𝑢𝑡 ′(𝐴 + 𝐵 + 𝐶𝑖𝑛 )
o 𝐶𝑜𝑢𝑡 = (𝐴 + 𝐵)𝐶𝑖𝑛 + 𝐴𝐵

According to the equation, the 𝐶𝑜𝑢𝑡 ′ will be created at the first stage in this topology. The sum
will be calculated after.

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Figure 3 FA 28T.

However, this topology still has some disadvantages such as: long stacking PMOS, loading to
𝐶𝑜𝑢𝑡 (2𝐶𝐷 + 6𝐶𝐺 + 𝐶𝑊 )…

➢ Second, another solution uses Mirror Adder.

Figure 4 FA 24T – Mirror Adder.

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Figure 5 Summarized the topologies and equations of 1-bit Full Adder.

Check: Students must show in your report these results

➢ The waveform to prove the circuit works correctly.

➢ Show measurements result shown in Table 1. Moreover, please present how to

measure or calculate rising/falling propagation delay, propagation delay, and speed of design.
In addition, to define speed of your design, students can use critical path method.

Original FA FA 28T FA 24T

(Figure 2) (Figure 3) (Figure 4)

𝑡𝑟𝑖𝑠𝑒 - Rising time (10%-90%)

𝑡𝑓𝑎𝑙𝑙 - Falling time (90%-10%)

𝑡𝑝𝑑𝑟 – Rising propagation delay

(90%-50%)

𝑡𝑝𝑑𝑓 – Falling propagation delay

(10%-50%)

𝑡𝑝𝑑 – Average propagation delay

(50% - 50%)

Power consumption

Speed

Table 2 Measurement result of a 1-bit Full Adder.

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Questions:

➢ Due to the topology shown in Figure 3, why do people implement the PDN of the first
stage using equation 𝐶𝑜𝑢𝑡 = (𝑨 + 𝑩)𝑪𝒊𝒏 + 𝐴𝐵 instead of 𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝑨𝑪𝒊𝒏 + 𝑩𝑪𝒊𝒏?

Figure 6 The PDN using 𝐶𝑜𝑢𝑡 = (𝑨 + 𝑩)𝑪𝒊𝒏 + 𝐴𝐵 (left), and 𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝑨𝑪𝒊𝒏 + 𝑩𝑪𝒊𝒏 (right).

➢ Due to the topology shown in Figure 3, at the PDN of the first stage, why do people
put 𝐶𝑖𝑛 on top in this topology?

Figure 7 The PDN with 𝐶𝑖𝑛 connecting 𝐶𝑜𝑢𝑡 (left), and 𝐶𝑖𝑛 connecting to ground (right).

EXPERIMENT 2

Objective: Known how to design a basic sequential circuit.

Requirement: You will learn PRBS, or pseudo random binary sequence, which is a type of
algorithm-generated random signal.

Instructions:

➢ A pseudo random binary sequence (PRBS) is often used as model data to test a high-
speed serial interface devices for emulating a mission mode. It is mathematically randomized

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bit stream so that is well neutralized and balanced data. A PRBS bit stream can be generated
by using a linear feedback shift register (LFSR).
➢ Figure 1 illustrates an example of a 4-bit LFSR and its shifting data pattern.
o When the shift register is filled up with a seed pattern of all 1’s here, the table
in the right hand side depicts how the register contents change and put out a series of PRBS.
o Right after the final bit, it returns to the top of the bit stream.
o There are 15 bits of pseudo random bit stream generated.

Figure 8 Linear Feedback Shift Register (LFSR).

Figure 9 Illustrate the PRBS-4 algorithm in more detail.

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➢ Figure 8 illustrates how the 15-bit PRBS pattern looks like a waveform. There are 8
edges toggling in the 15 bits NRZ pattern, containing eight 1’s and seven 0’s. This is a general
feature of a PRBS shown in Table 3.

Figure 10 Waveform of PRBS by 4-bit LFSR.

LFSR n−𝒃𝒊𝒕 n 4 7

PRBS Length 2𝑛 − 1 15 127

# 𝒐𝒇 "1"𝒔 2𝑛−1 8 64
# 𝒐𝒇 "𝟎"𝒔 2𝑛−1 − 1 7 63
# 𝒐𝒇 𝒆𝒅𝒈𝒆𝒔 2(𝑛−1) 8 64

Table 3 Features of LFSR and PRBS.

➢ An n-bit LFSR generates 2𝑛 − 1 bits of PRBS. By carefully looking at the bit pattern in
the shift register, you can see there are all 4-bit combinations appeared except all 0’s. If
students feed the pattern of “0000”, the shift register would be stuck, and it generates only 0’s
infinitely. A seed pattern must not be all 0’s. So, one of the 15 4-bit patterns can be accepted
as a seed.
➢ The linear feedback shift register is implemented as a series of Flip-Flops as a shift
register. Several taps off of the shift register chain are used as inputs to either
an XOR or XNOR gate. The output of this gate is then used as feedback to the beginning of the
shift register chain, hence the Feedback in LFSR.

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Figure 11 4-Bit LFSR using XOR gate.

➢ Students can use any schematic of DFF you want, even the design presented in
laboratory 2. In addition, students should study some types of shift register already existed
such as: SIPO, SISO, PISO, PIPO.

Figure 12 Some types of Shift Register.

➢ In general, a shift register has a clock, a serial input 𝑆𝑖𝑛 , a serial output 𝑆𝑜𝑢𝑡 , and 𝑁
parallel outputs 𝑄[𝑁 − 1: 0]. In case DFF is positive edge triggered, on each rising edge of the
clock, a new bit is shifted in from Sin and all the subsequent contents are shifted forward. The
last bit in the shift register is available at 𝑆𝑜𝑢𝑡 . Shift registers can be viewed as serial-to-
parallel converters. The input is provided serially (one bit at a time) at 𝑆𝑖𝑛 . After 𝑁 cycles, the
past 𝑁 inputs are available in parallel at 𝑄.
➢ A shift register can be constructed from 𝑁 flip-flops connected in series, as shown in
Figure 13(b). Some shift registers also have a reset signal to initialize all of the flip-flops.

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(a) (b)

Figure 13 (a) Shift register symbol (b) Shift register schematic.

➢ Before running simulation your PRBS generator, please remember to transmit input
data for your design. This work can be done by using vbit source (in analogLib) with MOS
device to isolate when transmit data period is complete or set up some initial conditions
(ADE L>Simulation>Convergence Aids>Initial Condition) … However, for any method used,
please explain it.

Check:

➢ Show the schematics of your design, and waveform prove your design work correctly.
➢ Define and show how to measure clock speed.
➢ Students can refer to this Python code to check your result or any online generator
found.

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# -*- coding: utf-8 -*-

"""
Created on Tue Oct 10 22:48:56 2023

@author: nelsonn
"""
import matplotlib.pyplot as plt

#Generate binary string using PRBS-7

#number of bit you want

n = int(input('Number of bit of PRBS you want: '))

#random a number from 0 <= x < 2^n -1

state = int(input('Initial state: '), 2)

output_PRBS = []

for i in range(2**n - 1):

print(state & 1, end = '')
output = state & 1
output_PRBS.append(output)
newbit = (state ^ (state >> 1)) & 1
state = ((state >> 1) | (newbit << (n-1)))

print('A randomized bit stream: ', output_PRBS)

print('Length of randomized bit stream = ', len(output_PRBS))

#Plotting
plt.tight_layout()
plt.figure(figsize=(15, 8))
plt.step(range(len(output_PRBS)), output_PRBS, drawstyle='steps',
color='r')
plt.title('PRBS')
plt.ylabel('Voltage Level')
plt.grid(True)
plt.show()

Figure 14 PRBS generator in Python programming language.

➢ Use this PRBS generator to verify the adder (any topology you want) in experiment 1.
Show the schematics of your design, and waveform.

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❖ ONE MORE THING…

After completing this lab, please answer the following questions.

▪ How much time did you spend completing this lab?

▪ Is there any problem when you do? Please let me know.

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