2

Setup the Design Environment

Synthesis and Simulation Setup Files
target_library = {kcells.db pads.db} link_library = {. kcells.db pads.db} symbol_library = {kcells.sdb} edifout_netlist_only = true

In this step you setup the synthesis and simulation design environment by using the Synopsys setup files. Some of the variables that need to be specified before you can run synthesis and gate-level simulation include the technology and symbol libraries of the target technology, gate-level simulation libraries, as well as the search path to these and other libraries and design references.

From RTL Description to Layout

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2.1 Copy A Sample Synthesis Setup File

There are a number of variables that need to be set before you can run the Synopsys synthsis tools. These variables are set in the .synopsys_dc.setup file. Fortunately, almost all technologies that support Synopsys synthesis comes with a sample synthesis setup file. You must copy this file into your design directory and name it .synopsys_dc.setup. You should also create a sub-directory named WORK in your working directory. This directory is used by synopsys as a temporary working directory when it analyzes the HDL files. (To know how you can change the meaning and mapping of this directory, read about the design_lib variable in synopsys).

Go to your design directory cd design_dir Copy the sample synthesis file from the directory containing the technology design kit for Synopsys. cp /CMC/kits/technology/synopsys/technology.version/dotfiles/dc_dot_file .synopsys_dc.setup Make a directory called Work. This directory will contain a virtual library called WORK which is where Synopsys will put the compiled and intermediate files. The library name is not the smae as the directory name. We make them close for convenience. design_dir Your design directory. Put your Verilog or VHDL files here. technology The name of the technology you are targeting. Examples are bicmos, mitel15, cmosis5, and cmosp35. version The version of the technology CMC design kit for Synopsys. Examples are 1.1 and 2.1 dc_dot_file The name of the sample synthesis setup file. In some technologies this sample file is given the name .synopsys_dc.setup (i.e. it is a hidden file and hence you have to list all dot files in order to check if it exist - use the Unix command ls .synopsys_*), while in others, the name is usually target_lib.synopsys_dc.setup, where target_lib is the name of the target library in the technology, e.g. kcells in the bicmos technology.

TUTORIAL STEP

At the Unix prompt, type:

cd design_dir mkdir Work cp /CMC/kits/cmosp35/synopsys/dotfiles/ .synopsys_dc.setup .synopsys_dc.setup

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2.2 Verify/Edit the Synthesis System Variables

Open the .synopsys_dc.setup file in an editor to verify/edit it to make sure that the synthesis system variables described below are set correctly. Note that apart from these variables, the setup file might contain other variables such as bus naming and EDIF options. Variables not described below should be left unchanged.

search_path This specifies the directories to be searched by the synthesis tools for files. It should include at least the following:
search_path = {. design_kit_dir//syn synopsys_dir/libraries/syn}

TUTORIAL STEP

where . indicates the directory you started the synthesis tools from (your design directory) target_library Specifies a list of technology libraries of components used when compiling a design.
example: target_library = {hcells.db}

company = put_your_company_name_here designer = put_your_name_here search_path = {.} search_path = search_path + {/CMC/tools/synopsys/libraries/syn} search_path = search_path + {/CMC/kits/ cmosp35/synopsys/1998.02/syn}

link_library Specifies a list of design files and libraries used during linking. Linking resolves design references by connecting the design to all library components and designs it references. For this reason include an asterisk (*) in the list to include all the designs in your design library.
example: link_library = {* hcells.db}

symbol_library Specifies the libraries that contain the graphical information of symbols of components used when displaying the schematic of a compiled design. Files for symbol libraries usually end in .sdb extension.
example: target_library = {hcells.sdb}

designer Your name (the designer). This is displayed on the design schematics.
example: designer = Peter Nyasulu

company The companys name where the Synopsys tools are installed. It is also displayed on design schematics.
example: company = Carleton University

design_kit_dir The directory containing the technology design kit for Synopsys. Normally it should be /CMC/kits/technology/synopsys/technology.version, where technology is the name of the technology (e.g mitel15, bicmos, cmosis5) and version is the kit version (e.g. 1.1) synopsys_dir The Synopsys tools root directory. Normally it should be /CMC/tools/synopsys.3.4b.

From RTL Description to Layout

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2.3 Setup the Synopsys VSS Simulation (VHDL Only)

Most of the variables required to simulate a design using the Synopsys VHDL System Simulator (VSS) are already setup correctly in the Synopsys generic VSS setup file (.synopsys_vss.setup). However, there are still a few variables that need to be customized for your design simulation. Firstly, for gate-level simulation, you need to specify the path to the Full Time Gate-level Simulation (FTGS) libraries of your target technology. FTGS libraries contain both the gate functionality as well as gate delays. You may also optionally specify the time step of the simulation.

Go to your design directory cd design_dir Using your favorite editor, open/create the file .synopsys_vss.setup. For example, if you are using emacs editor, type the following at the Unix prompt: emacs .synopsys_vss.setup & In the file, specify the following variables: FTGS Library This defines the names of the libraries to be used in the RTL file for gate-level simulation, as well as the path to the actual FTGS libraries (the defined library name doesnt have to be the same as the actual name of the library). You must define this for each of the target library used in your design (libraries specified in the target_library variable in .synopsys_dc.setup file). Syntax: gate_library: /CMC/kits/technology/synopsys/ technology.version/sim/target_library_name Example (when using the cmosis5 technology): hcells: /CMC/kits/cmosis5/synopsys/cmosis5.1.1// 3.4b/sim/hcells Simulation Time Base/Resolution The units and resolution of the simulation times. For example, to set simulation units to nanoseconds, and the resolution to 100 picoseconds, add the following lines in the setup file: TIME BASE = NS TIME_RES_FACTOR = 0.1 Editor Editor that synopsys invokes when you execute any of the Synopsys environment edit file commands. The default editor is set to vi. For example, to set the editor to Emacs, include the following line in the setup file (assuming emacs is the command that is used to invoke the Emacs editor): EDITCMD = emacs

TUTORIAL STEP

TIME_BASE = NS TIME_RES_FACTOR = 0.1 EDITCMD = emacs

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