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Performance Comparison of 2D and 3D Torus Network-on-Chip Architectures

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract Using the Torus topology in the two and three-dimensional NoCs (3D NOCs) is attractive solution for system performance improvement by reducing the interconnect length, hop count, etc. The 3D-Torus NOC has a high reliability in the presence of permanent faults and fast communication. We also carry out the high-level simulation of on chip network using NS2 to verify the analytical analysis. Index Terms NoC (Network on chip), embedded applications, fault-tolerant, torus, NS2.

1 INTRODUCTION
With continuously shrinking feature size, more and more processing cores and memories are integrated on a single chip. Two major trends, i.e. communication-centric interconnect architecture based on network-on-chip (NoC) that addresses scalability challenges as well as bandwidth bottleneck [1][2] and three dimensional integrated circuits (3D ICs) that alleviate interconnect latency pressure as well as heterogeneous integration problems [3] [4] [5] [6], are emerging for such complex integrated systems. NoC architecture provides a wide design space including network topology, routing algorithm, and router architecture, all of which affect the system performance at the expense of different amounts of network resources; therefore the network architecture for such embedded applications should be carefully selected so as to meet the requirements [7]. Such embedded applications often demand very tight design constraints in terms of cost and performance; thus the silicon budget available for their on-chip network infrastructure should be modest as long as the required performance is met. Network-on-Chips (NoCs) have been studied to connect a number of processing cores on a single chip by introducing a network structure similar to that of parallel computers [8]. the ability to implement them over multiple die layers on the same chip. It can also reduce form factor in applications where size is critical, while effective heat dissipation and temperature control can be a challenge. To get the most benefit out of 3D chip stacks in multiprocessor systems, the communication architecture has to support efficient and high throughput vertical communication. In this article we examine the scalability of the NoC for such systems. Furthermore, the emerging three-dimensional (3D) integration and process technologies allow the design of multi-level Integrated Circuits (ICs). As illustrated in [12], this creates new design opportunities in NoC design. In order to satisfy the demands of emerging systems for scaling, performance and functionality 3D integration is a way to accommodate these demands [13]. For example, a considerable reduction can be achieved in the number and length of global interconnection using threedimensional integration. On deciding whether to choose a two-dimensional (2D) or 3D NoC as an architecture it is shown in [14, 15] that 3D NoCs are advantageous, providing better performance.

3 NETWORK AND SYSTEM ARCHITECTURE

One of the widely used NoC topologies is the Mesh architecture. We analyze the performance of a Mesh-based NoC in presence of permanent faults With IP routing are adopted.

2. BACKGROUND 2.1 THREE DIMENSIONAL NOC

Besides NoCs, three-dimensional integrated circuits (3D ICs) are another attractive solution for system performance improvement by reducing the interconnect length. [9] However a major new paradigm for continued Moores law integration is 3D chip stacks based on a variety of vertical interconnection techniques [10], [11]. 3D integration provides opportunities for cost reduction and yield improvement in integration of different technologies such as CMOS, DRAM and MEMS circuits through

3.1. Protocol
Circuit switching involves a physical path from source to destination which is reserved prior to data transmission. In packet switching, however, packets containing routing information are forwarded on a per-hop basis [16]. The common characteristic of NoC architectures is that the constituent IP cores communicate with each other through switches. We assume that the buffer size in each resource is infinite but finite in switches. This implies that

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the packet being dropped cannot happen in resources but only take place in switches [17].

cores, where a blue circle represents a network interface of the core and a red square represents a router connecting other routers or network interfaces.

3.2 Topology and Hardware Architectures

Our NOC is a scalable packet switched communication platform for single chip design. The NOC architecture consists of a mesh of switches with some resources. Resources Are Heterogeneous or can be homogeneously. A resource can be intellectual properties (IPs). Two different network topologies have simulated namely Mesh and Bruijn. The size of both topologies is 8*8 switches that shown as below:

3.3. FAULT MODEL

There exist several dimensions in classifying the possible fault occurrences during the life cycle of an MPSoC. We list the classification as follows: Duration In terms of duration, the faults can be classified into transient faults and permanent faults [18]. Location In general, MPSoC designs consist of two integrated parts, the Processing Elements (PEs) and Networkon-Chip (NoC). Faults can occur in both parts. In the case that a fault occurs in the PEs, the computation results will be erroneous. Dynamic fault detecting and masking actions are needed to make sure the erroneous results will not contaminate the application environment. In the case that a fault occurs in the communication path, such as link failure and scrambled messages, a fault-tolerant communication protocol suite, including error-resilient coding schemes, are needed to ensure the reliable delivery of on-chip messages on top of an unreliable on-chip communication substrate. Time to Failure, Faults can occur throughout the lifetime of an IC. Using the point when the chip is packaged and tested as the watershed event, we distinguish between before-shelf faults and after-shelf faults.

4. EVALUATIONS
One of the widely used NoC topologies is the Torus architecture. We analyze the performance of a Torusbased NoC in presence of permanent faults With IP routing. The Torus-based 2D and 3D NoCs simulated by NS2 (a network simulator). We simulated a 4x4x4 Torus based 3D-NOC and compared it with a 8x8 Torus 2DNOC. We reduce all parameters as multiply of 1000 to support the simulation time.

(a)

5. SIMULATION RESULTS
The simulation results of the proposed integrated approach are presented in Figures 3 and 4. The NoC topologies that were tested were 2D and 3D Torus ones of 64 nodes (Figure 1). In this section, the proposed scheme is evaluated through simulations in terms of performance.

5.1. THROUGHPUT & BANDWIDTH

As shown in fig. 2, when a permanent fault in time 1.2 occurs, therefore the communication load between of mentioned resources was reduces.

(b) Fig . 1. 2D and 3D Torus with equal switches and resources As shown in fig. 1, our on-chip network topologies with 64

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5.3. END TO END DELAY

End to end delay is another parameter that we consider for evaluation the performance of these architectures.

Fig. 2. supported bandwidth in 2D and 3D NoC Torus.

5.2. FAULT-TOLERANCE
As shown in fig .3, when a permanent fault occurs in communication path, the number of lost packets in mentioned architectures was equal to each other.

Fig. 4. Average end to end delay in two architecture.

As shown in fig .4, the average end-to-end delay between of mentioned cores in two-Dimensional Torus was the less than three-Dimensional Torus architecture. This means the data travels in two-Dimensional Torus was faster than three-Dimensional Torus architecture, with equal switches and resources.

5.4. Hop Count

Hop count refer to the number of switches through which a data packet passes from source to the destination, and consider for energy consumption in NoC. The deference of average hop count in this architecture has shown in fig. 5.

Fig. 1. Lost packets in both architecture.

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two dimentional torus architecture proposed in this paper could empower high throughput of data transmission with dramatic hop-Count reduction.

REFERENCES
[1] W. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, in Design Automation Conference, 2001, Proceedings, pp 684689, 2001. [2] L. Benini and G. DeMicheli, Networks on chips: A new SoC paradigm, Computer, vol. 35, no. 1, pp. 7078, 2002. [3] K. Bernstein, New Dimensions in Performance, System, vol. 2002, no. 2004, p. 2006, 2000. [4] T. Vucurevich, The Long Road to 3-D Integration: Are We There Yet, in Keynote speech at the 3D Architecture Conference, 2007. [5] G. Loh, Y. Xie, and B. Black, Processor design in 3D die-stacking technologies, IEEE Micro, vol. 27, no. 3, pp. 3148, 2007. [6] Y. Xie, G. Loh, B. Black, and K. Bernstein, Design space exploration for 3D architectures, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 2, no. 2, pp. 65103, 2006. [7]H. Matsutani, M. Koibuchi, H. Amano1, " Tightly-Coupled Multi-Layer Topologies for 3-D NoCs," proceedings of the Parallel Processing ICPP 2007, page 75, Sept. 2007. [8] W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," In Proceedings of the Design Automation Conference," pp. 684689, June 2001. [9] Y. Ye1, L. Duan, J. Xu1, J. Ouyang, M. Kwai Hung, Y. Xie, "3D Optical Networks-on-chip (NoC) for Multiprocessor Systems-on-chip (MPSoC)" In proceedings of the 2009 IEEE International Conference on 3D System Integration ,pp. 1-6, IEEE Press, 2009. [10] K. Banerjee, S. Souri, P. Kapur, and K. Saraswat, "3-d ics: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, 89(5):602633, May 2001. [11] A.W. Topol et al, "Three-dimensional integrated circuits," IBM Journal of Research and Development, 50(4):491506, 2006. [12] V. F. Pavlidis and E. G. Friedman, "3-D topologies for networks-onchip," IEEE TVLSI, 15(10):10811090, 2007. [13] E. Beyne, "3D system integration technologies," In International Symposium on VLSI Technology, Systems, and Applications, 2006. [14] A. Bartzas, N. Skalis, K. Siozios, and D. Soudris, "Exploration of alternative topologies for application-specic 3D networks-on-chip," In Proc. of WASP, 2007. [15] B. Feero and P. P. Pande. Performance evaluation for threedimensional networks-on-chip. In Proc. of ISVLSI, 2007. [16] T. Bjerregaard and S. Mahadevan, A survey of research and practices of network-on-chip, ACM Comput. Surv., vol. 38, no. 1, p. 1, 2006. [17] Yi-Ran Sun, Shashi Kumar, Axel Jantsch , Simulation and Evaluation for a Network on Chip Architecture Using Ns-2. [18] D. K. Pradhan. Fault-Tolerant Computer System Design. Prentice-Hall, Inc., 1996.

Fig. 2. Average hop count in both architecture.

As shown in fig. 5, the 2D-Torus has fewer hop count related to 3D-Torus architecture. These hop count has not effect on fault or bandwidth. The effect of min hop count was in the time to transfer the data between resources. Thus total delay for transfer a file with 4 Megabit was shown in fig. 6.

Fig. 3. Total Delay for transfer 4Megabit data.

As shown in fig. 6, total delay for transfer 4 Megabit data in 2D torus (because of the less hop count) was fewer than 3D torus.

5. CONCLUSIONS AND FUTUREWORK

Through detailed simulation-based analysis of the reliabitiy and network performance, we can consider that