SMES Laboratory 2 SystemC-TLM

1 Preparation

Study the material provided in moodle and at this page: https://www.doulos.com/knowhow/systemc/tlm2.

2 HW/SW Matrix multiplication

(Based on: ECE576 Uni. of Arizone, USA)

2.1 Overview
Use SystemC and transaction-level modeling
(TLM) to implement the system in figure shown
at the side, which executes a matrix
multiplication
as
a
hardware/software
partitioned design consisting of a software
component (SW), hardware coprocessor (HW),
and memory communicating over a shared bus
(bus).
The complete algorithm is shown below. The data of the matrix c[][] shall be stored in the memory, the
ADDMUL operation shall be executed in the HW component, which can also store one integer value, and the bus
control as well as the execution of the algorithm shall be realized by the SW component.
#define SIZE 5
int main() {
int i,j,k;
for(i=1;i<=SIZE;i++)
for(j=1;j<=SIZE;j++)
c[i][j] = 0;
for(i=1;i<=SIZE;i++)
for(j=1;j<=SIZE;j++)
for(k=1;k<=SIZE;k++)
c[i][j] += a[i][k] * b[k][j];
return 0;
}

2.2 Bus component

The bus implementation should consist of two interfaces, a bus master interface (bus_master_if) and a bus
servant interface (bus_servant_if) with support for directly modeling the various stages of the bus
communication protocol. Further, the bus implementation should support single data read and single data write
operations. The bus arbitration scheme can be freely chosen. The interface is shown below.
// Bus Master Interface
class bus_master_if : virtual public sc_interface
{
public:
virtual void Request(unsigned mst_id, unsigned addr, unsigned op,
unsigned len)= 0;
virtual bool WaitForAcknowledge(unsigned mst_id) = 0;
virtual void ReadData(unsigned &data) = 0;
virtual void WriteData(unsigned data) = 0;
};

// Bus Servant Interface

class bus_servant_if : virtual public sc_interface
{
public:
virtual void Listen(unsigned &req_addr, unsigned &req_op,
unsigned &req_len) = 0;
virtual void Acknowledge() = 0;
virtual SendReadData(unsigned data) = 0;
virtual ReceiveWriteData(unsigned &data) = 0;
};

The bus Request() should provide all information necessary to indicate what transaction is requested on the bus.
During the Request(), sufficient information should be provided such that any servant component listening to
the bus will receive the required information for responding (or determining if they should respond) to the
request. For example, consider an implementation in which only one bus master is present. In this scenario, the
bus master's Request() would need to include all information for the request such that the servants listening
(i.e., waiting within Listen() function) to the bus can respond with the Acknowledge() if the request is for them.
In this scenario, the acknowledge comes directly from the servant component as no arbiter is be present and
only one master is waiting for the acknowledge.
In a TLM implementation, components acting as bus masters should not be aware of the arbitration method.
Instead, all bus masters are provided the same protocol that hides the details of the arbitration such that the
WaitForAcknowledge() will wait until an Acknowledge() has been made by a servant component in response to
the bus master's request. While the bus arbitration is responsible for sending the acknowledge to correct master
component, the acknowledge comes from the servant component.

The WaitForAcknowledge() called by a master component should not return until an Acknowledge() has been
provided by a servant component in response to the current bus request. In other words, the bus component is
not responsible for generating the acknowledge, but rather simply forwarding an acknowledge from a servant
component.

2.3 Software Component

All communication between the software and hardware components cab be based on a freely chosen
addressing scheme (e.g., mapped). The application software that is not partitioned to hardware can be directly
modeled as C/C++ code within the software component. All array data (specifically arrays a, b, and c) are stored
within the memory component and all reads from or writes to these arrays must be accessed through the
shared bus.

2.4 Hardware Component

The hardware component can act as both a master and slave of the shared bus. Thus, the hardware component
should have two ports: one connecting to the bus_master_if of the bus and one connecting to the
bus_servant_if of the shared bus. All communication between the software and hardware components of the
bus must be implemented using the same memory addressing.

2.5 Memory Component

The arrays a, b, and c are located within a single memory component. You will need to determine both the
minimum required size for the memory as well define the specific addresses at which the memory is located.
The a and b data values within the memory should be initialized at the beginning of simulation from the memory
components constructor. The content for these arrays is as follows:
a = { 0,0,0,0,0,0,0,0,9,4,7,9,0,12,14,15,16,11,0,2,
3,4,5,6,0,4,3,2,1,2,0,2,7,6,4,9};
b = { 0,0,0,0,0,0,0,0,9,4,7,9,0,12,14,15,16,11,0,2,
3,4,5,6,0,4,3,2,1,2,0,2,7,6,4,9};