module ALU(ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output

Zero; assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase end

endmodule

module ALUControl(ALUOp, FuncCode, ALUCtl); input [1:0] ALUOp; input [5:0] FuncCode; output reg [3:0] ALUCtl; always @(ALUOp, FuncCode) begin if ( ALUOp == 2 ) case (FuncCode) 32: ALUCtl<=2; // add 34: ALUCtl<=6; //subtract 36: ALUCtl<=0; // and 37: ALUCtl<=1; // or 39: ALUCtl<=12; // nor 42: ALUCtl<=7; // slt default: ALUCtl<=15; // should not happen endcase else case (ALUOp) 0: ALUCtl<=2; 1: ALUCtl<=6; default: ALUCtl<=15; // should not happen endcase end

endmodule

module RegFile(ra1, rd1 , ra2 , rd2 , clk , RegWrite , wa ,wd ); input[4:0] ra1; output[31:0] rd1; input[4:0] ra2; output[31:0] rd2; input clk; input werf ; input[4:0] wa; input[31:0] wd; reg [31:0] registers[31:0]; assign rd1 = registers[ra1]; assign rd2 = registers[ra2]; always@ ( posedge clk ) if (RegWrite) registers[wa] <= wd; endmodule

module PC(clk , instruction , input clk ; input[31:0] instruction ; reg[31:0] npc; input zero ; input jump ; input branch ; wire[31:0] pcInc; wire[31:0] Branch1 ; wire[15:0] address; wire[31:0] branchAdd; reg[31:0] mux1; wire select1 ; wire[31:0] jumpAdd ; output [31:0] pc ; reg [31:0] pc ; assign assign assign assign assign

zero , branch , jump , pc );

select1 = branch & zero ; pcInc = pc + 4 ; address = instruction[15:0]; Branch1 = {{16{address[15]}},address[15:0]} ; branchAdd = pcInc + ( branch << 2 ) ; )

// sign extension

always@( branchAdd or pcInc or select1 begin

if ( select1 == 1 ) mux1 = branchAdd ; else mux1 = pcInc ; end assign jumpAdd = ( instruction[25:0] << 2 ); always@ ( jump or jumpAdd or mux1 ) begin if ( jump == 1 ) npc = jumpAdd ; else npc = mux1; end always @(posedge clk ) pc <= npc;

endmodule