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1) Introduction to Mixed Signal Design 2) Circuit Characterization & Performance Estimation Delay Estimation Logical Effort & Transistor Sizing Power Dissipation Interconnect
1P 4P
3) Logic Level Synthesis & Verification Introduction to Synthesis Transistor & Logic Level Synthesis Combinational Logic Synthesis Algorithms & Boolean Space Binary Decision Diagram(BDD,ROBDD) Sequential Logic Optimization
4P
4) High-Level Synthesis Hardware Models for High-level Synthesis Internal Representation Of The Input Algorithm Allocation, Assignment & Scheduling :Some Algorithms
4P
5) Digital System Using Verilog Introductions & Verilog Naming Conventions Structural Gate Level Modeling Switch Level Modeling Design Hierarchies Behavioral & RTL Modeling: Blocking & Non-blocking Assignments
6P
7) VLSI Testing & Verification Testing: Why test? Difference between testing & verification. Physical faults & their modeling: Fault equivalence, dominance & collapsing. Fault simulation: parallel , deductive & concurrent techniques
6P
Test pat tern generation for combinational circuits : Boolean difference, D-algorithm, Podem Test pattern generation for sequential circuits : ad-hoc and structures techniques scan path and boundary scan, Built - in self test techniques , DFT
6P
Fundamental concepts of quantum structures, Carbon Nan tubes (CNT), SET. Biomedical Electronics Spintronics Molecular Electronics
9) Frequency response, stability and noise issues in amplifiers: Diode Connected Load,
6P