Hot-Carrier Effects in MOS Devices by Eiji Takeda, Cary Y. Yang, and Akemi Miura-Hamada by Eiji Takeda, Cary Y. Yang, and Akemi Miura-Hamada - Read Online

Book Preview

Hot-Carrier Effects in MOS Devices - Eiji Takeda

You've reached the end of this preview. Sign up to read more!
Page 1 of 1

1

Preface

This book represents a compilation of recently published results and analyses on the subject of hot carriers in metal–oxide–silicon devices. It is an updated and substantially expanded version of the book on the same subject written in Japanese by the first author and published by Nikkei in 1987. It is intended to be a reference for practicing device engineers as well as researchers in academia and industry. Knowing full well that the subject matter is exceedingly dynamic, the authors designed the contents in such a way that the findings would still be useful to the reader even after they have been supplanted by results subsequent to the book’s publication.

The book is organized using a bottom-up scheme, where the early chapters contain fundamental scientific knowledge and later ones technology development. The first chapter is a comprehensive review of MOS device physics to a level equivalent to what is covered in a first-year graduate course on semiconductor devices. No prior exposure to MOS device physics is required, even though some knowledge of electrostatics and modern physics would be helpful. The next two chapters treat the origins of hot carriers and how they affect device operations (DC), respectively. AC response and process-induced effects are introduced in Chapter 4, including mechanical effects. Chapter 5 presents a survey of phenomena at low operating temperatures and at low applied voltages. The final three chapters examine the details of device structures and their relationship with various hot-carrier phenomena, leading to what is popularly known as drain engineering. Specifically, Chapter 7 contains an in-depth comparison between the two standard drain structures, DDD and LDD, while Chapter 8 introduces the GOLD structure.

A reference list with almost two thousand articles is included. Although not all of them are cited in the text, the list nonetheless represents an attempt by the authors to include most, if not all, publications related to the subject matter published prior to the completion of the manuscript.

A task of this magnitude would not be possible without the support, guidance, advice, and valuable time and effort of many individuals. First and foremost, the authors are indebted to the management teams of the Central Research Laboratory of Hitachi, Ltd., especially Dr. Yasutsugu Takeda, Senior Executive Managing Director, who provided support for the first author’s research on this subject over the past decade and a half and who generously hosted the visits of the second author and his students under the Hitachi Research Visit Programs (HIVIPS). The vision of Professor Takashi Tokuyama in making the initial suggestion to produce such a volume and his graciousness in hosting the second author’s three-month visit to Tsukuba University during the planning and development phase are greatly appreciated.

The authors are deeply grateful to their numerous collaborators over the past fifteen years, who have contributed to the advancement of this important field. They are also grateful to the many authors and publishers who have granted permissions to reproduce figures and text from their publications. Special thanks are extended to Dr. Bruce E. Deal, who co-taught a course on semiconductor surfaces and interfaces with the second author, for using draft versions of this book as text, and for his valuable suggestions. The valuable assistance of the library staff, especially Edward Wladas, at Santa Clara University during the compilation of the reference list is gratefully acknowledged. Outstanding technical assistance was provided by Dr. Jianmin Qiao, Dr. Raymond Li, and Ashawant Gupta during various stages of manuscript preparation. Finally the second author expresses his heartfelt gratitude to all of his students who were first exposed to the subject of MOS devices in his classes and are applying that knowledge in their current professions, and to his research students, from whom he has derived much insight into the field.

Eliji Takeda, Hitachi Ltd.

Cary Y. Yang, Santa Clara University

Akemi Miura-Hamada, Hitachi Ltd.

Chapter 1

Mos Device Fundamentals

The object of this chapter is twofold. It provides the reader with a brief but self-contained treatment of metal-oxide-semiconductor (MOS) device physics. While minimal background of semiconductor device physics is assumed in this treatment, the device specialist may find it useful to review the more advanced topics contained in this chapter before proceeding with subsequent chapters. The second purpose is to orient the reader to the approach used throughout this book. The approach is based on the assumption that understanding of empirical phenomena can be attained to some extent with appropriate modeling of the physical system. We hope that the content in this chapter will serve to provide the reader with the background information and understanding necessary for studies of hot-carrier effects.

This chapter begins with a short historical narrative on MOS devices and proceeds with a complete treatment of the MOS diode. The MOS field-effect transistor (MOSFET) operation is discussed next, with emphasis on short-channel effects. The chapter concludes with an introductory survey of key issues surrounding the subject of hot carriers.

1.1 From Discrete to ULSI

The first MOSFET device structure was proposed by Lilienfeld in 1928 [see the detailed historical account in Sah, 1988d]. But it was not until the late 1950s that the first stable working device was fabricated and tested. The subsequent successful applications of MOS capacitors and transistors hinged upon the understanding and control of the properties of the oxide layer and the oxide–silicon interface.

Through the legendary innovations of Noyce [1961] and Kilby [1976], the first monolithic integrated circuits consisting of resistors, capacitors, diodes, and transistors were fabricated on a single silicon substrate. With support from the U.S. government in the early 1960s, the development of integrated circuits blossomed and by 1970, large-scale integration (LSI) based on MOS technology started to emerge. The first LSI chip measured 3 mm × 3 mm and contained several thousand components. In the 1980s, very large-scale integration (VLSI) became the standard technology for memory and logic applications. The VLSI chip is usually less than 2 cm × 2 cm in size and typically contains several million transistors. In the early 1990s, advanced lithography, etching, and deposition techniques allowed further decrease in transistor dimensions and the corresponding increase in density of each silicon chip. The era of ultra LSI (ULSI) was born.

Despite such phenomenal advances in silicon integrated circuit technology, some basic problems remain as far as the oxide and oxide–silicon interface are concerned. For example, understanding of the physical mechanisms governing the initial stage of thermal oxidation is still lacking. Also the technology of silicon surface preparation is largely empirical and no unified scientific basis has been established. Lastly, and certainly not the least significant, the exact nature of the oxide–silicon interface traps and their creation and annihilation are far from being well understood.

1.2 Physics of the MOS Diode

The operation of MOSFET, which is a four-terminal device, is based on the properties of the two-terminal MOS structure. The MOS diode (or capacitor) is also important in its own right, in terms of actual applications as well as its utility as a test structure. The device is usually fabricated by oxidizing a crystalline silicon substrate, depositing a conducting film on the resulting amorphous SiO2 layer, forming the gate, and finally metallizing the gate and the substrate, forming the necessary ohmic contacts. The fabrication process, no matter how well controlled, introduces defects at the SiO2 − Si interface, which critically affects the device characteristics of both the diode and the transistor. Moreover, the amorphous SiO2 layer is highly susceptible to various charges, both fixed and mobile, and the defects present in the layer can serve as trap centers for carriers. A schematic description of the charges in the MOS structure is shown in Figure 1.1 [Deal, 1980].

Figure 1.1 Schematic of oxide and interface charges in a MOS diode.

1.2.1 THE IDEAL MOS DIODE

An idealized model would be to assume that all charges shown in Figure 1.1 are zero. In addition, the work function difference between the gate metal and the Si substrate is assumed to be zero. This model simplifies the analysis and serves as the basis for nonideal considerations.

1.2.1.1 Energy Band Diagrams

When a DC voltage VG is applied across the device, charges are induced in the semiconductor near the oxide interface. An electric field results and the energy bands bend accordingly. This phenomenon is illustrated in Figure 1.2 for a device with a p-type substrate. When no gate voltage is applied, the device is in the flat-band state (Figure 1.2a). For negative VG, holes are accumulated near the interface (Figure 1.2b). This region becomes depleted of carriers when VG is positive (Figure 1.2c). Further increase in VG results in the formation of an n-type region (Figure 1.2d), known as the inversion layer. The semiconductor is assumed to be in thermal equilibrium throughout the gate voltage sweep. In addition, the semiconductor is assumed to be nondegenerate so that carriers obey Boltzmann statistics.

Figure 1.2 Energy band diagram of a p -substrate MOS diode in (a) accumulation, (b) flat band, (c) depletion, and (d and e) inversion states.

The band bending parameter, sometimes known as surface potential, ψs, serves as a simple indicator of the state of the MOS diode. When ψs = 0, the condition corresponds to flat band. Negative ψs gives rise to hole accumulation, while positive ψs results in carrier depletion and eventually inversion. When the semiconductor surface becomes as n-type as the substrate is p-type, i.e.,

   (1.1)

where n and p denote electron and hole concentrations, respectively, the condition is known as the onset of strong inversion. Under this condition,

   (1.2)

where ni is the intrinsic carrier concentration, T the absolute temperature in degrees Kelvin, k the Boltzmann constant, and q the unit electronic charge. The following summarizes the above description for a p-substrate MOS diode.

   (1.3)

It should be noted that this description is generic for a p-type substrate and is completely independent of the ideal MOS assumptions.

The MOS diode in accumulation resembles a parallel-plate capacitor, with charge buildup on either side of the oxide. The situations in depletion and inversion are somewhat more complicated and require closer scrutiny. We now proceed to present two solutions of this electrostatics problem.

1.2.1.2 Solution with the Depletion Approximation

The charge density in the semiconductor substrate is given by

   (1.4)

where N+D and N−A the ionized donor and acceptor impurity concentrations, respectively. Using the depletion approximation for the MOS diode in the depletion state, Eq. (1.4) becomes

   (1.5)

where W is the depletion width and NB is negative for p-type substrate. For uniform doping, NB is a constant of position. Solution of the one-dimensional Poisson equation

   (1.6)

yields the electric field

   (1.7)

s is the semiconductor permittivity. From simple electrostatics the band-bending parameter can be expressed as

   (1.8)

Conversely, the depletion width can be written as

   (1.9)

The treatment thus far is applicable to either p-type or n-type substrates.

The total charge per unit area in the p-type semiconductor substrate in depletion/inversion is given by

   (1.10)

where Qn is the electron charge in the inversion layer and QB is the space charge in the depletion region. Integration of Poisson’s equation [Eq. (1.6)] yields

   (1.11)

In depletion, Qn is assumed to be negligibly small and QB = qNBW under the depletion approximation. Together with Eqs. (1.7) and (1.10), Eq. (1.11) is thus verified. However, in order to extend the depletion approximation to treat inversion, additional assumptions have to be made. In view of the charge screening provided by the inversion layer, one assumes that when strong inversion is reached, the depletion width is maximized so that further increase in VG would not increase W. Thus this maximum or saturated width is given by

   (1.12)

Beyond the onset of strong inversion, QB is independent of VG and Qn is no longer negligible.

The gate voltage consists of an oxide component and ψs. The drop across the oxide is given by

   (1.13)

ox, tox, and Cox are the oxide permittivity, thickness, and capacitance, respectively. In depletion, using Eqs. (1.9) and (1.10), one obtains

   (1.14)

At the onset of strong inversion, ψs = 2ϕB and VG becomes the so-called threshold voltage

   (1.15)

For an n-type substrate, identical arguments lead to

   (1.16)

where

   (1.17)

Despite the serious conceptual shortcomings of this simplified description, it is the basis of all analyses for the MOSFET. For the MOS diode, it is sometimes necessary to relax some of these assumptions and treat the electrostatics problem a bit more rigorously. This analysis will be presented following a brief description of the ideal capacitance–voltage characteristics in the next section.

1.2.1.3 Capacitance–Voltage Characteristics

Based on the depletion approximation, one can deduce the capacitance for the MOS diode in accumulation, depletion, and inversion. To simplify the present discussion, two additional assumptions are made. First, the DC gate voltage sweep rate is such that sufficient minority carriers are generated in the inversion layer during the sweep. This prevents deep depletion from occurring, which would result in a nonequilibrium situation. In practice, this can be accomplished by proper illumination of device to create the necessary carriers in the inversion layer. Second, at this stage we confine ourselves to AC gate voltage signals having frequencies sufficiently high that the charge fluctuation is dominated by the space charge near the edge of the depletion region. In other words, minority carrier generation in the inversion layer cannot keep up with the AC signal. Under these constraints, the MOS diode can be represented as a series combination of two capacitor as shown in Figure 1.3. The oxide capacitance, Cox, was given previously in Eq. (1.13), while the semiconductor capacitance, Cs, represents charge fluctuations in the substrate.

Figure 1.3 High-frequency circuit model of an ideal MOS diode.

The capacitance in accumulation is simply given by Cox, since the device in this state resembles a parallel-plate capacitor. Alternatively, one can view that as a result of majority carrier buildup near the interface, Cs is so large that Cox dominates the series combination. Under the depletion approximation, this domination persists up to flat band. This is illustrated in Figure 1.4 by the broken curve. The existence of a depletion region when the device is in depletion gives rise to a semiconductor capacitance per unit area

   (1.18)

Figure 1.4 High-frequency capacitance–voltage characteristics of an ideal MOS diode. The solid curve indicates exact solution, while the broken curve is derived from the depletion approximation.

The capacitance of the series combination becomes

   (1.19)

Recognizing from Eqs. (1.8) and (1.14) that

   (1.20)

W can be expressed as

   (1.21)

where

Substituting Eq. (1.21) into Eq. (1.19) yields

   (1.22)

for the device in depletion.

When the onset of strong inversion is reached, W ceases to increase further. Thus a minimum semiconductor capacitance results.

   (1.23)

This leads to a minimum MOS capacitance

   (1.24)

The broken curve in Figure 1.4 reveals the entire CVG behavior under the depletion approximation.

One important utility of this approximation is the determination of substrate doping, NB. From Eqs. (1.23) and (1.24), one obtains

   (1.25)

Thus Wm can be determined from the maximum and minimum values of the CVG curve. But Wm is also given by Eq. (1.12). Combining it with Eq. (1.2) and assuming extrinsic behavior for the bulk substrate, namely,

   (1.26)

one arrives at

   (1.27)

Equation (1.27) can be solved iteratively to yield NB.

It is important to note that the depletion approximation is most severe near flat band. When the device approaches flat band from accumulation, the capacitance starts to decrease as a result of the series combination of Cox and Cs. This behavior is illustrated by the solid curve in Figure 1.4. In fact, this result can be obtained directly from an exact solution of Poisson’s equation. A sketch of this solution will be presented next.

1.2.1.4 General Solution

One must recognize at the outset that the semiconductor capacitance, Cs, is defined as charge fluctuations in the substrate as a result of changes in band bending. Expressed in a more compact form,

   (1.28)

In view of (0) can be determined, then the MOS capacitance is obtained.

To facilitate the solution of this electrostatics problem, we examine the MOS diode in the depletion state with a schematic band diagram shown in Figure 1.5. Poisson’s equation in the semiconductor region is written as

   (1.29)

Figure 1.5 Detailed energy band diagram of the p -substrate of a MOS diode in depletion/weak inversion.

where ψ is the electrostatic potential with the reference in the semiconductor bulk, i.e., ψ(∞) = 0. Since ρs = 0 in the bulk, NB = nbulk – pbulk. Simple deduction using Figure 1.5 results in

   (1.30)

Thus Eq. (1.29) can be written as

   (1.31)

where β ≡ q/kT is used. Multiplying and integrating, one obtains

   (1.32)

where LD is the so-called extrinsic Debye length

   (1.33)

and

   (1.34)

The electric field at the semiconductor surface is given by

   (1.35)

The semiconductor charge is then given by

   (1.36)

Thus the semiconductor capacitance becomes

   (1.37)

In the limit ψs → 0, or flat band, Eq. (1.37) reduces to

   (1.38)

This leads to the MOS flat-band capacitance

   (1.39)

The gate voltage corresponding to CFB is known as the flat-band voltage, VFB. For the ideal MOS diode, it follows from definition that VFB = 0. It is apparent that with a room-temperature value of several hundred angstroms for LD, CsFB is comparable to Cox, resulting in a significant reduction of the MOS capacitance when flat band is reached from accumulation. The solid curve in Figure 1.4 represents a solution based on Eq. (1.37) and C = (1/Cox + 1/Cs)− 1 for accumulation and depletion. The band bending has been converted to gate voltage through

It is instructive to examine the behavior of the semiconductor charge as a function of band bending. This behavior for a p-substrate MOS diode as shown in Figure 1.6 reveals that in depletion/weak inversion (2 ϕB > ψs > 0), Qs varies roughly as ψ¹/²s, which supports the depletion approximation. However, the spatial variation of the charge density is not well represented by the depletion approximation in the vicinity of the depletion region edge, as shown in Figure 1.7. The drop-off of the true charge density is not abrupt and occurs over a distance comparable to LD around the depletion region edge. In strong inversion, Qs varies roughly as

Figure 1.6 Semiconductor charge as a function of band bending. (Reprinted by permission from John Wiley & Sons, Inc., from S. M. Sze, Physics of Semiconductor Devices, Wiley, New York (© 1988 John Wiley & Sons, Inc.).)

Figure 1.7 Comparison of charge density representations.

where the second term, which represents the inversion charge, dominates for large ψs as shown in Figure 1.6. Comparing this behavior with that in depletion, this variation lends some credibility to the assumption that the depletion width saturates in strong inversion.

The semiconductor capacitance versus band bending behavior given by Eq. (1.37) is shown in Figure 1.8. As in the charge case, the behavior in depletion resembles that given by the depletion approximation.

Figure 1.8 Semiconductor capacitance for a p -substrate MOS diode.

1.2.2 NONIDEAL CONSIDERATIONS

A real MOS capacitor generally differs from the ideal one. As shown in Figure 1.1, the device contains oxide and interface charges, which give rise to changes in CVG behavior. The gate–substrate work function difference is usually not zero. Further, substrate dopant concentration can vary with position.

This section is organized as follows. Work function difference, fixed oxide charge, oxide trapped charge, and mobile ions are treated together, since they result in voltage-independent flat-band voltage shifts from the ideal behavior. The interface trapped charge, on the other hand, varies with the surface potential (band bending), which in turn varies with gate voltage. Thus interface charges give rise to to voltage-dependent flat-band shifts as well as changes in ψs vs. VG behavior. The latter causes a stretch-out of the CVG curve. Following the two subsections on oxide and interface charges, a discussion of the effect of nonuniform substrate doping is presented.

1.2.2.1 Voltage-Independent Flat-Band Shifts

A difference is gate–substrate work function, ϕms ≡ ϕm– ϕs, results in band bending in the substrate to accommodate a uniform Fermi level in equilibrium. To return to flat-band condition, a gate voltage of VG = ϕms must be applied. Thus the flat-band voltage shift due to work function difference is simply ϕms.

The oxide charges, regardless of their origins, are distributed across the entire insulating layer. A schematic of the electrostatics is shown in Figure 1.9. The oxide charge distribution, ρox(x), includes fixed oxide charge, oxide trapped charge, and mobile ions. In principle, these are quite different physical entities with very different distributions (see Figure 1.1). In practice, these charges manifest themselves in similar fashions electrically and thus are not easy to distinguish [Nicollian and Brews, 1982]. As in work-function difference, the band bending resulting from these charges can be made to vanish with a suitable gate voltage. From the electrostatics scheme shown in Figure 1.9, using superposition across the oxide layer, one can deduce that ρox(x) requires a gate voltage of ∆V to achieve flat band [Sze, 1981]. ∆V is given