CISC Processor Design
Hardware Flowchart
Virendra Singh
Indian Institute of Science
Bangalore
virendra@[Link]
Lecture 5
SE-273: Processor Design
MIN Datapath
IRE
IRF
Internal A Bus
AO
PC
T2
R0
R1
DO
Rn
T1
ALU
k
DI
Internal B Bus
External Data
External Address
Bus (EDB)
Bus (EAB)
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Flowcharts
ADD RX AR RY
ADD RX AI (RY)
Register-to-Register
RR
ADD
Register-to-Memory
RM
ADD
rx a alu
ry b alu
edb di
ry b ao
di b alu
rx a alu
t1 b ry
IRE
AO PC T2
R0 R1
Internal
A Bus
IRF
DO
Rn
Internal
B Bus
Jan 28, 2008
T1
ALU
State
k
DI
Sequence
ry b ao
t1 a do
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Flowcharts
ADD RX AR RY
Register-to-Register
R
ADD
edb irf
pc b ao
rx a alu
ry b alu
t1 b ry
pc a alu
+1 alu
t1 b pc
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ADD RX AI (RY)
Register-to-Memory
RM
ADD
Execution
Speed
edb irf
pc b ao
edb di
ry b ao
di b alu
rx a alu
ry b ao
t1 a do
pc a alu
+1 alu
t1 b pc
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Level 1 Flowchart - ADD
ADD RX AR RY
Register-to-Register
R
ADD
rx a alu
ry b alu
edb irf
pc b ao
pc a alu
+1 alu
t1 b ry
Operation
tasks
irf ire
t1 b pc
Housekeeping
tasks
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
Level 2 Flowchart - ADD
ADD RX AR RY
Register-to-Register
R
ADD
rx a alu
ry b alu
edb irf
pc b ao
pc a alu
+1 alu
t1 b ry
Jan 28, 2008
irf ire
t1 b pc
ADD
rx a alu
ry b alu
Merger
Speed
Identical states
edb irf
pc a alu, ao
t1 b ry
+1 alu
irf ire
t1 b pc
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Level 2 Flowchart - ADD
R
ADD RX AI (RY)
Register-to-Memory
ADD
RM
edb irf
pc a alu, ao
+1 alu
edb di
ry b ao
edb irf
pc b ao
di b alu
rx a alu
ry b ao
t1 a do
pc a alu
+1 alu
edb di
ry b ao
t1 a pc
irf ire
t1 b pc
di b alu
rx a alu
IRE
AO PC
(EAB)
R0 R1
Internal
A Bus
Internal
B Bus
Jan 28, 2008
t1 a do
ry b ao
IRF
DO
Rn
T1
ALU
ADD
k
DI
irf ire
(EDB)
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Level 2 Flowchart - ADD
ADD RX AI (RY)
Register-to-Memory
ADD
RM
edb irf
pc b ao
di b alu
rx a alu
ry b ao
t1 a do
pc a alu
+1 alu
AO PC T2
(EAB)
R0 R1
Internal
A Bus
irf ire
t1 b pc
Internal
B Bus
Jan 28, 2008
T1
ALU
edb di
ry b ao, t2
t1 a pc
di b alu
rx a alu
irf ire
t1 a do
t2 b ao
IRF
DO
Rn
ADD
edb irf
pc a alu, ao
+1 alu
edb di
ry b ao
IRE
k
DI
(EDB)
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Level 2 Flowchart - ADD
ADD RX AR RY
Register-to-Register
Do level2 flowchart of the fastest
instruction
Point out inadequacy in Datapath
AO PC T2
(EAB)
R0 R1
Internal
A Bus
IRF
DO
Rn
Internal
B Bus
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T1
ALU
ADD
rx a alu
ry b alu
when AO is connected
to B (internal) bus only
IRE
k
DI
edb irf
pc b ao
t1 a ry
pc a alu
+1 alu
irf ire
t1 b pc
(EDB)
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Flowchart
Flowchart
How many sequences?
Motorola 68000 (14 address modes and 50
instruction types)
Control Word Sequence
Address Mode Sequence
Calculate address (may or may not include operand fetch)
Execution Sequence
Completes the execution (after address mode sequence)
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Control Word Sequence
Address Mode Sequence
Can be shared for different instructions
Calculate the operand address
Fetch the operand
Place the operand in DIN
Execution Sequence
Address mode sequences can be shared
Find the operand in DIN
Execute the instruction (without knowing how the address
was calculated etc..)
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Level1 Flowchart
Level1 Flowchart
At the beginning of instruction execution, IRE is
assumed to contain the current instruction
Instruction execution begins with the address
mode sequence
The execution sequences for Register-toRegister instructions cannot be shared
The execution sequences for standard dual
operand instructions are identical
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Level 1 FlowchartAddress Mode Sequences
Base Plus Displacement
Register Indirect
edb di
pc a alu, ao
+1 alu
edb di
ry b ao, t2
t1 a pc
di b alu
ry a alu
edb di
t1 b ao, t2
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Level 1 FlowchartAddress Mode Sequences
IRE
Branch Instruction
AO PC T2
edb irf
ry a alu, ao
+1 alu
(EAB)
R0 R1
Internal
A Bus
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
Z = 0 (no branch)
Z = 1 (Branch)
edb irf
pc a alu, ao
+1 alu
irf ire
t1 b pc
irf ire
t1 b pc
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IRF
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Level 1 Flowchart Execution Sequences
Execution sequences with memory operand reference
STORE
LOAD
edb irf
di b rx, t2 pc a alu, ao
+1 alu
t2 a alu
0 alu
rx a alu, do edb irf
t2 b ao
pc a alu, ao
+1 alu
0 alu
irf ire
t1 b pc
irf ire
t1 b pc
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Level 1 Flowchart Execution Sequences
Execution sequences with memory operand reference
SUB
ADD
di b alu
rx a alu
edb irf
pc a alu, ao
+1 alu
di b alu
rx a alu
edb irf
pc a alu, ao
+1 alu
t1 a do
t2 b ao
irf ire
t1 b pc
t1 a do
t2 b ao
irf ire
t1 b pc
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Level 1 Flowchart Execution Sequences
Execution sequences with memory operand reference
TEST
AND
di b alu
rx a alu
edb irf
pc a alu, ao
+1 alu
di b t2
edb irf
pc a alu, ao
+1 alu
t1 a do
t2 b ao
irf ire
t1 b pc
t2 a alu
0 alu
irf ire
t1 b pc
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Level 1 Flowchart Execution Sequences
Execution sequences for Register-to-Register and special instructions
STORE
LOAD
edb irf
ry a alu,rx
pc a alu, ao
0 alu
+1 alu
rx a alu, ry edb irf
pc a alu, ao
0 alu
+1 alu
irf ire
t1 a pc
irf ire
t1 a pc
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Level 1 Flowchart Execution Sequences
Execution sequences for Register-to-Register and special instructions
SUB
ADD
rx a alu
ry b alu
edb irf
pc a alu, ao
+1 alu
rx a alu
ry b alu
edb irf
pc a alu, ao
+1 alu
t1 a ry
irf ire
t1 a pc
t1 a ry
irf ire
t1 a pc
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Level 1 Flowchart Execution Sequences
Execution sequences for Register-to-Register and special instructions
PUSH
POP
edb di
edb irf
ry a alu, ao pc a alu, ao
+1 alu
+1 alu
di b rx
t1 a ry
irf ire
t1 a pc
ry a alu
-1 alu
edb irf
pc a alu, ao
+1 alu
rx a do
t1 b ao, ry
irf ire
t1 a pc
IRE
AO PC T2
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Merged Level 1 Flowchart:
Address Mode Sequences
Base Plus Displacement
Register Indirect
edb di
pc a alu, ao
+1 alu
edb di
ry b ao, t2
abdm1
adrm1
t1 a pc
abdm2
di b alu
ry a alu
abdm3
edb di
t1 b ao, t2
IRE
AO PC T2
abdm4
(EAB)
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R0 R1
Internal
A Bus
IRF
DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EDB)
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Merged Level 1 Flowchart:
Address Mode Sequences
IRE
Branch Instruction
edb irf
ry a alu, ao
+1 alu
AO PC T2
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DO
Rn
T1
ALU
k
DI
Internal
B Bus
(EAB)
(EDB)
brzz1
Z = 0 (no branch)
Z = 1 (Branch)
irf ire
t1 b pc
R0 R1
Internal
A Bus
IRF
brzz2
edb irf
pc a alu, ao
+1 alu
brzz3
irf ire
t1 b pc
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brzz4
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
LOAD
LOAD
edb irf
di b rx, t2 pc a alu, ao
+1 alu
t2 a alu
0 alu
di b rx, t2
edb irf
pc a alu, ao
+1 alu
ldrm1
irf ire
t1 b pc
irf ire
t1 b pc
t2 a alu
0 alu
ldrm2
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
STORE
STORE
rx a alu, do edb irf
t2 b ao
pc a alu, ao
+1 alu
0 alu
irf ire
t1 b pc
rx a alu, do
t2 b ao
0 alu
edb irf
pc a alu, ao
+1 alu
strm1
strm2
irf ire
t1 b pc
strm3
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
ADD, AND, SUB
ADD
di b alu
rx a alu
t1 a do
t2 b ao
edb irf
pc a alu, ao
+1 alu
irf ire
t1 b pc
di b alu
rx a alu
t1 a do
t2 b ao
edb irf
pc a alu, ao
+1 alu
irf ire
t1 b pc
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oprm1
oprm2
oprm3
oprm4
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
TEST
TEST
di b t2
t2 a alu
0 alu
edb irf
pc a alu, ao
+1 alu
irf ire
t1 b pc
di b t2
edb irf
pc a alu, ao
+1 alu
test1
irf ire
t1 b pc
t2 a alu
0 alu
test2
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
LOAD
edb irf
ry a alu,rx
pc a alu, ao
0 alu
+1 alu
irf ire
t1 a pc
LOAD
edb irf
pc a alu, ao
ry a rx, t2
+1 alu
ldrr1
irf ire
t1 b pc
t2 a alu
0 alu
ldrr2
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
STORE
STORE
rx a alu, ry edb irf
pc a alu, ao
0 alu
+1 alu
irf ire
t1 a pc
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edb irf
pc a alu, ao
rx b ry, t2
+1 alu
irf ire
t1 b pc
t2 a alu
0 alu
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strr1
strr2
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
ADD
rx a alu
ry b alu
t1 a ry
edb irf
pc a alu, ao
+1 alu
irf ire
t1 a pc
ADD, SUB, AND
rx a alu
ry b alu
oprr1
edb irf
pc a alu, ao
t1 a ry
+1 alu
irf ire
t1 a pc
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oprr2
oprr3
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Level 1 Flowchart Execution Sequences
Execution sequences for Register-to-Register and special instructions
POP
POP
edb di
ry a alu, ao
edb di
edb irf
+1 alu
popr1
ry a alu, ao pc a alu, ao
+1 alu
+1 alu
di b rx
di b rx
t1 a ry
irf ire
t1 a pc
t1 a ry
popr2
edb irf
pc a alu, ao
+1 alu
popr3
irf ire
t1 a pc
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popr4
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
PUSH
PUSH
ry a alu
ry a alu
-1 alu
rx a do
t1 b ao, ry
edb irf
pc a alu, ao
+1 alu
irf ire
t1 a pc
-1 alu
rx a do
t1 b ao, ry
edb irf
pc a alu, ao
+1 alu
irf ire
t1 a pc
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push1
push2
push3
push4
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Level 2 Flowcharts
Format for Level 2 flowchart state
Label B
Label A
Access Type
ALU and CC
Tasks
Duplicates
Page and Loc
State ID
Synonym
Acess
Width
Next State
DR Data Read
DW Data Write
IR - Instruction Read
NA No aceess
S Set
N Not set
X Dont care
BC Branch conditionally
IB Instruction branch
SB Sequence branch
StateID Direct branch
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Level 2 Flowchart:
Address Mode Sequences
Base Plus Displacement
(RY+d)@
ir
edb di
pc a alu, ao
+1 alu
add-n
abdm1
abdm2
di b alu
ry a alu
add-n
abdm3
abdm4
na
t1 a pc
abdm2
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x-n
abdm3
na
dr
edb di
t1 b ao, t2
x-n
abdm4
sb
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Level 2 Flowchart:
Address Mode Sequences
Register Indirect
RY@
dr
edb di
pc a alu, ao
+1 alu
x-n
adrm1
sb
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Level 2 Flowchart:
Address Mode Sequences
Branch Instruction
edb irf
ry a alu, ao
+1 alu
brzz1
ir
add-n
bc
Z = 1 (Branch)
irf ire
t1 b pc
brzz2
Jan 28, 2008
na
Z = 0 (no branch)
edb irf
pc a alu, ao
+1 alu
ir
add-n
x-n
brzz3
ib
brzz4
irf ire
t1 b pc
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brzz4
na
x-n
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ib
Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem
RX
di b rx, t2
edb irf
pc a alu, ao
+1 alu
ldrm1
irf ire
t1 b pc
t2 a alu
0 alu
ldrm2
Jan 28, 2008
LOAD
ir
add-x
ldrm2
na
add-s
ib
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX
Mem
rx a alu, do
t2 b ao
0 alu
strm1
edb irf
pc a alu, ao
+1 alu
strm1
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STORE
dw
add-s
strm2
ir
irf ire
t1 b pc
strm3
na
x-n
ib
add-n
strm3
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX OP Mem Mem
di b alu
rx a alu
oprm1
ADD, AND, SUB
na
op-s
oprm2
t1 a do
t2 b ao
oprm2
dw
x-s
oprm3
Jan 28, 2008
ir
edb irf
pc a alu, ao
+1 alu
add-n
oprm3
oprm3
irf ire
t1 b pc
oprm4
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na
x-n
ib
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem ALU
di b t2
edb irf
pc a alu, ao
+1 alu
test1
irf ire
t1 b pc
t2 a alu
0 alu
test2
Jan 28, 2008
TEST
ir
add-x
test2
na
add-s
ib
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
RX OP RY RY
ADD, SUB, AND
rx a alu
ry b alu
oprr1
edb irf
pc a alu, ao
t1 a ry
+1 alu
oprr2
Jan 28, 2008
na
na
irf ire
t1 a pc
op-s
oprr2
x-n
oprr3
ir
ib
add-n
oprr3
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
RX RY
edb irf
pc a alu, ao
ry a rx, t2
+1 alu
ldrr1
irf ire
t1 b pc
t2 a alu
0 alu
ldrr2
Jan 28, 2008
LOAD
ir
add-x
ldrr2
na
add-s
ib
RX RY
edb irf
pc a alu, ao
rx b ry, t2
+1 alu
strr1
irf ire
t1 b pc
t2 a alu
0 alu
STORE
ir
add-x
strr2
na
add-s
strr2
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ib
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
RY@ RX
RY+1 RY
edb di
ry a alu, ao
+1 alu
popr1
di b rx
t1 a ry
popr2
Jan 28, 2008
POP
dr
add-n
popr2
na
x-n
popr3
edb irf
pc a alu, ao
+1 alu
popr3
irf ire
t1 a pc
popr4
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ir
add-n
popr4
na
x-n
ib
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Thank You
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