Chapter

4: the MOS transistor

1. Introduction
First products in Complementary Metal Oxide Silicon (CMOS) technology appeared in the market in
seventies. At the beginning, CMOS devices were reserved for logic, as they offer the highest density (in
gates/mm2), and the lowest static power consumption. Most highfrequency circuitry was carried out in
bipolar technology. As a result, a lot of analog functions were realized in bipolar technology. The
technologydevelopment,whichisdrivenbydigitalcircuits(inparticularbyflashmemories),leadtosmaller
andfasterCMOSdevices.Atthebeginningoftheseventies,1mtransistorslengthwasconsideredshort.
Currently,CMOStechnologywith22nmchannellengthisavailable.Inthelasttwentyyearsalotofanalog
circuitsstartedtobedevelopedinCMOStechnology.Infact,thetechnologyscalingenabledCMOSdevices
athigherfrequenciesofworking,alsofortheanalogcounterpart.
Today,CMOSandbipolartechnologiesareincompetitionoverawidefrequencyregionupto100GHz.
Thechallengeindeed,tochoicethetechnologythatfulfillsbestthesystemandcircuitrequirementsata
reasonablecost.BipolarismoreexpensivethanstandardCMOStechnology.Moreover,mostsystemsand
circuitsaremixedsignal,i.e.theyincludedigitalandanalogparts.Inthepast,separatedintegratedcircuits
werededicatedtotheanalog(bipolar)anddigital(CMOS)circuits.Asanalogcircuitswerealsoavailablein
CMOS technology, this technology started to offer the opportunity to integrate cheap, high density and
lowpowerdigitalcircuits,aswellasanalogcircuits,inthesamechip.Thisbringsenormousadvantagesin
terms of reduced costs and smaller form factors of electronic devices. Currently, CMOS technology
dominates the market. Bipolar transistors field of applications is reduced to very high frequencies of
working.

2. The MOS transistor structure

Fig.4.1showsacrosssectionofatypicalntypeMOS(NMOS)transistor.

Fig.4.1CrosssectionofatypicalNMOStransistor.

Fig. 4.2 shows the top view of a typical NMOS transistor. The main transistors dimensions, i.e. the
channellength(L)andwidth(W),areindicated.

Fig.4.2TopviewofatypicalNMOStransistor.

The twodeeplyntype dopedactiveareasofSourceandDrain arefabricatedina ptypesubstrate. A

thin layer of silicon dioxide is growth in the region between the Source and the Drain. A conductive
material (generally polysilicon) covers the silicon dioxide, implementing the Gate terminal. The Gate
terminalregulatesthecurrentconductionbetweenSourceandDrain.
The Bulk terminal biases the ntype substrate, which is common to all NMOS transistors. The Bulk
terminal is set to the lowest voltage available for the circuit, generally the ground. This makes the pn
junctionbetweentheactiveareasofSourceandDrain,andthesubstrate,inverselybiased.Practically,the
twoactiveareasresultelectricallyisolated,aswellasallNMOStransistorsonthesamesubstrate.Current
conductionbetweenSourceandDrainispossibleonlywhenanopportunevoltageisappliedtotheGate.
ComplementaryMOS(CMOS)technologyincludesbothNMOSandPMOStransistors.PMOStransistor
hasptypedeeplydopedactiveareasofSourceandDrainfabricatedinantypesubstrate.Inastandard
CMOS technology, PMOS transistors is built in a Nwell obtained in a ptype substrate. Fig. 4.3 shows a
NMOSandaPMOSdevicesintegratedonthesamesilicondie.

Fig.4.3NMOSandPMOStransistorsfabricatedonthesamesilicondie.

In digital gates, the Bulk terminals of NWells of PMOS transistors are connected to the supply.
However,sincetheNWellisisolatedfromtherestofthesubstrate,itsBulkterminalcanbeconnectedtoa
voltage different with respect to the supply. In analog circuits, the Bulk terminal of PMOS transistors is
oftenconnectedtotheSource,inordertoreducethethresholdvoltageshiftduetotheBodyeffect.This
effect occurs when Source and Bulk are not biased to the same voltage. While this effect can be always
mitigatedinPMOStransistors,itcannotbeavoidedinNMOStransistorswhentheSourceisconnectedtoa
voltagedifferentfromtheground,whereitsBulkisbounded.
Fig. 4.4 shows the NMOS and the PMOS transistors symbols used in CMOS circuits. When the Bulk
terminalhasastandardconnection(i.e.tothegroundandtothesupplyforNMOSandPMOStransistors,
respectively)itisnotdrawn.

Fig.4.4NMOSandPMOStransistorssymbolsusedinCMOScircuits.

3. Large signal behavior of MOS transistors

The NMOS transistor is a strongly nonlinear device. Its transfer characteristics depends on the bias
conditions.InordertostudytheNMOStransistorbehavior,fourregionsofoperationaredistinguished:

cutoffregion;
linearortrioderegion;
saturationregion;
weakinversion.

In the following, these four regions of operation and the NMOS secondary effects are analyzed in
details.
3.1 Interdiction region
To derive the transfer characteristics of the NMOS transistor let start considering all its terminals
grounded,asFig.4.5shows.

Source

Gate

Drain

n+

n+
ptype
substrate

Depletion
regions

Bulk

Fig.4.5NMOStransistorwithallitsterminalsgrounded.

Then+islandsofSourceandDrainarecompletelyenvelopedbyadepletionlayer,asithappensinpn
junctions.IftheGateSourcevoltage(VGS)isnull,theSourceandtheDrainregionsareseparatedbyaback
tobackpnjunctions.ThecircuitisequivalenttothatonereportedinFig.4.6.

Fig.4.6EquivalentcircuitofanNMOStransistorwithallterminalsbiasedtoground.

Gateterminalresultsfloating.DiodesofFig.4.6representjunctionsformedbythentypeSourceand
Drain regions and the ptype substrate. Since these junctions are inversely biased, they behave like an
extremely high resistance. Device is off, as current conduction between Source and Drain cannot occur.
Thisregionofoperationiscalledcutoffregion.
NowconsidertheBulk,theSourceandtheDraingrounded,whileapositiveVGSisappliedtotheGate,as
Fig.4.7shows.


Fig.4.7NMOStransistorwitha0<V G S <V TH .

TheGateandthesubstrateformacapacitorwiththesilicondioxideasdielectric.Positivechargesare
accumulatedontheGate,whilenegativechargesareattractedinthesubstrate.Initially,negativecharges
accumulatedinthesubstratearemanifestedbythecreationofadepletionregionunderthechannel,that
excludes holes under the Gate. However, in this conditions, current cannot flows between Source and
Drain,andthedeviceisstillincutoffregion.
3.2 Linear or triode region
As VGS reaches a critical value called threshold voltage, VTH, a thin layer of electrons at the interface
between silicon dioxide and substrate is induced. The layer of electrons forms a conducting channel
betweenSourceandDrain.Thisphenomenaisknownasinversion.
When VGS>VTH, the NMOS transistor is on, i.e. the conducting channel is formed, then a current flow
betweenSourceandDraincanexist.
In order to have a current between Source and Drain, a positive VDS has to be applied. The NMOS
transistorsituationisillustratedbyFig.4.8.


Fig.4.8NMOStransistorwithaV G S >V TH ,andV D S >0.

The positive VDS produces a horizontal electric field that makes the channel charge, Qch, flowing
betweenSourceandDrainfordrifteffect.TheresultingIDScurrentcanbecalculatedasfollows:
Eq.4.1

whereNisthetotalnumberofelectroncomposingthechannelcharge,qistheelectroncharge,andtdis
thedrifttimerequiredtocrossthechannelbyanelectron.QchismodulatedbytheVGSvoltagethatexceeds
the threshold voltage, VTH, i.e. VGSVTH which is called the overdrive voltage, Vov. Vov produces a vertical
electricfield which generateselectronsaccumulationintheconducting channel.Qchcan becalculatedas
follows:
Eq.4.2

whereLandWarethechannellengthandwidth,respectively,andCoxistheGatecapacitanceperunit
area.Coxisgivenbytheratiobetweenthepermectivity,ox,andthickness,tox,ofthesilicondioxide:
Eq.4.3

InstandardCMOStechnologiesofthelasttwentyyearstox isaboutfiftytimeslowerthantheminimum
channellengthLmin:
Eq.4.4
50

Drift time, td, is directly proportional to the channel length L, and inversely proportional to the drift
velocityofelectrons,vd,asequation4.3shows:
Eq.4.5

Driftvelocity,vd,isproportionaltothehorizontalelectricfield,y,i.e.:
Eq.4.6

where n is the electron mobility in the channel. The value of the horizontal electric field, y, is,
approximately,calculatedasfollows:
Eq.4.7

Substitutingequations4.2,4.3,4.4,and4.5,intoequation4.1thefollowingexpressionforIDSisget:
Eq.4.8

wherekniscalledconductivityfactorforNMOStransistors.Itisgivenby:
Eq.4.9

Equation4.8describesthetransfercharacteristicsofaNMOStransistor,asVDSiskeptlow,i.e.VDS<VGS
VTH.Inthisbiascondition,theNMOStransistoroperatesinthelinear,ortriode,region.Fig.4.9showsthe
IDSVDScurvesoftheNMOStransistoroperatinginlinearregion,withVGSasparameter.

Fig.4.9I D S V D S curvesoftheNMOStransistorinlinearregionwithV G S asparameter.

Equation4.6predictsthatIDSisproportionaltoVDS.Practically,inlinearregion,theNMOStransistoracts
likeavariableresistance,Ron,whosevaluedependsonVov.Roniscalculatedasfollows:
Eq.4.10

AsVDSisincreased,thechargechannelnarrowsatthedrainend.Infact,VDSmodifiesthevoltage,and,
then,thechargealongthechannel.ThevoltagecomponentduetoVDSismaximumatthedrainend,while
itiszeroattheSourceend.SupposingalineardistributionofthevoltagecomponentduetoVDSalongthe
channel, its average value can be approximately estimated to be VDS/2. Therefore, a more accurate
calculationofthechannelchargeisgetbyaddingVDS/2inequation4.2:
Eq.4.11

Considering equation 4.11, and repeating the same steps than before, a more accurate calculation of
theIDScurrentinlinearregionisalsopossible:
Eq.4.12

IDSvaluesobtainedbyadoptingequations4.9and4.12,areveryclosewhenVDSismuchlessthanVov.

3.3 Saturation region

AsVDSapproachesVGSVTH,thechannelchargeapproacheszeroattheDrainend.Infacts,thechannel
chargeissustainedbyaGateDrainvoltage,VGD,atthedrainside,whichislessthanVGSattheSourceside.
WhenVDScompensatesfortheoverdrivevoltageVGSVTH,VGDresultstobeequaltothethresholdvoltage
VTH,asequation4.13predicts:
Eq.4.13

Inthisbiascondition,nochannelchargeisavailableattheDrainend.Theconductingchannelpinches
off,disconnectingtheDrain.Fig.4.10showstheNMOStransistorsituation.TheVDSvaluethatproducesthe
channelpinchoffiscalledsaturationvoltage(VDS,sat).ItcorrespondstoVGSVTH,i.etheoverdrivevoltage.

Fig.4.10NMOStransistorwithaV G S >V TH ,andV D S =V G S V TH .

SubstitutingtheVDSvalueinequation4.10,theexpressionoftheIDSatthepinchoffisobtained:
Eq.4.14

, a depletion region is formed between the pinchoff point and the

As VDS increases over
Drain. Since the voltage between the Gate and the pinchoff point is VTH by definition, the VDS part that
exceeds
, stands across this depletion region. Therefore, when VDS increases, this depletion
region enlarges, and the pinchoff point moves toward the Source. Fig. 4.11 shows the NMOS transistor
status.


Fig.4.11NMOStransistorwithaV G S >V TH ,andV D S >V G S V TH .

FurtherincrementsofVDSover
donotproducemodificationsonthevoltageacrosschannel
region,thereforethehorizontalelectricfieldiskeptconstant.Thus,theIDScurrent,whichisduetothedrift
effect of the channel charge by the horizontal electric field, remains equal to that one expressed by
equation 4.12. Equation 4.12 predicts that IDS depends only on Vov, not on VDS, when the conducting
channelpinchesoff.Thisregionofoperationiscalledsaturationregion.
Fig.4.12showstheIDSVGSinputcharacteristicoftheNMOStransistorinsaturationregion.TheIDSVGS
curvefitthesquarelawexpressedinequation4.12,anditmeetstheVGSaxisatVTH.

IDS

VTH

VGS

Fig.4.12I G S V G S inputcharacteristicoftheNMOStransistorinsaturationregion.

Fig. 4.13 shows the ideal IDSVDS output characteristics with VGS as parameter. These curves do not
includesthechannelmodulationeffect.

Fig.4.13IdealI D S V D S curvesoftheNMOStransistorwithV G S asparameter.

SincethedepletionregionlengthLaugmentsasVDSincreases,thelengthoftheregioncontainingthe
channelcharge,i.e.theeffectivechannellengthLeff,isreduced.Infacts:
Eq.4.15

AmoreaccurateexpressionofIDS,includesLeff:
Eq.4.16

BecauseLeffdependsonVDS,alsoIDSchangeswithVDSinthesaturationregion.Thiseffectisknownas
channellengthmodulation.IDSexpressioncanberearrangedasfollows:
Eq.4.17

AccordingtoequationxxxthedepletionregionlengthLiscalculatedasfollows:
Eq.4.18

Therefore:
Eq.4.19

1
,

Substitutingequation4.19in4.16,andneglectingVDS,satwithrespecttoVDS,thefollowingexpressionfor
IDSisobtained:

Eq.4.20

where,whichiscalledchannelmodulationparameter,isequalto:
Eq.4.21

Fig. 4.14 shows the IDSVDS curves of the NMOS transistor with channel modulation effect and VGS as
parameter.

Fig.4.14I D S V D S curvesoftheNMOStransistorwithchannelmodulationeffectandV G S as
parameter.

Byextrapolatingthecurvesinsaturationregion,allofthemmeettheVDSaxisinthesamepointequalto
1/.Theinverseof,1/,canbecomparedtotheEarlyvoltage,VA,inbipolartransistors.
3.4 Weak inversion
The passage from the off to the on state of the NMOS transistor is not drastic. Supposing the NMOS
transistorinoffstate(i.e.VGS<VTH),asVGSapproachesVTH,ifVDSisnonnull,asmallIDScurrentstartsflowing.
WhenVGSisaroundVTH,thetransistoroperatesinaregioncalledweakinversion.
Fig.4.15showstheNMOStransistorsituation.

Fig.4.15NMOStransistorwithaV G S V TH ,V D S >0.

In this condition the conducting channel is not completely formed. Since there is not much charge,
current cannot flows for drift but diffusion. Practically, the NMOS transistor behaves like a NPN bipolar
transistor, with the Source and the Drain regions corresponding to the Emitter and the Collector,
respectively,whiletheptypesubstrateunderthesilicondioxidecorrespondstotheBase.SubstitutingIC
andVBEwithIDSandVsurrespectively,inequation3.xxx,IDScanbecalculatedasfollows:

Eq.4.22

whereISistheprocessdependentinversesaturationcurrent,Vsuristhevoltageatthesurfacebetween
thesilicondioxideandtheptypesubstrate,andVtisthethermicvoltage.
TheoxidecapacitanceCoxstandsbetweentheGateandtheptypesubstrateunderthesilicondioxide,
and the ptype substrate and Source junction forms a capacitance CJS. The surface voltage Vsur, can be
calculatedbyconsideringthecapacitivedividermadeupofCoxandCJS,asfollows:
Eq.4.23

whereniscalledslopefactor.Itrangesbetween1and2.Itiscalculatedasfollows:
Eq.4.23_1

Substitutingequation4.23inequation4.22thefollowingexpressionoftheIDScurrentinweakinversion
isobtaining:
Eq.4.24

Fig.4.16showstheIDSVDSoutputcharacteristicsincludingalsotheweakinversionregion.

Fig.4.16I D S V D S curvesoftheNMOStransistorincludingtheweakinversionregion.

Table 4.1 summarizes the NMOS transistor characteristic equations for different regions of operation,
andthebiasconditionsrequiredtohavethem.
Regionofoperation Characteristicequation
Cutoff
IDS=0
Linearortriode

1

2

Saturation

Weakinversion

VGS
<VTH
>VTH

VDS

<VGSVTH

>VTH

>VGSVTH

VTH >0V

Table4.1SummaryoftheNMOStransistorcharacteristicequationsfordifferentregionsof
operation

Example 4.1

Problem. Consider the NMOS in Fig. 4.17. Assume n=600

, Cox=

, VTH=0.5V, W=10um, L=1um,

VG=1V,VDD=5V.FindtheIDScurrent.

Fig.4.17NMOStransistoroftheexample4.1.

Solution.EvaluateVGSandcomparetoVTH:
Eq. 4.25

AsVGSismorethanVTH,theNMOStransistorison.NowcalculateVDSandcompareittoVDSsat:
Eq.4.26

0.5

AsVDSismorethanVDSsat,theNMOStransistoroperatesinsaturationregion.NotethatVDSsatisequalto
thetransistoroverdriveVov.Nowevaluatethetransistorconductivityfactorkn:
Eq.4.27

1.2

Now,accordingtoequation4.14,calculatetheIDScurrent:
Eq.4.28

300

3.5 The threshold voltage

The threshold voltage, VTH, is the voltage required to form the conducting channel under the silicon
dioxide. In order to examine VTH, lets consider Source and Drain grounded, and a negative VBS and a

positive VGS voltages applied to the Bulk and the Gate, respectively. Fig. 4.17 shows the situation of the
NMOStransistor.

0<VGS<VTH
Gate

Source

Drain

tdep
Qdep
ptype
substrate

n+

Depletion
region

n+

Bulk
VBS

Fig.4.18NMOStransistorwitha0<VGS VTH,VBS<0V,andSourceandDraingrounded.
VTH consists of different contributions. Firstly, VTH is required to sustain depletion layer charge. The
depletion layer charge per unit area Qdep, is proportional to the charge per unit volume, qNA, and the
depletionregiondepth,tdep,underthesilicondioxide:
Eq.4.29

Astheinversionlayerchannelchargestartsforming,thevoltageatthesurfacesilicondioxidesubstrate
isabouttwicetheFermilevelf.Accordingtoeq.2.xxx,tdepiscalculatedasfollows:
Eq.4.30

Theminimumtdepand,thentheminimumdepletionlayerchargeperunitarea,Qdep0,isobtainedforVBS
null.Inthisbiascondition,alsotheminimumthresholdvoltage,VTH0,isget:
Eq.4.31

where istheworkfunctionsdifferencebetweentheGatepolysiliconandthesiliconsubstrate,and
QSS is a positive charge density due to imperfections of the silicon crystal atthe surface between silicon
dioxideandptypesubstrate.
ThecalculationofthethresholdvoltageforanonnullVBSisreportedinthefollowing:
Eq.4.32

where:
Eq.4.33

Equation4.28predictsthedependencyofVTHonVBS.ThisphenomenaisknownasBodyeffect,andis
calledBodyeffectcoefficient.
Fig. 4.18 shows the

curves of the NMOS transistor operating in saturation, with VBS as

parameter. As IDS depends on the square of VGS in saturation region,

changes linearly with VGS.

line intercepts the VGS axes in a point equal to VTH. This point is shifted to the right, i.e. the
thresholdvoltagemovestowardhighervalues,asVBSdecreases.

Fig.4.19

curvesoftheNMOStransistorwithVBSasparameter.

4. Large signal model of the NMOS transistor

In the last paragraph, transfer characteristics of the NMOS transistor have been get. However, due
fabricationlimitations,anumberofpassiveelementsmustbetakenunderconsiderationtogetacomplete
largesignalmodeloftheNMOStransistor.
Fig.4.20showsthecrosssectionofatypicalNMOStransistorwithIDScurrentsourceandparasitics.IDS
currentsourcerepresentstheIDScurrentmodel.

Gate

Source
Drain
CGS,ov CGS CGD CGD,ov
RS
RD
CBS DBS IDS CCBGBD
type
DBD
substrate
Bulk

Fig.4.20CrosssectionofatypicalNMOStransistorwithIDScurrentsourceandparasitics.
The two n+ islands of Source and Drain have a certain resistivity. Therefore, they give rise to contact
resistances,representedbyRSandRD.Theyvaluesarelimitedtofewohms.
ZoominginbetweenSourceandGate,asdoneinFig.4.21,asmallregionofoverlapoftheGateover
theSourceisobserved.ThesamehappensattheDrainside.

Fig.4.21CrosssectionofatypicalNMOStransistorwithI D S currentsourceandparasitics.

TheseoverlapregionsproduceparasiticcapacitancesmodeledbyCGS,ov andCGD,ov..Thevaluesofthese
capacitancesarecalculatedasfollows:
Eq.4.34

whereXovisthelengthoftheoverlapregion.
The contact resistances and the overlap capacitances have a linear behavior, i.e. their values do not
dependonthebiasconditionoftheNMOStransistor.

TheNMOStransistorstructurealsoincludestwopnjunctionsformedbythen+SourceandDrainislands
and the ptype substrate. These pnjunctions are represented by DBS and DBD diodes. As the ptype
substrate is biased at the minimum voltage available for the circuits, DBS and DBD are inversely biased.
ThereforetheyarepassedbyaninversecurrentIGR.Accordingtoequation 2.xxxIGRvalueiscalculatedas
follows:
Eq.4.35

where A is the area of the pnjunction, xj is the depletion region depth, ni is the intrinsic carrier
concentration,0istheminoritycarrierlifetime.
Asdescribedin 2.xxx,parasiticcapacitancesareassociatedwiththedepletionregions.Threedepletion
regions can be distinguished in the NMOS transistor structure: two depletion regions around the Source
and the Drain island, and a third depletion region under the Gate. The parasitic capacitances associated
with these depletion regions are represented by CBS, CBG and CBD. These capacitances have a non linear
behavior,sincetheirvaluesdependonthevoltageattheirends,asequation2.xxxpredicts.
TheGate,thesilicondioxideandtheptypesubstrateformtheGatecapacitance,CG,whichisintrinsicto
theoperationoftheNMOStransistor,sinceitisusedtocontrolthechannelcharge.AsCoxisthesilicon
dioxide capacitance per unit area, then CoxWL is the maximum value of the total Gate capacitance. Fig.
4.22plotsCGoverCoxWLversusVGS.

Fig.4.22C G overC o x WLversusV G S .

When the NMOS transistor is off, the conducting channel does not exist, and Source and Drain result
disconnected. In this condition, the total Gate capacitance stands between Gate and Bulk, adding its
contributiontoCBGwhichincludesalsothecapacitanceduetothedepletionregionundertheGate.
Whenthetransistorison,theconductingchannelformsthesecondplateof the Gate capacitance.In
saturationregion,onlytheSourceisconnectedwiththeconductingchannel.ThereforemostoftheGate
capacitancestandsbetweenGateandSource,formingtheCGScapacitancewhichisabout CoxWL.The

Drain has a small influence on the channel charge, therefore the GateDrain capacitance CGD can be
neglected. In linear region, a continuous conducting channel is extended between Source and Drain. The
GatecapacitanceisdividedbetweenSourceandDraininsimilarparts.Infact,inlinearregion,CGDandCGS
valuesarearound CoxWL.
DBSand DBDdiodes, CGSand CGD, and capacitances associated with the depletion regions (CBG, CBD, and
CBS)haveanonlinearbehavior,aswellastheIDScurrent.

5. The PMOS transistor

InCMOStechnology,thePMOStransistorisfabricatedinaNwellobtainedinaptypesubstrate.Fig.
4.23showsacrosssectionofatypicalPMOStransistor.

Source
p+

Gate

Drain

p+
Nwell
ptype
substrate

Bulk
p+

Bulk

Fig.4.23CrosssectionofatypicalPMOStransistor.

The operation mode of PMOS and NMOS transistors are similar. In both devices, the creation of a
conductingchannelisrequiredtohaveacurrentflowingbetweenSourceandDrain.However,inthePMOS
transistor,thechannelchargeismadeofholes,while,intheNMOStransistor,thechannelchargeismade
ofelectrons.InPMOSaswellasNMOStransistors,currentisduetothedriftofthechannelchargefrom
Source toward the Drain by the horizontal electric field. In the NMOS transistor, the channel charge
(electrons)isnegative,generatinganegativeSourceDraincurrent,ISD(i.eapositiveIDS),while,inthePMOS
transistor,thechannelchargeispositive(holes),generatingapositiveISDcurrent.
Moreover, in PMOS transistors, Drain and Gate have to be biased to a voltage less than the Source
voltageinordertoattractholes.Infacts,VTH,VGSandVDSarenegativeinthePMOStransistor,whilethey
arepositiveintheNMOStransistor.
AsforNMOStransistor,alsoPMOStransistorhasfourmainregionsofoperations:

cutoff;
linearortriode;
saturation;
weakinversion.

To derive characteristic equations of PMOS transistors, it is not necessary repeating the analytic
procedureusedfortheNMOStransistor.Itissufficient toperformsubstitutionsreportedintable4.2,in
characteristicequationsoftheNMOStransistor:
NMOS PMOS
IDS ISD
VGS VSG
VDS VSD
VTH VTH
np
Table4.2SubstitutionsrequiredtoderivethecharacteristicequationsofthePMOStransistor .

Table 4.3 summarizes The characteristic equations of the PMOS transistor and the bias conditions
requiredtohavethem.
Regionofoperation Characteristicequation
Cutoff
ISD=0
Linearortriode

1

2

Saturation

Weakinversion

VSG
>VTH
<VTH

VSD

>VSG+VTH

<VTH

<VSG+VTH

VTH <0V

Table4.3SummaryofthePMOStransistorcharacteristicequationsfordifferentregionsof
operation

ForthePMOStransistoritisalsopossibletousethesamecharacteristicequationsandbiasconditions
disequations for the NMOS transistor, substituting currents and voltages with their absolute values, as
table4.4reports:
Regionofoperation Characteristicequation
Cutoff
|IDS|=0
Linearortriode
| | | |
Saturation

1

2

Weakinversion

|
2

| 1
|

|
|

|
|

|VGS|
<|VTH|
>|VTH|

|VDS|

<|VGS||VTH|

>|VTH|

>|VGS||VTH|

|VTH| >0V

Table4.4SummaryofthePMOScharacteristicequationsandbiasconditionsfordifferent
regionsofoperationwithabsolutevaluesofcurrentandvoltages

AsinthePMOStransistor,ISDisduetothedriftofholes,theholemobility,p,hastobeconsidered.The
mobilityofholesisquitelessthanelectrons,asequation4.35predicts:
Eq.4.36

2.5

Therefore, a PMOS transistor has to be larger than a NMOS transistor in the same bias conditions in
ordertoprovidethesamecurrent.
However,inPMOStransistorsitispossibletomitigatethethresholdvoltageshiftduetotheBodyeffect.
Infacts,sinceptypesubstrateisboundedtoground,i.e.totheminimumvoltageavailableforthecircuit,
the pnjunction formed by the Nwell and the ptype substrate is always inversely biased. As the Nwell
results always isolated, it is possible to connect its Bulk terminal to the Source, in order to null the VBS

voltage,reducingtheBodyeffect.WhilethiseffectcanbealwaysmitigatedinPMOStransistors,itcannot
be avoided in NMOS transistors when the Source is connected to a voltage different from the ground,
whereitsBulkisbounded.

6. Analysis of the bias conditions of a MOS transistor

TosolveacircuitincludingaMOStransistorbyhand,itisrequiredtodetermineitsregionofoperation.
Asexplainedinpreviousparagraphs,theregionofoperationofaMOStransistordependsonvoltagesatits
terminals. Assuming that voltages at the MOS transistor terminals are known, in order to determine the
region of operation of a MOS transistor, at firstly it is required to verify if transistor is on or off by
comparingitsVGStoVTH.IftheMOStransistorisoff,thenitisoperatingincutoffregion.Otherwise,ifthe
MOS transistor is on, then its VDS should be compared to VDSsat in order to verify if it is operating in
saturationortrioderegion.
Fig. 4.24 shows the algorithm to follow in order to determine the region of operation of a NMOS
transistorasVGSandVDSareknown.

Fig.4.24AlgorithmfordeterminingthebiasconditionsofaNMOStransistorbyhand.

Considering the absolute values of VDS, VGS and VTH voltages, the same algorithm can be applied to a
PMOStransistor.
Example 4.2
Problem.ConsidertheNMOStransistorreportedinFig.4.25.AssumeVTH=0.5VVG=0.8V,VD=2V.Findthe
operationregionoftheNMOStransistor.


Fig.4.25NMOStransistorbiasedbyV G andV D voltages.

Solution.EvaluateVGSandcomparetoVTH:
Eq.4.37

0.8

0.5

AsVGSismorethanVTH,theNMOStransistorison.NowcalculateVDSandcompareittoVDSsat:
Eq.4.38

0.3

AsVDSismorethanVDSsat,theNMOStransistoroperatesinsaturationregion.
Example 4.3
Problem. Consider the PMOS transistor reported in Fig. 4.26. Assume VTH=0.5V VG=3V, VS=5V and
VD=4V.FindtheoperationregionofthePMOStransistor.

VS
VG
VD

Fig.4.26PMOStransistorbiasedbyV G ,V s ,andV D voltages.

Solution.Evaluate|VGS|andcompareto|VTH|:
Eq. 4.37

0.5

As|VGS|ismorethan|VTH|,thePMOStransistorison.Nowcalculate|VDS|andcompareitto|VDSsat|:
Eq.4.38

1.5

As|VDS|islessthan|VDSsat|,thePMOStransistoroperatesintrioderegion.

However,asacircuitincludingaMOStransistoristobesolvedbyhand,generally,thebiasvoltagesat
theMOStransistorterminalsarenotaprioriknown.Therefore,itisnotpossibletoapriorideterminedthe
MOS transistor region of operation. Hence, it is needed to make a starting hypothesis on its region of
operation. Then, the MOS transistor characteristic equation coherent with the starting hypothesis is
defined.AstheMOStransistorcharacteristicequationisknown,itispossibletosolvethecircuit.Oncethe
circuit is solved, it is required to verify the starting hypothesis on its region of operation. If the starting
hypothesis is not verified, then the procedure for solving the circuit is to be restarted with a different
startinghypothesis,untilthestartinghypothesisisverified.Fig.4.27showsthealgorithmforsolvingthea
circuitincludingaMOStransistorbyhand.

Start
Makeanhypothesison
theregionofoperation
oftheMOS
Solvethecircuit

Isthestarting
hypothesisverified?

No

Yes
Thecircuithasbeen
correctlysolved

Fig.4.27AlgorithmforsolvingacircuitincludingaMOStransistorbyhand.

Example 4.4
Problem. Consider the circuit reported in fig. 4.28. Assume VTH=0.5V, Kn=1mA/V2, VG=2V, VDD=5V,
RS=1k,RD=2k.Solvethecircuit.

Fig.4.28Circuittobesolvedintheexample4.4.

Solution.Establishadirectionandsetalabelforeachcurrentinthecircuit,asdoneinfig.4.29.


Fig.4.28Circuitoftheexample4.4withcurrentslabelsanddirections.

ApplyingtheKirchoffscurrentlawtotheSourceoftheNMOStransistor,itisget:
Eq.4.39

where IDS is the DrainSource current flowing into the NMOS transistor. Suppose that the NMOS
transistorworksinsaturationregion.Therefore,equation4.14canbeusedtodetermineIDS.Replacingthe
expressionsofcurrentsoftheNMOStransistorandtheresistorRSintoequation4.39,itisget:
Eq.4.40

Solvingequation4.40,twosolutionsforVSareobtained:0.677Vand3.646V.However,thesecondone
hastobewaivedasitmeansthattheNMOStransistorhastobeondespiteitsSourcevoltageishigherthan
theGatevoltage,whichisnotphysicallypossible.Therefore,VSisequalto0.677V.Hence,theIDScurrentis
equalto677A.VDiscalculateasfollows:
Eq.4.41

3.646 V

Onceallcurrentsandvoltagesinthecircuithavebeencalculated,thenthehypothesismadeaboutthe
regionofoperationoftheNMOStransistorhastobeverified.Therefore,VDSvoltagehastobecalculated
andcomparedtoVDSsat,i.e.:
Eq.4.42

2.969 V

0.823

As VDS is more than VDSsat, the hypothesis of the NMOS transistor operating in saturation region is
verified.

Example 4.5
Problem. Consider the circuit reported in fig. 4.30. Assume VTH=0.5V, Kp=1mA/V2, VG=3.5V, VDD=5V,
RD=2k.SolvethecircuitandfindtheminimumvalueofRD,RDmin,thatbringsintrioderegionthePMOS
transistor.


Fig.4.30Circuittobesolvedintheexample4.5.

Solution.Establishadirectionandsetalabelforthecurrentinthecircuit,asdoneinfig.4.31.

Fig.4.31Circuitoftheexample4.5withcurrentlabelanddirection.

SupposethatthePMOStransistorworksinsaturationregion.Therefore,equationforPMOStransistor
operatinginsaturationregionreportedintable4.3canbeusedtodetermineISD,i.e.:
Eq.4.43

1mA

ApplyingtheKirchoffscurrentlawtotheDrainofthePMOStransistor,itisget:
Eq.4.44

Hence,theDrainvoltageVDiscalculateasfollows:
Eq.4.45

2 V

Onceallcurrentsandvoltagesinthecircuithavebeencalculated,thenthehypothesismadeaboutthe
regionofoperationofthePMOStransistorhastobeverified.Therefore,VSDvoltagehastobecalculated
andcomparedtoVSDsat,i.e.:
Eq.4.42

3 V

As VSD is more than VSDsat, the hypothesis of the PMOS transistor operating in saturation region is
verified.
TheminimumvalueofRD,RDmin,thatbringsintrioderegionthePMOStransistor,makesVSDequalto
VSD,sat,i.e.:

Eq.4.43

Fromequation4.43itisget:
Eq.4.44

7. Small signal model of the MOS transistor

Thesmallsignalmodelisusedinordertosimplifythecalculationofthegainandtheinputandoutput
impedances in analog circuits including MOS transistors. The complexity of the model is increased
accordingtotheanalysistoperform.
7.1 Small signal circuit
ConsidertheNMOStransistorinfig.4.32.withbiasvoltagesVGandVDDappliedasshown.

Fig.4.32NMOStransistorwithbiasingandasmallsignalvgsappliedtotheGate.

AssumingthattheNMOStransistorison(i.e.VG>Vth),then,aDrainSourcebiascurrent,IDS,flowsacross
the device. As a voltage signal vgs is applied in series with VG, a small drain current variation ids is
generated.Forsmallvaluesofvgs,idsisdirectlyrelatedtovgsbythetransconductanceparameter,gm,which
isdefinedasfollows:
Eq.4.45

Thereforeidsisobtainedasfollows:
Eq.4.46

Thisrelationcanbeexplainedinanalternativeway,byrecurringtotheTaylorseriesexpansionoftheIds
currentexpression,i.e.:
Eq.4.47

ForsmallGateSourcevoltagevariation,
,(i.e.forsmallvaluesofvgs)isitpossibletohaveagood
approximationofIdscurrentbystoppingtothefirsttermoftheTaylorexpansion,i.e.:
Eq.4.48

ConsidertheNMOStransistorinfig.4.33,withasmallsignal,vds,appliedtotheDrain.Assumingthatthe
NMOStransistorison,thentheDrainSourcecurrent,Ids,changeswithvds.

Fig.4.33NMOStransistorwithbiasingandasmallsignalvdsappliedtotheDrain.

ItispossibletocalculateIdsvariation,ids,duetovds,asfollows:
Eq.4.49

wheregdsisthesmallsignaloutputconductance,calculatedasfollows:
Eq.4.50

TheGateoftheMOSisisolatedfromthechannelbythesiliconoxide.Therefore,atlowfrequency,the
Gatecurrentisaboutzero,whiletheinputimpedanceisaboutinfinite,asaconsequence.
CombiningtheprecedingsmallsignalelementsyieldsthesmallmodeloftheMOStransistorshownin
Fig.4.34.

Fig.4.34Basicmodelofthesmallsignalcircuit.

This is the basic model of the small signal circuit. It does not includes the dependence of the Drain
SourcecurrentontheBulkvoltageduetotheBodyeffect,andtheparasiticcapacitances.Infact,theBulk

Source voltage changes the threshold voltage, which changes the DrainSource current when the Gate
Sourcevoltageisfixed.Therefore,afurthertransconductanceterm,theBulktransconductance,isrequired
totheMOSmodel.TheBulktransconductanceisdefinedasfollows:
Eq.4.51

Athighfrequency,theeffectsoftheparasiticcapacitancescannotbeneglected.
Fig. 4.35 shows the small signal circuit including CGS and CGD capacitances and the Bulk
transconductance.

Fig.4.35Completemodelofthesmallsignalcircuit.

Thisisthecompletemodelofthesmallsignalcircuit.
7.2 Small signal circuit parameters calculation
The calculation of the small signal circuit parameters of a MOS transistor depends on its region of
operation.
In saturation region, the transconductance of a NMOS transistor is calculated from equation 4.20 by
differentiatingwithrespecttoGateSourcevoltage,Vgs,i.e.:

Eq.4.52

Accordingtothelastexpressionofgmfoundinequation4.52,thetranscoductanceofaNMOStransistor
isproportionaltothesquarerootofthebiascurrent,IDS.Thisisakeydifferencewithrespecttothebipolar
transistorwhichhasatransconductanceproportionaltothebiascurrent.Therefore,thetransconductance
forgivencurrent,i.e.thecurrentefficiency,ismuchhigherinbipolarthanMOStransistors.
However, in weak inversion, the transconductance of a NMOS transistor is proportional to the bias
currentIDS,asthetransistorcurrenthasanexponentialdependencyontheGateSourcevoltage,Vgs.Inthis
case, the current efficiency of MOS transistors is closer to that one of the bipolar transistors. In fact, in
weakinversion,thetransconductanceiscalculatedfromequation4.24bydifferentiating:
Eq.4.53

Topushatransistorinweakinversion,reducingthetransistoroverdriveisneeded.Thishasimportant
impact on the circuit performance like offset, noise, etc., therefore it is not always possible. Moreover,
reducingthetransistoroverdrivebykeepingaconstantbiascurrent,impliesthatthetransistorssizesmust
be increased. But larger transistors introduce bigger parasitic capacitances, limiting the operation
frequency.
Fig. 4.36 shows the real behavior of the MOS transistor transconductance, gm, when its GateSource
voltage,VGS,isincreased.ItisassumedthattheDrainSourcevoltage,VDS,ishighenoughnottomakethe
transistorgoinginlinearregion.

saturation
region

gm

velocity
saturation

weak
inversion
VGS

VTH
Fig.4.36MOStransistortransconductance,gm,versusVGS.

ForhighvalueofVGStheMOStransistorgmsaturates.Infact,increasingVGS,theelectricfieldinsidethe
transistoraugmentstoo.Forlowelectricfieldintensities,thedriftvelocityofelectronsisproportionalto
theelectricfield,accordingtoequation4.6.Astheelectricfieldintensityapproachesthecriticalvalue,c,
the drift velocity of the electrons reaches its upper limit (i.e. the scattering limited velocity) due to the
increasingscatteringresistance.Thisphenomenacanbedescribedbyintroducingamorecomplexmodel
for the electron mobility. Equation 4.54 shows a first order approximation model for the mobility that
consideritsreductionattheincreaseoftheGateSourcevoltage,VGS[xxx]:
Eq.4.54

wheren0istheelectronmobilityforanullelectricfield,whiletheparameterdependsonthecritical
electricfiled,c,andthetransistorlengthL:
Eq.4.55

Therefore,thephenomenaofvelocitysaturationismoreevidentforshortchanneldevices.

By replacing the expression of the electron mobility reported by equation 4.54 in equation 4.20, the
followingmodelfortheDrainSourcecurrentisfound:
Eq.4.55

For large values of VGS (i.e.

), an substantially linear dependency of the DrainSource

current,IDS,versusthegatesourcevoltage,VGS,occurs:
Eq.4.56

Inthiscondition,thetransconductancereachesitsmaximum,gm,sat,thatdoesnotdependsontheGate
Source,VGS:
Eq.4.57

In linear region, the transconductance of a NMOS transistor is calculated from equation 4.8 by
differentiatingwithrespecttoGateSourcevoltage,Vgs,i.e.:
Eq.4.58

In saturation region, the output conductance is calculated from equation 4.20 by differentiating with
respecttotheDrainSourcevoltage,Vds,asfollows:
Eq.4.59

Similarly,inlinearregion,theoutputconductanceiscalculatedfromequation4.8bydifferentiatingwith
respecttotheDrainSourcevoltage,Vds,asfollows:
Eq.4.60

Usingequation4.20theBulktransconductanceinsaturationregioniscalculatedasfollows:
Eq.4.61

where is the rate of change of the threshold voltage with the BulkSource voltage due to the Body
effect.Fromequations4.32and2.xxx,iscalculatedasfollows:
Eq.4.62

whereCJSisthecapacitanceperunitareaformedbysubstrateSourcejunction.
Theratiobetweengmbandgmisanimportantparameterinpractice.Fromequation4.61,itisget:
Eq.4.59

This is a powerful relationship, but it does not provide an accuratvalue as depends on the bias
conditions.Thefactortypicallyrangesfrom0.1to0.3,thereforetheBulktransconductanceis310times
smallerthantheMOStransconductance.

To derive the expressions of small signal circuit parameters of PMOS transistors, it is not necessary
repeating the analytic procedure used for the NMOS transistor. It is sufficient to perform substitutions
reportedintable4.2,intheequationsobtainedtocalculatethesmallsignalcircuitparametersofaNMOS
transistor.

8. Gain stages with a single MOS transistor

The small signal equivalent circuits of Bipolar and MOS transistors are quite similar. The two devices
differs mainly in the values of some parameters. MOS transistors have a substantially infinite Gate
resistance, in contrast with the finite Base resistance, r, of bipolar transistors. On the other hand, the
BipolartransistorhasatransconductanceoneorderofmagnitudelargerthanthatofMOStransistors,with
the same current. According to the situations, MOS of Bipolar transistors are preferable. For example, if
high input impedance amplifiers are required, they can more easily implemented by using a MOS
technology.Ifalargergainisrequired,thenaBipolartransistorismoresuited.Designersmustappreciate
the similarities and the differences between Bipolar and MOS technologies, in order to make an
appropriatetechnologychoice.
AsfortheBipolartransistors,MOStransistorsareabletoprovideausefulgaininthreeconfigurations:
commonSource,commonDrainandcommonGateconfigurations.
8.1 Common Source configuration
Thecommonsourceamplifierisshowninfigure4.37.

Fig.4.37Commonsourceamplifier.

AsFigure4.37shows,theSourceisconnectedtotheground,i.e.itiscommontothegroundnetwork.
TheinputsignalisappliedtotheGate,whiletheoutputsignalistakenfromtheDrain.
Theoutputvoltage,VO,iscalculatedasfollows:
Eq.4.60

AsVi<VTH,nocurrentflowsthroughtheNMOStransistor,therefore:
Eq.4.61

0 and

AsViisincreasedbeyondthethresholdvoltage,VTH,theNMOStransistorstartsconducting.TheNMOS
transistoroperatesinsaturationregionuntilVo>ViVTH.Accordingtoequation4.14,astheNMOStransistor
isinsaturationregion,theDrainSourcecurrentisgivenby:
Eq.4.62

Combiningequations4.60e4.62thefollowinginputoutputrelationshipisget:
Eq.4.63

BykeepingonincreasingtheVivoltage,theNMOStransistorgoesinlinearregionasVo<ViVTH.
Accordingtoequation4.8,thefollowinginputoutputrelationshipisget:
Eq.4.64

AstheoutputconductanceaugmentswhentheNMOStransistorenterthelinearregion,thevoltage
gaindropsdramatically.
Theresultinginputoutputcharacteristicisreportedinfigure4.38.

Fig.4.38InputoutputcharacteristicofacommonSourceamplifier.

Theslopeofthischaracteristicatanyoperatingpoint,correspondstothesmallsignalgainatthatpoint.
Inlinearregiontheslopeisreduced,confirmingthatthevoltagegaindrops.
AssumingthatasmallvoltagesignalisappliedtotheGate,figure4.39showsthecorrespondingsmall
signalequivalentcircuit:

Fig.4.39SmallsignalequivalentcircuitofcommonSourceamplifier.

Theoutputvoltage,vo,isgivenbythevoltagedropontheresistiveload,

.Asthecurrentflowing

intheresistiveloadisthatprovidedbythecurrentgenerator,theoutputvoltageiscalculated:
Eq.4.65

Therefore,thevoltagegain,AV,iscalculatedasfollows:

Eq.4.66
As

,thenthevoltagegainbecomes:

Eq.4.67

ThevoltagegainincreasesbyaugmentingRD.However,forlargeRDvaluestheoutputconductanceof
theNMOS,gds,isnomorenegligible.Aleast,as
Eq.4.68

,thefollowingvoltagegainisget:

AssumingthattheNMOStransistorworksinsaturationregion,byreplacingequations4.52and4.59in
equation4.68,thefollowingdependencyofthegainontheDrainSourcecurrent,IDS,isget:
Eq.4.69

By reducing the DrainSource current, IDS, the voltage gain increases. However, according to equation
4.14, reducing the DrainSource current of an MOS transistor with a constant geometry, produces a
decreaseoftheoverdrivevoltage.Inpractical,theMOStransistorispushedtoworkinweakinversion.In
weakinversion,thetransconductanceoftheNMOSisproportionaltotheDrainSourcecurrent,IDS.Then,
byreplacingequations4.53and4.59inequation4.68,theexpressionofthevoltagegainchanges:

Eq.4.70

Thisisthemaximumvalueofthevoltagegain.ItdoesnotdependontheDrainSourcecurrent,IDS,nor
ontheMOStransistoraspectratio, .Itonlydependsonthechannelmodulationparameter, ,whichis
reverselyproportionaltotheMOStransistorlength,L,andtheslopefactor,n,whichismainlycorrelatedto
thefabricationprocess.
AstheinputsignalisappliedtotheGateterminal,theinputresistanceoftheamplifierisaboutinfinite.
TheoutputresistanceiscalculatedbyconsideringthesmallsignalequivalentcircuitreportedinFig.4.40.

it
vi

gds

gmvi

vt

RD

Fig.4.40Smallsignalequivalentcircuitforthecalculationoftheoutputresistanceofacommon
Sourceamplifier.

Forthecalculationoftheoutputresistance,Ro,theinputsignal,vi,isnulledbydefinition.Therefore,the
currentofthecurrentgenerator(i.e.gmvi)iszerotoo.Inpractical,itislikethecurrentgeneratordoesnot
exist,whiletheparallelofRDand1/gdsremains.Theoutputresistance,Ro,iscalculatedasfollows:
Eq.4.70

Example 4.6
Problem. Consider the circuit reported in fig. 4.41. Assume VTH=1V, Kn=5mA/V2, VDD=10V, RL=4k,
R1=8.5k, R2=1.5k, CL=10nF, Ci. Calculate the bias point and the voltage gain versus the frequency,
.TracetheBodediagramofthevoltagegain.Evaluatethemaximuminputvoltageamplitudebefore
theNMOStransistor,M1,goestothelinearregion.

Fig.4.41Circuittobesolvedintheexample4.6.

Solution.Tocalculatethebiaspointitispossibletosimplifythecircuitbynullingthecapacitancesand
theinputsignal,asitisdoneinfigure4.42.

Fig.4.42Circuitoftheexample4.6withoutcapacitancesandwithanullinputsignal.

AstheGatedoesnotadsorbanycurrent,theGatevoltageVG,iscalculatedasapartitionofVDDonR2
resistor:
Eq.4.71

1.5

As VG=VGS>VTH the transistor is switched on. Suppose that the NMOS transistor works in saturation
region.Therefore,equationforNMOStransistoroperatinginsaturationregionreportedinequation4.14
canbeusedtodetermineIDS,i.e.:
Eq.4.72

1.25mA

Theoutputbiasvoltage,VO,iscalculatedasfollows:
Eq.4.73

Once that the circuit has been solved, it is required to verify the initial hypothesis, i.e. the NMOS
transistorworkinginsaturationregion.Itmeansthatthefollowingconditiononthedrainsourcevoltage
VDS,reportedintable4.1,istobeverified:
Eq.4.74

0.5

As this condition is satisfied, the initial hypothesis of NMOS transistor working in saturation region is
verified.
Inordertocalculatethevoltagegain,thesmallsignalequivalentcircuitisreportedinfigure4.43.

Fig.4.43Smallsignalequivalentcircuitofthecircuitoftheexample4.6.

If the channel modulation parameter is not specified, assume that

>>RD . Therefore the output

transistor conductance, gds, can be neglected for the drawing of the small signal equivalent circuit, and,
then,forthecalculationofthevoltagegain.ApplyingtheKirkoffscurrentlawtotheoutputnode,itresults
thatthecurrentofthecurrentgeneratorpassesthroughtheoutputloadconsistingoftheparallelofRD
andCL,andproducingavoltagedropequaltovo.Therefore,voiscalculatedasfollows:
Eq.4.75

Thevoltagegainis,then,calculated:
Eq.4.76

Asequation4.76shows,thevoltagegainhasapole,p1:
Eq.4.77

25krad/s

Calculatetheabsolutevalueofthevoltagedcgain,
Eq.4.78

0 ,bycombiningequations4.76and4.52:

20

26

Figure4.44showstheasymptoticBodediagramofthevoltagegain.Atlowfrequency,themagnitude
hasaconstantvalueequaltothevoltagedcgain.Startingfromthepolefrequency,|p1|,thevoltagegain
decreaseswithaslopeof20dB/decade.Atlowfrequencythephaseis180duethenegativesignofthe
voltagegain.Thepolep1producesaphaseshiftof90,leadingthephaseto270athigherfrequencies.


Fig.4.44AsymptoticBodediagramofthevoltagegainfortheexample4.6.

In order to solve the last point of the example, consider the condition on Vds reported in table 4.1 in
ordertokeepontheNMOStransistor,M1,operatinginsaturationregion,i.e.:
Eq.4.79

Butatdc:
Eq.4.80

Therefore,bycombiningequations4.79and4.80itisget:
Eq.4.81

Disequation 4.81 is satisfied until vi is kept lower than the edge value vi,max which is calculated by
imposing:
Eq.4.82

ByreplacingthevaluesofVO,VGandgmRDfoundinequations4.71,4.73,and4.78,inequation4.82,itis
get:
Eq.4.83

167

8.2 Common Drain configuration

Thecommondrainamplifierisshowninfigure4.45.

VDD
Vi

Vo
RS

Fig.4.45Commondrainamplifier.

AsFigure4.45shows,theDrainisconnectedtoVDDwhichisgroundforthesignal,i.e.theDrainnodeis
common to the ground network of the small signal equivalent circuit. The input signal is applied to the
Gate,whiletheoutputsignalistakenfromtheSource.
Theoutputvoltage,VO,iscalculatedasfollows:
Eq.4.84

AsVi<VTH,nocurrentflowsthroughtheNMOStransistor,therefore:
Eq.4.85

0 and

AsViisincreasedbeyondthethresholdvoltage,VTH,theNMOStransistorstartsconducting.TheNMOS
transistor operates in saturation region until Vi>VDD+VTH. According to equation 4.14, as the NMOS
transistorisinsaturationregion,theDrainSourcecurrentisgivenby:
Eq.4.86

Combiningequations4.84e4.86thefollowinginputoutputrelationshipisget:
Eq.4.87

Fromequation4.87itisget:
Eq.4.88

Theresultinginputoutputcharacteristicisreportedinfigure4.46.


Fig.4.46InputoutputcharacteristicofacommonDainamplifier.

AssumingthatasmallvoltagesignalisappliedtotheGate,figure4.47showsthecorrespondingsmall
signalequivalentcircuit:

Fig.4.47SmallsignalequivalentcircuitofcommonDrainamplifier.

Theoutputvoltage,vo,isgivenbythevoltagedropontheresistiveload,

.Asthecurrentflowing

intheresistiveloadisthatprovidedbythecurrentgenerator,theoutputvoltageiscalculated:

Eq.4.89
But

,therefore,thevoltagegain,AV,iscalculatedasfollows:

Eq.4.90

As

,thenthevoltagegainbecomes:

Eq.4.91

ThevoltagegainincreasesbyaugmentingRS.Aleast,as
Eq.4.92

1,thefollowingvoltagegainisget:

Asthe gainisaboutunitary,thisgain stageisalsocalled Sourcefollower(itislikethe Sourcevoltage

followstheGatevoltage).TheinputsignalisappliedtotheGateterminal,thereforetheinputresistance
of the amplifier is about infinite. The output resistance is calculated by considering the small signal
equivalentcircuitreportedinFig.4.48.

Fig.4.48Smallsignalequivalentcircuitforthecalculationoftheoutputresistanceofacommon
Drainamplifier.

Forthecalculationoftheoutputresistance,Ro,theinputsignal,vi,isnulledbydefinition.Therefore,the
current of the current generator is equal to gmvt. In practical, the current generator produces a current
proportionaltothevoltagedroponitsends(vt),thereforeitbehaveslikearesistorwith1/gmvalue.The
outputresistance,Ro,iscalculatedastheparallelof1/gm,RSand1/gds,i.e.:
Eq.4.93

Assuming1/

,theoutputresistance,Ro,isassmallas1/gm.Asthisgainstagehasanhigh

inputimpedance,alowoutputimpedanceandanaboutunitarygain,itisoftenusedasvoltagebufferto
separatetwocascadedstagesinordertolimittheloadeffectsofthesecondstageonthefirstone.

 Example 4.7
Problem. Consider the circuit reported in fig. 4.49. Assume VTH=1V, Kn=5mA/V2, VDD=10V, RS=4k,
RL=4k, R2=8.5k, R1=1.5k, Co=10nF, Ci=4F. Calculate the bias point and the voltage gain versus the
frequency,

.TracetheBodediagramofthevoltagegain.

Fig.4.49Circuittobesolvedintheexample4.7.

Solution.Tocalculatethebiaspointitispossibletosimplifythecircuitbynullingthecapacitancesand
theinputsignal,asitisdoneinfigure4.50.

Fig.4.50Circuitoftheexample4.7withoutcapacitancesandwithanullinputsignal.

AstheGatedoesnotadsorbanycurrent,theGatevoltageVG,iscalculatedasapartitionofVDDonR2
resistor:
Eq.4.94

8.5

As VG=VGS>VTH the transistor is switched on. Suppose that the NMOS transistor works in saturation
region.Therefore,equationforNMOStransistoroperatinginsaturationregionreportedinequation4.14
canbeusedtodetermineIDS,i.e.:
Eq.4.95

ButVSisdeterminedbythevoltagedroponRSresistor,i.e.:
Eq.4.96

ByreplacingVSinequation4.95bytheexpressionfoundinequation4.96,asecondorderequationis
getwheretheonlyvariableisIDS:
Eq.4.97

Twosolutionsarepossibleforequation4.97,:
Eq.4.98

1.73

and

2.03

ButtheonlyIDS,1hasaphysicalsignificant.IDS,2isnotafeasiblesolution.Infact,ifIDS=IDS,2,VGSresultsto
belessthanathresholdvoltageVTH,whichmeansthattheNMOStransistorshouldbeswitchedoff,and,at
thesametime,itshouldbepassedbyanonnullcurrent.
Once that the circuit has been solved, it is required to verify the initial hypothesis, i.e. the NMOS
transistorworkinginsaturationregion.Itmeansthatthefollowingconditiononthedrainsourcevoltage
VDS,reportedintable4.1,istobeverified:
Eq.4.99

10

6.5

As this condition is satisfied, the initial hypothesis of NMOS transistor working in saturation region is
verified.
Inordertocalculatethevoltagegain,thesmallsignalequivalentcircuitisreportedinfigure4.51.

Fig.4.51Smallsignalequivalentcircuitofthecircuitoftheexample4.7.

If the channel modulation parameter is not specified, assume that

>>RS . Therefore the output

transistor conductance, gds, can be neglected. In order to simplify the gain calculation it is possible to
expressthevoltagegain,AV,asfollows:
Eq.4.100

Eq.4.101

where:

Theoverallimpedance,Zs,connectedtothesourceoftheNMOStransistoriscalculatedasfollows:
Eq.4.102

Byconsideringequation4.91,andreplacingRSwithZSthefollowing gainisget:
Eq.4.103

The gainisgetaspartitionofVSvoltageonRL,i.e.:
Eq.4.103

Therefore,byreplacingequations4.101,4.102,4.103inequation4.100,theoverallvoltagegain,AV,is
getasfollows:

Eq.4.104

Asequation4.104shows,thevoltagegain,Av,hastwozeroatthenullfrequencyandtwopoles,p1and
p2:
Eq.4.105

25krad/s;

196rad/s.

Fromequation4.104,calculatetheabsolutevalueofthevoltagegainathighfrequencies( ):
Eq.4.106

Figure 4.52 shows the asymptotic Bode diagram of the voltage gain, Av. The two zeros at the null
frequency introduce a 40dB/decade slope of the gain curve at low frequency. The two poles p1 and p2
determineagainslopevariationsof20dB/decadeeach.Athighfrequencies,themagnitudehasaconstant
valueaboutequalto0dB.Atlowfrequencythephaseis180duethetwozeros.Thetwopolesintroduce
aphaseshiftof90each,leadingthephaseto0athigherfrequencies.

20

0 0
10

10

2
3
4
5
10 |p2| 10
10 |p1| 10
frequency(rad/s)

20

10

10

10

10

20dB/decadeslope

40

60
40dB/decadeslope

80

100

120

180
90

10

10

10 |p2| 10
10 |p1| 10
frequency(rad/s)

Fig.4.52AsymptoticBodediagramofthevoltagegainfortheexample4.7.

8.3 Common Gate configuration

ThecommonGateamplifierisshowninfigure4.53.


Fig.4.53CommonGateamplifier.

AsFigure4.53shows,theGateisconnectedtoafixedvoltageVbwhichisgroundforthesignal,i.e.the
Gate node is common to the ground network of the small signal equivalent circuit. The input signal is
appliedtotheSource,whiletheoutputsignalistakenfromtheDrain.
Theoutputvoltage,VO,iscalculatedasfollows:
Eq.4.107

AsVi>VbVTH,nocurrentflowsthroughtheNMOStransistor,therefore:
Eq.4.108

0 and

AsViisdecreasedbeyondVbVTH,theNMOStransistorstartsoperatinginsaturationregion.TheDrain
Sourcecurrent,IDS,isgivenby:
Eq.4.109

Accordingtoequation4.108thefollowinginputoutputrelationshipisget:
Eq.4.110

Equation4.111isvaliduntiltheNMOStransistorkeeponoperatinginsaturationregion,i.e.untilthe
followingconditionissatisfied:
Eq.4.111

ThepreviousdisequationissatisfiedasViishigherthanthelimitvalueVi,min:
Eq.4.112

FoVi<Vi,mintheNMOStransistoroperatesinlinearregion.
Theresultinginputoutputcharacteristicisreportedinfigure4.54.

Vo
VDD
linearregion

saturation interdiction
region
region

Vi,min

Vi

VbVTH

Fig.4.54InputoutputcharacteristicofacommonGateamplifier.

AssumingthatasmallvoltagesignalisappliedtotheSource,figure4.55showsthecorrespondingsmall
signalequivalentcircuit:

Fig.4.55SmallsignalequivalentcircuitofcommonGateamplifier.

Assuming

negligible,theoutputvoltage,vo,isgivenbythevoltagedropontheresistiveload,RD.As

the current flowing in the resistive load is provided by the current generator, the output voltage is
calculatedasfollows:
Eq.4.113
But

,therefore,thevoltagegain,AV,iscalculatedasfollows:

Eq.4.114

TheinputresistanceiscalculatedbyconsideringthesmallsignalequivalentcircuitreportedinFig.4.56.

Fig.4.56Smallsignalequivalentcircuitforthecalculationoftheinputresistanceofacommon
Gateamplifier.

ByapplyingtheKirkoffscurrentlawtotheSourcenode,andneglectingthecurrentflowingingdsasitis
assumedtobeverysmall,thefollowingequationisget:

Eq.4.115

Fromequation4.115theinputresistance,Ri,isget:
Eq.4.116

Theoutputresistance,Ro,iscalculatedbyconsideringthesmallsignalequivalentcircuitreportedinFig.
4.57.

Fig.4.57Smallsignalequivalentcircuitforthecalculationoftheoutputresistanceofacommon
Gateamplifier.

Forthecalculationoftheoutputresistance,Ro,theinputsignal,vi,isnulledbydefinition.Therefore,the
currentofthecurrentgeneratorisnull.Therefore,fromtheoutputnode,itisseentheparallelofRDand
1/gds,i.e.:
Eq.4.117

Assuming1/gds<<RD,theoutputresistance,Ro,isaboutequaltoRD.
Example 4.8
Problem.Considerthecircuitreportedinfig.4.58.AssumeVTH=1V,Kn=5mA/V2,VDD=10V,RD=4k,Vb=5V,
20

VDD=10V. Design the amplifier in order to have a voltage gain,

in the frequency range

between20Hzand20kHz.

Fig.4.58Circuittobesolvedintheexample4.8.

Solution. Assume that the NMOS transistor operates in saturation region. Consider the small signal
equivalentcircuitreportedinfigure4.59,inordertocalculatethevoltagegain .

Fig.4.59Smallsignalequivalentcircuitofthecircuitoftheexample4.8.

Tosimplifythecalculationitispossibletodecomposethevoltagegainasfollows:
Eq.4.118

Fromequation4.114itispossibletoderive

byreplacingRDwith

Eq.4.119

Tocalculate

,i.e.:

considerthecircuitreportedinfigure4.60,wheretheTheveninsequivalentcircuit

seen from the Source of the NMOS transistor has been considered instead of the overall small signal
equivalent circuit. The Thevenins equivalent circuit corresponds to the input resistance ( 1/ ) of the
commonGateamplifier.


Fig.4.60Smallsignalequivalentcircuitoftheexample4.8withtheTheveninsequivalentcircuitseenfrom
theSourceoftheNMOStransistors.

Thevsvoltageisobtainedaspartitionoftheinputvoltage,vi,on

Eq.4.120

,therefore:

Bycombiningequations4.118,4.119,and4.120itisget:
Eq.4.121

The decoupling capacitance Ci generates a zero at the null and a low frequency pole, p1, while the CL
capacitancegeneratesanhighfrequencypolep2:
Eq.4.122

In the frequency range between the two poles, i.e. | |

follows:
Eq.4.123

Accordingtothespecifications,
Eq.4.124

| |

| |

| |

| |, the voltage gain is calculated as

| | hastobeequalto20dB,therefore:
|

2.5

According to eq. 4.52, from the transconductane gm and the conducibility factor Kn of the NMOS
transistor,itisgetthevalueoftheDrainSourcecurrent,IDS:
Eq.4.125

312.5

Accordingtoeq.4.14,theNMOStransistoroverdrive,Vov,isgivenby:
Eq.4.126

250

Withreferencetofig.4.59,theSourcevoltageatdc,i.e.consideringthecapacitorCiasanopencircuit,
iscalculatedbyapplyingtheKirkoffslawforvoltages,i.e.:

Eq.4.127

3.750

At dc, the RS resistor is passed by the IDS current, while the VS voltage drops at its ends. Therefore its
valueisgetasfollows:
Eq.4.128

12

Byspecificationsthelowerfrequencypole,p1,hastobesetat20Hz,therefore:
Eq.4.129

| |

10

Byspecificationsthelowerfrequencypole,p2,hastobesetat20kHz,therefore:
Eq.4.130

| |

ThelastchecktodoisontheoperationregionoftheNMOStransistor.Ithasbeenassumedthatthe
NMOStransistoroperatesinsaturationregion.Thishappensifthefollowingconditionissatisfied:
Eq.4.131
As

8.75 ,thepreviousdisequationissatisfied.