CPSC 457

CPSC 457
Virtual Memory

Fall 2017

Contains slides from Mea Wang, Andrew Tanenbaum and Herbert Bos, Silberschatz, Galvin and Gagne

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Virtual memory
physical
memory
(RAM)
process's
● virtual memory is a memory management technique virtual
memory
○ allows the OS to present a process with logical
address space that appears contiguous
another
○ while physical address space can be process
discontiguous
○ and some parts of logical address space can be
mapped to a backing store
● improves memory management
● allows parts of programs to be 'swapped' in/out
DISK

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Paging
● paging is the most common implementation of physical
memory
virtual memory (RAM)

● virtual address space is divided into pages: process's frame 0

virtual frame 1
○ fixed size blocks memory
frame 2
page 0
○ usually power of 2, range 512B ― 16MB page 1
● physical memory is divided into (page) frames page 2

○ same size as pages

page
● pages map to frames via a lookup table called page table

table (logical → physical address mapping)

frame m-1
● avoids external fragmentation, since no holes
● each process can have its own page table page n-1

(ptr in PCB)
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Paging

● if a program tries to address a page that does not map to physical memory
○ CPU issues a trap ― called page fault
○ OS suspends the process
○ OS locates the missing page on disk
□ what happens if not on disk? → invalid page fault
results in a crash, segmentation fault, core dump ...
○ OS loads the missing page from disk
○ OS updates the page table
○ OS resumes the process
● if OS only loads pages as a result of page fault, we call that demand paging

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Paging
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Paging

● page table translates logical addresses → physical addresses

● to run a program of size N pages
○ OS needs to find N free frames
○ and then load the program into them
● we must keep track of all free frames in the OS
● we still need memory management techniques
● also, we need a similar mechanism for the backing store
○ backing store is also split into pages
● note: we still have internal fragmentation

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Paging example
● virtual address space = 64KB
● physical address space = 32KB
● page size = 4KB
● calculate:
○ frame size = ?
○ # of pages = ?
○ # of frames = ?

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Paging example
● virtual address space = 64KB
● physical address space = 32KB
● page size = 4KB
● calculate:
○ frame size = 4KB (same as page size)
○ # of pages = 16 (64KB / 4KB)
○ # of frames = 8 (32KB / 4KB)

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Paging example
● Assume page size = 2KB, and a process needs 71 KB to load. How many pages do we need?

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Paging example
● Assume page size = 2KB, and a process needs 71 KB to load. How many pages do we need?

○ we need 35 pages + 1 KB → OS needs to find 36 free frames

● do the frames need to be contiguous? NO!

○ OS allocates 36 frames anywhere

○ but the logical address space is contiguous

● Observations:

○ one frame will have 1KB of unused space (internal fragmentation)

○ no external fragmentation since there are no holes between frames

○ but what if there are no free frames?

□ what to do if all physical memory is used up

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Demand paging performance
● paging performance is commonly evaluated by the effective access time for memory access
● Let:
○ p = probability of page fault or page fault rate ( 0 <= p <= 1)
□ p = 0 → all pages are in memory, no page fault
□ p = 1 → all pages are on disk, all memory accesses are page faults
○ ma = memory access time
○ pfst = page fault service time, ie. how long does it take to service a page fault
● Then:
○ effective access time: EAT = (1-p) * ma + p * (pfst + ma)
● Non-realistic example: calculate EAT if page fault probability is 50%, ma = 1ms and pfst = 10ms
○ EAT = (1-0.5) * 1ms + 0.5 * (10ms + 1ms) = 0.5ms + 5.5ms = 6ms
● Realistic example: calculate EAT if page fault probability is 1/1000, ma = 100ns and pfst = 10ms
○ EAT = (1-0.001) * 100ns + 0.001 * 10,000,100ns ~= 10099.9ns
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 CPSC 457
Demand paging performance
● paging performance is commonly evaluated by the effective access time for memory access
● Let:
○ p = probability of page fault or page fault rate ( 0 <= p <= 1)
□ p = 0 → all pages are in memory, no page fault
□ p = 1 → all pages are on disk, all memory accesses are page faults
○ ma = memory access time
○ pfst = page fault service time, ie. how long does it take to service a page fault
● Then:
○ effective access time: EAT = (1-p) * ma + p * (pfst + ma)
● Non-realistic example: calculate EAT if page fault probability is 50%, ma = 1ms and~101
pfst x=slower
10ms
○ EAT = (1-0.5) * 1ms + 0.5 * (10ms + 1ms) = 0.5ms + 5.5ms = 6ms
● Realistic example: calculate EAT if page fault probability is 1/1000, ma = 100ns and pfst = 10ms
○ EAT = (1-0.001) * 100ns + 0.001 * 10,000,100ns ~= 10099.9ns
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Address translation scheme
● Address generated by CPU is divided into:
○ Page number (p) – used as an index into a page table which contains base address of
corresponding frame in physical memory
○ Page offset (d) – combined with base address to define the physical memory address that is
sent to the memory unit

m-bit logical address space (2m), and n-bit page size (2n)

Example: 16-bit logical address 1010101001100101b, and 210 page size

6-bit page number 10 bit page offset

101010b 1001100101b
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Paging hardware

p = page number
d = page offset
f = frame number
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Paging Model of Logical and Physical Memory

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Paging Model of Logical and Physical Memory
0:

4: i
0: a j
k
1: b l
2: c 8: m
n
3: d o
4: e p
0: 5 12:
5: f 1: 6
logical address physical
6: g 2: 1
space memory
7: h 3: 2 16:
8: i
4 bytes per 9: j
10: k page table 20: a
page
b
11: l c
12: m d
24: e
13: n f
14: o g
h
15: p 28:
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Free frames

before allocation after allocation

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Page Table Implementation

● page table is kept in main memory

● page-table base register (PTBR) points to the page table
● page-table length register (PTLR) indicates size of the page table
● in this scheme every data/instruction access requires at least two memory accesses
○ one for page table lookup + one more for instruction fetch
● this can be reduced by using a special fast-lookup hardware cache called translation lookaside
buffer (TLB)
○ TLBs are extremely fast and extremely small (64 to 1K entries)
○ on TLB miss, value is loaded into TLB for faster access next time

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TLB as associative memory
● TLB is often implemented as associative memory
○ hardware capable of fast parallel search based on content

● given a "Page #", TLB will return corresponding "Frame #" in constant amount of time
● but TLB only stores a subset of the page table
● if TLB does not contain entry for "page #", it must be obtained from page table in memory
○ TLB-hit vs TLB-miss
● effective memory-access time = (1-p) * (tlbs + 2 * ma) + p * (tlbs + ma)
p = probability of TLB-hit (TLB-hit ratio), tlbs = TLB search time 19
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Paging hardware with TLB

● effective memory-access time

= (1-p) * (tlbs + 2 * ma) + p * (tlbs + ma) 20
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Memory protection

● memory protection is usually implemented by associating a protection bit with each frame
○ the bit indicates if read-only or read-write access is allowed
○ note: we can can also add other protection bits (execute only, etc)
● valid bit ― another bit in each page table entry:
○ valid=1 indicates that the corresponding frame is in physical memory
○ valid=0 (“invalid”) the corresponding frame is not in physical memory
○ alternative: use page-table length register (PTLR) to indicate which pages not in RAM
● any violations result in a trap to the kernel, eg.:
○ accessing page with invalid bit set → page fault
○ accessing page past the PTLR → page fault
○ trying to write to a page with read-only bit set → general protection fault

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Typical structure of page table entry
aka dirty bit
set by hardware
automatically on
aka valid/invalid bit
write access
invalid → page fault

set by hardware
various bits, eg.
automatically on
read/write/execute
any access
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Structure of the Page Table

● page tables can get huge using straight-forward methods

○ consider a 32-bit logical address space (still common), with page size of 4 KB (212)
○ page table would have to contain 1 million entries (232 / 212 = 220)
○ if each entry is 4 bytes → page table would use up 4MB of memory (homework: verify)
○ for 64-bit systems, page table can get "very" big (homework: do the math)
● solutions:
○ Hierarchical Paging
○ Hashed Page Tables
○ Inverted Page Tables
○ … stay tuned

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Summary
● address space, logical/virtual, physical
● MMU, base & limit registers
● address binding - compile- / load- / execution-time
● swapping
● free memory management
○ fixed/dynamic partitioning
○ bitmaps, linked lists
○ placement algorithms: first fit, best fit, worst fit, next fit, quick fit
● virtual memory
○ pages, frames, demand paging, page table, page fault, effective access time

Reference: 3.1 - 3.2.2, 3.3 (Modern Operating Systems)

8.1 - 8.5, 9.1 - 9.2 (Operating System Concepts)
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Review

● Name two registers used in a simple MMU implementation.

● Explain logical address / physical address.
● What is the purpose of an MMU?
● Best fit memory allocation is faster than first fit. True or False
● Virtual address space is the same as physical address space. True or False
● Page size is the same as frame size. True or False
● Define: page, frame, demand paging, page table, page fault

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Questions?

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