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Traffic light controller establishes a set of rules and instructions that drivers, pilots, train engineers, and ship captains rely on to avoid collisions and other hazards. Traffic control systems include signs, lights and other devices that communicate specific directions, warnings, or requirements. They are already mentioned that MCU, PLC and so on can be used as the hardware of traffic light controller. There are several control ways, such as neural networks, fuzzy control and etc. However, only the research and implementation of 2-phase traffic light controller was mentioned in the cited references above. While in actual application, multi-branch intersections and the case that it has obvious change of traffic flow in the same intersection on different time are commonly exist. Therefore, adjustable multi-phase intelligent traffic light controller is needed. The adaptability and applicability of the system can be strengthened if the specific phase of the traffic light controller can be chosen by the number of the intersection branches and the traffic flow. So, according to the above analysis, this paper provides the design thought of adjustable multi-phase traffic light controller based on VHDL language, and give the right simulation results by using XILINX.
Fast transportation systems and rapid transit systems are nerves of economic developments for any nation. All developed nations have a well developed transportation system with efficient traffic control on road, rail and air. Transportation of goods, industrial products, manpower and machinery are the key factors which influence the industrial development of any country. Mismanagement and traffic congestion results in long waiting times, loss of fuel and money. It is therefore utmost necessary to have a fast, economical and efficient traffic control system for national development.
The monitoring and control of city traffic is becoming a major problem in many countries. With the ever increasing number of vehicles on the road, the Traffic Monitoring Authority has to find new methods of overcoming such a problem. The measures taken are development of new roads and flyovers in the middle of the city; building of several ring such as
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DESIGN OF INTELLIGENT TLC BASED ON VHDL the inner ring road, middle ring road and outer ring road; introduction of city trains such as the light rapid transit (LRT), and monorails; restricting of large vehicles in the city during peak hours; and also development of sophisticated traffic monitoring and control systems. Growing numbers of road users and the limited resources provided by current infrastructures lead to ever increasing traveling times.
One way to improve traffic flow and safety of the current transportation system is to apply automation and intelligent control methods to roadside infrastructure and vehicles. Transportation research has the goal to optimize transportation flow of people and goods. As the number of road users constantly increases, and resources provided by current infrastructures are limited, intelligent control of traffic will become a very important issue in the future.
The problems of typical conventional traffic light Controller are mentioned below:
1.1.1 Heavy Traffic Jams
With increasing number of vehicles on road, heavy traffic congestion has substantially increased in major cities. This happened usually at the main junctions commonly in the morning, before office hour and in the evening, after office hours. The main effect of this matter is increased time wasting of the people on the road. The solution for this problem is by developing the program which different setting delays for different junctions. The delay for junctions that have high volume of traffic should be setting longer than the delay for the junction that has low of traffic. This operation is calling Normal Mode.
1.1.2 No traffic, but still need to wait
At certain junctions, sometimes even if there is no traffic, people have to wait. Because the traffic light remains red for the preset time period, the road users should wait until the light turn to green. If they run the red light, they have to pay fine. The solution of this problem is by developing a system which detects traffic flow on each road and set timings of signals accordingly. Moreover, synchronization of traffic signals in adjacent junctions is also necessary.
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DESIGN OF INTELLIGENT TLC BASED ON VHDL
1.1.3 Emergency car stuck in traffic jam
Usually, during traffic jam, the emergency vehicle, such as ambulance, fire brigade and police will be stuck especially at the traffic light junction. This is because the road users waiting for the traffic light turn to green. This is very critical problem because it can cause the emergency case become complicated and involving life.
1.1.4 Lack of Traffic Information to users
Present traffic systems fail to provide traffic information including congested roads and alternate routes available in case of congestion.
In the proposed Intelligent Traffic Light Controller (ITLC) all these limitations of existing controller are eliminated. The proposed project of ‘Intelligent Traffic Light Controller’ uses based on VHDL and has advantages of efficient control and fast response time. The problem of fixed timing traffic light is totally eliminated in this project.
Most of the present intelligent traffic lights are sensor based with a certain algorithm that controls the switching operation of the system. This approach considers the traffic to be moving smoothly and hence does not require any management or monitoring of traffic conditions.
Traffic light optimization is a complex problem. Even for single junctions there might be no obvious optimal solution. With multiple junctions, the problem becomes even more complex, as the state of one light influences the flow of traffic towards many other lights. Another complication is the fact that flow of traffic constantly changes, depending on the time of day, the day of the week, and the time of year. Roadwork and accidents further influence complexity and performance.
In practice most traffic lights are controlled by fixed-cycle controllers. A cycle of configurations is defined in which all traffic gets a green light at some point. The split time determines for how long the lights should stay in each state. Busy roads can get preference by
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DESIGN OF INTELLIGENT TLC BASED ON VHDL adjusting the split time. The cycle time is the duration of a complete cycle. In crowded traffic, longer cycles lead to better performance. The offset of a cycle defines the starting time of a cycle relative to other traffic lights. Offset can be adjusted to let several lights cooperate, and for example create green waves.
Fixed controllers have to be adapted to the specific situation to perform well. Often a table of time-specific settings is used to enable a light to adapt to recurring events like rush hour traffic. Setting the control parameters for fixed controllers is a lot of work, and controllers have to be updated regularly due to changes in traffic situation. Unique events cannot be handled well, since they require a lot of manual changes to the system. Fixed controllers could respond to arriving traffic by starting a cycle only when traffic is present, but such vehicle actuated controllers still require lots of fine-tuning.
Most research in traffic light control focuses on adapting the duration or the order of the control cycle. In our approach we do not use cycles, but let the decision depend on the actual traffic situation around a junction, which can lead to much more accurate control. Of course, our approach requests that Information about the actual traffic situation can be obtained by using different sensors or communication systems.
1.3 WHY VHDL: 1.3.1 INTRODUCTION TO VHDL:
The VHSIC Hardware Description Language (VHDL) is any industry standard language used to describe hardware from the abstract to concrete level. The language not only defines the syntax but also defines very clear simulation semantics for each language construct. It is strong typed language and is often verbose to write. Provides extensive range of modeling capabilities, it is possible to quickly assimilate a core subset of the language that is both easy and simple to understand without learning the more complex features.
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3. especially for radar 1940 . Gordon E. Claire Kilby (Texas Instruments) .Ted Hoff (Intel) .CDC 1604 1959 .10 components on 9 mm2 1959 .DESIGN OF INTELLIGENT TLC BASED ON VHDL Very Large Scale Integration – design/manufacturing of extremely small.3.Russell Ohl (Bell Laboratories) .first transistorized computer .2300 transistors on 9 mm2 Since then . complex circuitry using modified semiconductor material – – integrated circuit (IC) may contain millions of transistors.Jack St.Seymour Cray (Control Data Corporation) .first integrated circuit .first transistor 1956 Nobel Physics Prize Late 1950s . each a few mm in size applications wide ranging: most electronic logic devices 1.Robert Norton Noyce (founder. Bardeen.Shockley.first pn junction 1948 .3 WHY USE VHDL? Quick Time-to-Market o Allows designers to quickly develop designs requiring tens of thousands of logic gates o Provides powerful high-level constructs for describing complex logic o Supports modular design methodology and multiple levels of hierarchy 5 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .2 ORIGINS OF VHDL: Much development motivated by WWII need for improved electronics.continued improvement in technology has allowed for increased performance as predicted by Moore’s Law 1.purification of Si advances to acceptable levels for use in electronics 1958 . Fairchild Semiconductor) . Moore found Intel 1971 . Brattain (Bell Laboratories) .improved integrated circuit 1968 .first microprocessor (4004) .Noyce.
6 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . STRONGLY TYPED LANGUAGE. Good for ASIC Migration Allows user to pick any synthesis tool. VHDL executes statements at the same time in parallel as in Hardware. SUPPORTS SEQUENTIAL STATEMENTS. SUPPORTS FOR TEST & SIMULATION. SUPPORTS MULTIVALUED LOGIC.(almost) no manual assembly 1.1 CONCURRENCY: VHDL is a concurrent language. ranging from algorithm level to gate level Can model concurrent and sequential behaviors of digital systems Supports design hierarchy as interconnections of components Can explicitly model the timing of digital systems Integration improves the design – – – Lower parasitic = higher speed Lower power consumption Physically smaller Integration reduces manufacturing cost . verification and synthesis of digital systems Supports many levels of abstraction. complex. and powerful language for design.DESIGN OF INTELLIGENT TLC BASED ON VHDL One language for design and simulation Allows creation of device-independent designs that are portable to Multiple vendors. SUPPORTS HIERARCHIES. simulation.3. HDL differs with Software languages with respect to Concurrency only.3.4 BASIC FEATURES OF VHDL CONCURRENCY. SUPPORTS FOR VENDOR DEFINED LIBRARIES.4. or device A very verbose. 1. vendor.
3. Also gives the responses made by the DUT against specifications for correct results to ensure the functionality. the designer has to write another program known as “TEST BENCH”. 1.4.3. Different types in LHS & RHS are illegal in VHDL.4. Allows different type assignment by conversion. being composed of three lower level modules i.3.5 LEVELS OF ABSTRACTION • • • Dataflow : gate level representation Structural : hierarchically interconnected components Behavioral : algorithm level representation 7 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .3. Half-Adder and OR gate. As the case with any conventional languages.5 SUPPORTS HIRERCHIES Hierarchy can be represented using VHDL. It generates a set of test vectors and sends them to the design under test (DUT).3 SUPPORTS FOR TEST & SIMULATION To ensure that design is correct as per the specifications.2 SUPPORTS SEQUENTIAL STATEMENTS VHDL supports sequential statements also. It executes one statement at a time in sequence only.4.4.DESIGN OF INTELLIGENT TLC BASED ON VHDL 1.4 STRONGLYTYPED LANGUAGE VHDL allows LHS & RHS operators of same type. 1.3. Consider example of a Full-adder which is the top-level module. 1. 1.e.
2 SRUCTURAL LEVEL: In this style of modeling the entity is described as a set of interconnected statements.3.3. The component instantiation statement is the primary mechanism used for describing such a model of an entity. 1. as a net list. loops.3. The behavior of the entity is not explicitly apparent from its model.3 BEHAVIORAL LEVEL: The behavior of the entity is expressed using sequentially executed.DESIGN OF INTELLIGENT TLC BASED ON VHDL 1. that is. This functionality shows the flow of information through the entity. The primary mechanism for modeling the dataflow behavior of an entity is using the concurrent signal assignment statement.1 DATA FLOW LEVEL: In this style of modeling the flow of data through the entity is expressed using concurrent signal assignment statements. An entity is modeled as a set of components connected by signals. procedural code.5.5. etc. A component instantiated in a structural description must first be declared using a component declaration. blocks operate concurrently This style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. which is very similar in syntax and semantics to that of a high level programming languages such as C or Pascal. which is expressed primarily using concurrent signal assignment statements and block statements. o Can maintain state The complete process is like a “big gate” Like gates. A Dataflow model specifies the functionality of the entity without explicitly specifying its structure.5. Built from “process” blocks Each block is sequential internally o Can use variables o Can use conditionals. 1. 8 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .
A basic identifier may contain only capital ‘A’ . ‘a’ . Must not include two successive underscore characters. 1. • Single dimensional array are synthesizable. 1.3. VHDL is not case sensitive. 1.8 COMPOSITE TYPES There are two composite types ARRAY: • Contain many elements of the same type. Reserved word cannot be used as identifiers. May not end with a underscore character.6 VHDL IDENTIFIERS • • Identifiers are used to name items in a VHDL model. 9 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .3.3. • Array can be either single or multidimensional.’9’. RECORD: Contain elements of different types.’Z’ . underscore character ‘_’ • • • • • Must start with a alphabet.’z’.7 OBJECTS There are three basic object types in VHDL • Signal: represents interconnections that connect components and ports. • The synthesis of multidimensional array depends upon the synthesizer being used. The object type could be a scalar or an array. ‘0’ . • Constant: a fixed value. Process statement has a declarative part (before the keyword begin) and a statement part (between the keywords begin and end process). • Variable: used for local storage within a process. The statements appearing within the statement part are sequential statements and are executed sequentially.DESIGN OF INTELLIGENT TLC BASED ON VHDL Process statement is the primary mechanism used to model the behavior of an entity.
10 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . ‘Z’.3. ‘1’.DESIGN OF INTELLIGENT TLC BASED ON VHDL 1. ‘X’. ‘H’. ‘W’.10 SIGNAL ARRAY – A set of signals may also be declared as a signal array which is a concatenated set of signals.3. – – – This is done by defining the signal of type bit_vector or std_logic_vector. bit_vector and std_logic_vector are types defined in the ieee. ‘0’.9 THE STD_LOGIC TYPE It is a data type defined in the std_logic_1164 package of IEEE library It is an enumerated type and is defined as type std_logic is (‘U’. ‘L’. Signal array is declared as : <type>(<range>) Example: signal data1:bit_vector(1 downto 0) signal data2: std_logic_vector(7 down to 0).’-’) ‘u’ unspecified ‘x’ unknown ‘0’ strong zero ‘1’ strong one ‘z’ high impedance ‘w’ weak unknown ‘l’ weak zero ‘h’ weak one ‘-’ don’t care 1.std_logic_1164 package. signal address : std_logic_vector(0 to 15).
3.1: operators in VHDL 1.defines the interface (e. An architecture may contain: 11 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .13 ARCHITECTURE Architecture .g. Entity describes the design interface.3.3.12 ENTITY Entity .one possible implementation (or realization) of the “insides” of the “black box”. 1. inputs/outputs) to a ‘black box’ which performs a specific function. The properties of these interconnections are defined.DESIGN OF INTELLIGENT TLC BASED ON VHDL 1. The interconnections of the design unit with the external world are enumerated..11 OPERATORS: The operators used in the VHDL as list out in the table Table1.
A function has to have a return statement with an expression the value of the expression defines the result returned by the function. The mode is always in.3. 12 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Default class is constant. 1. An impure function may return different values even if the parameters are the same. 1. Process is synchronized with the other concurrent statements using the sensitivity list or wait statement. All processes in an architecture behave concurrently.3. Process repeats forever. Whereas a pure function always returns the same values as parameters. a function cannot change its argument and can only return a value. Function parameters can only be of type constant or signal. which describe the behavior in a process. Statements. Simulator takes Zero simulation time to execute all statements in a process.DESIGN OF INTELLIGENT TLC BASED ON VHDL • • • • data declarations concurrent signal assignment component instantiations process blocks Architecture defines the functionality of the entity. An architecture belongs to a specific entity. Various constructs are used in the description of the architecture. unless suspended.15 FUNCTION Unlike procedure.14 SEQUENTIALPROCESSING (PROCESS) Process defines the sequential behavior of entire or some portion of the design. It forms the body of the VHDL code. are executed sequentially.
B: in bit_vector(7 downto 1). or “10010” B: bitvec.3. ‘1’.3.2 Cutting Edge Technology • • FPGA (can be found in many systems) VHDL (1998 DOD requires all ASIC suppliers to deliver VHDL description of the ASIC and their sub components at both the behavioral level and structural level) • Put FPGA and VHDL in your resume! 13 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .188.8.131.52 Design Process: 1.16 Designing with VHDL 1. D: std_logic. Testing 3. Design entry 2. Synthesis 4. (IEEE library) 1. standard cell. or ‘0’. C: real.15.3. Testing (VHDL) (VHDL test vector simulation) (FPGA. C: integer. full custom) (logic analyzer) 1.1 Data Types Supported • • • • • • • • bit bit_vector constants bitvec integer real std_logic User defined A: in bit.DESIGN OF INTELLIGENT TLC BASED ON VHDL 1.
DSP applications) Optical Switches Has made highly sophisticated control systems mass-producable and therefore cheap 14 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .analogue or digital • It is concerned with forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor • Microprocessors – – • • • • personal computers microcontrollers Memory .DRAM / SRAM Special Purpose Processors .3.DESIGN OF INTELLIGENT TLC BASED ON VHDL 1.17 PROBLEMS IN VHDL: • • • • • • • • • No generic packages No function pointers File I/O is pretty clumsy ..ASICS (CD players.18 VLSI APPLICATIONS: VLSI is an implementation technology for electronic circuitry .3. No math library yet can use C-interface No standard package for low level simulation No support for high level simulation with message queues Arbitrary data types make user-interface a problem Just too complex! 1..
1→ Project Navigator Note: Your start-up path is set during the installation process and may differ from the one above.1. 2.1. you can access online help for additional information about the ISE software and related tools. or start ISE from the Start menu by selecting: Start → All Programs → Xilinx ISE 10.1 HOW TO CREATE A PROJECT IN XILINX 2.1. do either of the following: • Press F1 to view Help for the specific tool or function that you have selected or highlighted. It contains information about creating and maintaining your complete design flow in ISE. Figure 2. To open Help.3 Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board.2 Accessing Help At any time during the tutorial.1. 15 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . double-click the desktop icon.1: ISE Help Topics 2.1 Starting the ISE Software To start ISE.DESIGN OF INTELLIGENT TLC BASED ON VHDL 2. • Launch the ISE Help Contents from the Help menu.
2. 4... When the table is complete. 6. At the end of the next section. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 16 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Click Next to move to the device properties page. Type tutorial in the Project Name field. Leave the default values in the remaining fields. Click next to proceed to the Create New Source window in the New Project Wizard. Select File > New Project. your new project will be complete. The New Project Wizard appears. Fill in the properties in the table as shown below: ♦Product Category: All ♦ Family: Spartan3 ♦ Device: XC3S200 ♦ Package: FT256 ♦ Speed Grade: -4 ♦ Top-Level Source Type: HDL ♦ Synthesis Tool: XST (VHDL/Verilog) ♦ Simulator: ISE Simulator (VHDL/Verilog) ♦ Preferred Language: Verilog (or VHDL) ♦ Verify that Enable Enhanced Design Summary is selected. your project properties will look like the following: 7.DESIGN OF INTELLIGENT TLC BASED ON VHDL To create a new project: 1. Verify that HDL is selected from the Top-Level Source Type list. 3. 5.
Determine the language that you wish to use for the tutorial. you will create the top-level HDL file for your design. 3.1.4 Create an HDL Source In this section.2: Project Device Properties 2.1. 2. or skip to the “Creating a Verilog Source” section. 2. Click the New Source button in the New Project Wizard. 4. 5. Then.1. continue either to the “Creating a VHDL Source” section below. Verify that the Add to project checkbox is selected. Type in the file name counter. 6. Select VHDL Module as the source type. Declare the ports for the counter design by filling in the port information as shown below: 17 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Click Next.5 Creating a VHDL Source Create a VHDL source file for the project as follows: 1.DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure 2.
Click next. Click Next. and the counter displays in the Source tab.Summary dialog box to complete the new source file template. and then Finish in the New Source Wizard . The source file containing the entity/architecture pair displays in the Workspace. as shown below: 18 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . 8. then Finish.3 define module 7.DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure 2.1. then Next.
1. Place the cursor just below the begin statement within the counter architecture. Using the “+” symbol. 19 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . 5. 2. With Simple Counter selected.4: New Project in ISE 2. Close the Language Templates. This step copies the template into the counter source file. browse to the following code example: VHDL → Synthesis Constructs → Coding Examples → Counters → Binary → Up/Down Counters → Simple Counter 4. Open the Language Templates by selecting Edit → Language Templates… Note: You can tile the Language Templates and the counter file by selecting Window → Tile Vertically to make them both visible. 1.DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure 2. 3. or select the Use Template in File toolbar button. To do this you will use a simple counter code example from the ISE Language Templates and customize it for the counter design. select Edit → Use in File.6 Using Language Templates (VHDL) The next step in creating the new source is to add the behavioral description for the counter.1.
select Test Bench Wave Form as the source type. and type counter_tbw in the File Name field. Add the following line below the end process.7 Final Editing of the VHDL Source 1.1. Click Finish. 4. Click Next. statement: COUNT_OUT <= count_int. setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. You need to set the clock frequency. and name. and it displays the source directory. The test bench waveform is a graphical view of a test bench. Save the file by selecting File → Save. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Customize the source file for the counter design by replacing the port and signal name placeholders with the actual ones as follows: ♦ replace all occurrences of <clock> with CLOCK ♦ replace all occurrences of <count_direction> with DIRECTION ♦ replace all occurrences of <count> with count_int 3. 2. Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. In the New Source Wizard. 3. Select the counter HDL file in the Sources window.8 Design Simulation Verifying Functionality using Behavioral Simulation. 5. Click Next. Create a new test bench source by selecting Project → New Source. 2. 20 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Create the test bench waveform as follows: 1.1. 2. 4. 7. Add the following signal declaration to handle the feedback of the counter output below the architecture declaration and above the first begin statement: signal count_int : std_logic_vector(3 downto 0) := "0000". 6. The Summary page shows that the source will be added to the project. type.DESIGN OF INTELLIGENT TLC BASED ON VHDL 2.
2. ♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. and mixed language designs. ♦ Initial Length of Test Bench: 1500 ns. is added to the Offset value automatically. This chapter provides a brief conceptual overview of the ModelSim simulation environment. System Verilog. ♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The design requirements correspond with the values below. Basic simulation flow Project flow Multiple library flow Debugging tools 21 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .2 HOW TO CREATE A PROJECT IN MODELSIM: 2. ♦ Clock Low Time: 20 ns.2. ♦ Offset: 0 ns.DESIGN OF INTELLIGENT TLC BASED ON VHDL The requirements for this design are the following: ♦ The counter must operate correctly with an input clock frequency = 25 MHz.1 INTRODUCTION: ModelSim is a verification and simulation tool for VHDL. Verilog. ♦ Global Signals: GSR (FPGA) Note: When GSR(FPGA) is enabled. 100 ns. It is divided into fourt opics. Fill in the fields in the Initialize Timing dialog box with the following information: ♦ Clock High Time: 20 ns. ♦ Input Setup Time: 10 ns. which you will learn more about in subsequent lessons. ♦ Output Valid Delay: 10 ns.
Loading the Simulator with Your Design and Running the Simulation With the design compiled. 22 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . You can simulate your design on any platform without having to recompile your design.2. the simulation time is set to zero. and you enter a run command to begin simulation. Figure 2.1 Basic Simulation Flow . "Work" is the library name used by the compiler as the default destination for compiled design units.2 BASIC SIMULATION FLOW: The following diagram shows the basic steps for simulating a design in ModelSim. all designs are compiled into a library. you compile your design units into it.DESIGN OF INTELLIGENT TLC BASED ON VHDL 2. Assuming the design loads successfully.2.Overview Lab Creating the Working Library In ModelSim. You typically start a new simulation in ModelSim by creating a working library called "work". The ModelSim library format is compatible across all supported platforms. you load the simulator with your design by invoking the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Compiling Your Design After creating the working library.
VHDL: Copy counter.2.vhd and tcounter. 2. c. Create the working library. a. Select File > New > Library. Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows. Type work in the Library Name field (if it isn’t already entered automatically).v files from /<install_dir>/examples/tutorials/verilog/basicSimulation to the new directory. Verilog: Copy counter.v and tcounter.vhd files from /<install_dir>/examples/tutorials/vhdl/basicSimulation to the new directory. b. Click OK. Click Close. you can use ModelSim’s robust debugging environment to track down the cause of the problem.2).3 CREATE THE WORKING DESIGN LIBRARY: Before you can simulate a design. 3. 1. b. 23 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . 2.DESIGN OF INTELLIGENT TLC BASED ON VHDL Debugging Your Results If you don’t get the results you expect. you must first create a library and compile the source code into that library. Select File > Change Directory and change to the directory you created in step 1. you will see the Welcome to ModelSim dialog. Upon opening ModelSim for the first time. This opens a dialog where you specify physical and logical names for the library (Figure 2.2. a. We’ll be doing the former. Create a new directory and copy the design files for this lesson into it. You can create a new library or map to an existing library. Start by creating a new directory for this exercise (in case other users will be working with these lessons). Start ModelSim if necessary.
ini). work Library in the Workspace 24 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . The _info file must remain in the directory to distinguish it as a ModelSim library. Do not edit the folder contents from your operating system.DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure 2.3.3) and records the library mapping for future reference in the ModelSim initialization file (modelsim.2. Figure 2.2. ModelSim also adds the library to the list in the Workspace (Figure 2. all changes should be made from within ModelSim.2 The Create a New Library Dialog ModelSim creates a directory called work and writes a specially-formatted file named _info into that directory.2.
2. If so. a.2.DESIGN OF INTELLIGENT TLC BASED ON VHDL When you pressed OK in step 3c above. The files are compiled into the work library. Many command-line equivalents will echo their menu-driven functions in this fashion.v.4). Select both counter.v modules from the Compile Source Files dialog and click Compile. 1. Figure 2.v and tcounter. click Done. This opens the Compile Source Files dialog (Figure 2. If the Compile menu option is not available. You can compile by using the menus and dialogs of the graphic interface. 2. you probably have a project open.4 COMPILE THE DESIGN: With the working library created. When compile is finished. you are ready to compile your source files. Select Compile > Compile. b.v and tcounter. Compile counter. close the project by making the Workspace pane active and selecting File > Close from the menus. c. the following was printed to the Transcript: vlib work vmap work work These two lines are the command-line equivalents of the menu selections you made.4 Compile Source Files Dialog 25 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . or by entering a command at the ModelSim> prompt. as in the Verilog example below.2.
2. You will also see a tab named Files that displays all files included in the design.DESIGN OF INTELLIGENT TLC BASED ON VHDL 2.2. Entities. b. You can also load the design by selecting Simulate > Start Simulation in the menu bar. Load the test_counter module into the simulator. Figure 2. 26 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . With the Design tab selected.) and the path to the underlying source files (scroll to the right if necessary). View the compiled design units. you will see a new tab in the Workspace named sim that displays the hierarchical structure of the design (Figure 2. Double-click test_counter to load the design. click the ‘+’ sign next to the work library to show the files contained there.2. Select the test_counter module and click OK (Figure 2.6). This opens the Start Simulation dialog.5 LOAD THE DESIGN: 1. You can navigate within the hierarchy by clicking on any line with a ’+’ (expand) or ’-’ (contract) icon. click the ’+’ sign next to the work library to see the counter and test_counter modules. click the ’+’ icon next to the work library and you will see two design units (Figure 2.5). When the design is loaded. You can also see their types (Modules.7).2. In the Workspace. a. etc. On the Library tab.2.5 Verilog Modules Compiled into work Library 2. a.
you will see a new tab in the Workspace named sim that displays the hierarchical structure of the design (Figure 2.7 Workspace sim Tab Displays Design Hierarchy 27 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .7).6 Loading Design with Start Simulation Dialog When the design is loaded.2.2.DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure 2. You will also see a tab named Files that displays all files included in the design.2. Figure 2. You can navigate within the hierarchy by clicking on any line with a ’+’ (expand) or ’-’ (contract) icon.
Open the View menu and select Objects.6 RUN THE SIMULATION: Now you will open the Wave window. To see a list of the other debugging windows. You can also use the View > Wave menu selection to open a Wave window. registers. Select Add > Add All Signals to Wave (Figure 2. b.2. 28 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Add signals to the Wave window.8 Object Pane Displays Design Objects You may open other windows and panes with the View menu or with the view command. generics. Figure 2. constants and variables not declared in a process. Right-click test_counter to open a popup context menu. In the Workspace pane. nets. select the sim tab.2. a.9). add signals to it. select the View menu. Enter view wave at the command line. Data objects include signals. The Wave window is one of several windows available for debugging. Window panes within the Main window can be zoomed to occupy the entire Main window or undocked to stand alone. and parameters. You may need to move or resize the windows to your liking. 2. a. 1. The command line equivalent is: view objects The Objects pane (Figure 2. Open the Wave debugging window.2. c.DESIGN OF INTELLIGENT TLC BASED ON VHDL 2.8) shows the names and current values of data objects in the current region (selected in the Workspace).2. then run the simulation. 2. a. View design objects in the Objects pane.
Figure: 2. Run the simulation. 29 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Click the Run icon in the Main or Wave window toolbar.2. The simulation runs for 100 ns (the default simulation length) and waves are drawn in the Wave window. Enter run 500 at the VSIM> prompt in the Main window. Figure: 2. b.2. a. Click the Run -All icons on the Main or Wave window toolbar.9. The simulation advances another 500 ns for a total of 600 ns (Figure 2.10 Waves Drawn in Wave Window c. Using the Popup Menu to Add Signals to Wave Window 3.10).DESIGN OF INTELLIGENT TLC BASED ON VHDL All signals in the design are added to the Wave window.2.
Figure: 2.g.11 the Main Window 30 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .7 MAIN WINDOW: The Main window is composed of a number of "panes" and sub-windows that display various types of information about your design. The simulation stops running.DESIGN OF INTELLIGENT TLC BASED ON VHDL The simulation continues running until you execute a break command or it hits a statement in your code (e.g. Click the Break icon.2.. a Verilog $stop statement) that halts the simulation. simulation. the Dataflow window). You can also access other tools from the Main window that display in stand-alone windows (e. or debugging session. 2.2.. d.
1 The Main Window 31 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Table 2.2.DESIGN OF INTELLIGENT TLC BASED ON VHDL The following table describes some of the key elements of the Main window.
Both master and slave branches have the LEDs to display the countdown of running light. According to the different phase. When the hold signal is effective. the controller continue to run with former state. VARIABLE MULTI-PHASE TRAFFIC LIGHT CONTROLLER DESIGN AND ANALYSIS 3. This controller has reset and hold input signals. In 3-phase operation mode. 2phase. Both master and slave branches have green. In 4-phase operation mode. 3. The durations of all kinds of lights are variable.1 WHOLE DESIGN THROUGH: The intelligent traffic light controller this paper provides can be applied both in common intersections and multiple branches intersections.DESIGN OF INTELLIGENT TLC BASED ON VHDL 3. When the reset signal is invalid. but only green. this system provides their operation modes as shown in Figure 3. the left-hand turn light of the master and slave branches choose to shows 32 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . the controller began to run with the new settings. all lights extinguish and all the LEDs show noting both in master and slave branches. When the reset signal is valid. red and yellow lights work in slave branch. green. Meanwhile. all the lights work in master and slave branches. yellow and left-hand turn lights. the specific times are set by external input pins. green. When it comes to 2-phase operation mode. red and yellow lights work both on master and slave branches. When the hold signal is ineffective. yellow. red. 3-phase and 4-phase play important roles in practical traffic control. therefore.1. all the LEDs remain unchanged and all the red lights work both on master and slave branches. yellow and left-hand turn lights work on master branch.2 ANALYSIS OF THE RUNNING STATE: In actual traffic control. red. It needs to design external input pins on the controller in order to realize the aim of adjusting multi-phase based on actual traffic flow. the controller receives the settings of running time and phase number. red lights work in turn circularly. green.
33 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . all the signals of traffic lights both on master and slave branches are generated by the main controller. all traffic lights run as the modes shown in Figure 3. Generally speaking. Usually. the transition control can be achieved by finite state machine. The chart of system structure is shown in Figure 3. Both the LEDs on master and slave branches display the remaining running time in countdown form. the countdown numbers are provided and sent to LED display controller. Meanwhile. Figure 3. Benchmark clock of the system is provided by the external circuit. the total durations of green. left-hand turn and yellow light equal to the duration of red light. the sum time of green.1. the duration of red light is the longest.DESIGN OF INTELLIGENT TLC BASED ON VHDL between green and yellow lights. Main controller is the core of the system. left-hand turn and yellow lights equals to the red light’. According to different value of phase selection.3 STRUCTURE OF THE SYSTEM: The main functions components of the system are traffic lights controller.1. Multi-phase operation modes 3.2. For the convenience of programming and debugging. All the lights both on the master and slave branches are timed for the S unit. countdown controller and LED display controller.
and output signals such as traffic light control signals. the system is divided into two hierarchies. The main controller realized by the top module includes those input signals such as benchmark clock signal. It is sub-modules that realize traffic light control and LED display of countdown.3. phase selection signal. Figure 3. time setting signal. countdown signals and so on. Structure of Hierarchical Design 34 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure 3. top module and sub-modules. Structure of the system 3.2.3. as shown in Figure 3. hold signal and reset signal.4 HIERARCHICAL DESIGN THOUGHT: For programming convenience by VHDL language.
4 : component diagram 35 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .DESIGN OF INTELLIGENT TLC BASED ON VHDL COMONENT DIAGRAM: Figure3.
Red_w (red west)-‘1’. Red_w (red west)-‘1’. Traffic starts from the south direction. left & straight paths are free for traffic. west. Same flow is repeated for all four paths. Red_n (red north)-‘1’. DESIGN DESCRIPTION: 4. right. Le (left east)-‘1’.DESIGN OF INTELLIGENT TLC BASED ON VHDL 4. Pe_r (pedestrian east red)-‘1’. Ps_r (pedestrian south red)-‘1’. (South. in yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for traffic. In yellow2 phase only yellow lights will be “ON”. west. Initially the red light of all the directions is ON.1 ALGORITHM: Initially all red lights will be “ON” (south. Pn_r (pedestrian north red)-‘1’. Rs (right south)-‘1’. The signals that are ON now are: Ls (left south)-‘1’. Red_e (red east)-‘1’. Green lights of will be”ON”. To start the traffic light controller 1. east. Ss (straight south)-‘1’. now are Is (left south)-‘1’. Similarly when orange light of south direction is ON then the signals that are ON. Yellow phase is split as yellow1 & yellow2. hence the green light of south direction goes ON. Pw_r (pedestrian west red)-‘1’. Le (left east)-‘1’. pedestrian). 2. 36 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . east). north. north. Ys (yellow south)-‘1’.
Similarly when red light of south direction is ON then the signals that are ON. Pe_r (pedestrian east red)-‘1’.now are Ls (left south)-‘1’. Pe_r (pedestrian east red)-‘1’. During this time all ways are blocked for 1 second except left south (is-‘1’) and so on.DESIGN OF INTELLIGENT TLC BASED ON VHDL Red_n (red north)-‘1’. 37 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Pw_r (pedestrian west red)-‘1’.e. After that it goes clockwise for all direction (i. Red_w (red west)-‘1’. Red_e (red east)-‘1’. Pn_r (pedestrian north red)-‘1’. Red_e (red east)-‘1’.:-south then west then north then east) similarly. Pn_r (pedestrian north red)-‘1’. Ps_r (pedestrian south red)-‘1’. Red_n (red north)-‘1’. Pw_r (pedestrian west red)-‘1’. Ps_r (pedestrian south red)-‘1’.
in yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for traffic. right.DESIGN OF INTELLIGENT TLC BASED ON VHDL 4. (South. Same flow is repeated for all four paths. east.1: flow chart for traffic light contoller Initially all red lights will be “ON”(south. Yellow phase is split as yellow1 & yellow2. east). west. 38 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . north. north. In yellow2 phase only yellow lights will be “ON”. Green lights of will be “ON”. left & straight paths are free for traffic. pedestrian).2 FLOW CHART: Figure 4. west.
State diagrams require that the system described is composed of a finite number of states. sometimes. which differ slightly and have different semantics. Figure 4.3 STATE TRANSITION CHART: A state diagram is a type of diagram used in computer science and related fields to describe the behavior of systems. There are many forms of state diagrams.2: State transition chart for traffic light controller 39 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . this is indeed the case. while at other times this is a reasonable abstraction.DESIGN OF INTELLIGENT TLC BASED ON VHDL 4.
Pn_r (pedestrian north red). The output signals are used are: Ls (left south). Red_s (red south).1 RESULTS: 5. Same flow is repeated for all four paths (south. Yn (yellow north). Pw_g (pedestrian west green) Pn_g (pedestrian north green). Red_w (red west). In yellow2 phase only yellow lights will be “ON”. ln (left north). Se (straight east). Rs (right south). Yellow phase is split as yellow1 & yellow2. right.DESIGN OF INTELLIGENT TLC BASED ON VHDL 5. Rn (right north). east and pedestrian) as shown in the figure below. The input signals which are used are clk and rst.1. left & straight paths are free for traffic.1 Out put of Traffic Llight Controller Initially all red lights will be “ON” (south. Red_n (red north) Red_e (red east). west. and east). Pw_r (pedestrian west red). Sn (straight north). in yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for traffic. north. Yw (yellow west) and Ye (yellow east) 40 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Rw (right west). Green lights of will be”ON”. west. Ys (yellow south). Re (right east). lw (left west). Ps_g (pedestrian south green). Le (left east). north. Pe_g (pedestrian east green). Ps_r (pedestrian south red). Pe_r (pedestrian east red). Sw (straight west). Ss (straight south).
41 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .DESIGN OF INTELLIGENT TLC BASED ON VHDL Contd…….
1: Output waveform of traffic light controller 42 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure5.
Figure 5.2: top level symbol 43 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .2 Circuits obtained from code: The following are the circuits obtained by generating the code using XILINX.2 gives the list of inputs and outputs used & Figure 5.1.3 gives the detailed circuit Figure 5.DESIGN OF INTELLIGENT TLC BASED ON VHDL 5.
3: circuit model obtained by XILINX 44 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .DESIGN OF INTELLIGENT TLC BASED ON VHDL Figure 5.
Through the traffic light interface module we can implement this as a real time TLC system. and simulating with XILINX. 3-phase and 4.DESIGN OF INTELLIGENT TLC BASED ON VHDL 5. FUTURE SCOPE: Traffic light controller is implemented on SPARTAN-3 TRAINER using traffic light interface module. programming with VHDL language. This design thought can reduce the design cycle. The controller can be made into embedded circuit board to satisfy the need to update the valve of control phase according to the actual traffic flow in city's traffic intersections. 45 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING .2 CONCLUSIONS: The variable multi-phase (2-phase. improve the reliability and flexibility. There are simple rules for traffic lights on one mode.phase) intelligent traffic light controller can be realized by establishing system model. and complex ways of regulating a whole infrastructure of them. It is necessary to adjust general algorithms. The improvement of town traffic condition is largely dependent on the modern ways of traffic management and control. Simple dumped the whole program code of “DESIGN OF INTELLIGENT TRAFFIC LIGHT CONTROLLER BASED ON VHDL” in the SPARTAN-3 TRAINER kit. Advanced traffic signal controllers and control system contribute to the improvement of the traffic problem. The intelligent of traffic signal controller is introduced in this project with powerful functions.
(1992). No.19. pp. 2003. VSP BV Utrecht.1999.wakerly_3rd edition.4.  Baoxia Cui. pp. A distributed approach to optimized control of street traffic signals. Chunfeng Xu.  Hong Y S.“New electro sensitive traffic light using fuzzy neural network ”.36-38. Pergamon Press (1991). Olsder : The maxplus algebra applied to synchronization of traffic light processes.  M. 8. Instrument Technique and Sensor. 2008. 6.  Digital design principles and practices-john F. No. Computer Technology and Development. Yu Zhen. 6.  M. Hyunsoo J.J. Patriksson: The traffic assignment problem : models and methods. Zhiyong Liu. “Application of Fuzzy Control Intelligent Traffic Lights Monitoring System”. Pergamon Press (1991). Journal of Shenyang University of Technology.  Zhongsu Wang. CHENYan-ping. Editor M.  Haiying Zhang. 3.2007. Vol. Vol. (1994).3 BIBLOGRAPHY  Huancheng Liu. J. 5. “Application of PLC in the City Traffic Light Control System”.DESIGN OF INTELLIGENT TLC BASED ON VHDL 5.  N. Papageorgiou.-J. Papageorgiou.  R. pp: 181-183. Noirmoutier (1998). Instrument Technique and Sensor. Ji-ping Yang. 1992] Findler.  [Findler and Stapp. pp.B.759-767. and Stapp. H.2003 Vol. “New strategy in optimization of urban traffic signal timing controller”. 387-391 in concise encyclopedia of Traffic and Transportation Systems. 400408 in concise encyclopedia of Traffic and Transportation Systems.Microprocessors System Based Traffic Signal Controller”. Editor M. Fuzzy Systems IEEE Transactions Digital Object Identifier. 29. Actes de la 26`eme ´ecole de printemps d’informatique th´eorique. 18. van Egmond and G. Journal of Transportation Engineering.15. 46 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . Vol. Gartner: Road Traffic Control: Progression Methods p. Hounsel : Road Traffic Control : TRANSYT and SCOOT p. “A New Kind Of Multi. pp: 554557. 118-1:99–110. Vol. N. No. McDonald and N.
” Federal Highway Administration Publication No.com  www. Inc.gmvhdl.  Obenberger.  VHDL Language Reference Manual. Washington. Kraft.vhdl. Ranganathan  Fuzzy System Handbook by Cox  VHDL Analyzer User's Manual. 1987. Wen  IDUTC: An Intelligent Decision-Making System for Urban Traffic-Control Applications by M.org  en. J. “Surface Transportation Systems: The Role of Traffic Management Centers. Intermetrics..H. Inc.IEEE.org  www.  www. Intermetrics.wikipedia. 1987. Intermetrics.  VHDL Simulator User's Manual. D.com 47 KONERU LAKSHMAIAH COLLEGE OF ENGINEERING . January 2002.” ITS America.org  www. Inc..DESIGN OF INTELLIGENT TLC BASED ON VHDL  “Intelligent Transportation Systems in the Transportation Equity Act for the 21st Century. 1987. FHWA-jpo-99-040..”  A dynamic and automatic traffic light control expert system for solving the road congestion problem by W.sciencedirect.doulos. and W.C. Patel and N.  “National ITS Program Plan: A Ten-Year Vision...com  http://www.
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