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Control Logic Design and Algorithms

The document discusses various methods for designing control logic for digital logic and computer systems, including: 1) Using one flip-flop per state in a sequential register and decoder method to control a system. 2) Implementing control logic using a PLA to determine the next state and outputs based on the current state and inputs. 3) Developing a control state diagram and micro-operations sequence for an A/B register data processor that performs addition and subtraction using a sign-magnitude algorithm.

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Md. Sarafat Ayon
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67 views29 pages

Control Logic Design and Algorithms

The document discusses various methods for designing control logic for digital logic and computer systems, including: 1) Using one flip-flop per state in a sequential register and decoder method to control a system. 2) Implementing control logic using a PLA to determine the next state and outputs based on the current state and inputs. 3) Developing a control state diagram and micro-operations sequence for an A/B register data processor that performs addition and subtraction using a sign-magnitude algorithm.

Uploaded by

Md. Sarafat Ayon
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Control Logic Design

Digital Logic and Computer Design by


Mano
Section: 10.1-10.3, 10.6, 10.4
Lecturer: Md. Tawkat Islam Khondaker
Control Logic
One FF per State
Sequential Register & Decoder Method
PLA Control
Equipment Configuration
A/B
registers As / Bs A/B
n bits
SIGNED
numbers 1 bit n -1 bits
Derivation of the Algorithm
When two numbers A and B are added or
subtracted, eight possible combinations can
occur:
1. (+A) + (+B) 5. (+A) – (-B)
2. (+A) + (-B) 6. (+A) – (+B)
3. (-A) + (+B) 7. (-A) – (-B)
4. (-A) + (-B) 8. (-A) – (+B)
These eight combinations can be expressed as:
(±A) ± (±B)
Derivation of the Algorithm
Flowchart of Sign-Magnitude Add/Sub
Data Processor
Control Block Diagram
Control State Diagram
Control State Diagram

In T4: E = Cout is NOT executed until a clock pulse. But after the clock pulse, it goes
to T5 state. So E SHOULD BE CHECKED at T5 state.
Control State Diagram
Flowchart can result in a different state diagram as long as it follows the hardware
constraints and the system functions according to the specification.
For example, we can check Cout at T4 state instead of checking E at T5:
If Cout = = 1: Clear E @ T5 state
If Cout = = 0: Go directly to T6 state
Sequence of Micro-operations
Design of Hard-wired Control
Hard-Wired Control (Multiplication)
(Sec: 10.6)
Statement of the Problem
If last bit of Multiplier is 1: Add Multiplicand with the partial product and Right Shift
the partial product

If last bit of Multiplier is 1: Just Right Shift the partial product.


Equipment Configuration
A/B
registers As / Bs A/B
n bits
SIGNED
numbers 1 bit k = n -1 bits
Derivation of the Algorithm
Flowchart for Binary Multiplication
Control State Diagram for Multiplication
Data-Processor Specification
Hard-wired Control
with JK FF
Hard-wired Control
with JK FF
Micro-Program Control
The Microprogram
Micro-Program
Hardware Configuration
The Microprogram

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