Copyright © 2023 NR. All rights reserved.

NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR
trademarks may be used without written permission. NR products appearing in this document may
be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and benefits
afforded under P.R. China and international copyright and patent laws in its products, including but
not limited to software, firmware and documentation. NR Engineering Co., Ltd. is licensed to use
this document as well as all intellectual property rights owned or held by NR Electric Co., Ltd,
including but not limited to copyright, rights in inventions, patents, know-how, trade secrets,
trademarks and trade names, service marks, design rights, database rights and rights in data, utility
models, domain names and all similar rights.

The information in this document is provided for informational use only and does not constitute a
legal contract between NR and any person or entity unless otherwise specified. Information in this
document is subject to change without prior notice.

To the extent required the products described herein meet applicable IEC and IEEE standards, but
no such assurance is given with respect to local codes and ordinances because they vary greatly.

Although every reasonable effort is made to present current and accurate information, this
document does not purport to cover all details or variations in equipment nor provide for every
possible contingency to be met in connection with installation, operation, or maintenance. Should
further information be desired or should particular problems arise which are not covered sufficiently
for your purposes, please do not hesitate to contact us.
 Preface

Preface

About This Manual

The technical manual describes the protection, automation, control, and supervision functions of
PCS S series device for line distance protection, and contains operation principle descriptions, and
lists function blocks, logic diagrams, input and output signals, setting parameters and technical
data, sorted per function, as well as the hardware of the device. The manual can be used as a
technical reference during the engineering phase and during normal service. In addition, the
manual also includes a glossary that lists and defines technical terms used throughout the manual.

Product Documentation Set

The intended use of manuals throughout the product lifecycle is shown in the figure below.

The datasheet (DS) contains describes the control, protection, measurement and supervision
functions with the information of relevant hardware for the device.

The selection guide (SLG) contains the explanation about the application option, the firmware
option, the software option, the hardware option and etc., and is instructive about how to order the

PCS-902S Line Distance Relay I

Date: 2023-08-01
Preface

device based on expected configurations.

The technical manual (TM) contains operation principle descriptions, and lists function blocks,
logic diagrams, input and output signals, setting parameters and technical data, sorted per function.
The manual can be used as a technical reference during the engineering phase, installation and
commissioning phase, and during normal service.

The application manual (AM) contains application descriptions and instructions on how to
engineer the device using the configuration tool PCS-Studio. The manual can be used to find out
when and for what purpose a typical protection function can be used. The manual also recommends
a sequence for the engineering of protection, control, measurement and supervision functions, HMI
functions as well as communication engineering.

The communication protocol manual (CPM) describes the communication protocols supported
by the device. The manual concentrates on the vendor-specific implementations.

The operation and commissioning manual (OCM) contains instructions on how to operate and
commission the device. The manual describes how to identify disturbances and how to view
calculated and measured power grid data to determine the cause of a fault. The manual also
describes the process of testing the device in a substation which is not in service.

The installation and maintenance manual (IMM) contains instructions on how to install, maintain
and disposal the device. The manual provides procedures for mechanical and electrical installation,
lifecycle maintenance and repairing, and scrap disposal when decommissioning.

The cybersecurity manual (CM) describes the process for handling cyber security when
communicating with the device. Certification, Authorization with role-based access control, and
product engineering for cyber security related events are described and sorted by function. The
guideline can be used as a technical reference during the engineering phase, commissioning phase,
and during normal service.

The settings guide (STG) contains instructions on how to calculate the device's settings of various
functions (including the protection, automation, control, and supervision functions) according to the
different system parameters and fault conditions.

Safety Information
This manual is not a complete index of all safety measures required for operation of the equipment
(module or device). However, it comprises important information that must be followed for personal
safety, as well as to avoid material damage. Information is highlighted and illustrated as follows
according to the degree of danger:

Indicates an imminently hazardous situation that, if not avoided, will

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, could

result in death or serious injury.

II PCS-902S Line Distance Relay

Date: 2023-08-01
 Preface

Indicates a potentially hazardous situation that, if not avoided, may

result in minor or moderate injury or equipment damage.

Indicates that property damage can result if the measures specified are

not taken.

Important information about the device, product handling or a certain

section of the documentation which must be given particular attention.

Instructions and Warnings

The following hazard statements apply to this device.

Disconnect or de-energize all external connections BEFORE opening this

device. Contact with hazardous voltages and currents inside this device can
cause electrical shock resulting in injury or death.

Contact with instrument terminals can cause electrical shock that can result
in injury or death.

Use of this equipment in a manner other than specified in this manual can
impair operator safety safeguards provided by this equipment.

Have only qualified personnel service this equipment. If you are not qualified
to service this equipment, you can injure yourself or others, or cause
equipment damage.

This device is shipped with default passwords. Default passwords should

be changed to private passwords at installation. Failure to change each
default password to a private password may allow unauthorized access. NR
shall not be responsible for any damage resulting from unauthorized access.

PCS-902S Line Distance Relay III

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Preface

DO NOT look into the fiber (laser) ports/connectors.

DO NOT look into the end of an optical cable connected to an optical output.

DO NOT perform any procedures or adjustments that this instruction

manual does not describe.

During installation, maintenance, or testing of the optical ports, ONLY use

the test equipment qualified for Class 1 laser products!

Incorporated components, such as LEDs, transceivers, and laser emitters,

are NOT user serviceable. Return units to NR for repair or replacement.

Equipment components are SENSITIVE to electrostatic discharge (ESD).

Undetectable permanent damage can result if you do not use proper ESD
procedures. Ground yourself, your work surface, and this equipment
BEFORE removing any cover from this equipment. If your facility is not
equipped to work with these components, contact NR about returning this
device and related NR equipment for service.

Insufficiently rated insulation can deteriorate under abnormal operating

conditions and cause equipment damage. For external circuits, use wiring
of SUFFICIENTLY RATED insulation that will not break down under
abnormal operating conditions.

SEVERE power and ground problems can occur on the communications

ports of this equipment as a result of using non-standard cables. Use the
wiring method recommended in the manual for communication terminals.

IV PCS-902S Line Distance Relay

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 Preface

DO NOT connect power to the relay until you have completed these
procedures and receive instruction to apply power. Equipment damage can
result otherwise.

Use of controls or adjustments, or performance of procedures other than

those specified herein, may RESULT IN hazardous radiation exposure.

The firmware may be upgraded to add new features or enhance/modify

existing features, please MAKE SURE that the version of this manual is
compatible with the product in your hand.

Document Conventions

⚫ The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The
Glossary also contains definitions of important terms.

⚫ Menu path is connected with the arrow "→" and bold.

For example: the access path of protection settings is: MainMenu→Settings→Protection

Settings

⚫ Settings not in the table should be placed in brackets.

For example: the system setting [Opt_SysFreq]

⚫ Cross-references are presented in italics.

For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1

⚫ Binary input signals, binary output signals, analogues, LED lights, buttons, and other fixed
meanings, should be written in double quotes and bold.

For example: press the button "ENT".

Symbols

PCS-902S Line Distance Relay V

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Preface

AND Gate OR Gate

& & & >=1 >=1 >=1

2 inputs 3 inputs 4 inputs 2 inputs 3 inputs 4 inputs

OR Gate Comparator

>=2

2-out-of-3 2 inputs

Logic Input

BI xxx SIG xxx

Binary signal Input Signal input
SET xxx EN xxx
Setting input Enable input

Timer

10ms 2ms 0ms [Tset2]

Fixed delay pickup (10ms), fixed Fixed delay pickup, settable

delay dropout (2ms) delay dropout

[Tset1] 0ms [Tset1] [Tset2]

Settable delay pickup, fixed delay Settable delay pickup, settable

dropout delay dropout
Timer
t
t

Optional definite-time or inverse-

time characteristics

VI PCS-902S Line Distance Relay

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 Preface

Primary Equipment

G M 52

Generator Motor Circuit breaker Disconnector

2-windings 3-windings Auto-

Reactor Capacitor
Transformer Transformer transformer
3CT
*
3VT

Current Voltage
Earth Bus
transformer transformer

Phase Label Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN, YN, BN
ABC L123 RYB
U (voltage) V U

Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2

Warranty

NR can provide up to 10-year warranty for this product. For warranty details, please consult the
manufacturer or agent for more information.

PCS-902S Line Distance Relay VII

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Preface

Document Structure

This manual is a comprehensive work covering the theories of protection, control, supervision,
measurement, etc. and the structure & technical datas of relevant hardwares. Read the sections
that pertain to your application to gain valuable information about using the device. To concentrate
on the target sections of this manual as your job needs and responsibilities dictate. An overview of
each manual section and section topics follows.

1 Introduction
Introduces features, summarizes functions and applications of the device.

2 Technical Data
Lists device specifications, type tests, and ratings.

3 Protection Functions
Describes the function of various protection elements, gives detailed specifics on protection
scheme logic, provides the relevant logic diagrams.

4 Control Functions
Describes the logic for the control of up to 15 disconnectors and 2 circuit breakers, synchronism
check for manual closing and voltage selection logic for different application scenario.

5 Measurement
Provides information on viewing fundamental and rms metering quantities for voltages and currents,
as well as power and energy metering data.

6 Supervision
Describes self-supervision technique to help diagnose potential difficulties should these occur and
includes the list of status notification messages. Provides a troubleshooting chart for common
device operation problems.

7 System Functions
Describes how to perform fundamental operations such as clock synchronization, communicating
with the device, switching active setting group, checking relay status, reading event reports and
SER (Sequential Events Recorder) records.

8 Hardware
Describes the hardware structure, typical wiring and CT requirements of the device, and provides
general technical information on the plug-in modules, including pin or interface definition, view and
function description.

9 Settings
Provides a list of all settings and their ranges, unit, steps, defaults. The organization of the settings
is similar to the settings organization in the device and in the configuration tool (PCS-Studio).

VIII PCS-902S Line Distance Relay

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 Preface

Appendix A Glossary
Describes the abbreviations adopted in this manual.

Document Revision History

PN: ZL_PCS-902S_X_Technical Manual_EN_Overseas General_X

Current version: R1.72

Corresponding Version Release

Description of change
Document Software Date

R1.00 R1.00 2019-01-24 ⚫ Form the original manual

⚫ Add stub differential protection

⚫ Add switchgear position verification

⚫ Add the description about digital substation application

⚫ Add the description about digital interface

⚫ Add technical data of GOOSE and SV

⚫ Add certifications of IEC 61850, DNP, PRP, HSR, IEEE

1588

⚫ Add alarm signals of GOOSE and SV

⚫ Delete switching setting group by input signals

⚫ Add NET-DSP plug-in module (NR6612B)

R1.10 R1.12 2019-11-25
⚫ Add SV communication settings

⚫ Add label settings

⚫ Add GOOSE send links and receiving links

⚫ Add SV links

⚫ Add CPU plug-in module, NR6106AC and related technical

data of optical fiber channel (wave length 1550nm)

⚫ Add typical application of single circuit breaker (double

busbars)

⚫ Add out-of-step protection

⚫ Modify the logic of automatic reclosing and add the related

PCS-902S Line Distance Relay IX

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Preface

settings

⚫ Add general communication settings: [IP_SyslogServer01],

[IP_SyslogServer02], [IP_SyslogServer03],

[IP_SyslogServer04]

⚫ Add three-phase current element, three-phase voltage

element and single-phase current element

⚫ Modify the description about switching setting groups via

binary inputs

⚫ Modify the technical data of breaker failure protection and

broken conductor protection

⚫ Add the technical data of transfer trip

⚫ Add CPU plug-in module (NR6106AK)

⚫ Modify the technical data of device′s power consumption

⚫ Modify the lower limit of the settings [VTS.t_DPU] and

[VTS.t_DDO]

⚫ Add synchrophasor measurement function

⚫ Modify the logic of distance protection

⚫ Modify the logic of VT circuit supervision

⚫ Modify I/O signals of switchgear control, synchronism

check and voltage selection

⚫ Add the description of base phase angle for angle value in

measurements

⚫ Modify the terms of "Energy Metering"

⚫ Modify the terms of "Energy Metering Settings"

⚫ Modify the technical data of binary input

⚫ Modify the description about switchgear trip counter

⚫ Modify the technical data of power supply

⚫ Delete the technical data of BNC port

⚫ Modify the operating time delay accuracy of negative-

X PCS-902S Line Distance Relay

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 Preface

sequence overvoltage protection and residual overvoltage

protection

⚫ Modify the operating time delay accuracy and dropout ratio

of breaker failure protection

⚫ Modify the dropout ratio of broken conductor protection

⚫ Modify the setting range of the setting [85.U_UV_WI]

⚫ Modify the logics of breaker failure protection and pole

discrepancy protection

⚫ Modify the logic of enabling distance protection

⚫ Modify the technical data of synchrophasor communication

⚫ Modify the technical data of protection class for front side

2020-01-22
⚫ Modify the description about remote control mode

⚫ Update the terms of reclosing

⚫ Modify the technical data of dropout time accuracy of

negative-sequence overvoltage protection and residual

overvoltage protection

⚫ Modify the explanation of the settings [Prot.U1n],

[Prot.U2n], [UB1.Syn.U1n], [UB1.Syn.U2n],

R1.11 R1.12
2020-02-19 [UL2.Syn.U1n], [UL2.Syn.U2n], [UB2.Syn.U1n]

[UB2.Syn.U2n], [CBx.25.Opt_ValidMode],

[Prot.Opt_CT_Measmt], [Prot.CB1.Opt_CT_Measmt] and

[Prot.CB2.Opt_CT_Measmt]

⚫ Add the information about the settings [MMTR.U2n] and

[MMTR.I2n]

⚫ Update current and voltage connection examples

2020-02-27 ⚫ Add output signal of transfer trip, "TT.BlkAR", and related

logic

⚫ Delete GOOSE communication settings

R1.20 R1.20 2020-06-01
⚫ Modify the logic of earth fault protection

PCS-902S Line Distance Relay XI

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⚫ Modify the logic of negative-sequence overcurrent

protection

⚫ Add the description about CT circuit failure blocking earth

fault protection and negative-sequence overcurrent

protection

⚫ Delete stage 5 and stage 6 of overfrequency protection,

underfrequency protection and frequency rate-of-change

protection

⚫ Modify the logics of AR

⚫ Modify the logic of reclosing numbers control

⚫ Modify the logics of switchgear control and DPS alarm

⚫ Modify the logic of dead check

⚫ Modify the description and sequence chart of jitter

processing

⚫ Modify the technical standard of power supply

⚫ Update PMU

⚫ Add thermal overload protection

⚫ Modify the logic of sending permissive signal in current

differential protection

⚫ Add CPU module (NR6106AQ) and IO module (NR6661A)

⚫ Modify the logics of pilot distance protection (POTT,

Blocking) and pilot directional earth-fault protection (PTT,

Blocking)

⚫ Add the settings: [85.En_Op_Ctrl_Send],

[85.En_PilotOp_Ctrl_Send], [85.En_52b_Ctrl_Send]

[85.En_52b_Echo] in "Pilot Scheme Settings"

⚫ Add the settings, [21L.PilotFwd.ZP.En_NegDir_Blk],

[21L.PilotFwd.ZG.En_NeuDir_Blk],

[21L.PilotFwd.ZG.En_NegDir_Blk] in "DistProt Settings"

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⚫ Revise CT requirement

⚫ Add the alarm signal "Alm_GOOSETest"

⚫ Add the alarm signal "P1.Fail_Board"

⚫ Add the setting [TT.En_CB_Ctrl]

⚫ Modify the logic of transfer trip

⚫ Add the status indication of LED "ALARM" and

explaination of configurable characteristics for all alarm

signals

⚫ Add CPU module, NR6106AR

⚫ Add BO module, NR6663A

⚫ Update the diagrams of typical applications

⚫ Modify the description about clock synchronization

⚫ Modify the explanation of the setting [Opt_TimeSyn]

⚫ Modify the logic of forward and reverse direction element

⚫ Add the setting [En_PopupRecord_Blkd]

R1.30 R1.40 2020-12-02
⚫ Revise the logic of frequency rate-of-change protection

⚫ Revise the description and handing suggestion of the alarm

signals "Fail_Sample" and "Alm_Sample"

⚫ Add the alarm signal "Alm_Quality"

⚫ Revise measurement scope and accuracy

⚫ Revise dead check logic

⚫ Update the range of the setting [MMTR.U2n].in Energy

Metering Settings

⚫ Modify the items in Power Quality

⚫ Modify the term definition in IEC61850 Communication

Settings and IEC103 Communication Settings

⚫ Delete the setting [En_NetPrintPort]

⚫ Add the setting [En_LAN1], [En_IP_Whitelist] and

[IP**_Whitelist] in General Communication Settings

PCS-902S Line Distance Relay XIII

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Preface

⚫ Modify the range of the settings [Addr_RS485-1] and

[Addr_RS485-2]

⚫ Modify the range, default value and description of the

setting [Opt_DualNetMode_MMS]

⚫ Modify the description of the settings [En_UR_TCP*_DNP]

⚫ Add the settings [En_MsgCtrlUR_TCP*_DNP]

⚫ Add the setting [En_IEC103_TCP&UDP_Port] in IEC103

Communication Settings

⚫ Add Modbus Communication Settings

⚫ Modify the logic of voltage selection for one-and-half circuit

breakers

⚫ Modify the measurements of harmonics

⚫ Modify the default value of the setting [Prot.U1n]

⚫ Modify the default value of the setting [UB1.Syn.U1n]

⚫ Modify the default value of the setting [UL2.Syn.U1n]

⚫ Modify the default value of the setting [UB2.Syn.U1n]

⚫ Modify the default value of the setting [RecDur_PostFault]

⚫ Delete the setting [50/51G.Opt_PolarizedVolt]

⚫ Add CPU plug-in modules, NR6106AF, NR6106AG,

NR6106AM, NR6106AN, NR6106AL and NR6106AP

⚫ Add the technical data of clock synchronization for BNC

port

⚫ Add BI plug-in modules, NR6604A and NR6611A

⚫ Add the technical data of binary input

⚫ Add PWR plug-in modules, NR6311A

⚫ Modify the technical data of power supply

⚫ Add the settings [21L1.ZG.En_NeuDir_Blk],

[21L1.ZG.En_NegDir_Blk] and [21L1.ZP.En_NegDir_Blk]

⚫ Modify the logic of zone 1 of distance protection

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 Preface

⚫ Modify the range of the settings [Prot.CB1.I1n] and

[Prot.CB2.I1n]

⚫ Update CT requirement

⚫ Modify the default value of the setting [En_TelnetPort]

⚫ Delete PPM

⚫ Revise the range of the setting [B01.Opt_NetMode],

NR6106 supports 2 groups of PRP

⚫ Add the setting [En_ConvModeSNTP] in Clock

Synchronization Settings

⚫ Modify the description of the setting [Opt_TimeSyn]

⚫ Revise the description about clock synchronization mode

⚫ Revise the description about clock synchronization priority

⚫ Revise DPS synthesis logic

⚫ Modify the technical data of mechanical tests

R1.31 R1.41 2021-04-02
⚫ Update the term definition of the setting

[En_103_TCP&UDP_Port]

⚫ Modify the logics of overfrequency protection,

underfrequency protection and frequency rate-of-change

protection

⚫ Add the settings [81Oi.Opt_Trp/Alm], [81Ui.Opt_Trp/Alm]

and [81Ri.Opt_Trp/Alm]

⚫ Modify the descriptions about overfrequency protection,

underfrequency protection and frequency rate-of-change

protection

⚫ Modify the range of the setting

[CBx.VoltSel.Opt_CBConfig]

R1.32 R1.42 2021-05-27 ⚫ Add the description about the summation current in

System Parameters

⚫ Add the description about the direction control to pilot

PCS-902S Line Distance Relay XV

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Preface

distance protection in Pilot Distance Protection

⚫ Add the description about the direction discrimination and

function test of pilot directional earth-fault protection in

Pilot Directional Earth-Fault Proteciton

⚫ Add the description about the direction control to distance

protection in Distance Protection

⚫ Add the description about AR initation by single-phase fault

⚫ Add the section "Product Documentation Set" in Preface

⚫ Update the section "Symbols" of Preface

⚫ Update the description about the product warranty

⚫ Delete the input signals of control function, "in_en" and

"in_blk"

⚫ Modiyf DPS synthesis logic

⚫ Modify the logic of closing operation and logic of open

operation

⚫ Update the description of the settings [25.U_DdChk] and

[25.U_LvChk]

⚫ Add the description about the summation current in

R1.40 R1.50 2021-11-05
System Parameters

⚫ Add the description about the direction control to pilot

distance protection in Pilot Distance Protection

⚫ Add the description about the direction discrimination and

function test of pilot directional earth-fault protection in

Pilot Directional Earth-Fault Proteciton

⚫ Add the description about the direction control to distance

protection in Distance Protection

⚫ Add the description about AR initation by single-phase fault

⚫ Add flashover protection

⚫ Modify the default value of the settings [IP_LAN1],

XVI PCS-902S Line Distance Relay

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 Preface

[IP_LAN2], [IP_LAN3] and [IP_LAN4]

⚫ Modify the default pickup and dropoff time of binary intputs

from 20ms to 10ms

⚫ Modify the descriptions and logics of breaker failure

protection

⚫ Add the "NOTICE" about the setting [FOx.Nx64k_C37.94],

which indicates whether the device support impedance-

based fault location for different setting value.

⚫ Modify the upper limit of the settings [50/51Pi.C],

[50/51Gi.C] and [50/51Qi.C].

⚫ Modify the range of the setting

[CBx.VoltSel.Opt_CBConfig]

⚫ Update AR time sequence diagram

⚫ Revise the technical data and the description of clock

synchronization port

⚫ Modify the logics of breaker failure protection

⚫ Add the settings [CBx.50BF.Opt_LogicMode]

⚫ Delete the settings [CBx.50BF.En_Curr] and

R1.50 R1.60 2022-01-26
[CBx.50BF.En_CBPos]

⚫ Modify the description of load encroachment and add the

corresponding settings

⚫ Delete the settings [21L.LoadEnch.phi] and

[21L.LoadEnch.R_Set]

⚫ Modify the description about IRIG-B and PPS of clock

synchronization

⚫ Revise the technical data of Clock Synchronization Port

R1.70 R1.70 2023-01-17
⚫ Revise the technical data of Measurement Scope and

Accuracy

⚫ Updat the range of the settings [Prot.U2n], [UB1.Syn.U2n],

PCS-902S Line Distance Relay XVII

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Preface

[UL2.Syn.U2n] and [UB2.Syn.U2n]

⚫ Modify the direction control element of phase overcurrent

protection and earth fault protection

⚫ Add the setting [50/51G.DIR.Opt_PolarizedVolt]

⚫ Add the output signal [Sig_CILOChk_Failed] in

Switchgear Control

⚫ Add the output signals [CBx.25.U_Dd_Blk_DdChk], ……

[CBx.25.Sig_SynChk_Failed] in Synchronism Check

⚫ Delete the section "Switchgear Trip Counter"

⚫ Add the description and the settings about ARP binding

⚫ Add the description about the debugging network port and

the debugging serial port

⚫ Update NET-DSP module from NR6112 to NR6113

⚫ Add the setting [t_Send_Heartbeat_Syslog]

⚫ Add the section "Mode and Behaviour"

⚫ Add the section "Circuit Breaker Supervison"

⚫ Add the description about mixed sampling mode

⚫ Add the settings [Num_Point_Interp_MixedSmpl]

[Opt_MixedSmpl] and [t_Comp_Interp_MixedSmpl]

⚫ Add the description about CT ratio inconsistency for stub

differential protection

⚫ Add the section "AC Analog Input Calibration"

⚫ Update the description of the setting [PDC**.Opt_Protocol]

⚫ Delete the settings [Cfg_NetPorts_Bond] and

[B01.Opt_NetMode]

⚫ Add the settings [B01.Grp01.Opt_NetMode] and

[B01.Grp02.Opt_NetMode] and their descriptions

⚫ Add the description about measurement CT for single CB

R1.72 R1.72 2023-08-01
application and the corresponding analog quantities

XVIII PCS-902S Line Distance Relay

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 Preface

⚫ Add PWR plug-in modules, NR6305E

⚫ Add the setting [En_AutoScroll_SLD] in Device Settings

⚫ Add the setting [Opt_Client_SameIP] in IEC61850

Settings

⚫ Modify the term definition relevant to control function

⚫ Add the second group of voltage/frequency/phase settings

⚫ Add the description about the second group of

voltage/frequency/phase settings

⚫ Add adaptive zero-sequence reactance line characterics

⚫ Modify the descriptions and logics about faulty phase

selection

PCS-902S Line Distance Relay XIX

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Preface

XX PCS-902S Line Distance Relay

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 1 Introduction

1 Introduction
1
Table of Contents

1.1 Application ....................................................................................................... 1-1

1.2 Functions ......................................................................................................... 1-3
1.3 Highlights ....................................................................................................... 1-11
1.4 Features.......................................................................................................... 1-12

List of Figures

Figure 1.1-1 Typical application of single circuit breaker (single busbar)............................ 1-1

Figure 1.1-2 Typical application of single circuit breaker (double busbars) ........................ 1-1

Figure 1.1-3 Typical application of double circuit breakers ................................................... 1-2

Figure 1.1-4 Sampled analogue values from MU and conventional CT/VT .......................... 1-2

Figure 1.2-1 Functional overview of PCS-902S ........................................................................ 1-3

PCS-902S Line Distance Relay 1-a

Date: 2023-08-01
 1 Introduction

1-b PCS-902S Line Distance Relay

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 1 Introduction

1.1 Application

PCS-902S protect overhead and underground lines, feeders, cables and series compensated lines
1
on all voltage levels with highest possible selectivity. The availability of various protection and
automation functions permits its utilization in all domains of line protection. The devices contain all
important auxiliary functions that are necessary today for safe network operation. This includes
control, measurement and monitoring functions. The large number of communication interfaces
and communication protocols satisfies the requirements of communication-based selective
protection and automation operation. Its modular structure permits line protection devices always
to be adapted flexibly to the individual requirements.

3CT 3CT

52 * * 52

3VT 3VT

CH1 CH1
PCS-902S Optical fibre channel or PLC channel PCS-902S
CH2 CH2

1VT 1VT
Communication channel via direct dedicated fibre, MUX or PLC

Figure 1.1-1 Typical application of single circuit breaker (single busbar)

3CT 3CT

52
* * 52

1VT 1VT

CH1 CH1
PCS-902S Optical fibre channel or PLC channel PCS-902S
CH2 CH2

3VT 3VT

Communication channel via direct dedicated fibre, MUX or PLC

3VT 3VT

Figure 1.1-2 Typical application of single circuit breaker (double busbars)

PCS-902S is a high-speed transmission line distance relay featuring single-pole & three-pole
tripping and reclosing with synchronism check. The device features extensive metering & data
recording including high-resolution data capture and reporting. PCS-902S features expanded
control equation programming for easy and flexible implementation of custom protection and
control schemes.

A simple and robust hardware design features efficient digital signal processing. Combined with
extensive self-testing, these features provide device reliability and enhance relay availability.

PCS-902S can be configured to support single circuit breaker application or double circuit breakers
application by PCS-Studio. If the device is applied to double circuit breakers mode, all protection
functions related to the number of circuit breaker will be affected.

PCS-902S Line Distance Relay 1-1

Date: 2023-08-01
 1 Introduction

52 52
1VT 1VT

*
*

1 3CT 3CT

3VT 3VT

CH1 CH1
52 52
PCS-902S Optical fibre channel or PLC channel PCS-902S
CH2 CH2
3CT 3CT

*
*

1VT Communication channel via direct dedicated fibre, MUX or PLC 1VT

1VT 1VT
52 52

Figure 1.1-3 Typical application of double circuit breakers

The PCS-902S is widely adopted not only for conventional substations, but also for digital
substations. It supports IEC 61850 Editions 1 and 2 and provides GOOSE and SV network
interfaces with high real-time performance. The process level network supports peer-to-peer (P2P)
mode and networking mode, including single network mode and dual network mode. The station
level network could also receive and send MMS messages (such as interlocking signals) or process
level GOOSE messages (such as circuit breakers or disconnectors positions and trip signals).

The PCS-902S allow the use of digital quantities (SV sampled signals), conventional quantities
(wired analog signals) or mixed implementations in networking mode. Time synchronization is
available in the device by the external clock source.

Line 1 Line 2

Bus1_CB 3VT Tie_CB Low-power CT Bus2_CB

Bus1 Bus2
3CT (ECT)
52
52

52

MU

1VT

Ethernet switch External clock source

AC Module SV Module

PCS-902S

Figure 1.1-4 Sampled analogue values from MU and conventional CT/VT

1-2 PCS-902S Line Distance Relay

Date: 2023-08-01
 1 Introduction

For the mixed mode, the digital quantities (SV sampled signals) is acquired 1
by CPU module and the conventional quantities (wired analog signals) is
acquired by analog input module. The sampling mode should be selected
according to the actual project application. If the mixed mode is selected,
SV sampled signals must adopt the networking mode, analog input module
must adopt 4CT/4VT (4 current inputs & 4 voltage inputs), and the external
clock source must be available. For voltage selection of the mixed mode,
the switched voltages must adopt the same sampling signal (SV sampled
signals or wired analog signals).

1.2 Functions

The functional overview of the device is shown in Figure 1.2-1.

Busbar

3VT

52
*

85 21L 67P 67G 67Q 32R 49P 50DZ 46BC 62P D 50BF 37 PMU 59P
3CT

21D 50/51P 50/51G 50/51Q 50F FR 59Q

78 FL

Data transmit/Rec eiv e

SOTF 59G

81O 27P

81U 81R

87STB (Only for one and a half breakers arrangement)

1VT
25 79

Line

Figure 1.2-1 Functional overview of PCS-902S

1 Protection

ANSI Protection functions Remark

⚫ Independent pilot zone (forward direction and reverse

85 Pilot distance protection
direction, mho or quadrilateral characteristics)

PCS-902S Line Distance Relay 1-3

Date: 2023-08-01
 1 Introduction

⚫ PUTT, POTT, Blocking, Unblocking, Zone Extension

⚫ Current reversal logic

1
⚫ Weak infeed echo or echo&trip

⚫ Open breaker echo

⚫ Directional zero-sequence comparison element for pilot

scheme
Pilot directional earth-fault
⚫ PTT, Blocking and Unblocking
protection
⚫ Current reversal logic

⚫ Open breaker echo

⚫ Up to 6 zones

⚫ 3 independent phase-to-ground distance elements for

each zone

⚫ 3 independent phase-to-phase distance elements for

each zone

⚫ Selectable quadrilateral characteristics or mho

characteristics

⚫ Independent impedance settings and time delays for

21L Distance protection
each zone

⚫ Zero-sequence current compensation for phase-to-

ground distance element

⚫ Selectable forward direction, reverse direction or non-

direction (except zone 1 that is fixed as forward direction)

⚫ Load encroachment for each zone

⚫ Power swing blocking and releasing for each zone

⚫ Faulty phase selection for each zone

⚫ Fixed forward direction

21D DPFC distance protection ⚫ High-speed operation

⚫ Supplementary for zone 1 of distance protection

78 Out-of-step protection ⚫ Easy to set and independent of system parameters

1-4 PCS-902S Line Distance Relay

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 1 Introduction

⚫ Up to 6 stages with independent logic

⚫ Voltage control element for each stage

1
⚫ Optional direction element for each stage, including

67P forward direction, reverse direction or non-direction

Phase overcurrent protection
50/51P ⚫ Optional definite-time characteristics and inverse-time

characteristics for each stage

⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Harmonic control element for each stage

⚫ Up to 6 stages with independent logic

⚫ Optional direction element for each stage, including

forward direction, reverse direction or non-direction

67G
Earth fault protection ⚫ Optional definite-time characteristics and inverse-time
50/51G
characteristics for each stage

⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Harmonic control element for each stage

⚫ Up to 2 stages with independent logic

⚫ Optional direction element for each stage, including

67Q Negative-sequence overcurrent forward direction, reverse direction or non-direction

50/51Q protection ⚫ Optional definite-time characteristics and inverse-time

characteristics for each stage

⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Via distance measurement elements

SOTF Switch onto fault ⚫ Via dedicated earth fault element

⚫ Via phase overcurrent element

⚫ Up to 2 stages with independent logic

49P Thermal overload protection
⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Up to 2 stages with independent logic

59P Phase overvoltage protection ⚫ Optional definite-time characteristics and inverse-time

characteristics for each stage

PCS-902S Line Distance Relay 1-5

Date: 2023-08-01
 1 Introduction

⚫ Optional phase voltage or phase-to-phase voltage

⚫ Optional “1-out-of-3” logic or “3-out-of-3” logic

1
⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Up to 2 stages with independent logic

⚫ Optional definite-time characteristics and inverse-time

characteristics for each stage

⚫ Optional phase voltage or phase-to-phase voltage

27P Phase undervoltage protection ⚫ Optional “1-out-of-3” logic or “3-out-of-3” logic

⚫ Blocked by instantaneous VT circuit failure

⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Optional auxiliary criterion, including CB position check

and current check

Negative-sequence overvoltage ⚫ Up to 2 stages with independent logic

59Q
protection ⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Up to 2 stages with independent logic

59G Residual overvoltage protection
⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Up to 4 stages with independent logic

81O Overfrequency protection ⚫ Voltage control element

⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Up to 4 stages with independent logic

81U Underfrequency protection ⚫ Voltage control element

⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Up to 4 stages with independent logic

Frequency rate-of-change
81R ⚫ Voltage control element
protection
⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Up to 2 stages with independent logic

32R Reverse power protection
⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Optional auxiliary criterion, including CB position check

37 Undercurrent protection
and current check

1-6 PCS-902S Line Distance Relay

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 1 Introduction

⚫ Selectable trip purpose or alarm purpose for each stage

⚫ Phase-segregated re-trip and three-phases re-trip

1
⚫ Optional current check criterion (phase overcurrent

element, zero-sequence overcurrent element, negative-

50BF Breaker failure protection
sequence overcurrent element)

⚫ Optional contact check criterion

⚫ Two time delays

⚫ Protect the T-zone in one-and-a-half breaker and ring

87STB Stub differential protection
breaker arrangements

⚫ Clear the dead zone faults between CT and the circuit

50DZ Dead zone protection
breaker

⚫ Adopt the ratio of negative-sequence current to positive-

46BC Broken conductor protection sequence current (Ι2/Ι1) to detect the broken conductor.

⚫ Selectable trip purpose or alarm purpose

⚫ Initiated by three auxiliary contacts of phase-segregate

circuit breaker
62PD Pole discrepancy protection
⚫ Optional auxiliary criterion (zero-sequence current

element or negative-sequence current element)

⚫ Optional current criterion (phase overcurrent element,

50F Flashover protection zero-sequence overcurrent element, negative-sequence

overcurrent element)

⚫ Independent logic for auto-reclosing and manually

25 Synchronism check
closing

⚫ One shot or multi-shot

⚫ 1-pole AR, 3-pole AR or 1/3-pole AR

79 Auto-reclosing ⚫ Optional trigger mode, including protection operating and

external binary input

⚫ Support synchro-check and voltage check

PMU Phasor measurement unit ⚫ Compatible with IEEE C37.118-2005, IEEE C37.118.1-

PCS-902S Line Distance Relay 1-7

Date: 2023-08-01
 1 Introduction

2011, IEEE C37.118.2-2011 and IEEE C37.118.1a-

2014.
1
⚫ Single-ended impedance-based method

FL Fault location ⚫ Zero-sequence mutual coupling compensation for

parallel lines

DPFC is the abbreviation of deviation of power frequency component.

2 Control

⚫ Circuit breaker & disconnector control (Remote/local)

⚫ Synchronism check for auto-reclosing and manual closing

⚫ Voltage selection

3 Synchrophasor measurement

⚫ Synchronize with the GPS time by IRIG-B time source

⚫ Calculate synchronized phasors, including: Ua, Ub, Uc, U1, U2, U0, Ia, Ib, Ic, I1, I2, I0

⚫ Calculate analog values, including: active power (P), reactive power (Q), frequency,
ROCOF (df/dt)

⚫ Transmit binary status of the IED to PDC (Phasor Data Concentrator) according to IEEE
C37.118 standard

⚫ Realize high accurate measurement of the phasors and analogs according to the IEEE
C37.118.1-2011 and IEEE C37.118.1a-2014 standard.

⚫ Communicate with PDC according to IEEE C37.118-2005 and IEEE C37.118.2-2011

⚫ Supporting P Class or M Class measurement (user selectable)

⚫ Measurement of up to 32 binary status (user configurable)

⚫ Output of synchrophasor with timestamp, support of multiple protocols (TCP, TCP-UDP,

UDP) and multiple data rates (2f0, f0, f0/2) for maximum 4 clients (PDC)

4 Measurement

⚫ Current and voltage measurement at a 2.4KHz sampling rate

⚫ Current and voltage measurement at a 9.6KHz sampling rate

⚫ Energy metering (active and reactive energy are calculated in import respectively export
direction)

1-8 PCS-902S Line Distance Relay

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 1 Introduction

⚫ Power (Apparent/Real/Reactive)

⚫ Power factor

⚫ Frequency
1
⚫ Current, voltage and active/reactive power calibration

5 Recording

⚫ Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.

⚫ 64 disturbance waveforms records (The file format of disturbance recorder is compatible

with international COMTRADE file.)

⚫ 64 high-frequency waveforms records (The file format of disturbance recorder is

compatible with international COMTRADE file.)

6 Supervision

⚫ VT circuit supervision

⚫ CT circuit supervision

⚫ Trip/Close coil supervision

⚫ Self diagnostic

⚫ Pilot communication channel supervision

⚫ DC power supply supervision

⚫ Channel status statistic

⚫ System frequency supervision

⚫ Circuit breaker supervision (contact travel time, interrupted current, trip counter, remaining life,
accumulated abrasion, etc.)

7 Pilot channel scheme

⚫ Optional single- or dual- pilot channels (fiber optic)

⚫ Support G.703 and C37.94

8 Communication interface

⚫ 2 or 4 100Base-TX copper Ethernet ports for SCADA communication

⚫ 2 or 4 100Base-FX optical Ethernet ports for SCADA communication

⚫ 2 RS-485 serial ports for SCADA communication

⚫ Extendable 1000Base-SX optical Ethernet port for PRP and HSR

⚫ 1 RS-485 serial port for clock synchronization

PCS-902S Line Distance Relay 1-9

Date: 2023-08-01
 1 Introduction

⚫ 1 TTL serial port for clock synchronization

⚫ 1 BNC port for clock synchronization

1 ⚫ 1 front RJ-45 port for debugging

⚫ 1 rear RJ-45 port for debugging

The device provides the menu "DbgPort Info" to display the status of the
debugging network port and the debugging serial port, and open or close
the ports.

9 Communication protocol

⚫ IEC 61850 Editions 1 and 2

⚫ IEC 60870-5-103

⚫ DNP3.0

⚫ Modbus

⚫ IEC 62439 Parallel Redundancy Protocol (PRP)

⚫ IEC 62439 High-availability Seamless Redundancy (HSR)

⚫ IEEE 802.1w Rapid Spanning Tree Protocol (RSTP)

10 Digital application

⚫ IEC 61850 MMS Server

⚫ IEC 61850-8-1 GOOSE

⚫ IEC 61850-9-2LE SV

⚫ 4 100Base-TX electrical or 100Base-FX optical Ethernet port (station level)

⚫ Extendable 100Base-FX optical Ethernet port (process level)

⚫ Extendable 1000Base-SX optical Ethernet port (process level)

11 Clock synchronization

⚫ IRIG-B: IRIG-B via serial port (RS-485 or TTL level) or BNC port (TTL level)

⚫ PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), BNC port (TTL level) or
binary input

⚫ IEEE 1588: Clock message based on IEEE 1588 via Ethernet network

⚫ SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network

⚫ Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol

1-10 PCS-902S Line Distance Relay

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 1 Introduction

12 Cyber security

⚫ NERC CIP

⚫ IEC 62351
1
⚫ IEC 62443

⚫ IEEE 1686

13 User interface

⚫ Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and set-point
adjustment

⚫ Push buttons for open/close, switch for selection between local and remote control, and
user's login and logout authority management

⚫ 4 Programmable operator push-buttons with user-configurable labels

⚫ Up to 18 programmable target LEDs with user-configurable labels

⚫ 1 RS-232 rear ports for printer

⚫ Language switchover—English + selected language

⚫ Configuration tool—PCS-Studio

14 Miscellaneous

⚫ User programmable logic

⚫ Fault phase selection

⚫ Switching system phase sequences function (ABC or ACB)

1.3 Highlights

⚫ Unified software & hardware platform, comprehensive power grid solutions of protection, control,
measurement and monitoring, easy to use and maintain.

⚫ High reliability and redundancy design for drive systems of the sampling circuit and the output
circuit ensure that the overall reliability of the device is high. Real-time sampling based on dual
AD can mutually check and detect the potential abnormality in the sampling circuit in time. The
control power supply of the output relay is independent with the control circuit of trigger signals,
which can prevent from undesired operation caused by the abnormality of drive circuit of output
relays.

⚫ Various function modules can satisfy various situations according to the different requirements
of users. Flexible and universal logic programming, user-defined configuration of BI/BOs,
buttons and LEDs and powerful analogue programming are supported.

⚫ Modularized hardware design makes the device be easily upgraded or repaired by a qualified
service person. It can be combined with different I/O modules, with online self-check and

PCS-902S Line Distance Relay 1-11

Date: 2023-08-01
 1 Introduction

monitoring function, and the device can be restored from abnormal operation only need to
replace a single abnormal module.

1 ⚫ Support memory check and error correction function, ensure high reliability and safety.

⚫ Support the internet communication protocol of native PRP/HSR and RSTP.

⚫ Fully compatible with IEC 61850 edition 1 & edition 2, support MMS service, IEC 62351
communication service, GOOSE communication in station level & process level, SV
communication with multi-sampling rate.

⚫ Fully complies with cyber security standards, including IEC62443, IEC62351, IEEE1686,
NERC-CIP, support role-based access control (RBAC), security audit, security encryption
communication and security tool, improve the cyber security capability of devices.

⚫ Powerful COMTRADE fault and disturbance recording function is supported. The whole
recording time is automatically configurable by the fault duration, which is convenient to fault
analysis and replay. The recording sample rate is up to 9.6kHz.

⚫ Settable secondary rated current (1A/5A) and settable voltage threshold of binary input

⚫ Support small size and large size LCD, control and multifunction button

⚫ Support flush mounting, semi-flush mounting, surface mounting, wall mounting and other
mounting methods.

⚫ Cross screw IO, CT/VT terminals can support AWG12 specification connector and 4mm2 lead

⚫ Multiple variants with case size 1/1 or 1/2 × 19"

⚫ Protection class of front side is up to IP54

⚫ PCS-Studio is the configuration tool providing all the related functionality for PCS S series
devices. It ranges from device configuration to entire substation design of bay integration.

⚫ Support IEEE 1588, IRIG-B clock synchronization

⚫ Support actual system phase sequence, either ABC or ACB, incorrect connection of actual
phase sequence can automatically be verified and relevant protection functions can be blocked.

⚫ Equipped with high-speed large capacity output relay, its operation speed is less than 1ms and
its break capacity is up to 10A. The real-time supervision for output drive circuit can detect the
abnormality in advance.

⚫ Support setup up to 40 users and allow each user to own different password and access
authority.

1.4 Features

⚫ Two-terminal transmission line application, including overhead line and cable

⚫ Distance Protection

1-12 PCS-902S Line Distance Relay

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 1 Introduction

 Distance protection adopts the half-wave algorithm, and its typical operation time is 12-
15ms.

 6 zones distance protection, independent zero-sequence compensation factor for each 1

zone, the phase-to-ground and phase-to-phase characteristics of distance protection can
be set independently.

 The unique power swing blocking releasing logic can properly supervise distance
protection during power swing, which ensures distance protection to operate correctly for
internal faults during power swing, and prevents distance protection from mal-operation
during power swing.

Transmission Line
⚫ The distance protection based on the polarized voltage is suitable for series compensated lines,
its protection range is automatically adaptive according to the current and not affected by the
system infeed, which prevents distance protection from the overreaching.

⚫ The unique phase selector has the same protection zone as operation element. The phase
selection is automatically resulted according to the reliability of phase selector, so that to avoid
probable mistaken multi-phase selection by adopting overreaching phase selector.

⚫ The overcurrent protection is combined with harmonic blocking and cold load starting logic,
which can prevent from mal-operation affected by impulse current while the transformer is
initiated on no-load.

⚫ Selectable IEC, ANSI inverse-time characteristics curves that can be defined by users, and the
selection of inverse-time drop-off curve is supported.

⚫ Support single-ended impedance-based fault location, mutual compensation for parallel lines
arrangement is also available.

⚫ Both dedicated fiber channel and multiplexing fiber channel are supported, and single mode
and multi-mode channel combination operation mode is enabled. Communication rate supports
64kbit/s and 2Mbit/s, and communication protocol supports C37.94 and G.703.

⚫ Optional synchrophasor measurement

PCS-902S Line Distance Relay 1-13

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 1 Introduction

1-14 PCS-902S Line Distance Relay

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 2 Technical Data

2 Technical Data

Table of Contents

2.1 Electrical Specifications ................................................................................. 2-1 2

2.1.1 AC Current Input................................................................................................................... 2-1

2.1.2 AC Voltage Input................................................................................................................... 2-1

2.1.3 Power Supply ....................................................................................................................... 2-1

2.1.4 Binary Input .......................................................................................................................... 2-3

2.1.5 Binary Output ....................................................................................................................... 2-6

2.2 Mechanical Specifications .............................................................................. 2-7

2.3 Ambient Temperature and Humidity Range .................................................. 2-8
2.4 Communication Port ....................................................................................... 2-8
2.4.1 EIA-485 Port ......................................................................................................................... 2-8

2.4.2 Ethernet Port ........................................................................................................................ 2-8

2.4.3 Optical Fiber Port ................................................................................................................. 2-9

2.4.4 Print Port............................................................................................................................. 2-10

2.4.5 Clock Synchronization Port ................................................................................................ 2-10

2.5 Type Tests ...................................................................................................... 2-10

2.5.1 Environmental Tests ........................................................................................................... 2-10

2.5.2 Mechanical Tests ................................................................................................................ 2-10

2.5.3 Electrical Tests.................................................................................................................... 2-11

2.5.4 Electromagnetic Compatibility ............................................................................................ 2-11

2.6 Certifications.................................................................................................. 2-13

2.7 Liquid Crystal Display (LCD) ........................................................................ 2-13
2.8 Terminals ........................................................................................................ 2-14
2.8.1 Ring Ferrule ........................................................................................................................ 2-14

2.8.2 Pin Ferrule .......................................................................................................................... 2-14

2.9 Measurement Scope and Accuracy ............................................................. 2-14

2.10 Management Function................................................................................. 2-15

PCS-902S Line Distance Relay 2-a

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 2 Technical Data

2.10.1 Control Performance ........................................................................................................ 2-15

2.10.2 Clock Performance ........................................................................................................... 2-15

2.10.3 Fault and Disturbance Recording .................................................................................... 2-15

2.10.4 Binary Input Signal ........................................................................................................... 2-15

2 2.11 Synchrophasor Measurement .................................................................... 2-16

2.11.1 Synchrophasor Measurement under Steady-state .......................................................... 2-16

2.11.2 Frequency and ROCOF Measurement under Steady-state ............................................ 2-16

2.11.3 Active and Reactive Power Measurement under Steady-state........................................ 2-17

2.11.4 Synchrophasor Measurement under Modulation ............................................................. 2-18

2.11.5 Frequency and ROCOF Measurement under Modulation ............................................... 2-18

2.11.6 Synchrophasor Measurement under Frequency Ramp ................................................... 2-18

2.11.7 Frequency and ROCOF Measurement under Frequency Ramp ..................................... 2-19

2.11.8 Synchrophasor Measurement under Step Change.......................................................... 2-19

2.11.9 Frequency and ROCOF Measurement under Step Change............................................ 2-19

2.11.10 Measurement Reporting Latency ................................................................................... 2-20

2.11.11 Synchrophasor Communication ..................................................................................... 2-20

2.12 Protective Functions ................................................................................... 2-20

2.12.1 Fault Detector (FD)........................................................................................................... 2-20

2.12.2 Distance Protection (21L)................................................................................................. 2-21

2.12.3 Phase Overcurrent Protection (50/51P) ........................................................................... 2-21

2.12.4 Earth Fault Protection (50/51G) ....................................................................................... 2-22

2.12.5 Negative-sequence Overcurrent Protection (50/51Q) ..................................................... 2-23

2.12.6 Overvoltage Protection (59P) ........................................................................................... 2-24

2.12.7 Negative-sequence Overvoltage Protection (59Q) .......................................................... 2-24

2.12.8 Residual Overvoltage Protection (59G) ........................................................................... 2-25

2.12.9 Undervoltage Protection (27P) ......................................................................................... 2-25

2.12.10 Overfrequency Protection (81O) .................................................................................... 2-25

2.12.11 Underfrequency Protection (81U) .................................................................................. 2-25

2.12.12 Frequency Rate-of-change Protection (81R) ................................................................. 2-26

2.12.13 Reverse Power Protection (32R) ................................................................................... 2-26

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 2 Technical Data

2.12.14 Undercurrent Protection (37).......................................................................................... 2-26

2.12.15 Breaker Failure Protection (50BF) ................................................................................. 2-27

2.12.16 Stub Differential Protection (87STB) .............................................................................. 2-27

2.12.17 Dead Zone Protection (50DZ) ........................................................................................ 2-27

2.12.18 Broken Conductor Protection (46BC) ............................................................................ 2-27

2
2.12.19 Pole Discrepancy Protection (62PD) ............................................................................. 2-27

2.12.20 Thermal Overload Protection (49P) ............................................................................... 2-28

2.12.21 Flashover Protection (50F)............................................................................................. 2-28

2.12.22 Transfer Trip (TT) ........................................................................................................... 2-28

2.12.23 Auto-reclosing (79) ......................................................................................................... 2-28

2.12.24 Transient Overreaching .................................................................................................. 2-28

2.12.25 Impedance-Based Fault Location (FL)........................................................................... 2-28

2.13 Communication Functions ......................................................................... 2-29

2.13.1 GOOSE ............................................................................................................................ 2-29

2.13.2 SV ..................................................................................................................................... 2-29

PCS-902S Line Distance Relay 2-c

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 2 Technical Data

2-d PCS-902S Line Distance Relay

Date: 2023-08-01
 2 Technical Data

2.1 Electrical Specifications

2.1.1 AC Current Input

Phase rotation ABC or ACB

Nominal frequency (fn) 50Hz, 60Hz 2

Rated current (In) 1A/5A (settable)

Linear to 0.05In~40In

Thermal withstand

-continuously 4In

-for 10s 30In

-for 1s 100In

-for half a cycle 250In

Burden <0.05VA/phase @1A, <0.25VA/phase @5A

Number Up to 7 current input according to various applications

2.1.2 AC Voltage Input

Phase rotation ABC or ACB

Nominal frequency (fn) 50Hz, 60Hz

Rated voltage (Un) 100V~130V

Linear to 1V~300V

Thermal withstand Phase-to-ground Phase-to-phase

-continuously 300V 519V

-10s 600V 1038V

-1s 660V 1141V

Burden at rated <0.10VA/phase @100V

Number Up to 7 voltage input according to various applications

2.1.3 Power Supply

Rated voltage 24/30/48/60Vdc 110/125/220/250Vdc

Permissible voltage range IEC 61000-4-11:2017

PCS-902S Line Distance Relay 2-1

Date: 2023-08-01
 2 Technical Data

IEC 61000-4-29:2000

18~72Vdc 88~300Vdc

IEC 60255-26:2013
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage

2 Quiescent condition <15W (default hardware configuration)

Additional for each

0.25W~0.35W
energized SFP socket

Quiescent condition: <1W

0.004W @ 24Vdc

0.015W @ 48Vdc
Additional for each energized
0.080W @ 110Vdc
binary input (common negative
0.106W @ 125Vdc
supply)
0.320W @ 220Vdc
Additional for each binary
Burden 0.410W @ 250Vdc
input (BI) module
0.014W @24Vdc

0.031W @48Vdc
Additional for each energized
0.096W @110Vdc
binary input (independent negative
0.115W @125Vdc
supply)
0.270W @220Vdc

0.330W @250Vdc

Additional for each binary Quiescent condition: <0.1W

output (BO) module Additional for each energized relay: <0.44W

Additional module for SV

<7W
sampling

Rated voltage 100/110/115/120/127/220/230/240/250Vac

IEC 61000-4-11:2017
Permissible voltage range
IEC 61000-4-29:2000

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 2 Technical Data

80~275Vac

IEC 60255-26:2013
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage

Quiescent condition <15W (default hardware configuration)

2
Additional for each
0.25W~0.35W
energized SFP socket

Quiescent condition: <1W

0.004W @ 24Vdc

0.015W @ 48Vdc
Additional for each energized
0.080W @ 110Vdc
binary input (common negative
0.106W @ 125Vdc
supply)
0.320W @ 220Vdc
Additional for each binary
Burden 0.410W @ 250Vdc
input (BI) module
0.014W @24Vdc

0.031W @48Vdc
Additional for each energized
0.096W @110Vdc
binary input (independent negative
0.115W @125Vdc
supply)
0.270W @220Vdc

0.330W @250Vdc

Additional for each binary Quiescent condition: <0.1W

output (BO) module Additional for each energized relay: <0.44W

Additional module for SV

<7W
sampling

2.1.4 Binary Input

Settable pickup voltage and dropout voltage (common negative supply)

Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc

Rated current drain 0.73mA 0.83mA 1.47mA 1.67mA

On value (default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc

PCS-902S Line Distance Relay 2-3

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 2 Technical Data

Off value (default set) <55Vdc <62.5Vdc <110Vdc <125Vdc

Maximum permissible voltage 300Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 84 (6U, 1/2 × 19'', ring ferrule), 105 (6U, 1/2 × 19'', pin ferrule),

2 Number 259 (6U, 1/1 × 19'', ring ferrule) or 329 (6U, 1/1 × 19'', pin ferrule) binary

inputs according to various hardware configurations

Settable pickup voltage and dropout voltage (common negative supply)

Rated voltage 110Vac 220Vac

On value (default set) 69.3~132Vac 138.6~264Vac

Off value (default set) <55Vac <110Vac

Maximum permissible voltage 300Vac

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 84 (6U, 1/2 × 19'', ring ferrule), 105 (6U, 1/2 × 19'', pin ferrule),

Number 259 (6U, 1/1 × 19'', ring ferrule) or 329 (6U, 1/1 × 19'', pin ferrule) binary

inputs according to various hardware configurations

Settable pickup voltage and dropout voltage (common negative supply)

Rated voltage 24Vdc 48Vdc

Rated current drain 0.16mA 0.32mA

On value (default set) 15.12~28.8Vdc 30.24~57.6Vdc

Off value (default set) <12Vdc <24Vdc

Maximum permissible voltage 300Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 84 (6U, 1/2 × 19'', ring ferrule), 105 (6U, 1/2 × 19'', pin ferrule),

Number 259 (6U, 1/1 × 19'', ring ferrule) or 329 (6U, 1/1 × 19'', pin ferrule) binary

inputs according to various hardware configurations

Settable pickup voltage and dropout voltage (independent negative supply)

Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc

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 2 Technical Data

Rated current drain 0.86mA 0.92mA 1.23mA 1.33mA

On value (default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc

Off value (default set) <55Vdc <62.5Vdc <110Vdc <125Vdc

Maximum permissible voltage 300Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min) 2

Up to 48 (6U, 1/2 × 19'', ring ferrule), 51 (6U, 1/2 × 19'', pin ferrule), 139

Number (6U, 1/1 × 19'', ring ferrule) or 149 (6U, 1/1 × 19'', pin ferrule) binary

inputs according to various hardware configurations

Settable pickup voltage and dropout voltage (independent negative supply)

Rated voltage 110Vac 220Vac

On value (default set) 69.3~132Vac 138.6~264Vac

Off value (default set) <55Vac <110Vac

Maximum permissible voltage 300Vac

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 48 (6U, 1/2 × 19'', ring ferrule), 51 (6U, 1/2 × 19'', pin ferrule), 139

Number (6U, 1/1 × 19'', ring ferrule) or 149 (6U, 1/1 × 19'', pin ferrule) binary

inputs according to various hardware configurations

Settable pickup voltage and dropout voltage (independent negative supply)

Rated voltage 24Vdc 48Vdc

Rated current drain 0.58mA 0.66mA

On value (default set) 15.12~28.8Vdc 30.24~57.6Vdc

Off value (default set) <12Vdc <24Vdc

Maximum permissible voltage 300Vdc

Withstand voltage 2000Vac, 2800Vdc (1 min)

Up to 48 (6U, 1/2 × 19'', ring ferrule), 51 (6U, 1/2 × 19'', pin ferrule), 139

Number (6U, 1/1 × 19'', ring ferrule) or 149 (6U, 1/1 × 19'', pin ferrule) binary

inputs according to various hardware configurations

PCS-902S Line Distance Relay 2-5

Date: 2023-08-01
 2 Technical Data

2.1.5 Binary Output

Tripping/signaling contact

Output mode Potential free contact

Max. system voltage 250Vac, 300Vdc

2 Continuous carry 10A

Pickup time (Typical value) <5ms

Dropout time (Resistive load) <6ms

0.5A@48Vdc

0.35A@110Vdc

Breaking capacity (L/R=40ms) 0.30A@125Vdc

0.20A@220Vdc

0.15A@250Vdc

0.5A@48Vdc

0.35A@110Vdc
Cyclic capacity (2.5 cycle/second,
0.30A@125Vdc
L/R=40ms)
0.20A@220Vdc

0.15A@250Vdc

30A@3s
Short duration current
50A@1s

Durability (Loaded contact) 10000 operations

Up to 44 (6U, 1/2 × 19'', ring ferrule), 56 (6U, 1/2 × 19'', pin ferrule), 135

Number (6U, 1/1 × 19'', ring ferrule) or 175 (6U, 1/1 × 19'', pin ferrule) binary

outputs according to various hardware configurations

Heavy-capacity tripping contact

Output mode Potential free contact

MOV protection (maximum voltage) 350Vdc, 275Vac

Continuous carry 10A

Pickup time (Typical value) <1ms

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 2 Technical Data

Dropout time (Resistive load) <10ms

10A@48V

10A@110V
Breaking capacity (L/R=40ms)
10A@125V

10A@250V 2
10A@48V L/R=40ms
Cyclic capacity (4cycles in 1 second,
10A@110V L/R=40ms
followed by 2 minutes idle for thermal
10A@125V L/R=40ms
dissipation)
10A@250V L/R=20ms

30A@3s
Short duration current
50A@1s

Durability (Loaded contact) 10000 operations

Up to 12 (6U, 1/2 × 19'') or 40 (6U, 1/1 × 19'') binary outputs according

Number
to various hardware configurations

2.2 Mechanical Specifications

Chassis color Silver grey

Approx. 8.66kg (6U, 1/2 × 19'')

Weight per device
Approx. 13.88kg (6U, 1/1 × 19'')

Chassis material Aluminum alloy

Location of terminal Rear panel of the device

Device structure Plug-in modular type @ rear side, integrated frontplate

Protection Class

Standard IEC 60529-2013

IP52

Front side IP54 (valid for surface mounting mode of 6U, 1/2 × 19'' case with sealing

strip)

Other sides IP50

Rear side, connection terminals IP20

PCS-902S Line Distance Relay 2-7

Date: 2023-08-01
 2 Technical Data

2.3 Ambient Temperature and Humidity Range

Standard IEC 60255-1:2009

-40°C to +80°C (Readability of display may be impaired below -20°C

Operating temperature
2 and above 70℃)

Transport and storage temperature

-40°C to +80°C
range

Permissible humidity 5%-95%, without condensation

Pollution degree Ⅱ

Altitude <3000m

2.4 Communication Port

2.4.1 EIA-485 Port

Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

Protocol IEC 60870-5-103:1997 or Modbus

Max. capacity 32

Max. transmission distance 500m

Safety level Isolation to ELV level

Twisted pair Screened twisted pair cable

2.4.2 Ethernet Port

Connector type RJ-45

Transmission standard 100Base-TX

Max. transmission distance 100m

Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850

Safety level Isolation to ELV level

Connector type LC

Characteristics Glass optical fiber

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 2 Technical Data

Fibre type Multi-mode

Wave length 1310nm

Transmission standard 100Base-FX

Max. transmission distance 2km

Min. transmission power 50μm: -24dBm 62.5μm: -20dBm 2

Min. receiving power -31dBm

Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850

Safety level Isolation to ELV level

2.4.3 Optical Fiber Port

For Process Level

Characteristics Glass optical fiber

Connector type LC

Fibre type Multi-mode

Transmission standard 100Base-FX

Max. transmission distance 2km

Wave length 1310nm/850nm

Min. transmission power -20dBm

Min. receiving power -31dBm

For Pilot Communications

Characteristics Glass optical fiber

Connector type ST or FC

Fibre type Single mode Multi-mode

Wave length 1310nm 1550nm 850nm

Transmission power -11.0dBm~-7.0dBm 0dBm~5dBm 62.5μm: -20dBm~-12dBm

Min. receiving power -38dBm -36dBm 62.5μm: -32dBm

Max. transmission distance 60km 120km 62.5μm: 2km

PCS-902S Line Distance Relay 2-9

Date: 2023-08-01
 2 Technical Data

2.4.4 Print Port

Type RS-232

Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

Printer type EPSON® 300K printer

2 Safety level Isolation to ELV level

2.4.5 Clock Synchronization Port

Type RS-485 differential level (Serial port)

Input Demodulated IRIG-B or PPS

Maximum voltage 6Vdc

Input impedance 12kΩ

Isolation 500Vdc

Accuracy 0.2μs

Type TTL level (Serial port or female BNC port)

Input Demodulated IRIG-B or PPS

Nominal voltage 5Vdc±10%

Maximum voltage 5.5Vdc

Characteristic impedance 50Ω

Isolation 500Vdc

Accuracy 0.2μs

2.5 Type Tests

2.5.1 Environmental Tests

Dry cold test IEC60068-2-1:2007

Dry heat test IEC60068-2-2:2007

Damp heat test, cyclic IEC60068-2-30:2005

2.5.2 Mechanical Tests

Vibration IEC 60255-21-1:1988 Class Ⅱ

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Shock IEC 60255-21-2:1988 Class Ⅱ

Bump IEC 60255-21-2:1988 Class Ⅰ

Seismic IEC 60255-21-3:1988 Class Ⅱ

2.5.3 Electrical Tests

Standard IEC 60255-27:2013

2
Dielectric tests Test voltage 2kV, 50Hz, 1min

Impulse voltage tests Test voltage 5kV

Overvoltage category Ⅲ

Insulation resistance measurements Isolation resistance >100MΩ@500VDC

2.5.4 Electromagnetic Compatibility

IEC 60255-26:2013

1MHz burst disturbance test Common mode: class Ⅲ 2.5kV

Differential mode: class Ⅲ 1.0kV

IEC 61000-4-2-2008 class Ⅳ

Electrostatic discharge test For contact discharge: 8kV

For air discharge: 15kV

IEC 60255-26:2013 class Ⅲ

Frequency sweep

Radiated amplitude-modulated

Radio frequency interference tests 10V/m (rms), f=80~1000MHz, 1400~2700MHz

Spot frequency

Radiated amplitude-modulated

10V/m (rms), f=80MHz/160MHz/450MHz/900MHz

IEC 60255-26:2013

Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 5kHz, 5/50ns

Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns

IEC 60255-26:2013
Surge immunity test
Power supply, AC input, I/O port: class Ⅳ, 1.2/50μs

PCS-902S Line Distance Relay 2-11

Date: 2023-08-01
 2 Technical Data

Common mode: 4kV

Differential mode: 2kV

IEC 60255-26:2013

Power supply, AC, I/O, Comm. Terminal: Class Ⅲ, 10V (rms), 150
Conducted RF electromagnetic
2 disturbance
kHz~80MHz

Spot frequency

10V (rms), f=27MHz/68MHz

Power frequency magnetic field IEC 61000-4-8: 2009

immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s

IEC 61000-4-9:2016
Pulse magnetic field immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s

Damped oscillatory magnetic field IEC 61000-4-10:2016

immunity class Ⅴ, 100kHz & 1MHz–100A/m

IEC 60255-26:2013

Conducted emission 0.15MHz~0.50MHz: 79dB (μV) quasi peak, 66dB (μV) average

0.50MHz~30MHz: 73dB (μV) quasi peak, 60dB (μV) average

IEC 60255-26:2013

30MHz~230MHz: 40dB (μV/m) quasi peak @10m,

50dB (μV/m) quasi peak @3m

Below 1GHz
230MHz~1000MHz: 47dB (μV/m) quasi peak @10m,

Radiated emission 57dB (μV/m) quasi peak @3m

1GHz~3GHz: 56dB (μV/m) average, 76dB (μV/m)

peak @3m
Above 1GHz
3GHz~6GHz: 60dB (μV/m) average, 80dB (μV/m)

peak @3m

Auxiliary power supply performance IEC 60255-26:2013

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 2 Technical Data

Voltage dips: Up to 200ms for dips to 40% of rated voltage without reset

Voltage short interruptions: 50ms for interruption without rebooting

(typical configuration)

2.6 Certifications 2
⚫ ISO9001:2015

⚫ ISO14001:2015

⚫ ISO45001:2018

⚫ ISO/IEC27001:2013

⚫ CMMI L5

⚫ EMC: 2014/30/EU, EN 60255-26:2013

⚫ Products safety (LVD): 2014/35/EU, EN 60255-27:2014

⚫ IEC 61850: Edition 2, Parts 6, 7-1, 7-2, 7-3,7-4 and 8-1

⚫ IEC 61850: Edition 2, GOOSE Performance Class P1 (3ms)

⚫ IEEE 1588: IEEE Std C37.238TM-2017

⚫ DNP: DNP 3.0

⚫ PRP: IEC 62439-3 Ed.3 (IS 2016)

⚫ HSR: IEC 62439-3 Ed.3 (IS 2016)

⚫ WEEE: 2012/19/EU, EN 50419:2006

⚫ RoHS: 2011/65/EU, IEC 62321-4:2013, IEC 62321-5:2013, IEC 62321-6:2015, IEC 62321-7-
1:2015, IEC 62321-7-2:2017

⚫ RoHS: (EU) 2015/863, IEC 62321-8:2015

2.7 Liquid Crystal Display (LCD)

Type Resolution

Large size 320x240 pixels

PCS-902S Line Distance Relay 2-13

Date: 2023-08-01
 2 Technical Data

2.8 Terminals

2.8.1 Ring Ferrule

Connection Type Wire Size Screw Type Torque

2 AC current Screw terminals, 1.5~4mm2 lead M4 1.6~1.8 N·m

AC voltage Screw terminals, 0.8~4mm2 lead M4 1.6~1.8 N·m

Power supply Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N·m

Contact I/O Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N·m

Grounding (Earthing) connection BVR type, 0.8~4mm2 lead M3 0.6~0.8 N·m

2.8.2 Pin Ferrule

Connection Type Wire Size Screw Type Torque

Power supply Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N·m

Contact I/O Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N·m

2.9 Measurement Scope and Accuracy

Item Range Accuracy

±0.2° at 0.2×In＜I＜4.0×In
Phase range 0°~360°
±0.5° at 0.1×In＜I＜0.2×In

Frequency fn±5Hz Max. 0.002Hz

±0.7% of I at 0.1×In＜I＜0.2×In

Current 0.1~4.00In ±0.4% of I at 0.2×In＜I＜0.5×In

±0.2% of I at 0.5×In＜I＜4.0×In

Voltage 5~300V 0.2% of U at 5V<U<300V

±1% of P, @Un, at 0.1×In＜I＜0.2×In

Active power (W) 0.1~4.00In
±0.5% of P, @Un, at 0.2×In＜I＜4.0×In

±1% of Q, @Un, at 0.1×In＜I＜0.2×In

Reactive power (VAr) 0.1~4.00In
±0.5% of Q, @Un, at 0.2×In＜I＜4.0×In

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 2 Technical Data

±1% of S, @Un, at 0.1×In＜I＜0.2×In

Apparent power (VA) 0.1~4.00In
±0.5% of S, @Un, at 0.2×In＜I＜4.0×In

±1% of Wh, @Un, at 0.1×In＜I＜0.2×In

Energy (Wh) 0.1~4.00In
±0.5% of Wh, @Un, at 0.2×In＜I＜4.0×In

±1% of VArh, @Un, at 0.1×In＜I＜0.2×In

2
Energy (VArh) 0.1~4.00In
±0.5% of VArh, @Un, at 0.2×In＜I＜4.0×In

2.10 Management Function

2.10.1 Control Performance

Control mode Local or remote

Response time of local control ≤1s

Response time of remote control ≤3s

2.10.2 Clock Performance

Real time clock accuracy ≤1s/day

Accuracy of GPS synchronization ≤1ms

External time synchronization IRIG-B (200-98), PPS, IEEE 1588 or SNTP protocol

2.10.3 Fault and Disturbance Recording

Settable pre-disturbance, post-disturbance and maximum recorded

Duration & Recording position
duration

Sampling rate Up to 9.6kHz

2.10.4 Binary Input Signal

Resolution of binary input signal ≤1ms

Binary input mode Potential-free contact

PCS-902S Line Distance Relay 2-15

Date: 2023-08-01
 2 Technical Data

2.11 Synchrophasor Measurement

2.11.1 Synchrophasor Measurement under Steady-state

2.11.1.1 P Class TVE Limit

2 Influence Quantity Reference Condition Range Max TVE (%)

Frequency range fn (50Hz, 60Hz) ±2.0Hz 0.5

Voltage magnitude 100% rated 80% to 120% rated 0.5

Current magnitude 100% rated 10% to 200% rated 0.5

Phase angle |fin–f0|<0.25Hz ±π radians 0.5

Single harmonic distortion <0.2% (THD) 1%, each harmonic up to 50th 1

Out-of-band interference <0.2% of input signal magnitude None None

2.11.1.2 M Class TVE Limit

Influence Quantity Reference Condition Range Max TVE (%)

Frequency range fn (50Hz, 60Hz) ±5.0Hz for Fs≥25 0.5

Voltage magnitude 100% rated 10% to 120% rated 0.5

Current magnitude 100% rated 10% to 200% rated 0.5

Phase angle |fin–f0|<0.25Hz ±π radians 0.5

Single harmonic distortion <0.2% (THD) 10%, each harmonic up to 50th 1

<0.2% of input signal 10% of input signal magnitude for

Out-of-band interference 1.3
magnitude Fs≥10

2.11.2 Frequency and ROCOF Measurement under Steady-state

2.11.2.1 P Class Error Limit

Influence Quantity Reference Condition Max FE

Signal frequency Frequency=fn 0.005Hz (range: f0±2.0)

Single harmonic distortion <0.2% (THD) Fs>20 0.005Hz (1% each harmonic up to 50th)

Out-of-band interference <0.2% of input signal magnitude No requirements

Influence Quantity Reference Condition Max RFE

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Signal frequency Frequency=fn 0.4Hz/s (range: f0±2.0)

Single harmonic distortion <0.2% (THD) Fs>20 0.4Hz/s (1% each harmonic up to 50th)

Out-of-band interference <0.2% of input signal magnitude No requirements

2.11.2.2 M Class Error Limit

Influence Quantity Reference Condition Max FE

2
Signal frequency Frequency=fn 0.005Hz (range: ±5.0Hz for Fs≥25)

Single harmonic distortion <0.2% (THD) Fs>20 0.025Hz (10% each harmonic up to 50th)

0.01Hz (interfering signal 10% of signal

Out-of-band interference <0.2% of input signal magnitude
magnitude)

Influence Quantity Reference Condition Max RFE

Signal frequency Frequency=fn 0.1Hz/s (range: ±5.0Hz for Fs≥25)

Single harmonic distortion <0.2% (THD) Fs>20 6Hz/s (10% each harmonic up to 50th)

0.1Hz/s (interfering signal 10% of signal

Out-of-band interference <0.2% of input signal magnitude
magnitude)

2.11.3 Active and Reactive Power Measurement under Steady-state

2.11.3.1 P Class Error Limit

Influence Quantity Reference Condition Range Max Err (%)

Frequency range fn (50Hz, 60Hz) ±2.0Hz 1

Voltage magnitude 100% rated 80% to 120% rated 1

Current magnitude 100% rated 10% to 200% rated 1

Phase angle |fin–f0|<0.25Hz ±π radians 1

Single harmonic distortion <0.2% (THD) 1%, each harmonic up to 50th 1

Out-of-band interference <0.2% of input signal magnitude None None

2.11.3.2 M Class Error Limit

Influence Quantity Reference Condition Range Max Err (%)

Frequency range fn (50Hz, 60Hz) ±5.0Hz for Fs≥25 1

Voltage magnitude 100% rated 10% to 120% rated 1

PCS-902S Line Distance Relay 2-17

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 2 Technical Data

Current magnitude 100% rated 10% to 200% rated 1

Phase angle |fin–f0|<0.25Hz ±π radians 1

Single harmonic distortion <0.2% (THD) 10%, each harmonic up to 50th 1

<0.2% of input signal 10% of input signal magnitude

Out-of-band interference 1.5
2 magnitude for Fs≥10

2.11.4 Synchrophasor Measurement under Modulation

Reference Condition: 100% rated signal magnitude, f nominal

2.11.4.1 P Class TVE Limit

Modulation Level Range Max TVE

kx=0.1, ka=0 radian 3%

Modulation frequency 0.1 to less of Fs/10 or 2Hz
kx=0, ka=0.1 radian 3%

2.11.4.2 M Class TVE Limit

Modulation Level Range Max TVE

kx=0.1, ka=0 radian 3%

Modulation frequency 0.1 to less of Fs/5 or 5Hz
kx=0, ka=0.1 radian 3%

2.11.5 Frequency and ROCOF Measurement under Modulation

Reference Condition: 100% rated signal magnitude, f nominal

2.11.5.1 P Class

Modulation Level Max FE Max RFE

kx=0.1, ka=0 radian 0.06 Hz 3 Hz/s

kx=0, ka=0.1 radian 0.06 Hz 3 Hz/s

2.11.5.2 M Class

Modulation Level Max FE Max RFE

kx=0.1, ka=0 radian 0.3 Hz 30 Hz/s

kx=0, ka=0.1 radian 0.3 Hz 30 Hz/s

2.11.6 Synchrophasor Measurement under Frequency Ramp

Reference Condition: 100% rated signal magnitude, & f nominal at start

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 2 Technical Data

TVE Limit
Test Signal
Ramp Rate PMU Class Ramp Range Max TVE

P class ±2Hz 1%
Linear frequency ramp ±1.0Hz/s
M class Less of ±(Fs/5) or ±5Hz 1%

2.11.7 Frequency and ROCOF Measurement under Frequency Ramp 2

Reference Condition: 100% rated signal magnitude and 0 radian base angle

2.11.7.1 P class

Test Signal Transition Time Error Requirements for Compliance

Max FE Max RFE

Ramp tests ±2/Fs for the start and end of ramp
0.01Hz 0.4Hz/s

2.11.7.2 M class

Test Signal Transition Time Error Requirements for Compliance

Max FE Max RFE

Ramp tests ±2/Fs for the start and end of ramp
0.01Hz 0.2Hz/s

2.11.8 Synchrophasor Measurement under Step Change

Reference Condition: all test conditions nominal at start or end of step

2.11.8.1 P class

Step Change Specification Response Time (s) |Delay time| (s) Max Overshoot/ Undershoot

Magnitude ±10%, kx=±0.1, ka=0 2/f0 1/(4×Fs) 5% of step magnitude

Angle ±10°, kx=0, ka=±π/18 2/f0 1/(4×Fs) 5% of step magnitude

2.11.8.2 M class

Step Change Specification Response Time (s) |Delay time| (s) Max Overshoot/ Undershoot

Magnitude ±10%, kx=±0.1, ka=0 7/Fs 1/(4×Fs) 10% of step magnitude

Angle ±10°, kx=0, ka=±π/18 7/Fs 1/(4×Fs) 10% of step magnitude

2.11.9 Frequency and ROCOF Measurement under Step Change

Reference Condition: all test conditions nominal at start or end of step

PCS-902S Line Distance Relay 2-19

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 2 Technical Data

2.11.9.1 P Class

Step Change Specification Frequency Response Time ROCOF Response Time

Magnitude step 5/f0 6/f0

Phase step 5/f0 6/f0

2 2.11.9.2 M Class

Step Change Specification Frequency Response Time ROCOF Response Time

Magnitude step 14/f0 Greater of 14/f0 or 14/Fs

Phase step 14/f0 Greater of 14/f0 or 14/Fs

2.11.10 Measurement Reporting Latency

Performance class Maximum Measurement Reporting Latency (s)

P class 2/Fs

M class 7/Fs

2.11.11 Synchrophasor Communication

Item Data

Output rate 100/50/25 FPS at 50Hz, 120/60/30/20/15/12/10 FPS at 60Hz

Supported protocol TCP, TCP-UDP, UDP (Unicast/Broadcast/Multicast)

Supported client number Max. 4 PDCs

2.12 Protective Functions

2.12.1 Fault Detector (FD)

2.12.1.1 DPFC Current Element

Current setting accuracy ≤2.5%×Setting or 0.02In, whichever is greater

2.12.1.2 Residual Current Element

Current setting accuracy ≤2.5%×Setting or 0.02In, whichever is greater

2.12.1.3 Negative-sequence Current Element

Current setting accuracy ≤2.5%×Setting or 0.02In, whichever is greater

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 2 Technical Data

2.12.2 Distance Protection (21L)

Impedance setting accuracy ≤2.5%×Setting or 0.1Ω, whichever is greater

Resetting ratio 1.05

Operating time accuracy ≤1%×Setting+30ms

≤5% (SIR≤30) 2
Transient overreaching
≤10% (SIR≥30)

2.12.3 Phase Overcurrent Protection (50/51P)

Without direction controlled element

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤25ms (at 2 times current setting)

Operating time accuracy (Definite-

≤1%×Setting or 25ms (at 2 times current setting)
time characteristics)

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
characteristics)

Dropout time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics)

Dropout time accuracy (Inverse-time

≤5% of calculated value or 30ms
characteristics)

Dropout ratio 0.95

With direction controlled element

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤40ms (at 2 times current setting)

Operating time accuracy (Definite-

≤1%×Setting or 40ms (at 2 times current setting)
time characteristics)

PCS-902S Line Distance Relay 2-21

Date: 2023-08-01
 2 Technical Data

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
characteristics)

Dropout time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics)

2 Dropout time accuracy (Inverse-time

≤5% of calculated value or 30ms
characteristics)

Dropout ratio 0.95

Phase angel accuracy ≤3°

2.12.4 Earth Fault Protection (50/51G)

Without direction controlled element

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Pickup time ≤25ms (at 2 times current setting)

Operating time accuracy (Definite-

≤1%×Setting or 25ms (at 2 times current setting)
time characteristics)

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
characteristics)

Dropout time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics)

Dropout time accuracy (Inverse-time

≤5% of calculated value or 30ms
characteristics)

Dropout ratio 0.95

With direction controlled element

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤40ms (at 2 times current setting)

Operating time accuracy (Definite- ≤1%×Setting or 40ms (at 2 times current setting)

2-22 PCS-902S Line Distance Relay

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 2 Technical Data

time characteristics)

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
characteristics)

Dropout time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics) 2
Dropout time accuracy (Inverse-time
≤5% of calculated value or 30ms
characteristics)

Dropout ratio 0.95

Phase angel accuracy ≤3°

2.12.5 Negative-sequence Overcurrent Protection (50/51Q)

Without direction controlled element

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Pickup time ≤25ms (at 2 times current setting)

Operating time accuracy (Definite-

≤1%×Setting or 25ms (at 2 times current setting)
time characteristics)

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
characteristics)

Dropout time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics)

Dropout time accuracy (Inverse-time

≤5% of calculated value or 30ms
characteristics)

Dropout ratio 0.95

With direction controlled element

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤40ms (at 2 times current setting)

PCS-902S Line Distance Relay 2-23

Date: 2023-08-01
 2 Technical Data

Operating time accuracy (Definite-

≤1%×Setting or 40ms (at 2 times current setting)
time characteristics)

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
characteristics)

2 Dropout time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics)

Dropout time accuracy (Inverse-time

≤5% of calculated value or 30ms
characteristics)

Dropout ratio 0.95

Phase angel accuracy ≤3°

2.12.6 Overvoltage Protection (59P)

Pickup voltage 1.0×Setting

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤35ms (at 1.1 times voltage setting)

Operating time accuracy (Definite-

≤1%×Setting or 35ms (at 1.1 times voltage setting)
time characteristics)

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% voltage tolerance or 40ms (1.1≤U/Up≤2)
characteristics)

Dropout time accuracy ≤1%×Setting or 30ms

Dropout ratio Settable 0.93~1.00, default value: 0.98

2.12.7 Negative-sequence Overvoltage Protection (59Q)

Pickup voltage 1.0×Setting

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤35ms (at 1.1 times voltage setting)

Operating time accuracy ≤1%×Setting or 35ms (at 1.1 times voltage setting)

Dropout time accuracy ≤1%×Setting or 30ms

Dropout ratio Settable 0.93~1.00, default value: 0.98

2-24 PCS-902S Line Distance Relay

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 2 Technical Data

2.12.8 Residual Overvoltage Protection (59G)

Pickup voltage 1.0×Setting

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤35ms (at 1.1 times voltage setting)

Operating time accuracy ≤1%×Setting or 35ms (at 1.1 times voltage setting) 2
Dropout time accuracy ≤1%×Setting or 30ms

Dropout ratio Settable 0.93~1.00, default value: 0.98

2.12.9 Undervoltage Protection (27P)

Pickup voltage 1.0×Setting

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤35ms (at 0.9 times voltage setting)

Operating time accuracy (Definite-

≤1%×Setting or 35ms (at 0.9 times voltage setting)
time characteristics)

Operating time accuracy (Inverse-time

≤5% of calculated value + 1% voltage tolerance or 50ms (U/Up≤0.9)
characteristics)

Dropout time accuracy ≤1%×Setting or 30ms

Dropout ratio Settable 1.00~1.20, default value: 1.03

2.12.10 Overfrequency Protection (81O)

Pickup frequency 1.0×Setting

Frequency setting accuracy ≤ 0.01Hz

Pickup time ≤70ms

Operating time accuracy ≤1%×Setting+70ms

Dropout time accuracy ≤40ms

Dropout frequency 1.0×Setting

2.12.11 Underfrequency Protection (81U)

Pickup frequency 1.0×Setting

Frequency setting accuracy ≤ 0.01Hz

PCS-902S Line Distance Relay 2-25

Date: 2023-08-01
 2 Technical Data

Pickup time ≤70ms

Operating time accuracy ≤1%×Setting+70ms

Dropout time accuracy ≤40ms

Dropout frequency 1.0×Setting

2 2.12.12 Frequency Rate-of-change Protection (81R)

Pickup frequency 1.0×Setting

Frequency rate-of-change setting

≤ 0.02Hz
accuracy

Pickup time ≤70ms

Operating time accuracy ≤1%×Setting+70ms

Dropout time accuracy ≤40ms

Dropout frequency 1.0×Setting

2.12.13 Reverse Power Protection (32R)

Pickup power 1.0×Setting

Power setting accuracy ≤2%×Setting or 0.01pu, whichever is greater

Current setting accuracy ≤1%×Setting or 0.01pu, whichever is greater

Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater

Pickup time ≤25ms (at 2 times power setting)

Operating time accuracy ≤1%×Setting or 25ms (at 2 times power setting)

Dropout time accuracy ≤30ms

Dropout ratio 0.95

2.12.14 Undercurrent Protection (37)

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Pickup time ≤25ms (at 0.5 times current setting)

Operating time accuracy ≤1%×Setting or 25ms (at 0.5 times current setting)

Dropout time accuracy ≤30ms

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 2 Technical Data

Dropout ratio 1.1

2.12.15 Breaker Failure Protection (50BF)

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Operating time accuracy ≤1%×Setting or 20ms (at 2 times current setting)

2
Pickup time ≤20ms (at 2 times current setting)

Dropout time <20ms (at 2 times current setting)

Dropout ratio 0.95

2.12.16 Stub Differential Protection (87STB)

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Operating time accuracy ≤1%×Setting or 30ms (at 2 times current setting)

Dropout ratio 0.97

2.12.17 Dead Zone Protection (50DZ)

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Operating time accuracy ≤1%×Setting or 30ms (at 2 times current setting)

Dropout ratio 0.97

2.12.18 Broken Conductor Protection (46BC)

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

I2/I1 setting accuracy ≤ 0.02

Operating time accuracy ≤1%×Setting or 30ms (at 2 times current setting)

Dropout ratio 0.98

2.12.19 Pole Discrepancy Protection (62PD)

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

PCS-902S Line Distance Relay 2-27

Date: 2023-08-01
 2 Technical Data

Operating time accuracy ≤1%×Setting or 30ms (at 2 times current setting)

Dropout ratio 0.97

2.12.20 Thermal Overload Protection (49P)

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

2 ≤5% of the calculated value + 1% of current tolerance, or 35ms
Operating time accuracy
(1.2≤I/Ip≤30)

Dropout time ≤30ms

2.12.21 Flashover Protection (50F)

Pickup current 1.0×Setting

Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Operating time accuracy ≤1%×Setting or 30ms (at 2 times current setting)

Dropout ratio 0.97

2.12.22 Transfer Trip (TT)

Pickup time 5ms

Operating time accuracy ≤1%×Setting or 5ms

2.12.23 Auto-reclosing (79)

Phase angel accuracy: ≤2°

Synchronism check Voltage setting accuracy: ≤1%×Setting or 0.1V, whichever is greater

Frequency setting accuracy: 0.01Hz

synchronism check time accuracy ≤1%×Setting+20ms

Reclaim time accuracy ≤1%×Setting+20ms

Reclosing time accuracy ≤1%×Setting+20ms

2.12.24 Transient Overreaching

Accuracy for all high-speed protection ≤2%

2.12.25 Impedance-Based Fault Location (FL)

Single-ended impedance-based For multi-phase faults: < ±2.5% (Tolerance will be higher in case of

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 2 Technical Data

method single-phase fault with high ground resistance.)

2.13 Communication Functions

2.13.1 GOOSE

Receiving Control Block (RCB) Max. 16 (Typical configuration: 50×FCD+200×BOOL+16×FLOAT)

2
Sending Control Block (SCB) Max. 8 (Typical configuration: 100×BOOL)

Receiving route delay Max. 2ms

Sending route delay Max. 3ms

The capacity of GOOSE receiving and sending is determined by the

number of configured boards and control & protection functions.

2.13.2 SV

Receiving Control Block (RCB) Max. 6 (per board)

Receiving route delay Max. 2ms

The capacity of SV receiving is determined by the number of configured

boards and control & protection functions.

PCS-902S Line Distance Relay 2-29

Date: 2023-08-01
 2 Technical Data

2-30 PCS-902S Line Distance Relay

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 3 Protection Functions

3 Protection Functions

Table of Contents

3.1 Three-phase Current Element (TCUR3P) ....................................................... 3-1

3.1.1 Function Description............................................................................................................. 3-1

3.1.2 Function Block Diagram ....................................................................................................... 3-1

3.1.3 I/O Signals ............................................................................................................................ 3-2

3
3.2 Three-phase Voltage Element (TVOL3P) ....................................................... 3-3
3.2.1 Function Description............................................................................................................. 3-3

3.2.2 Function Block Diagram ....................................................................................................... 3-3

3.2.3 I/O Signals ............................................................................................................................ 3-4

3.3 Single-phase Current Element (TCUR1P) ...................................................... 3-4

3.3.1 Function Description............................................................................................................. 3-4

3.3.2 Function Block Diagram ....................................................................................................... 3-5

3.3.3 I/O Signals ............................................................................................................................ 3-5

3.4 System Parameters ......................................................................................... 3-5

3.4.1 Function Description............................................................................................................. 3-5

3.4.2 Settings................................................................................................................................. 3-6

3.5 Circuit Breaker Position Supervision ............................................................ 3-8

3.5.1 Function Description............................................................................................................. 3-8

3.5.2 Function Block Diagram ....................................................................................................... 3-8

3.5.3 I/O Signals ............................................................................................................................ 3-9

3.5.4 Logic ................................................................................................................................... 3-10

3.6 Fault Detector (FD) ........................................................................................ 3-12

3.6.1 Function Description........................................................................................................... 3-12

3.6.2 Function Block Diagram ..................................................................................................... 3-14

3.6.3 I/O Signals .......................................................................................................................... 3-14

3.6.4 Logic ................................................................................................................................... 3-15

3.6.5 Settings............................................................................................................................... 3-15

PCS-902S Line Distance Relay 3-a

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 3 Protection Functions

3.7 Optical Pilot Channel (FO) ............................................................................ 3-15

3.7.1 Function Description........................................................................................................... 3-16

3.7.2 Function Block Diagram ..................................................................................................... 3-22

3.7.3 I/O Signals .......................................................................................................................... 3-22

3.7.4 Logic ................................................................................................................................... 3-22

3.7.5 Settings............................................................................................................................... 3-23

3.8 Pilot Distance Protection (85) ....................................................................... 3-23

3 3.8.1 Functions Description ......................................................................................................... 3-24

3.8.2 Function Block Diagram ..................................................................................................... 3-42

3.8.3 I/O Signals .......................................................................................................................... 3-42

3.8.4 Settings............................................................................................................................... 3-43

3.9 Pilot Directional Earth-fault Protection (85) ................................................ 3-45

3.9.1 Functions Description ......................................................................................................... 3-45

3.9.2 Function Block Diagram ..................................................................................................... 3-53

3.9.3 I/O Signals .......................................................................................................................... 3-53

3.9.4 Settings............................................................................................................................... 3-54

3.10 DPFC Distance Protection (21D) ................................................................ 3-55

3.10.1 Functions Description ....................................................................................................... 3-55

3.10.2 Function Block Diagram ................................................................................................... 3-57

3.10.3 I/O Signals ........................................................................................................................ 3-57

3.10.4 Logic ................................................................................................................................. 3-58

3.10.5 Settings............................................................................................................................. 3-59

3.11 Distance Protection (21L)............................................................................ 3-59

3.11.1 Functions Description ....................................................................................................... 3-59

3.11.2 Quadrilateral Distance Protection..................................................................................... 3-60

3.11.3 Mho Distance Protection .................................................................................................. 3-63

3.11.4 Zero-sequence Current Compensation ............................................................................ 3-68

3.11.5 Load Encroachment ......................................................................................................... 3-70

3.11.6 Power Swing Blocking and Releasing.............................................................................. 3-70

3.11.7 Faulty Phase Selection ..................................................................................................... 3-73

3-b PCS-902S Line Distance Relay

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 3 Protection Functions

3.11.8 Time Delay Characteristics ............................................................................................... 3-76

3.11.9 Function Block Diagram ................................................................................................... 3-77

3.11.10 I/O Signals ...................................................................................................................... 3-77

3.11.11 Logic................................................................................................................................ 3-79

3.11.12 Settings ........................................................................................................................... 3-85

3.12 Series Compensation .................................................................................. 3-91

3.12.1 Series Compensation System Introduction ...................................................................... 3-92

3.12.2 Functions Description ....................................................................................................... 3-93 3

3.13 Out-of-step Protection (78) ......................................................................... 3-97
3.13.1 Function Description ........................................................................................................ 3-98

3.13.2 Function Block Diagram ................................................................................................. 3-103

3.13.3 I/O Signals ...................................................................................................................... 3-103

3.13.4 Logic ............................................................................................................................... 3-103

3.13.5 Settings........................................................................................................................... 3-104

3.14 Distance SOTF Protection (21SOTF)........................................................ 3-105

3.14.1 Function Description ...................................................................................................... 3-105

3.14.2 Function Block Diagram ................................................................................................. 3-106

3.14.3 I/O Signals ...................................................................................................................... 3-106

3.14.4 Logic ............................................................................................................................... 3-106

3.14.5 Settings........................................................................................................................... 3-109

3.15 Phase Overcurrent Protection (50/51P) ....................................................3-110

3.15.1 Function Description .......................................................................................................3-111

3.15.2 Function Block Diagram ................................................................................................. 3-121

3.15.3 I/O Signal ........................................................................................................................ 3-122

3.15.4 Logic ............................................................................................................................... 3-123

3.15.5 Settings........................................................................................................................... 3-123

3.16 Phase Current SOTF Protection (50PSOTF) ............................................ 3-128

3.16.1 Function Description ...................................................................................................... 3-128

3.16.2 Function Block Diagram ................................................................................................. 3-129

3.16.3 I/O Signals ...................................................................................................................... 3-129

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 3 Protection Functions

3.16.4 Logic ............................................................................................................................... 3-129

3.16.5 Settings........................................................................................................................... 3-130

3.17 Earth Fault Protection (50/51G) ................................................................ 3-131

3.17.1 Function Description ...................................................................................................... 3-131

3.17.2 Function Block Diagram ................................................................................................. 3-140

3.17.3 I/O Signal ........................................................................................................................ 3-140

3.17.4 Logic ............................................................................................................................... 3-141

3 3.17.5 Settings........................................................................................................................... 3-141

3.18 Residual Current SOTF Protection (50GSOTF) ....................................... 3-145

3.18.1 Function Description ...................................................................................................... 3-145

3.18.2 Function Block Diagram ................................................................................................. 3-146

3.18.3 I/O Signals ...................................................................................................................... 3-146

3.18.4 Logic ............................................................................................................................... 3-146

3.18.5 Settings........................................................................................................................... 3-147

3.19 Negative-sequence Overcurrent Protection (50/51Q) ............................. 3-147

3.19.1 Function Description ...................................................................................................... 3-147

3.19.2 Function Block Diagram ................................................................................................. 3-155

3.19.3 I/O Signal ........................................................................................................................ 3-155

3.19.4 Logic ............................................................................................................................... 3-156

3.19.5 Settings........................................................................................................................... 3-156

3.20 Phase Overvoltage Protection (59P) ........................................................ 3-159

3.20.1 Function Description ...................................................................................................... 3-159

3.20.2 Function Block Diagram ................................................................................................. 3-164

3.20.3 I/O Signal ........................................................................................................................ 3-165

3.20.4 Logic ............................................................................................................................... 3-166

3.20.5 Settings........................................................................................................................... 3-166

3.21 Residual Overvoltage Protection (59G) ................................................... 3-168

3.21.1 Function Description ...................................................................................................... 3-168

3.21.2 Function Block Diagram ................................................................................................. 3-170

3.21.3 I/O Signal ........................................................................................................................ 3-170

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 3 Protection Functions

3.21.4 Logic ............................................................................................................................... 3-171

3.21.5 Settings........................................................................................................................... 3-171

3.22 Negative-sequence Overvoltage Protection (59Q) ................................. 3-171

3.22.1 Function Description ...................................................................................................... 3-172

3.22.2 Function Block Diagram ................................................................................................. 3-174

3.22.3 I/O Signals ...................................................................................................................... 3-174

3.22.4 Logic ............................................................................................................................... 3-174

3.22.5 Settings........................................................................................................................... 3-175 3

3.23 Phase Undervoltage Protection (27P) ...................................................... 3-175
3.23.1 Function Description ...................................................................................................... 3-175

3.23.2 Function Block Diagram ................................................................................................. 3-180

3.23.3 I/O Signal ........................................................................................................................ 3-180

3.23.4 Logic ............................................................................................................................... 3-181

3.23.5 Settings........................................................................................................................... 3-182

3.24 Overfrequency Protection (81O) .............................................................. 3-184

3.24.1 Function Description ...................................................................................................... 3-184

3.24.2 Function Block Diagram ................................................................................................. 3-185

3.24.3 I/O Signals ...................................................................................................................... 3-185

3.24.4 Logic ............................................................................................................................... 3-186

3.24.5 Settings........................................................................................................................... 3-186

3.25 Underfrequency Protection (81U)............................................................. 3-186

3.25.1 Function Description ...................................................................................................... 3-187

3.25.2 Function Block Diagram ................................................................................................. 3-188

3.25.3 I/O Signals ...................................................................................................................... 3-188

3.25.4 Logic ............................................................................................................................... 3-189

3.25.5 Settings........................................................................................................................... 3-189

3.26 Frequency Rate-of-change Protection (81R) ........................................... 3-189

3.26.1 Function Description ...................................................................................................... 3-189

3.26.2 Function Block Diagram ................................................................................................. 3-191

3.26.3 I/O Signals ...................................................................................................................... 3-191

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 3 Protection Functions

3.26.4 Logic ............................................................................................................................... 3-192

3.26.5 Settings........................................................................................................................... 3-192

3.27 Reverse Power Protection (32R) .............................................................. 3-192

3.27.1 Function Description ...................................................................................................... 3-193

3.27.2 Function Block Diagram ................................................................................................. 3-194

3.27.3 I/O Signals ...................................................................................................................... 3-194

3.27.4 Logic ............................................................................................................................... 3-195

3 3.27.5 Settings........................................................................................................................... 3-195

3.28 Thermal Overload Protection (49P) .......................................................... 3-196

3.28.1 Function Description ...................................................................................................... 3-196

3.28.2 Function Block Diagram ................................................................................................. 3-199

3.28.3 I/O Signals ...................................................................................................................... 3-200

3.28.4 Settings........................................................................................................................... 3-200

3.29 Undercurrent Protection (37) .................................................................... 3-201

3.29.1 Function Description ...................................................................................................... 3-201

3.29.2 Function Block Diagram ................................................................................................. 3-204

3.29.3 I/O Signals ...................................................................................................................... 3-204

3.29.4 Logic ............................................................................................................................... 3-205

3.29.5 Settings........................................................................................................................... 3-205

3.30 Breaker Failure Protection (50BF) ............................................................ 3-206

3.30.1 Function Description ...................................................................................................... 3-206

3.30.2 Function Block Diagram ................................................................................................. 3-209

3.30.3 I/O Signals ...................................................................................................................... 3-209

3.30.4 Logic ............................................................................................................................... 3-210

3.30.5 Settings........................................................................................................................... 3-213

3.31 Stub Differential Protection (87STB) ........................................................ 3-214

3.31.1 Function Description ...................................................................................................... 3-215

3.31.2 Function Block Diagram ................................................................................................. 3-216

3.31.3 I/O Signals ...................................................................................................................... 3-216

3.31.4 Logic ............................................................................................................................... 3-217

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 3 Protection Functions

3.31.5 Settings........................................................................................................................... 3-219

3.32 Dead Zone Protection (50DZ) ................................................................... 3-219

3.32.1 Function Description ...................................................................................................... 3-219

3.32.2 Function Block Diagram ................................................................................................. 3-220

3.32.3 I/O Signals ...................................................................................................................... 3-220

3.32.4 Logic ............................................................................................................................... 3-220

3.32.5 Settings........................................................................................................................... 3-221

3.33 Broken Conductor Protection (46BC) ...................................................... 3-221 3

3.33.1 Function Description ...................................................................................................... 3-222

3.33.2 Function Block Diagram ................................................................................................. 3-222

3.33.3 I/O Signals ...................................................................................................................... 3-222

3.33.4 Logic ............................................................................................................................... 3-223

3.33.5 Settings........................................................................................................................... 3-223

3.34 Pole Discrepancy Protection (62PD) ........................................................ 3-224

3.34.1 Function Description ...................................................................................................... 3-224

3.34.2 Function Block Diagram ................................................................................................. 3-224

3.34.3 I/O Signals ...................................................................................................................... 3-224

3.34.4 Logic ............................................................................................................................... 3-225

3.34.5 Settings........................................................................................................................... 3-226

3.35 Flashover Protection (50F) ....................................................................... 3-226

3.35.1 Function Description ...................................................................................................... 3-226

3.35.2 Function Block Diagram ................................................................................................. 3-227

3.35.3 I/O Signals ...................................................................................................................... 3-227

3.35.4 Logic ............................................................................................................................... 3-227

3.35.5 Settings........................................................................................................................... 3-228

3.36 Transfer Trip (TT) ....................................................................................... 3-228

3.36.1 Function Description ...................................................................................................... 3-229

3.36.2 Function Block Diagram ................................................................................................. 3-229

3.36.3 I/O Signals ...................................................................................................................... 3-229

3.36.4 Logic ............................................................................................................................... 3-230

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 3 Protection Functions

3.36.5 Settings........................................................................................................................... 3-231

3.37 Trip Logic (TRP) ......................................................................................... 3-232

3.37.1 Function Description ...................................................................................................... 3-232

3.37.2 Function Block Diagram ................................................................................................. 3-233

3.37.3 I/O Signals ...................................................................................................................... 3-233

3.37.4 Logic ............................................................................................................................... 3-234

3.37.5 Settings........................................................................................................................... 3-237

3 3.38 Automatic Reclosure (79).......................................................................... 3-237
3.38.1 Function Description ...................................................................................................... 3-238

3.38.2 Function Block Diagram ................................................................................................. 3-252

3.38.3 I/O Signals ...................................................................................................................... 3-253

3.38.4 Settings........................................................................................................................... 3-254

3.39 VT Circuit Supervision (VTS) .................................................................... 3-257

3.39.1 Function Description ...................................................................................................... 3-257

3.39.2 Function Block Diagram ................................................................................................. 3-258

3.39.3 I/O Signals ...................................................................................................................... 3-258

3.39.4 Logic ............................................................................................................................... 3-259

3.39.5 Settings........................................................................................................................... 3-260

3.40 CT Circuit Supervision (CTS) ................................................................... 3-260

3.40.1 Function Description ...................................................................................................... 3-260

3.40.2 Function Block Diagram ................................................................................................. 3-261

3.40.3 I/O Signals ...................................................................................................................... 3-261

3.40.4 Logic ............................................................................................................................... 3-261

3.40.5 Settings........................................................................................................................... 3-262

3.41 Impedance-Based Fault Location (FL) ..................................................... 3-262

3.41.1 Function Description ...................................................................................................... 3-262

3.41.2 Function Block Diagram ................................................................................................. 3-266

3.41.3 I/O Signals ...................................................................................................................... 3-267

3.41.4 Settings........................................................................................................................... 3-267

3-h PCS-902S Line Distance Relay

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 3 Protection Functions

List of Figures

Figure 3.5-1 Logic of trip&closing circuit supervision.......................................................... 3-10

Figure 3.5-2 Logic of CB position supervision ...................................................................... 3-10

Figure 3.5-3 Logic of circuit breaker position ........................................................................ 3-11

Figure 3.5-4 Logic of pole open states ................................................................................... 3-12

Figure 3.6-1 Logic of fault detector ......................................................................................... 3-15

Figure 3.7-1 Direct optical link up to 2km with 850nm .......................................................... 3-16 3
Figure 3.7-2 Direct optical link up to 60km with 1310nm or up to 120km with 1550nm .... 3-17

Figure 3.7-3 Connect to a communication network via communication convertor .......... 3-17

Figure 3.7-4 Connect to a communication network via MUX-64 .......................................... 3-18

Figure 3.7-5 Connect to a communication network via MUX-2M ......................................... 3-18

Figure 3.7-6 Schematic diagram of communication channel time ...................................... 3-21

Figure 3.7-7 Logic of receiving signal i................................................................................... 3-22

Figure 3.7-8 Logic of sending signal i ..................................................................................... 3-22

Figure 3.7-9 Logic of channel alarm ........................................................................................ 3-23

Figure 3.8-1 Logic of enabling pilot distance protection ...................................................... 3-24

Figure 3.8-2 Logic of receiving signal ..................................................................................... 3-26

Figure 3.8-3 Logic of zone extension ...................................................................................... 3-27

Figure 3.8-4 Simple schematic of PUTT .................................................................................. 3-28

Figure 3.8-5 Logic of pilot distance protection (PUTT) ......................................................... 3-30

Figure 3.8-6 Simple schematic of POTT ................................................................................. 3-30

Figure 3.8-7 Logic of pilot distance protection (POTT) ......................................................... 3-34

Figure 3.8-8 Simple schematic of system fault ...................................................................... 3-35

Figure 3.8-9 Simple schematic of blocking ............................................................................ 3-35

Figure 3.8-10 Logic of pilot distance protection (Blocking) ................................................. 3-36

Figure 3.8-11 Logic of pilot distance protection (Unblocking) ............................................. 3-37

Figure 3.8-12 Current reversal ................................................................................................. 3-37

Figure 3.8-13 Logic of current reversal blocking ................................................................... 3-38

Figure 3.8-14 Line fault description......................................................................................... 3-39

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Figure 3.8-15 Weak infeed logic during pickup...................................................................... 3-40

Figure 3.8-16 Weak infeed echo logic without pickup .......................................................... 3-40

Figure 3.8-17 Weak infeed trip logic without pickup ............................................................. 3-41

Figure 3.8-18 Simplified CB echo logic for POTT .................................................................. 3-41

Figure 3.9-1 Logic of enabling pilot directional earth-fault protection ............................... 3-46

Figure 3.9-2 Logic of receiving signal ..................................................................................... 3-46

Figure 3.9-3 Simple schematic of permissive scheme.......................................................... 3-47

3 Figure 3.9-4 Logic of pilot directional earth-fault protection (permissive scheme) .......... 3-48

Figure 3.9-5 Simple schematic of blocking ............................................................................ 3-49

Figure 3.9-6 Logic of pilot directional earth-fault protection (Blocking)............................. 3-50

Figure 3.9-7 Logic of pilot directional earth-fault protection (Unblocking) ........................ 3-51

Figure 3.9-8 Current reversal ................................................................................................... 3-51

Figure 3.9-9 Logic of current reversal blocking ..................................................................... 3-52

Figure 3.9-10 Simplified CB Echo logic for POTT.................................................................. 3-53

Figure 3.10-1 Operation characteristic for forward fault ...................................................... 3-56

Figure 3.10-2 Operation characteristic for reverse fault ....................................................... 3-57

Figure 3.10-3 Logic of DPFC distance protection .................................................................. 3-58

Figure 3.11-1 Quadrilateral forward direction distance element .......................................... 3-60

Figure 3.11-2 Quadrilateral reverse direction distance element .......................................... 3-61

Figure 3.11-3 Quadrilateral non direction distance element ................................................ 3-61

Figure 3.11-4 Shift impedance characteristics of forward direction ................................... 3-62

Figure 3.11-5 Shift impedance characteristics of reverse direction .................................... 3-62

Figure 3.11-6 Mho forward direction distance element ......................................................... 3-64

Figure 3.11-7 Mho reverse direction distance element ......................................................... 3-64

Figure 3.11-8 Mho non-direction distance element ............................................................... 3-65

Figure 3.11-9 Shift mho impedance characteristics .............................................................. 3-66

Figure 3.11-10 Phase-to-ground operating characteristics for forward fault ..................... 3-66

Figure 3.11-11 Phase-to-phase operating characteristics for forward fault ....................... 3-67

Figure 3.11-12 Operating characteristics for reverse fault ................................................... 3-67

Figure 3.11-13 Operating characteristics of three-phase close up fault ............................. 3-67

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 3 Protection Functions

Figure 3.11-14 Operating characteristics of three-phase close up fault ............................. 3-68

Figure 3.11-15 Phase-to-phase mutual inductance ............................................................... 3-68

Figure 3.11-16 Zero-sequence mutual inductance for double-circuit lines ........................ 3-69

Figure 3.11-17 Distance element with load encroachment ................................................... 3-70

Figure 3.13-18 Faulty phase selection based on I2 and I0.................................................... 3-74

Figure 3.13-19 Logic of faulty phase selection for AG fault ................................................. 3-74

Figure 3.13-20 Faulty phase selection based on I2 and I0.................................................... 3-75

Figure 3.13-21 Logic of faulty phase selection for ACG fault............................................... 3-75 3
Figure 3.13-22 Logic of faulty phase selection for AB fault and ABC fault ........................ 3-76

Figure 3.11-19 Logic of enabling distance protection (i=1~6) .............................................. 3-79

Figure 3.11-20 Logic of enabling short time delay (i=2~6) .................................................... 3-79

Figure 3.11-21 Logic of zone 1 of distance protection (phase-to-ground).......................... 3-80

Figure 3.11-22 Logic of zone 1 of distance protection (phase-to-phase)............................ 3-81

Figure 3.11-23 Logic of distance protection (phase-to-ground, i=2~6) ............................... 3-82

Figure 3.11-24 Logic of distance protection (phase-to-phase, i=2~6) ................................. 3-83

Figure 3.11-25 Logic of distance protection operating (zone 1) .......................................... 3-83

Figure 3.11-26 Logic of distance protection operating (zone i, i=2~6) ................................ 3-84

Figure 3.11-27 Logic of PSBR (i=1~6) ..................................................................................... 3-84

Figure 3.12-1 The schematic diagram of series compensation system.............................. 3-92

Figure 3.12-2 The influence on short-circuit impedance ...................................................... 3-93

Figure 3.12-3 Equivalent circuit of series compensated line ............................................... 3-94

Figure 3.12-4 Equivalent circuit of internal fault in series compensated line .................... 3-94

Figure 3.12-5 Voltage variation of DPFC distance protection .............................................. 3-95

Figure 3.12-6 Zone 1 overreaching during external fault in forward direction ................... 3-96

Figure 3.12-7 Asymmetrical fault ............................................................................................. 3-97

Figure 3.13-1 Dual-machine equivalent system ..................................................................... 3-98

Figure 3.13-2 Dual-machine equivalent system ..................................................................... 3-99

Figure 3.13-3 Variation curve of oscillation center voltage (Acceleration) ....................... 3-100

Figure 3.13-4 Variation curve of oscillation center voltage (Deceleration) ....................... 3-100

Figure 3.13-5 The variation rule of oscillation center voltage ............................................ 3-101

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Figure 3.13-6 Vector diagram of the oscillation center voltage ......................................... 3-101

Figure 3.13-7 Operation characteristic of zone detector element ..................................... 3-102

Figure 3.13-8 Logic of enabling out-of-step protection ...................................................... 3-103

Figure 3.13-9 Logic of out-of-step protection ...................................................................... 3-104

Figure 3.14-1 Logic of enabling distance SOTF protection ................................................ 3-106

Figure 3.14-2 Logic of auto-reclosing signal........................................................................ 3-106

Figure 3.14-3 Logic of manual closing signal ...................................................................... 3-107

3 Figure 3.14-4 Logic of distance SOTF protection by manual closing signal (i=2~4) ....... 3-108

Figure 3.14-5 Logic of distance SOTF protection by 1-pole or 3-pole AR (i=2~4)............ 3-108

Figure 3.14-6 Logic of distance SOTF protection ................................................................ 3-109

Figure 3.15-1 Logic of enabling phase overcurrent protection...........................................3-111

Figure 3.15-2 Pickup logic of phase overcurrent protection ...............................................3-111

Figure 3.15-3 Logic of voltage control element ................................................................... 3-112

Figure 3.15-4 Operating characteristics of the direction element ..................................... 3-112

Figure 3.15-5 Logic of forward and reverse direction element .......................................... 3-115

Figure 3.15-6 Logic of harmonic control element................................................................ 3-116

Figure 3.15-7 Definite-time operating curve of phase overcurrent protection ................. 3-117

Figure 3.15-8 Inverse-time operating curve of phase overcurrent protection ................. 3-118

Figure 3.15-9 Definite-time dropout characteristics of phase overcurrent protection .... 3-119

Figure 3.15-10 Inverse-time dropout curve of phase overcurrent protection .................. 3-120

Figure 3.15-11 Inverse-time dropout characteristics of phase overcurrent protection .. 3-121

Figure 3.15-12 Logic of phase overcurrent protection........................................................ 3-123

Figure 3.16-1 Logic of phase current SOTF protection....................................................... 3-130

Figure 3.17-1 Blocking scheme configuration ..................................................................... 3-132

Figure 3.17-2 Logic of enabling earth fault protection ........................................................ 3-132

Figure 3.17-3 Pickup logic of earth fault protection ............................................................ 3-132

Figure 3.17-4 Operating characteristics of direction control element .............................. 3-133

Figure 3.17-5 Logic of forward and reverse direction element .......................................... 3-134

Figure 3.17-6 Logic of harmonic control element................................................................ 3-135

Figure 3.17-7 Definite-time operating curve of earth fault protection ............................... 3-136

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 3 Protection Functions

Figure 3.17-8 Inverse-time operating curve of earth fault protection................................ 3-136

Figure 3.17-9 Definite-time dropout characteristics of earth fault protection .................. 3-138

Figure 3.17-10 Inverse-time dropout curve of earth fault protection ................................ 3-139

Figure 3.17-11 Inverse-time dropout characteristics of earth fault protection................. 3-140

Figure 3.17-12 Logic diagram of earth fault protection....................................................... 3-141

Figure 3.18-1 Logic of residual current SOTF protection ................................................... 3-147

Figure 3.19-1 Blocking scheme configuration ..................................................................... 3-148

Figure 3.19-2 Logic of enabling negative-sequence overcurrent protection ................... 3-148 3

Figure 3.19-3 Pickup logic of negative-sequence overcurrent protection........................ 3-148

Figure 3.19-4 Operating characteristics of direction control element .............................. 3-149

Figure 3.19-5 Logic of forward and reverse direction element .......................................... 3-150

Figure 3.19-6 Definite-time operating curve of NOC protection......................................... 3-151

Figure 3.19-7 Inverse-time operating curve of NOC protection ......................................... 3-152

Figure 3.19-8 Definite-time dropout characteristics of NOC protection ........................... 3-153

Figure 3.19-9 Inverse-time dropout curve of NOC protection ............................................ 3-154

Figure 3.19-10 Inverse-time dropout characteristics of NOC protection .......................... 3-155

Figure 3.19-11 Logic of negative-sequence overcurrent protection ................................. 3-156

Figure 3.20-1 Logic of enabling phase overvoltage protection ......................................... 3-160

Figure 3.20-2 Pickup logic of phase overvoltage protection.............................................. 3-161

Figure 3.20-3 Definite-time operating curve of phase overvoltage protection................. 3-162

Figure 3.20-4 Inverse-time operating curve of phase overvoltage protection ................. 3-163

Figure 3.20-5 Definite-time dropout characteristics of phase overvoltage protection ... 3-164

Figure 3.20-6 Logic of phase overvoltage protection ......................................................... 3-166

Figure 3.21-1 Logic of enabling residual overvoltage protection ...................................... 3-168

Figure 3.21-2 Pickup logic of residual overvoltage protection .......................................... 3-169

Figure 3.21-3 Definite-time operating curve of residual overvoltage protection ............. 3-169

Figure 3.21-4 Definite-time dropout characteristics of residual overvoltage protection 3-170

Figure 3.21-5 Logic of residual overvoltage protection ...................................................... 3-171

Figure 3.22-1 Logic of enabling negative-sequence overvoltage protection ................... 3-172

Figure 3.22-2 Pickup logic of negative-sequence overvoltage protection ....................... 3-172

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Figure 3.22-3 Definite-time operating curve of NOV protection ......................................... 3-173

Figure 3.22-4 Definite-time dropout characteristics of NOV protection............................ 3-173

Figure 3.22-5 Logic of negative-sequence overvoltage protection ................................... 3-174

Figure 3.23-1 Logic of enabling phase undervoltage protection ....................................... 3-176

Figure 3.23-2 Pickup logic of phase undervoltage protection ........................................... 3-177

Figure 3.23-3 Definite-time operating curve of phase undervoltage protection .............. 3-178

Figure 3.23-4 Inverse-time operating curve of phase undervoltage protection ............... 3-178
3 Figure 3.23-5 Definite-time dropout characteristics of phase undervoltage protection . 3-179

Figure 3.23-6 Logic of phase undervoltage protection ....................................................... 3-181

Figure 3.24-1 Logic of enabling overfrequency protection ................................................ 3-184

Figure 3.24-2 Pickup logic of overfrequency protection .................................................... 3-184

Figure 3.24-3 Definite-time operating curve of overfrequency protection ....................... 3-185

Figure 3.24-4 Logic of overfrequency protection ................................................................ 3-186

Figure 3.25-1 Logic of enabling underfrequency protection .............................................. 3-187

Figure 3.25-2 Pickup logic of underfrequency protection .................................................. 3-187

Figure 3.25-3 Definite-time operating curve of underfrequency protection ..................... 3-187

Figure 3.25-4 Logic of underfrequency protection .............................................................. 3-189

Figure 3.26-1 Logic of enabling frequency rate-of-change protection.............................. 3-190

Figure 3.26-2 Pickup logic of frequency rate-of-change protection .................................. 3-190

Figure 3.26-3 Definite-time operating curve of frequency rate-of-change protection ..... 3-190

Figure 3.26-4 Logic of frequency rate-of-change protection.............................................. 3-192

Figure 3.27-1 Logic of enabling reverse power protection ................................................. 3-193

Figure 3.27-2 Pickup logic of reverse power protection ..................................................... 3-193

Figure 3.27-3 Definite-time operating curve of reverse power protection ........................ 3-194

Figure 3.27-4 Logic of reverse power protection ................................................................. 3-195

Figure 3.28-1 Characteristic curve of thermal overload model .......................................... 3-197

Figure 3.28-2 Logic of enabling thermal overload protection ............................................ 3-197

Figure 3.28-3 Pickup logic of thermal overload protection ................................................ 3-198

Figure 3.28-4 Logic of thermal overload protection (phase A)........................................... 3-198

Figure 3.28-5 Logic of thermal overload protection ............................................................ 3-198

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Figure 3.29-1 Logic of enabling undercurrent protection ................................................... 3-202

Figure 3.29-2 Pickup logic of undercurrent protection ....................................................... 3-203

Figure 3.29-3 Definite-time operating curve of undercurrent protection .......................... 3-203

Figure 3.29-4 Logic of undercurrent protection ................................................................... 3-205

Figure 3.30-1 Logic of enabling breaker failure protection ................................................ 3-210

Figure 3.30-2 Breaker failure initiating logic by internal tripping ...................................... 3-210

Figure 3.30-3 Logic of breaker failure initiating signal abnormality.................................. 3-211

Figure 3.30-4 Logic of current/contact check (phase-segregated) .................................... 3-211 3

Figure 3.30-5 Logic of current/contact check (three-phase) .............................................. 3-212

Figure 3.30-6 Logic of breaker failure protection (phase-segregated).............................. 3-212

Figure 3.30-7 Logic of breaker failure protection (three-phase) ........................................ 3-213

Figure 3.31-1 Application for one-and-half circuit breakers ............................................... 3-215

Figure 3.31-2 Logic of enabling stub differential protection .............................................. 3-217

Figure 3.31-3 Logic of stub differential protection .............................................................. 3-218

Figure 3.32-1 Logic of enabling dead zone protection........................................................ 3-220

Figure 3.32-2 Logic of dead zone protection........................................................................ 3-221

Figure 3.33-1 Logic of enabling broken conductor protection .......................................... 3-223

Figure 3.33-2 Logic of broken conductor protection .......................................................... 3-223

Figure 3.34-1 Logic of enabling pole discrepancy protection............................................ 3-225

Figure 3.34-2 Logic of pole discrepancy protection............................................................ 3-225

Figure 3.35-1 Logic of enabling flashover protection ......................................................... 3-227

Figure 3.35-2 Logic of falshover protection ......................................................................... 3-228

Figure 3.36-1 Logic of enabling transfer trip ........................................................................ 3-230

Figure 3.36-2 Logic of transfer trip ........................................................................................ 3-231

Figure 3.37-1 Tripping logic.................................................................................................... 3-236

Figure 3.37-2 Breaker failure initiation logic ........................................................................ 3-236

Figure 3.38-1 Logic of enabling AR ....................................................................................... 3-238

Figure 3.38-2 Logic of AR mode selection ........................................................................... 3-239

Figure 3.38-3 Logic of synchronism check mode selection for AR................................... 3-239

Figure 3.38-4 Logic of synchronism check for AR .............................................................. 3-240

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Figure 3.38-5 Logic of AR block............................................................................................. 3-241

Figure 3.38-6 Logic of AR ready ............................................................................................ 3-242

Figure 3.38-7 Logic of tripping condition output ................................................................. 3-243

Figure 3.38-8 1-pole AR initiation (single-phase tripping) .................................................. 3-243

Figure 3.38-9 3-pole AR initiation (three-phases tripping).................................................. 3-244

Figure 3.38-10 1-pole AR initiation (single-phase CB state) ............................................... 3-244

Figure 3.38-11 3-pole AR initiation (three-phases CB state)............................................... 3-245

3 Figure 3.38-12 One-shot AR ................................................................................................... 3-245

Figure 3.38-13 Extra time delay of AR ................................................................................... 3-246

Figure 3.38-14 Reclosing output logic .................................................................................. 3-246

Figure 3.38-15 Wait to slave signal ........................................................................................ 3-247

Figure 3.38-16 Reclosing failure and success ..................................................................... 3-247

Figure 3.38-17 Single-phase transient fault.......................................................................... 3-250

Figure 3.38-18 Single-phase permanent fault ...................................................................... 3-250

Figure 3.38-19 Three-phase transient fault........................................................................... 3-251

Figure 3.38-20 Three-phase permanent fault ....................................................................... 3-251

Figure 3.39-1 Logic of VT circuit supervision (delay alarm)............................................... 3-259

Figure 3.39-2 Logic of VT circuit supervision (instantaneous alarm) ............................... 3-259

Figure 3.40-1 Logic of enabling CT circuit failure ............................................................... 3-261

Figure 3.40-2 Logic of CT circuit failure ............................................................................... 3-262

Figure 3.41-1 Schematic diagram of mutual coupling for parallel lines ........................... 3-263

Figure 3.41-2 Equivalent sequence network ........................................................................ 3-263

Figure 3.41-3 Equivalent circuit of single-phase fault with fault resistance .................... 3-265

List of Tables

Table 3.1-1 Output signals of three-phase current element ................................................... 3-2

Table 3.2-1 Input signals of three-phase voltage element ...................................................... 3-4

Table 3.2-2 Output signals of three-phase voltage element ................................................... 3-4

Table 3.3-1 Output signals of single-phase current element .................................................. 3-5

Table 3.4-1 System settings ....................................................................................................... 3-6

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Table 3.5-1 Input signals of CB position supervision ............................................................. 3-9

Table 3.5-2 Output signals of CB position supervision ........................................................ 3-10

Table 3.6-1 Output signals of fault detector ........................................................................... 3-14

Table 3.6-2 Settings of fault detector ...................................................................................... 3-15

Table 3.7-1 Input signals of optical pilot channel .................................................................. 3-22

Table 3.7-2 Output signals of optical pilot channel ............................................................... 3-22

Table 3.7-3 Settings of optical pilot channel .......................................................................... 3-23

Table 3.8-1 Input signals of pilot distance protection ........................................................... 3-42 3

Table 3.8-2 Output signals of pilot distance protection ........................................................ 3-43

Table 3.8-3 Settings of pilot distance protection ................................................................... 3-43

Table 3.9-1 Input signals of pilot directional earth-fault protection..................................... 3-53

Table 3.9-2 Output signals of pilot directional earth-fault protection ................................. 3-54

Table 3.9-3 Settings of pilot directional earth-fault protection............................................. 3-54

Table 3.10-1 Input signals of DPFC distance protection ....................................................... 3-57

Table 3.10-2 Output signals of DPFC distance protection .................................................... 3-58

Table 3.10-3 Settings of DPFC distance protection ............................................................... 3-59

Table 3.11-1 Input signals of distance protection .................................................................. 3-77

Table 3.11-2 Output signals of distance protection ............................................................... 3-78

Table 3.11-3 Settings of distance protection .......................................................................... 3-85

Table 3.11-4 Settings of pilot distance zone ........................................................................... 3-88

Table 3.13-1 Input signals of out-of-step protection ........................................................... 3-103

Table 3.13-2 Output signals of out-of-step protection ........................................................ 3-103

Table 3.13-3 Settings of out-of-step protection.................................................................... 3-104

Table 3.14-1 Input signals of distance SOTF protection ..................................................... 3-106

Table 3.14-2 Output signals of distance SOTF protection .................................................. 3-106

Table 3.14-3 Settings of distance SOTF protection ............................................................. 3-109

Table 3.15-1 Input signals of phase overcurrent protection ............................................... 3-122

Table 3.15-2 Output signals of phase overcurrent protection............................................ 3-122

Table 3.15-3 Settings of phase overcurrent protection ....................................................... 3-123

Table 3.16-1 Input signals of phase current SOTF protection............................................ 3-129

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Table 3.16-2 Output signals of phase current SOTF protection......................................... 3-129

Table 3.16-3 Settings of phase current SOTF protection .................................................... 3-130

Table 3.17-1 Input signals of earth fault protection ............................................................. 3-140

Table 3.17-2 Output signals of earth fault protection .......................................................... 3-140

Table 3.17-3 Settings of earth fault protection ..................................................................... 3-141

Table 3.18-1 Input signals of residual current SOTF protection ........................................ 3-146

Table 3.18-2 Output signals of residual current SOTF protection ..................................... 3-146
3 Table 3.18-3 Settings of residual current SOTF protection ................................................ 3-147

Table 3.19-1 Input signals of negative-sequence overcurrent protection ........................ 3-155

Table 3.19-2 Output signals of negative-sequence overcurrent protection ..................... 3-155

Table 3.19-3 Settings of negative-sequence overcurrent protection ................................ 3-156

Table 3.20-1 Input signals of phase overvoltage protection .............................................. 3-165

Table 3.20-2 Output signals of phase overvoltage protection ........................................... 3-165

Table 3.20-3 Settings of phase overvoltage protection....................................................... 3-166

Table 3.21-1 Input signals of residual overvoltage protection ........................................... 3-170

Table 3.21-2 Output signals of residual overvoltage protection ........................................ 3-171

Table 3.21-3 Settings of residual overvoltage protection ................................................... 3-171

Table 3.22-1 Input signals of negative-sequence overvoltage protection ........................ 3-174

Table 3.22-2 Output signals of negative-sequence overvoltage protection ..................... 3-174

Table 3.22-3 Settings of negative-sequence overvoltage protection ................................ 3-175

Table 3.23-1 Input signals of phase undervoltage protection ............................................ 3-180

Table 3.23-2 Output signals of phase undervoltage protection ......................................... 3-180

Table 3.23-3 Settings of phase undervoltage protection .................................................... 3-182

Table 3.24-1 Input signals of overfrequency protection ..................................................... 3-185

Table 3.24-2 Output signals of overfrequency protection .................................................. 3-185

Table 3.24-3 Settings of overfrequency protection ............................................................. 3-186

Table 3.25-1 Input signals of underfrequency protection ................................................... 3-188

Table 3.25-2 Output signals of underfrequency protection ................................................ 3-188

Table 3.25-3 Settings of underfrequency protection ........................................................... 3-189

Table 3.26-1 Input signals of frequency rate-of-change protection ................................... 3-191

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Table 3.26-2 Output signals of frequency rate-of-change protection ................................ 3-191

Table 3.26-3 Settings of frequency rate-of-change protection ........................................... 3-192

Table 3.27-1 Input signals of reverse power protection ...................................................... 3-194

Table 3.27-2 Output signals of reverse power protection ................................................... 3-195

Table 3.27-3 Settings of reverse power protection .............................................................. 3-195

Table 3.28-1 Input signals of thermal overload protection ................................................. 3-200

Table 3.28-2 Output signals of thermal overload protection .............................................. 3-200

Table 3.28-3 Settings of thermal overload protection ......................................................... 3-200 3

Table 3.29-1 Input signals of undercurrent protection ........................................................ 3-204

Table 3.29-2 Output signals of undercurrent protection ..................................................... 3-204

Table 3.29-3 Settings of undercurrent protection ................................................................ 3-205

Table 3.30-1 Input signals of breaker failure protection ..................................................... 3-209

Table 3.30-2 Output signals of breaker failure protection .................................................. 3-209

Table 3.30-3 Settings of breaker failure protection ............................................................. 3-213

Table 3.31-1 Input signals of stub differential protection ................................................... 3-216

Table 3.31-2 Output signals of stub differential protection ................................................ 3-217

Table 3.31-3 Settings of stub differential protection ........................................................... 3-219

Table 3.32-1 Input signals of dead zone protection ............................................................. 3-220

Table 3.32-2 Output signals of dead zone protection.......................................................... 3-220

Table 3.32-3 Settings of dead zone protection ..................................................................... 3-221

Table 3.33-1 Input signals of broken conductor protection ............................................... 3-222

Table 3.33-2 Output signals of broken conductor protection ............................................ 3-222

Table 3.33-3 Settings of broken conductor protection........................................................ 3-223

Table 3.34-1 Input signals of pole discrepancy protection ................................................. 3-224

Table 3.34-2 Output signals of pole discrepancy protection.............................................. 3-225

Table 3.34-3 Settings of pole discrepancy protection ......................................................... 3-226

Table 3.35-1 Input signals of flashover protection .............................................................. 3-227

Table 3.35-2 Output signals of flashover protection ........................................................... 3-227

Table 3.35-3 Settings of pole discrepancy protection ......................................................... 3-228

Table 3.36-1 Input signals of transfer trip ............................................................................. 3-229

PCS-902S Line Distance Relay 3-s

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 3 Protection Functions

Table 3.36-2 Output signals of transfer trip .......................................................................... 3-230

Table 3.36-3 Settings of transfer trip ..................................................................................... 3-231

Table 3.37-1 Input signals of trip logic .................................................................................. 3-233

Table 3.37-2 Output signals of trip logic ............................................................................... 3-233

Table 3.37-3 Settings of trip logic .......................................................................................... 3-237

Table 3.38-1 Reclosing number ............................................................................................. 3-249

Table 3.38-2 Input signals of AR ............................................................................................ 3-253

3 Table 3.38-3 Output signals of AR ......................................................................................... 3-253

Table 3.38-4 Settings of AR .................................................................................................... 3-254

Table 3.39-1 Input signals of VT circuit supervision ........................................................... 3-258

Table 3.39-2 Output signals of VT circuit supervision ........................................................ 3-258

Table 3.39-3 Settings of VT circuit supervision ................................................................... 3-260

Table 3.40-1 Input signals of CT circuit supervision ........................................................... 3-261

Table 3.40-2 Output signals of CT circuit supervision ........................................................ 3-261

Table 3.40-3 Settings of CT circuit supervision ................................................................... 3-262

Table 3.41-1 Input signals of fault location........................................................................... 3-267

Table 3.41-2 Output signals of fault location........................................................................ 3-267

Table 3.41-3 Settings of fault location ................................................................................... 3-267

3-t PCS-902S Line Distance Relay

Date: 2023-08-01
 3 Protection Functions

PCS-902S Line Distance Relay 3-u

Date: 2023-08-01
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 3 Protection Functions

3.1 Three-phase Current Element (TCUR3P)

Three-phase current element is responsible for pre-processing the sampled value of three-phases
currents and calculating sequence components, amplitudes and phase angles of three phase
currents, etc. All calculated information of three-phase current element is used for protection logic
calculation.

3.1.1 Function Description

Three-phase current element has following functions:

1. Pre-process three phase currents

3
2. Calculate information related to three-phase current

When any phase current is greater than 0.04In, the input current signals are valid and the valid
signal will be used by programmable logic application. CT circuit supervision of three-phase current
is carried out to detect whether CT circuit fails, which can refer to section 3.40 for details.

3.1.2 Function Block Diagram

TCUR3P TCUR3P

Prot.CBx.Ia_Sec Prot.Ia_Sec

Prot.CBx.Ib_Sec Prot.Ib_Sec

Prot.CBx.Ic_Sec Prot.Ic_Sec

Prot.CBx.I1_Sec Prot.I1_Sec

Prot.CBx.I2_Sec Prot.I2_Sec

Prot.CBx.3I0_Cal_Sec Prot.3I0_Cal_Sec

Prot.CBx.Ang(Ia-Ib) Prot.Ang(Ia-Ib)

Prot.CBx.Ang(Ib-Ic) Prot.Ang(Ib-Ic)

Prot.CBx.Ang(Ic-Ia) Prot.Ang(Ic-Ia)

Prot.CBx.Ang(Ia) Prot.Ang(Ia)

Prot.CBx.Ang(Ib) Prot.Ang(Ib)

Prot.CBx.Ang(Ic) Prot.Ang(Ic)

Prot.CBx.Ang(3I0_Cal) Prot.Ang(3I0_Cal)

Prot.CBx.Flg_OnLoad Prot.Flg_OnLoad

PCS-902S Line Distance Relay 3-1

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 3 Protection Functions

3.1.3 I/O Signals

Table 3.1-1 Output signals of three-phase current element

No. Output Signal Description

The amplitude of phase-A current corresponding to circuit breaker No.x
1 Prot.CBx.Ia_Sec
(secondary value)
The amplitude of phase-B current corresponding to circuit breaker No.x
2 Prot.CBx.Ib_Sec
(secondary value)
The amplitude of phase-C current corresponding to circuit breaker No.x
3 Prot.CBx.Ic_Sec
(secondary value)

3 4 Prot.CBx.I1_Sec
The amplitude of positive-sequence current corresponding to circuit breaker
No.x (secondary value)
The amplitude of negative-sequence current corresponding to circuit breaker
5 Prot.CBx.I2_Sec
No.x (secondary value)
The amplitude of calculated residual current corresponding to circuit breaker
6 Prot.CBx.3I0_Cal_Sec
No.x (secondary value)
Phase angle between phase-A and phase-B currents corresponding to circuit
7 Prot.CBx.Ang(Ia-Ib)
breaker No.x
Phase angle between phase-B and phase-C currents corresponding to circuit
8 Prot.CBx.Ang(Ib-Ic)
breaker No.x
Phase angle between phase-C and phase-A currents corresponding to circuit
9 Prot.CBx.Ang(Ic-Ia)
breaker No.x
10 Prot.CBx.Ang(Ia) Phase angle of phase-A current corresponding to circuit breaker No.x
11 Prot.CBx.Ang(Ib) Phase angle of phase-B current corresponding to circuit breaker No.x
12 Prot.CBx.Ang(Ic) Phase angle of phase-C current corresponding to circuit breaker No.x
Phase angle of calculated residual current corresponding to circuit breaker
13 Prot.CBx.Ang(3I0_Cal)
No.x
14 Prot.CBx.Flg_OnLoad Any phase current corresponding to circuit breaker No.x is greater than 0.04In
15 Ia_Sec The amplitude of phase-A current (secondary value)
16 Ib_Sec The amplitude of phase-B current (secondary value)
17 Ic_Sec The amplitude of phase-C current (secondary value)
18 I1_Sec The amplitude of positive-sequence current (secondary value)
19 I2_Sec The amplitude of negative-sequence current (secondary value)
20 3I0_Cal_Sec The amplitude of calculated residual current (secondary value)
21 Ang(Ia-Ib) Phase angle between phase-A and phase-B currents
22 Ang(Ib-Ic) Phase angle between phase-B and phase-C currents
23 Ang(Ic-Ia) Phase angle between phase-C and phase-A currents
24 Ang(Ia) Phase angle of phase-A current
25 Ang(Ib) Phase angle of phase-B current
26 Ang(Ic) Phase angle of phase-C current
27 Ang(3I0_Cal) Phase angle of calculated residual current
28 Flg_OnLoad Any phase current is greater than 0.04In

3-2 PCS-902S Line Distance Relay

Date: 2023-08-01
 3 Protection Functions

3.2 Three-phase Voltage Element (TVOL3P)

Three-phase voltage element is responsible for pre-processing the sampled value of three-phases
voltages and calculating sequence components, amplitudes and phases of three phase voltages,
etc. All calculated information of three-phase voltage element is used for the protection logic
calculation.

3.2.1 Function Description

Three-phase voltage element has following functions:

1. Pre-process three-phase voltages 3

2. Calculate information related to three phase voltages

VT circuit supervision of three-phase voltage is carried out to detect whether VT circuit fails, which
can refer to section 3.39 for details.

3.2.2 Function Block Diagram

TVOL3P

Prot.BI_En_VT Prot.Ua_Sec

Prot.Ub_Sec

Prot.Uc_Sec

Prot.U1_Sec

Prot.U2_Sec

Prot.3U0_Cal_Sec

Prot.Ang(Ua-Ub)

Prot.Ang(Ub-Uc)

Prot.Ang(Uc-Ua)

Prot.Ang(Ua)

Prot.Ang(Ub)

Prot.Ang(Uc)

Prot.Ang(3U0_Cal)

Prot.Ang(U1)

Prot.Ang(U2)

PCS-902S Line Distance Relay 3-3

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 3 Protection Functions

3.2.3 I/O Signals

Table 3.2-1 Input signals of three-phase voltage element

No. Input Signal Description

1 Prot.BI_En_VT Input signal of indicating that VT is in service

Table 3.2-2 Output signals of three-phase voltage element

No. Output Signal Description

1 Prot.Ua_Sec The amplitude of phase-A voltage (secondary value)
2 Prot.Ub_Sec The amplitude of phase-B voltage (secondary value)
3 3 Prot.Uc_Sec The amplitude of phase-C voltage (secondary value)
4 Prot.U1_Sec The amplitude of positive-sequence voltage (secondary value)
5 Prot.U2_Sec The amplitude of negative-sequence voltage (secondary value)
6 Prot.3U0_Cal_Sec The amplitude of calculated residual voltage (secondary value)
7 Ang(Ua-Ub) Phase angle between phase-A and phase-B voltages
8 Ang(Ub-Uc) Phase angle between phase-B and phase-C voltages
9 Ang(Uc-Ua) Phase angle between phase-C and phase-A voltages
10 Ang(Ua) Phase angle of phase-A voltage
11 Ang(Ub) Phase angle of phase-B voltage
12 Ang(Uc) Phase angle of phase-C voltage
13 Ang(3U0_Cal) Phase angle of calculated residual voltage
14 Ang(U1) Phase angle of positive-sequence voltage
15 Ang(U2) Phase angle of negative-sequence voltage

3.3 Single-phase Current Element (TCUR1P)

Single-phase current element is responsible for pre-processing residual current from parallel line
and calculates the magnitude and the phase angle, etc. All calculated information of single-phase
current element is used to accurately locate the fault for parallel lines arrangement.

3.3.1 Function Description

Single-phase current element has following functions:

1. Pre-process measured single-phase current

2. Calculate information related to single-phase current

3-4 PCS-902S Line Distance Relay

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 3 Protection Functions

3.3.2 Function Block Diagram

TCUR1P

3I0Adj.3I0_Ext_Sec

3I0Adj.Ang(3I0_Ext)

3I0Adj.Flg_OnLoad

3.3.3 I/O Signals

Table 3.3-1 Output signals of single-phase current element
3
No. Output Signal Description
1 3I0Adj.3I0_Ext_Sec The amplitude of residual current from parallel line (secondary value)
2 3I0Adj.Ang(3I0_Ext) Phase angle of residual current from parallel line
3 3I0Adj.Flg_OnLoad Single-phase current is greater than 0.04In

3.4 System Parameters

The device performs various protection functions by respective algorithms with the information
(currents and voltages) acquired from primary system through current transformer and voltage
transformer, so it is important to configure analogue input channels correctly.

Further to correct configuration of analogue input channels, other protected system information,
such as the parameters of voltage transformer and current transformer are also required.

The device is suitable for one-and-half circuit breakers arrangement, the summation current from
double circuit breakers is used to participate logic calculation. The summation current can be
fulfilled through secondary circuit outside the device if the ratio of dual CTs is the same, and the
device needs to be set as single circuit breaker mode. Furthermore, the summation current can
also be fulfilled inside the device by connecting the tow currents to the device, and the device
should be set as double circuit breakers mode. If the ratio of dual CTs is different, the CT ratio of
the first current circuit is fixed as the basis for current transformation.

3.4.1 Function Description

The device generally considers transmission line as its protected object, current flows from busbar
to line is considered as the forward direction.

The device uses a sampling rate of 24 samples per cycle, and the amplitudes of voltage and current
are calculated through Fourier filter algorithm. The data window is 1 cycle, and the actual amplitude
can be achieved when the cycle is expired. Two cycles of pre-fault voltage are memorized when
three-phase voltage drops suddenly due to a close up symmetrical solid fault.

PCS-902S Line Distance Relay 3-5

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 3 Protection Functions

3.4.2 Settings
Table 3.4-1 System settings

Name Range Step Unit Default Description

The number of active setting
group, several setting groups
Active_Grp 1~20 1 1 can be configured for
protection settings, and only
one is active at a time.
Name of the protected primary
3 PrimaryEquip_Name
Max
characters
20
DeviceName equipment, such as busbar,
transformer, etc.
Opt_SysFreq 50, 60 Hz 50Hz The system frequency.
This setting informs the device
of the actual system phase
sequence, either ABC or ACB.
ABC CT and VT inputs on the
Opt_PhSeq ABC
ACB device, labeled as A, B and C,
must be connected to system
phase A, B and C for correct
operation.
Primary rated voltage of VT
Prot.U1n 0.00~1100.00 0.01 kV 220.00 (protection voltage, phase-to-
phase value)
Secondary rated voltage of VT
Prot.U2n 1.00~500.00 0.01 V 100.00 (protection voltage, phase-to-
phase value)
Primary rated value of CT
corresponding to circuit
Prot.CBx.I1n 0~60000 1 A 1000
breaker No.x (protection
current)
Secondary rated value of CT
corresponding to circuit
Prot.CBx.I2n 1 or 5 A 1
breaker No.x (protection
current)
Primary rated voltage of
busbar No.1 VT (synchronism
UB1.Syn.U1n 0.00~1100.00 0.01 kV 220.00
voltage, phase-to-phase
value)
Secondary rated voltage of
busbar No.1 VT (synchronism
UB1.Syn.U2n 1.00~500.00 0.01 V 100.00
voltage, phase-to-phase
value)
UL2.Syn.U1n 0.00~1100.00 0.01 kV 220.00 Primary rated voltage of line

3-6 PCS-902S Line Distance Relay

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 3 Protection Functions

Name Range Step Unit Default Description

No.2 VT (synchronism
voltage, phase-to-phase
value)
Secondary rated voltage of
line No.2 VT (synchronism
UL2.Syn.U2n 1.00~500.00 0.01 V 100.00
voltage, phase-to-phase
value)
Primary rated voltage of
busbar No.2 VT (synchronism
UB2.Syn.U1n 0.00~1100.00 0.01 kV 220.00
voltage, phase-to-phase 3
value)
Secondary rated voltage of
busbar No.2 VT (synchronism
UB2.Syn.U2n 1.00~500.00 0.01 V 100.00
voltage, phase-to-phase
value)
Primary rated value of CT
3I0Adj.I1n 0~60000 1 A 1000 (residual current for mutual
coupling compensation)
Secondary rated value of CT
3I0Adj.I2n 1 or 5 A 1 (residual current for mutual
coupling compensation)
It is used to adjust the current
polarity of CT corresponding
to circuit breaker No.x.
Disabled
Prot.CBx.En_RevCT Disabled Disabled: keep connected
Enabled
current polarity unchanged
Enabled: make connected
current polarity reversed
It is used to adjust residual
current polarity from parallel
line.
Disabled
3I0Adj.En_RevCT Disabled Disabled: keep connected
Enabled
current polarity unchanged
Enabled: make connected
current polarity reversed
Enabling/disabling VT connect
Disabled
Prot.En_VT Enabled to the device, which is used for
Enabled
protection calculation
NoVoltSel Option of circuit breaker No.x
DblBusOneCB configuration, and it should be
CBx.VoltSel.Opt_CBConfig 3/2BusCB1 NoVoltSel set as "NoVoltSel" if no
3/2TieCB voltage selection is adopted.
3/2BusCB2 NoVoltSel: no voltage

PCS-902S Line Distance Relay 3-7

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 3 Protection Functions

Name Range Step Unit Default Description

selection
DblBusOneCB: one circuit
breaker for double busbar
3/2BusCB1: bus 1 side circuit
breaker for one and a half
breakers
3/2TieCB: line side circuit
breaker for one and a half
breakers

3 3/2BusCB2: bus 2 side circuit

breaker for one and a half
breakers

3.5 Circuit Breaker Position Supervision

The status of circuit breaker (CB) position is applied for protection and control functions in this
device, such as, SOTF protection, auto-reclose and VT circuit supervision, etc. The status of CB
position can be applied as input signals for other features configured by user.

3.5.1 Function Description

The signal reflecting CB position is acquired via the binary input with settable delay pickup and
drop-off, and forms digital signal used by protection functions. CB position can reflect the status of
each phase by means of phase-segregated inputs.

In order to prevent that incorrect status of CB position is input into the device via binary input, the
appropriate monitor method is used to check the rationality of the binary input. When the binary
input of CB open position is detected, the status of CB position will be supposed as incorrect and
an alarm [Alm_52b] will be issued if there is current detected in the line.

Together with the status of circuit breaker and the information of external circuit, this function can
be used to supervise control circuit of circuit breaker.

External manual closing binary input (ManCls) is only used for SOTF logic application, the control
of circuit breaker (CB) closing or opening should refer to Section 4.1.

3.5.2 Function Block Diagram

1. For phase-segregated circuit breaker

3-8 PCS-902S Line Distance Relay

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 3 Protection Functions

CB Position Supervision

CBx.52b_PhA CBx.Alm_52b

CBx.52b_PhB

CBx.52b_PhC

CBx.ManCls

CBx.Test

2. For non-phase segregated circuit breaker

3
TCCS

CBx.52a CBx.Alm_52b

CBx.52b CBx.TCCS.Alm

CBx.TCCS.Input

CBx.ManCls

CBx.Test

Trip&closing circuit supervision (TCCS) will be disabled automatically when it is used for phase-
segregated circuit breaker. x=1 or 2

3.5.3 I/O Signals

Table 3.5-1 Input signals of CB position supervision

No. Input Signal Description

1 CBx.52b_PhA Normally closed contact of A-phase of circuit breaker No.x
2 CBx.52b_PhB Normally closed contact of B-phase of circuit breaker No.x
3 CBx.52b_PhC Normally closed contact of C-phase of circuit breaker No.x
Maintenance status binary input of circuit breaker No.x
If any circuit breaker is in maintenance and out of service, CBx.52b or CBx.Test
4 CBx.Test should be set as "1" in fixed, and CB No.x will not be taken effect in corresponding
protection logics. (CB position supervision is still kept.) It is only available for
double circuit breakers mode.
External manual closing binary input of circuit breaker No.x, it is only applied to
5 CBx.ManCls
SOTF logic
6 CBx.52b Normally closed contact of three-phase of circuit breaker No.x
7 CBx.52a Normally open contact of three-phase of circuit breaker No.x
Control circuit failure of circuit breaker No.x (normally closed contacts of tripping
8 CBx.TCCS.Input position (52b) and closing position (52a) of three-phase circuit breaker are all de-
energized due to DC power loss of control circuit)

PCS-902S Line Distance Relay 3-9

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 3 Protection Functions

Table 3.5-2 Output signals of CB position supervision

No. Output Signal Description

1 CBx.Alm_52b Circuit breaker No.x position is abnormal
2 CBx.TCCS.Alm Control circuit of circuit breaker No.x is abnormal

The signal [CBx.52a] only takes effect in the tripping/closing circuit

supervision and not to affect any protection function. Only if tripping/closing
circuit supervision is configured, this signal needs to be connected to the
3 device.

3.5.4 Logic

BI [CBx.52a] >=1
>=1
BI [CBx.52b] 10s 10s CBx.TCCS.Alm

BI [CBx.TCCS.Input]

Figure 3.5-1 Logic of trip&closing circuit supervision

BI CBx.52b_PhA >=1
&
&
BI CBx.52b_PhB >=1
& &
>=1
10s 10s CBx.Alm_52b
BI CBx.52b_PhC >=1 >=1
&
BI CBx.52b

&

SIG CBx.Ia>I_Line

& >=1

SIG CBx.Ib>I_Line

&

SIG CBx.Ic>I_Line

Figure 3.5-2 Logic of CB position supervision

3-10 PCS-902S Line Distance Relay

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 3 Protection Functions

BI [CB1.52b_PhA] >=1
&
52b_PhA

BI [CB1.52b_PhB] >=1

BI [CB1.52b_PhC]
>=1
BI [CB1.52b]

BI [CB1.Test]
&
52b_PhB
BI [CB2.52b_PhA] >=1 3

BI [CB2.52b_PhB] >=1

BI [CB2.52b_PhC]
&
>=1 52b_PhC
BI [CB2.52b]

BI [CB2.Test]

Figure 3.5-3 Logic of circuit breaker position

x=1 or 2

I_Line is threshold value used to determine whether line is on-load or no-load. Default value 0.04In.

If there is any single phase tripping or breaker status [52b_Phx]=1 (x can be A, B or C) and
corresponding phase current is smaller than 0.04In, then single pole open state is confirmed by the
device.

If there is three pole tripping or breaker status of three phases are all open and three phase currents
are all smaller than 0.04In, then three pole open state is confirmed by the device.

PCS-902S Line Distance Relay 3-11

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 3 Protection Functions

SIG 52b_PhA &

50ms 0ms
SIG Ia<I_Line

SIG 52b_PhB &

50ms 0ms
SIG Ib<I_Line

SIG 52b_PhC &

50ms 0ms
SIG Ic<I_Line

>=1
3 SIG Trp A S
SET
Q &
50ms 0ms
Pole A open

SIG FD.Pkp R CLR Q

SIG Ia<I_Line
>=1
SET
SIG Trp B S Q & Pole B open
50ms 0ms
R CLR Q
SIG Ib<I_Line
>=1
SET
SIG Trp C S Q & Pole C open
50ms 0ms
R CLR Q
SIG Ic<I_Line

Figure 3.5-4 Logic of pole open states

Where:

TrpA, TrpB and TrpC are the tripping signals of the device.

3.6 Fault Detector (FD)

Fault detector is responsible to determine the fault appearance on the protected power system.
The device will switch to protection calculation after the fault detector picks up, for example the
calculation of distance protection, and to determine the operating logic. If the fault is within the
protected zone, the device will issue tripping command.

3.6.1 Function Description

The current amplitude is calculated based on the injected analogue quantities. The fault detector
continuously detects the change of phase-to-phase power frequency current and the calculated
zero-sequence and negative-sequence currents. The fault detector includes:

1. Fault detector based on DPFC current: DPFC current is greater than the setting value

2. Fault detector based on zero-sequence current: Zero-sequence current is greater than the setting
value

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 3 Protection Functions

3. Fault detector based on negative-sequence current: Negative-sequence current is greater than

the setting value

If any of the above conditions is satisfied, the fault detector will operate to start protection
calculation. The fault detectors based on DPFC current and zero-sequence current are always
enabled, and fault detector based on negative-sequence current could be enabled or disabled by
the setting. Pilot distance protection, pilot directional earth-fault protection, distance protection and
DPFC distance protection are controlled by these fault detector.

3.6.1.1 Fault Detector Based on DPFC Current

DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from that of a
cycle before. 3

I(k) is the current sampling point.

I(k-24) is the value of the sampling point before a cycle, 24 is the sampling points cycle.

200

100

-100

-200
0 20 40 60 80 100 120
Original Current
100

50

-50

-100
0 20 40 60 80 100 120
DPFC current

From above figures, it is concluded that DPFC can reflect the sudden change of current at the initial
stage of a fault and has a perfect performance of fault detection. It is used to determine whether
this pickup condition is met according to Equation 3.6-1.

For multi-phase short-circuit fault, DPFC phase-to-phase current has high sensitivity to ensure the
pickup of protection device. For usual single phase to earth fault, it also has sufficient sensitivity to
pick up except the earth fault with very large fault resistance. Under this condition, DPFC current
may be very small and the sensitivity is reduced, however, zero-sequence current is used to
remedy the reduction of the sensitivity.

This element adopts adaptive floating threshold varied with the change of load current continuously.
The change of load current is small and steady under normal or power swing condition, the adaptive
floating threshold with the ΔISet is higher than the change of current under these conditions and
hence maintains the element stability.

PCS-902S Line Distance Relay 3-13

Date: 2023-08-01
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 3 Protection Functions

The criterion is:

ΔIΦΦMAX>1.25ΔITh+ΔISet Equation 3.6-1

Where:

ΔIΦΦMAX: The maximum half-wave integration value of phase-to-phase current (ΦΦ=AB, BC, CA)

ΔISet: The fixed threshold value (i.e. the setting [FD.DPFC.I_Set])

ΔITh: The floating threshold value

The coefficient, 1.25, is an empirical value which ensures that the threshold is always higher than
3 the unbalance current of the system.

If operation condition are satisfied, the fault detector based on DPFC current will operate. The
pickup signal will maintain 5s after the fault detector based on DPFC current drops off.

3.6.1.2 Fault Detector Based on Zero-sequence Current

The operation condition will be satisfied when zero-sequence current (3I0) is greater than the
setting [FD.ROC.3I0_Set]. The fault detector based on zero-sequence current is always in service.

If operation condition are satisfied, the fault detector based on zero-sequence current will operate.
The pickup signal will maintain 5s after the fault detector based on zero-sequence current drops
off. (3I0: zero-sequence current is calculated from the vector sum of Ia, Ib and Ic)

3.6.1.3 Fault Detector Based on Negative-sequence Current

The operation condition will be satisfied when negative-sequence current (I2) is greater than the
setting [FD.NOC.I2_Set]. It can be enabled or disabled by the setting [FD.NOC.En].

If operation condition are satisfied, the fault detector based on negative-sequence current will
operate. The pickup signal will maintain 5s after the fault detector based on negative-sequence
current drops off.

3.6.2 Function Block Diagram

FD

FD.Pkp

FD.DPFC.Pkp

FD.ROC.Pkp

FD.NOC.Pkp

Alm_Pkp_FD

3.6.3 I/O Signals

Table 3.6-1 Output signals of fault detector

No. Output Signal Description

3-14 PCS-902S Line Distance Relay

Date: 2023-08-01
 3 Protection Functions

1 FD.Pkp The device picks up

2 FD.DPFC.Pkp DPFC current fault detector element operates.
3 FD.ROC.Pkp Zero-sequence current fault detector element operates.
4 FD.NOC.Pkp Negative-sequence fault detector element operates.
5 Alm_Pkp_FD Fault detector element operates for more than 50s.

3.6.4 Logic

SIG Ia Calculate DPFC phase-to- ΔIab>[FD.DPFC.I_Set]

phase current: >=1
ΔIab=Δ(Ia-Ib)
SIG Ib ΔIbc>[FD.DPFC.I_Set] FD.DPFC.Pkp

3
ΔIbc=Δ(Ib-Ic)
ΔIca=Δ(Ic-Ia)
SIG Ic ΔIca>[FD.DPFC.I_Set] >=1
0s 5s FD.Pkp

Calculate residual current:

3I0>[FD.ROC.3I0_Set] FD.ROC.Pkp
3I0=Ia+Ib+Ic

Calculate negative-
sequence current: I2
I2>[FD.NOC.I2_Set] &
FD.NOC.Pkp
EN FD.NOC.En

SIG FD.Pkp 50s 10s Alm_Pkp_FD

Figure 3.6-1 Logic of fault detector

3.6.5 Settings
Table 3.6-2 Settings of fault detector

Name Range Step Unit Default Remark

Current setting of DPFC current fault
FD.DPFC.I_Set (0.050~40.000)×In 0.001 A 0.100
detector element
Current setting of residual current
FD.ROC.3I0_Set (0.050~40.000)×In 0.001 A 0.100
fault detector element
Current setting of negative-sequence
FD.NOC.I2_Set (0.050~40.000)×In 0.001 A 0.100
current fault detector element
Enabling/disabling negative-
Disabled
FD.NOC.En Disabled sequence current fault detector
Enabled
element

3.7 Optical Pilot Channel (FO)

The devices can transmit Boolean quantities such as blocking signal, permissive signal and transfer
trip signal to the remote end via optical fibre channel. Up to 2 optical fibre channels are supported,
which can be dedicated optical fibre channel or multiplex channel, the channel mode could be
selected as single-mode or multi-mode. The communication rate can be 64kbits/s or 2048kbits/s,

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 3 Protection Functions

and G.703 or C37.94 are optional for communication protocol.

3.7.1 Function Description

8 digital bits are integrated in each frame of transmission message for various applications, and 8
binary signals are configurable. Each received message frame via fibre optical channel will pass
through security check to ensure the integrity of the message consistently. The communication
channel can be configured as single channel mode or as dual channels mode. (FOx, x can be 1 or
2) according to the optical pilot channel module selected.

3.7.1.1 Channel Interface

3 The device can adopt dedicated optical fibre channel or multiplex channel. The dedicated fibre channel
is usually recommended unless the received power does not meet the requirement if the transmission
line is too long. The channel connections with two kinds of communication rate, 64kbits/s or 2048kbits/s,
via dedicated optical fibre channel is shown in Figure 3.7-1and Figure 3.7-2. Two fibre cores of optical
cable are dedicated to current differential protection. For dual fibre optical channels application, two fibre
cores of optical cable are normally in service, and all data are exchanged via the other healthy core if
one core is failed.

Max 2km for 62.5/125μm multi-mode FO (C37.94, N×64kbits/s)

TX RX
IED1 IED2
RX TX

ST connectors ST connectors

Max 2km for 62.5/125μm multi-mode FO (C37.94, N×64kbits/s)

ST connectors (FO1) ST connectors (FO1)

TX RX

RX TX
IED1 IED2
TX RX

RX TX

ST connectors (FO2) ST connectors (FO2)

Figure 3.7-1 Direct optical link up to 2km with 850nm

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 3 Protection Functions

Max 60km or 120km for 9/125μm single-mode FO

TX RX
IED1 IED2
RX TX

FC connectors FC connectors

Max 60km or 120km for 9/125μm single-mode FO

FC connectors (FO1) FC connectors (FO1)

3
TX RX

RX TX
IED1 IED2
TX RX

RX TX

FC connectors (FO2) FC connectors (FO2)

Figure 3.7-2 Direct optical link up to 60km with 1310nm or up to 120km with 1550nm

The channel connections with two kinds of communication rate, 64kbits/s or 2048kbits/s, via single
channel or multiplex channel is shown in Figure 3.7-3, Figure 3.7-4 and Figure 3.7-5.

Multi-mode FO C37.94 (N×64kbit/s)

Communication convertor

E Interface
TX RX Link to
IED1 communicate
RX TX device
O

ST connectors ST connectors

Multi-mode FO C37.94 (N×64kbit/s)

ST connectors (FO1) ST connectors (FO1)

Communication convertor

TX RX E
Interface
RX TX Link to
IED1 communicate
TX RX device

RX TX O

ST connectors (FO2) ST connectors (FO2)

Figure 3.7-3 Connect to a communication network via communication convertor

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 3 Protection Functions

Single-mode FO G.703 (64kbit/s)

MUX-64

E Interface
TX RX Link to
IED1 communicate
RX TX device
O

ST connectors ST connectors

Single-mode FO G.703 (64kbit/s)

3 ST connectors (FO1) ST connectors (FO1)

MUX-64

TX RX E
Interface
RX TX Link to
IED1 communicate
TX RX device

RX TX O

ST connectors (FO2) ST connectors (FO2)

Figure 3.7-4 Connect to a communication network via MUX-64

Single-mode FO G.703-E1 (2048kbit/s)

MUX-2M

E Interface
TX RX Link to
IED1 communicate
RX TX device
O

ST connectors ST connectors

Single-mode FO G.703-E1 (2048kbit/s)

ST connectors (FO1) ST connectors (FO1)

MUX-2M

TX RX E
Interface
RX TX Link to
IED1 communicate
TX RX device

RX TX O

ST connectors (FO2) ST connectors (FO2)

Figure 3.7-5 Connect to a communication network via MUX-2M

The data format of protection transmission is shown as following table.

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 3 Protection Functions

Bit Data Frame Description

High Start bit The header data of transmission data format, 7E (hexadecimal)
Data information Including binary signals
CRC CRC
low Stop bit The ender of transmission data format, 7E (hexadecimal)

3.7.1.2 Communication Clock

The device transmits and receives messages based on respective clocks, which are called transmit
clock (i.e. clock TX) and receive clock (i.e. clock RX) respectively. Clock RX is fixed to be extracted from
message frame, which can ensure no slip frame and no error message received. Clock TX has two
options: 3
1. Use internal crystal clock, which is called internal clock. (master clock)

2. Use external clock. (slave clock)

Depend on the clock used by the device at both ends, there are three modes.

1. Master-master mode

Both ends use internal clock.

2. Slave-slave mode

Both ends use external clock.

3. Master-slave mode

One of them uses internal clock, the other uses external clock

The logic setting [FOx.Opt_ClkSrc] is used to select the communication clock. The internal clock is
enabled automatically when the logic setting [FOx.Opt_ClkSrc] is set as "Int". Contrarily, the external
clock is enabled automatically when the logic setting [FOx.Opt_ClkSrc] is set to "Ext".

If the device uses multiplex PCM channel, logic setting [FOx.Opt_ClkSrc] at both ends should be
set as "Ext" (Mode 2). If the device uses dedicated optical fibre channel, clock Mode 1 and Mode
3 can be used. Mode 1 is recommended in considering simplification to user, i.e. logic setting
[FOx.Opt_ClkSrc] at both ends should be set as "Int".

3.7.1.3 Identity Code

In order to ensure reliability of the device when digital communication channel is applied, settings
[FO.LocID] and [FO.RmtID] are provided as identity code to distinguish uniquely the device at remote
end using same channel.

Under normal conditions, the identity code of the device at local end should be different with that at
remote end. In addition, it is recommended that the identity code of all devices, i.e., the setting
[FO.LocID], should be unique in the system. The setting range is from 0 to 65535. Only for loop test,
they are set as the same.

The setting [FO.LocID] of the device at an end should be as same as the setting [FO.RmtID] of the
device at opposite end and the greater [FO.LocID] between them is chosen as the master end for

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 3 Protection Functions

sampling synchronism, the smaller [FO.LocID] is the slave end. If the setting [FO.LocID] is set as
same as the setting [FO.RmtID], that means the device in loopback testing mode.

The setting [FO.LocID] is packaged in the message frame and transmitted to the remote end. When
the received [FO.LocID] by local device from the device at remote end is same to the setting
[FO.RmtID] of local device, the received message from the remote end is valid, and data
information involved in message is considered in protection calculation. When these settings are
not matched, the message is considered as invalid and data information involved in message is
ignored, corresponding alarms will be issued.

3.7.1.4 Channel Statistics

3 The device has the function of on-line channel monitoring and channel statistics. It can produce
channel statistic report automatically at 9:00 every day and the report can be printed for operator
to check the channel quality. The monitoring contents of channel status are shown as follows, and
they can be viewed by the menu Main Menu→"Test"→"Counter"→"Pilot Chx Counter".

1. FOx.StartTime (starting time)

It shows the starting time of the channel status statistics of the device at local end.

2. FO.RmtID (ID code of the remote end)

It shows the ID information received by the device at local end now.

3. FOx.t_ChLag (propagation delay of channel x)

It shows the calculated communication channel time delay of the device at local end now (unit: us).
The calculation is based on the assumption that the sending and receiving channel paths are same.
The device measures propagation delay of communication channel based on the below principle.

Side S transmits a frame of message to side M, and meanwhile records the transmitting time "tss"
on the basis of clock on side S. When side M receives the message, it will record receiving time
"tmr" of the message with its own clock, and return a frame of message to side S at next fixed
transmitting time, meanwhile data of "tms-tmr" is included in the frame of message. Side S will
receive the message from side M at the time "tsr" and obtain the data of "tms-tmr".

Therefore, the propagation delay of the channel "Td" is obtained through calculation:

(tsr − t ss ) − (tms − t mr )
Td =
2

By using the above calculated "Td", the device automatically compensate time synchronization of
sampling data at each end and transmission time lag.

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 3 Protection Functions

T1

tss tsr "S"

tmr tms
Td T2
"M" 3

Figure 3.7-6 Schematic diagram of communication channel time

4. FOx.t_ChLag_Abs (absolute propagation delay of channel x)

It shows the difference between the time when the receiving end receives the data frame and the
time when the transmitting end transmits the data frame based on the same external clock source.

5. FOx.N_CRCFail (total number of error frame of channel x)

It shows the total number of the error frames of the device at local end from starting time of channel
statistics until now. Error frame means that this frame fails in CRC check.

6. FOx.N_FramErr (total number of abnormal messages of channel x)

It shows the total number of abnormal messages of the device at local end from starting time of
channel statistics until now.

7. FOx.N_FramLoss (total number of lost frames of channel x)

It shows the total number of the lost frames of the device at local end from starting time of channel
statistics until now.

8. FOx.N_RmtAbnor (total number of abnormal messages from the remote end of channel x)

It shows the total number of abnormal messages received from the remote end from starting time
of channel statistics until now.

9. FOx.N_CRCFailSec (total number of serious error frames of channel x)

It shows the total number of serious error frame seconds of the device at local end from starting
time of the channel statistics until now.

10. FOx.N_SynLoss (total number of loss synchronous of channel x)

It shows the total number of loss synchronous of the device at local end from starting time of the
channel statistics until now.

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 3 Protection Functions

3.7.2 Function Block Diagram

FOx

FOx.Enable FOx.On

FOx.Sendi FOx.Recvi

FOx.Alm

FOx.Alm_ID

3 3.7.3 I/O Signals

Table 3.7-1 Input signals of optical pilot channel

No. Input Signal Description

1 FOx.Enable Enabling channel x
2 FOx.Sendi Sending signal i of channel x (i=1, 2, 3, ......, 8)

Table 3.7-2 Output signals of optical pilot channel

No. Output Signal Description

1 FOx.On Channel x is enabled.
2 FOx.Recvi Receiving signal i of channel x (i=1, 2, 3, ......, 8)
3 FOx.Alm Channel x is abnormal
Received ID from the remote end is not as same as the setting [FO.RmtID] of the
4 FOx.Alm_ID
device in local end

3.7.4 Logic

SIG Receiving transfer signal i from remote side &

FOx.Recvi
SIG FOx.Alm >=1

SIG FOx.Alm_ID

SIG FOx.Enable &

FOx.On
EN [FOx.En]

Figure 3.7-7 Logic of receiving signal i

SIG FOx.Sendi &

Sending to the opposite end
SIG FOx.On

Figure 3.7-8 Logic of sending signal i

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 3 Protection Functions

i can be 1~8

SIG FOx.Alm_ID
&
SIG FOx.Alm_NoValFram FOx.Alm

SIG FOx.Alm_CRC >=1

EN FOx.Alm_Connect

Figure 3.7-9 Logic of channel alarm

3.7.5 Settings
3
Table 3.7-3 Settings of optical pilot channel

Name Range Step Unit Default Description

FO.LocID 0~65535 1 1 Identity code of the device at local end

FO.RmtID 0~65535 1 2 Identity code of the device at remote end

64
FO.BaudRate kbps 2048 Baud rate of optical pilot channel
2048

G.703
FO.Protocol C37.94 It is used to select protocol type, G.703 or C37.94
C37.94

The setting for the times of 64kbits/s, which is an

FOx.Nx64k_C37.94 1-12 1 12 N×64kbits/s standard defined by IEEE C37.94
standard
Option of internal clock or external clock
Ext
FOx.Opt_ClkSrc Int Ext: external clock
Int
Int: internal clock
Disabled
FOx.En Enabled Enabling/disabling channel x
Enabled

Current differential protection support C37.94 protocol. According to the

specific setting of multiplex channel, the amount of data that can be
transmitted is different, and the availability of impedance-based fault
location is also different.

FOx.Nx64k_C37.94 1~5 6~11 12

Impedance-based fault location - √ √

3.8 Pilot Distance Protection (85)

The instant distance protection with underreaching setting is impossible to isolate the fault at the

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 3 Protection Functions

remote end of the line, while distance protection with overreaching setting needs a time delay to
cooperate with downstream protection to maintain discrimination. Pilot distance protection that
exchanges distance protection information at both ends of the line can remove the internal fault
quickly, and will keep stability for external fault.

Pilot distance protection requires communication channel to exchange protection information at

both ends. The channel may be dedicated or multiplexed channel through optical fiber or any other
communication media. Pilot distance protection has schemes of permissive underreaching transfer
trip (PUTT), permissive overreaching transfer trip (POTT) and blocking. The device provides dual
pilot distance protections. The communication media and mode can be independent each other.

3 Pilot distance protection can be controlled by zero-sequence direction element or negative-

sequence direction element, and the weak infeed logic also needs zero/negative-sequence
direction element as an auxiliary criterion. The settings relevant to zero/negative-sequence
direction elements belong to earth fault protection and negative-sequence overcurrent protection
respectively. Hence, these settings should be also set correctly according the actural system
parameters even if earth fault protection and negative-sequence overcurrent protection are
disabled, so as to ensure that pilot distance protection will not be affected.

3.8.1 Functions Description

Pilot distance protection determines whether it will send the signal to the remote end according to
the discrimination result of the distance element or direction element. Pilot distance protection can
be divided into permissive scheme and blocking scheme according to whether the signal sent is
used to permit tripping or block tripping. For permissive scheme, it can be divided into overreaching
mode or underreaching mode according to the setting of distance element and scheme selected,
furthermore, it will provide the unblocking scheme as auxiliary function. For overreaching mode,
current reversal logic and weak infeed logic are available for parallel line operation and weak power
source situation respectively.

Pilot distance protection is used to protect the whole line, and its setting is set as 1.2 times the line
length at least, so the problem of overreaching does not exist and pilot distance protection,
compared with the distance protection, is not required to coordinate with other zones. The angle of
directional line in the second quadrant (α) and the angle of directional line in the fourth quadrant (β)
are as same as those of distance protection with quadrilateral characteristic.

SIG 85-x.Z.Enable &

85-x.Z.On
EN [85.Z.En]
&
SIG 85-x.Z.Block >=1 85-x.Z.Blocked

SIG Fail_Device
&
85-x.Z.Valid

Figure 3.8-1 Logic of enabling pilot distance protection

Pilot distance protection with permissive scheme receives permissive signal from the remote end,

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 3 Protection Functions

so as to combine with local discrimination condition to accelerate tripping, so it has high security.
Blocking scheme will operate with a short time delay [85.t_DPU_Blocking1] if forward pilot zone
element operates and not receiving blocking signal before the short time delay expired.

Pilot distance protection receives and sends signals via pilot channel, and the logic of receiving
signal is shown in Figure 3.8-2.

1. Non phase-segregated mode

For non-phase-segregated mode, "85-x.Recv1" means that permissive signal of any phase is
received from the remote end.

SET [85.Opt_Mode]=Blocking & 3

>=1

SIG 85-x.Recv1 &

SIG 85-x.Abnor_Ch1
>=1

SIG 85-x.Unblocking1 Valid

&
SET [85.Opt_Mode]=PUTT >=1

SET [85.Opt_Mode]=POTT
&
85-x.Valid_Recv1
EN [85.En_Ch_PhSeg]

2. Phase-segregated mode

For phase segregation mode, "85-x.Recv1" means that permissive signal of phase A is received
from the remote end.

SIG 85-x.Recv1 &

>=1
SIG 85-x.Abnor_Ch1 &
SIG 85-x.Unblocking1 Valid (Phase A)
&
85-x.Valid_Recv1 (Phase A)
SET [85.Opt_Mode]=PUTT >=1

SET [85.Opt_Mode]=POTT

EN [85.En_Ch_PhSeg]

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 3 Protection Functions

SIG 85-x.RecvB &

>=1
SIG 85-x.Abnor_Ch1 &
SIG 85-x.Unblocking1 Valid (Phase B)
&
85-x.Valid_Recv1 (Phase B)
SET [85.Opt_Mode]=PUTT >=1

SET [85.Opt_Mode]=POTT

EN [85.En_Ch_PhSeg]

3 SIG 85-x.RecvC &

>=1
SIG 85-x.Abnor_Ch1 &
SIG 85-x.Unblocking1 Valid (Phase C)
&
85-x.Valid_Recv1 (Phase C)
SET [85.Opt_Mode]=PUTT >=1

SET [85.Opt_Mode]=POTT

EN [85.En_Ch_PhSeg]

Figure 3.8-2 Logic of receiving signal

"85-x.Abnor_Ch1" is the binary signal that indicates whether the receiving signal is abnormal in
channel 1.

Pilot distance protection has the following application modes:

3.8.1.1 Zone Extension

When pilot scheme protection is out of service due to pilot channel failure or no pilot scheme
protection is provided. The fault outside zone 1 only can be cleared by zone 2 with a time delay. It
cannot ensure that all faults within protected line are cleared instantaneously. As a supplement of
pilot scheme protection, zone extension can clear the fault within the whole line instantaneously.
Different with pilot distance protection, zone extension can also operate for external close up fault
in parallel line, but power supply can be restored by AR. So zone extension should be blocked
when AR is out of service or not ready.

In order to prevent too many lines from disconnecting with system due to zone extension operate
when the circuit breaker is closed into permanent fault, zone extension should be blocked when
AR operates. For temporary fault, the line can be into service again after AR operates successfully.
For permanent fault in either local line or parallel line, distance protection with a time delay will
operate.

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 3 Protection Functions

SIG 85-x.ZX.Enable &

85-x.ZX.On
EN [85.ZX.En]
&
SIG 85-x.ZX.Block >=1 85-x.ZX.Blocked

SIG Fail_Device
&
85-x.ZX.Valid

SIG FD.Pkp &

&
SIG 85-x.ZX.Valid [85.t_DPU_ZX] 0 85-x.Op_ZX 3
SIG 85-x.AR_Ready &

SIG Pilot distance element

Figure 3.8-3 Logic of zone extension

Pilot distance element: pilot distance element meets the operating condition.

Zone extension uses the setting of forward pilot distance zone (ZPilot), and its operation
characteristic can be Mho or Quad.

3.8.1.2 Permissive Underreaching Transfer Trip (PUTT)

Distance elements zone 1 (Z1) with underreaching setting and forward pilot distance zone (ZPilot)
with overreaching setting are used for this scheme. Z1 element will send permissive signal to the
remote end and release tripping after Z1 time delay expired. After receiving permissive signal with
local pilot distance element pickup, a tripping signal will be released. The signal transmission
element for PUTT is set according to underreaching mode, so current reversal need not be
considered. For PUTT, there may be a dead zone under weak power source condition. If the fault
occurs outside Z1 zone at strong power source side, Z1 at weak power supply side may not operate
to trip and the corresponding permissive signal will not be issued, and pilot distance protection will
not operate. Therefore, the system fault can only be removed by Z2 at strong power source side
with time delay.

When the PUTT mode is used, the channel of the pilot directional earth-fault
protection should be independent. That means the setting
[85.DEF.En_IndepCh] should be set as "Enabled" if the pilot directional
earth-fault protection is enabled.

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 3 Protection Functions

ZPilot
Z2

Z1
M
EM A Fault B EN

Z1 N

Z2
ZPilot
3
Relay A Relay B
Z1 Z1

& &
85-x.Op_Z 85-x.Op_Z
ZPilot ZPilot

Figure 3.8-4 Simple schematic of PUTT

Pilot distance protection always adopts pilot channel 1, and the logic of PUTT is shown in Figure
3.8-5.

For non phase-segregated mode, "85-x.Send1" means that permissive signal of any phase is sent
to the remote end. However, for phase segregation mode, "85-x.Send1" means that permissive
signal of phase A is sent to the remote end.

1. Non phase-segregated mode

SIG 85-x.ExTrp 0 150ms

>=1
SIG 21L1.Op 0 100ms & &
85-x.Send1
SIG 85-x.Z.On

SET [85.Opt_Mode]=PUTT &

SIG FD.Pkp
&
SIG 85-x.Valid_Recv1 & & 8ms 0 85-x.Op_Z

EN [85.En_Ch_PhSeg]

SIG 85-x.Z.FwdDir

2. Phase-segregated mode

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 3 Protection Functions

SIG 21L.PilotFwd.ZG.StA
85-x.ZPilot.Fwd_PhA
SIG 21L.PilotFwd.ZG.StB

SIG 21L.PilotFwd.ZG.StC
Faulty Phase Selection 85-x.ZPilot.Fwd_PhB
SIG 21L.PilotFwd.ZP.StAB

SIG 21L.PilotFwd.ZP.StBC 85-x.ZPilot.Fwd_PhC

SIG 21L.PilotFwd.ZP.StCA

SIG 85-x.ExTrp 0 150ms

>=1
SIG 21L1.Op (Phase A) 0 100ms & &
85-x.Send1 (Phase A)
3
SIG 85-x.Z.On

SET [85.Opt_Mode]=PUTT &

SIG FD.Pkp
&
5ms 0 85-x.Op_Z
SIG 85-x.Valid_Recv1 (Phase A) & & (Phase A)

EN [85.En_Ch_PhSeg]

SIG 85-x.ZPilot.Fwd_PhA

SIG 85-x.ExTrp 0 150ms

>=1
SIG 21L1.Op (Phase B) 0 100ms & &
85-x.Send1 (Phase B)
SIG 85-x.Z.On

SET [85.Opt_Mode]=PUTT &

SIG FD.Pkp
&
5ms 0 85-x.Op_Z
SIG 85-x.Valid_Recv1 (Phase B) & & (Phase B)

EN [85.En_Ch_PhSeg]

SIG 85-x.ZPilot.Fwd_PhB

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 3 Protection Functions

SIG 85-x.ExTrp 0 150ms

>=1
SIG 21L1.Op (Phase C) 0 100ms & &
85-x.Send1 (Phase C)
SIG 85-x.Z.On

SET [85.Opt_Mode]=PUTT &

SIG FD.Pkp
&
5ms 0 85-x.Op_Z
SIG 85-x.Valid_Recv1 (Phase C) & & (Phase C)

3 EN [85.En_Ch_PhSeg]

SIG 85-x.ZPilot.Fwd_PhC

Figure 3.8-5 Logic of pilot distance protection (PUTT)

3.8.1.3 Permissive Overreaching Transfer Trip (POTT)

Pilot distance element will send permissive signal to remote end once it picks up and release
tripping signal upon receiving permissive signal from the remote end. When POTT is applied on
parallel lines arrangement and the setting (ZPilot) covers 50% of the parallel line, there may be a
problem under current reversal condition, settings for current reversal condition should be
considered, please refer to section 3.8.1.6 for details. Under weak power source condition, the
problem of dead zone at weak power source end is eliminated by the weak infeed logic, please
refers to section 3.8.1.7 for details.

ZPilot
Z2

Zpilot_Rev
M
EM A Fault B EN

N
Zpilot_Rev Z2
ZPilot

Relay A Relay B
& &
ZPilot >=1 85-x.Op_Z 85-x.Op_Z >=1 ZPilot

WI WI

Figure 3.8-6 Simple schematic of POTT

1. Non phase-segregated mode

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 3 Protection Functions

SIG 85-x.Z.FwdDir
&
SIG RevDir_ROC >=1 85-x.ZPilot.Fwd

SIG RevDir_NegOC

SIG Relay Trip &

>=1
EN [85.En_Trp_Send] 0 100ms >=1
SIG 85.Op_Z &

EN [85.En_PilotTrp_Send]

SIG 85-x.ExTrp 0 150ms 3

EN [85.En_52b_Echo]

SIG 52b_PhA
& >=1
& &
SIG 52b_PhB &
200ms 0
SIG 52b_PhC

EN [85.En_Ch_PhSeg] &

SIG 85-x.Valid_Recv1
&
SIG FD.Pkp 85-x.Send1

SET [85.Opt_Mode]=POTT

SIG 85-x.Z.On
&
& & 8ms 0 &
SIG 85-x.ZPilot.Fwd >=1 & 85-x.Op_Z

SIG WI Condition

SIG Current reversal blocking

2. Phase-segregated mode

SIG 21L.PilotFwd.ZG.StA
85-x.ZPilot.Fwd_PhA
SIG 21L.PilotFwd.ZG.StB

SIG 21L.PilotFwd.ZG.StC
Faulty Phase Selection 85-x.ZPilot.Fwd_PhB
SIG 21L.PilotFwd.ZP.StAB

SIG 21L.PilotFwd.ZP.StBC 85-x.ZPilot.Fwd_PhC

SIG 21L.PilotFwd.ZP.StCA

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 3 Protection Functions

EN [85.En_52b_Send] &
&

SIG 52b_PhA 150ms 0

SIG Relay Trip &

>=1 >=1
EN [85.En_Trp_Send] 0 150ms >=1
SIG 85.Op_Z &

EN [85.En_PilotTrp_Send]

3 SIG 85-x.ExTrp 0 150ms

EN [85.En_52b_Echo] & >=1

&
SIG 52b_PhA &
200ms 0
EN [85.En_Ch_PhSeg] &

SIG 85-x.Valid_Recv (Phase A)

&
85-x.Send1
SIG FD.Pkp
(Phase A)
SET [85.Opt_Mode]=POTT

SIG 85-x.ZPilot.Fwd_PhA >=1 &

5ms 0 85-x.Op_Z
& & (Phase A)
SIG WI Condition (Phase A) &
SIG 85-x.Z.On

SIG Current reversal blocking (Phase A)

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 3 Protection Functions

EN [85.En_52b_Send] &
&

SIG 52b_PhB 150ms 0

SIG Relay Trip &

>=1
EN [85.En_Trp_Send] 0 150ms >=1
SIG 85.Op_Z &

EN [85.En_PilotTrp_Send]

0 150ms

3
SIG 85-x.ExTrp

EN [85.En_52b_Echo] & >=1

&
SIG 52b_PhB &
200ms 0
EN [85.En_Ch_PhSeg] &

SIG 85-x.Valid_Recv (Phase B)

&
85-x.Send1
SIG FD.Pkp
(Phase B)

SET [85.Opt_Mode]=POTT

SIG 85-x.ZPilot.Fwd_PhB >=1 &

5ms 0 85-x.Op_Z
& & (Phase B)
SIG WI Condition (Phase B) &
SIG 85-x.Z.On

SIG Current reversal blocking (Phase B)

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 3 Protection Functions

EN [85.En_52b_Send] &
&

SIG 52b_PhC 150ms 0

SIG Relay Trip &

>=1
EN [85.En_Trp_Send] 0 150ms >=1
SIG 85.Op_Z &

EN [85.En_PilotTrp_Send]

3 SIG 85-x.ExTrp 0 150ms

EN [85.En_52b_Echo] & >=1

&
SIG 52b_PhC &
200ms 0
EN [85.En_Ch_PhSeg] &

SIG 85-x.Valid_Recv (Phase C)

&
85-x.Send1
SIG FD.Pkp
(Phase C)

SET [85.Opt_Mode]=POTT

SIG 85-x.ZPilot.Fwd_PhC >=1 &

5ms 0 85-x.Op_Z
& & (Phase C)
SIG WI Condition (Phase C) &
SIG 85-x.Z.On

SIG Current reversal blocking (Phase C)

Figure 3.8-7 Logic of pilot distance protection (POTT)

For current reversal blocking, please refer to section 3.8.1.6 for detail.

3.8.1.4 Blocking

Permissive scheme has high security, but it relies on pilot channel seriously. Pilot distance
protection will not operate when there is an internal fault with abnormal channel. Blocking scheme
could be considered as an alternative.

Blocking scheme takes use of the operation of pilot distance element to terminate sending of
blocking signal. Blocking signal will be sent once fault detector picks up without pilot distance
element operating. Pilot distance protection will operate with a short time delay if pilot distance
element operates and not receiving blocking signal after the timer expired.

The setting (ZPilot) in blocking scheme is overreaching, so the current reversal condition should
be considered. However, the short time delay of pilot distance protection has an enough margin for
current reversal, that this problem has been resolved.

The short time delay must consider channel delay and with a certain margin to set. As shown in
Figure 3.8-8, an external fault happens to line MN. The fault is behind the device at M side, for

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 3 Protection Functions

blocking scheme, the device at M side will send blocking signal to the device at N side. If channel
delay is too long, the device at side N has operated before receiving blocking signal. Hence, the
time delay of pilot distance protection adopted in blocking scheme should be set according to
channel delay.

Blocking signal
M N
EM Fault A B EN

Figure 3.8-8 Simple schematic of system fault 3

For blocking scheme, pilot distance protection will operate when there is an internal fault with
abnormal channel, however, it is possible that pilot distance protection issues an undesired trip
when there is an external fault with abnormal channel.

ZPilot

Zpilot_Rev
M
EM A Fault B EN

N
Zpilot_Rev
ZPilot

Relay A Relay B
FD.Pkp & & FD.Pkp

Zpilot & & Zpilot

[85.t_DPU_Blocking1] 85-x.Op_Z 85-x.Op_Z [85.t_DPU_Blocking1]

Figure 3.8-9 Simple schematic of blocking

Current reversal logic is only used for permissive scheme. For blocking scheme, the time delay of
pilot distance protection has enough margin for current reversal, so current reversal need not be
considered.

It is non-phase segregated mode for blocking scheme. Hence, the setting

[85.En_Ch_PhSeg] should be set as "Disabled" if pilot distance protection
adopts the blocking scheme.

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 3 Protection Functions

SIG 85-x.Z.FwdDir
&
SIG RevDir_ROC >=1 85-x.ZPilot.Fwd

SIG RevDir_NegOC

SIG Relay Trip &

>=1
EN [85.En_Trp_Send] 0 100ms >=1
SIG 85.Op_Z &

3 EN [85.En_PilotTrp_Send]

SIG 85-x.ExTrp 0 150ms

EN [85.En_52b_Send]

SIG 52b_PhA
& >=1
& &
SIG 52b_PhB 85-x.Send1

SIG 52b_PhC

SIG 85-x.Valid_Recv1
& &
SIG 85-x.ZPilot.Fwd >=1

SIG WI Condition

&
SIG FD.Pkp [85.t_DPU_Blocking1] 85-x.Op_Z

SET [85.Opt_Mode]=Blocking &

SIG 85-x.Z.On

Figure 3.8-10 Logic of pilot distance protection (Blocking)

3.8.1.5 Unblocking

Permissive scheme will trip only when it receives permissive signal from the remote end. However,
it may not receive a permissive signal from the remote end when pilot channel fails. For this case,
pilot distance protection can adopt unblocking scheme. Under normal conditions, the signaling
equipment works in the pilot frequency, and when the device operates to send permissive signal,
the signaling equipment will be switched to high frequency. While pilot channel is blocked, the
signaling equipment will receive neither pilot frequency signal nor high frequency signal. The
signaling equipment will provide a contact to the device as unblocking signal. When the device
receives unblocking signal from the signaling equipment, it will recognize channel failure, and
unblocking signal will be taken as permissive signal temporarily. The unblocking function can only
be used together with PUTT and POTT.

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 3 Protection Functions

EN [85.En_Unblocking1]

SIG 85-x.Unblocking1 & &

[85.t_Unblocking1] 0

SIG Detecting multi-phase fault >=1

SET [85.Opt_Ch1]=phase-to-ground
&
85-x.Unblocking1 Valid
SIG 85-x.Z.FwdDir

Figure 3.8-11 Logic of pilot distance protection (Unblocking)

3.8.1.6 Current Reversal 3

When there is a fault in one of the parallel lines, the direction of the fault current may change during
the sequence tripping of the circuit breaker at both ends as shown in Figure 3.8-12: When a fault
occurs on line C–D near breaker D, the fault current through line A-B to D will flow from A to B.
When breaker D is tripped, but breaker C is not tripped, the fault current in line A-B will then flow
from B to A. This process is the current reversal.

M N M N
Strong Weak
A B A B
source source
EM EN EM EN

C D C D

Direction of fault current Direction of fault current

flow before CB‘D’open flow after CB‘D’open

Figure 3.8-12 Current reversal

As shown above, the device A detects a forward fault while the device B detects a reverse fault
before break D is tripped. However, the device A detects a reverse fault while the device B detects
a forward fault after breaker D is tripped. There is a competition between pickup and drop off of
pilot zones in the device A and the device B when the fault measured by the device A changes from
the forward direction into reverse direction and vice versa for the device B. There may be
maloperation for the device in line A-B if the forward direction of the device B has operated but the
forward direction of the device A drops off slightly slower or the forward direction of the device B
has operated but the forward direction information of the device A is still received due to the channel
delay (the permissive signal is received).

In general, the following two methods shall be adopted to solve the problem of current reversal:

1. The fault shall be measured by means of the reverse element of the device B. Once the reverse
element of the device B operates, the send signals and the tripping circuit will be blocked for
a period of time after a short time delay. This method can effectively solve the problem of
competition between the device A and the device B, but there shall be a pre-condition. The
reverse element of the device B must be in cooperation with the forward element of the device
A, i.e. in case of a fault in adjacent lines, if the forward element of the device A operates, and
the reverse element of the device B must also operate. Once the bilateral cooperation fails,
the anticipated function cannot be achieved. In addition, the blocking time for sending signals

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 3 Protection Functions

and the tripping circuit after the reverse element of the device B operates shall be set in
combination with the channel time delay.

2. Considering the pickup and drop off time difference of distance elements and the channel time
delay between the device A and the device B, the maloperation due to current reversal shall
be eliminated by setting the time delay. The reverse direction element of the device is not
required for this method, the channel time delay and the tripping time of adjacent breaker shall
be taken into account comprehensively.

This protection device adopts the second method to eliminate the maloperation due to current
reversal.
3 SIG 85-x.Z.FwdDir &
t1 t2 Current reversal blocking
SIG Signal received conditon

Figure 3.8-13 Logic of current reversal blocking

t1: [85.t_DPU_CR1]

t2: [85.t_DDO_CR1]

Referring to above figure, when signal from the remote end is received without pilot forward zone
pickup, the current reversal blocking logic is enabled after t1 delay.

The time delay of t1 [85.t_DPU_CR1] shall be set the shortest possible but allowing sufficient time
for pilot forward zone pickup, generally set as 25ms.

Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked.
The logic will be disabled by either the dropoff of the signal or the pickup of pilot forward zone. A
time delay t2 [85.t_DDO_CR1] is required to avoid maloperation for the case that the pilot forward
zone (or forward element of pilot directional earth-fault protection) of device B picks up before the
signal from device A drops off. Considering the channel propagation delay and the pickup and drop-
off time difference of pilot forward zone (or pilot directional earth-fault element) with margin, t2 is
generally set between 25ms~40ms.

Because the time delay of pilot distance protection has an enough margin to current reversal,
current reversal blocking only used for permissive scheme not blocking scheme.

3.8.1.7 Weak Infeed

In case of a fault in line at one end of which there is a weak power source, the fault current supplied
to the fault point from the weak power source is very small or even nil, and the conventional distance
element could not operate. The weak infeed logic combines the protection information from the
strong power source end and the electric feature of the local end to cope with the case.

The weak infeed logic can be only applied for Blocking and POTT. The weak infeed logic has
options for echo or both echo and tripping.

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 3 Protection Functions

ZPilot

Z1 Zpilot_Rev
M
EM A Fault B EN

Z1 N
Zpilot_Rev

ZPilot

Load

Figure 3.8-14 Line fault description

3
Both forward direction element and reverse direction element of pilot distance protection are used
to discriminate weak infeed logic. When the weak infeed logic is enabled, distance forward and
reverse element and direction element of directional earth-fault protection do not operate with the
voltage lower than the setting [85.U_UV_WI] after the device picks up, upon receiving signal from
remote end, the weak infeed logic will echo the signal back to remote end for 200ms if the weak
infeed echo is enabled, the weak infeed end will echo signal and release tripping according to the
logic.

The setting (ZPilot_Rev) at weak source end must coordinate with the setting (ZPilot) at the remote
end. The coverage of ZPilot_Rev must exceed that of ZPilot at the remote end. ZPilot_Rev only
activates in the protection calculation when the weak infeed logic is enabled. In case of the weak
infeed logic not enabled, the setting coordination is not required.

ZPilot_Rev is only used for week infeed logic. ZPilot_Rev is calculated all the time when the device
picks up.

If the device does not pick up, and the weak infeed logic is enabled, upon receiving signal from
remote end with the voltage lower than the setting [85.U_UV_WI], the weak infeed logic will echo
back to remote end for 200ms. When either weak infeed echo or weak infeed tripping is enabled,
then the weak infeed logic is deemed to be enabled. During the device picking up, the weak infeed
logic is shown in Figure 3.8-15.

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 3 Protection Functions

SIG FwdDir_ROC & 85-x.DEF.FwdDir

SET 3I0>[85.DEF.3I0_Set]
>=1

SIG RevDir_ROC &

85-x.DEF.RevDir
SIG FD.ROC.Pkp
&
SIG 85-x.Z.FwdDir >=1 WI Conditon

SIG 85-x.Z.RevDir

3 SIG 85-x.Valid_Recv1 & &

85-x.WI
SIG FD.Pkp

EN [85.En_WI]

SET Up<[85.U_UV_WI] >=1 &

200ms 0 85-x.UV_WI
SET Upp<[85.U_UV_WI]

Figure 3.8-15 Weak infeed logic during pickup

For weak infeed end, the device may not pick up when a fault happens to the protected line. If the
device does not pick up, and the setting [85.En_WI_Pkp] is disabled weak infeed echo logic is valid.
(as shown in Figure 3.8-16) If the device does not pick up and the setting [85.En_WI_Pkp] is
enabled, weak infeed trip logic without pickup is executed. (as shown in Figure 3.8-17)

For permissive scheme, the signal receive condition means that the permissive signal is received
or the unblocking signal is valid.

SIG FD.Pkp &

EN [85.En_WI_Pkp]
&
85-x.Send1
SIG 85-x.Valid_Recv1
(WI echo)

EN [85.En_WI]

SET Up<[85.U_UV_WI] >=1 &

200ms 0 85-x.UV_WI
SET Upp<[85.U_UV_WI]

Figure 3.8-16 Weak infeed echo logic without pickup

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 3 Protection Functions

SIG FD.Pkp &

EN [85.En_WI_Pkp]
&
SIG WI Condition
&
SIG 85-x.Valid_Recv1 85-x.WI

EN [85.En_WI]

SET Up<[85.U_UV_WI] >=1 &

200ms 0 85-x.UV_WI
SET Upp<[85.U_UV_WI] 3
Figure 3.8-17 Weak infeed trip logic without pickup

For permissive scheme, the signal receive condition means that the permissive signal is received
or the unblocking signal is valid.

3.8.1.8 CB Echo

In order to make sure the pilot distance protection can operate correctly when one terminal is open,
CB Echo logic is provided. The device will initiate sending a pulse of 200ms permissive signal when
signal receive condition is met during CB is in open position.

SIG FD.Pkp

SIG 52b_PhA
&
>=1
SIG 52b_PhB

SIG 52b_PhC

SIG 85-x.Valid_Recv1 & &

200ms 0 &
SET [85.Opt_Mode]=POTT Send permissive signal

EN [85.En_52b_Echo]

Figure 3.8-18 Simplified CB echo logic for POTT

CB Echo logic is only applied to permissive overreach mode, and it is precondition is that the device
should not pick up. This logic will be terminated immediately once the device picks up.

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 3 Protection Functions

3.8.2 Function Block Diagram

85

85-x.Z.Enable 85-x.Z.On

85-x.Z.Block 85-x.ZX.On

85-x.Abnor_Ch1 85-x.Z.Blocked

85-x.Abnor_Ch2 85-x.ZX.Blocked

85-x.Rcv1 85-x.Z.Valid

3 85-x.RcvB 85-x.ZX.Valid

85-x.RcvC 85-x.Send1

85-x.ExTrp 85-x.SendB

85-x.Unblocking1 85-x.SendC

85-x.ZX.Enable 85-x.Op_Z

85-x.ZX.Block 85-x.Op_ZX

85-x.AR_Ready 85-x.ZX_St

85-x.Z.FwdDir

85-x.Z.RevDir

85-x.WI

85-x.UV_WI

85.Op_Z

85.Op_ZX

3.8.3 I/O Signals

Table 3.8-1 Input signals of pilot distance protection

No. Input Signal Description

1 85-x.Z.Enable Input signal of enabling pilot distance protection x (x=1 or 2)
2 85-x.Z.Block Input signal of blocking pilot distance protection x (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot distance
3 85-x.Abnor_Ch1
protection x (x=1 or 2)
Input signal of indicating that pilot channel 2 is abnormal for pilot distance
4 85-x.Abnor_Ch2
protection x (x=1 or 2)
Input signal of receiving permissive signal via channel No.1 for pilot distance
protection x, or input signal of receiving permissive signal of A-phase via channel
5 85-x.Recv1
No.1 for pilot distance protection x (only for phase-segregated command
scheme, x=1 or 2)
6 85-x.RecvB Input signal of receiving permissive signal of B-phase via channel No.1 for pilot

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 3 Protection Functions

distance protection x (only for phase-segregated command scheme, x=1 or 2)

Input signal of receiving permissive signal of C-phase via channel No.1 for pilot
7 85-x.RecvC
distance protection x (only for phase-segregated command scheme, x=1 or 2)
Input signal of initiating sending permissive signal from external tripping signal
8 85-x.ExTrp
for pilot distance protection x (x=1 or 2)
9 85-x.Unblocking1 Unblocking signal 1 of pilot distance protection x (x=1 or 2)
10 85-x.ZX.Enable Input signal of enabling zone extension (x=1 or 2)
11 85-x.ZX.Block Input signal of blocking zone extension (x=1 or 2)
12 85-x.AR_Ready AR has been ready for reclosing cycle.

Table 3.8-2 Output signals of pilot distance protection

3
No. Output Signal Description
1 85-x.Z.On Pilot distance protection x is enabled. (x=1 or 2)
2 85-x.ZX.On Zone extension of pilot distance protection x is enabled. (x=1 or 2)
3 85-x.Z.Blocked Pilot distance protection is blocked.
4 85-x.ZX.Blocked Zone extension of pilot distance protection is blocked.
5 85-x.Z.Valid Pilot distance protection is valid.
6 85-x.ZX.Valid Zone extension of pilot distance protection is valid.
Output signal of sending permissive signal 1 or sending A-phase permissive
7 85-x.Send1 signal of pilot distance protection x (only for phase-segregated command
scheme, x=1 or 2)
Output signal of sending B-phase permissive signal of pilot distance protection
8 85-x.SendB
x (only for phase-segregated command scheme, x=1 or 2)
Output signal of sending C-phase permissive signal of pilot distance protection
9 85-x.SendC
x (only for phase-segregated command scheme, x=1 or 2)
10 85-x.Op_Z Pilot distance protection x operates. (x=1 or 2)
11 85-x.Op_ZX Zone extension of pilot distance protection x operates. (x=1 or 2)
12 85-x.ZX_St Zone extension protection of pilot distance protection x starts (x=1 or 2)
13 85-x.Z.FwdDir Forward direction signal of pilot distance protection x (x=1 or 2)
14 85-x.Z.RevDir Reverse direction signal of pilot distance protection x (x=1 or 2)
15 85-x.WI Operation signal of weak infeed logic of pilot distance protection x (x=1 or 2)
16 85-x.UV_WI Undervoltage signal of weak infeed logic of pilot distance protection x (x=1 or 2)
General pilot distance protection operates, which is OR operation between 85-
17 85.Op_Z
1.Op_Z and 85-2.Op_Z
General zone extension of pilot distance protection operates, which is OR
18 85.Op_ZX
operation between 85-1.Op_ZX and 85-2.Op_ZX

3.8.4 Settings
Table 3.8-3 Settings of pilot distance protection

Name Range Step Unit Default Description

POTT
85.Opt_Mode PUTT POTT Option of pilot scheme
Blocking

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 3 Protection Functions

Name Range Step Unit Default Description

Disabled Enabling/disabling phase-
85.En_Ch_PhSeg Disabled
Enabled segregated signal scheme
Disabled Enabling/disabling weak infeed
85.En_WI Disabled
Enabled scheme
Undervoltage setting of weak
85.U_UV_WI 0.000~200.000 0.001 V 50.000
infeed logic
Enabling/disabling the device
pick up at weak infeed end.
Disabled For weak infeed end, If the

3
85.En_WI_Pkp Disabled
Enabled device does not pick up for
internal fault, it is used to enable
the device pick up.
Enabling/disabling sending
Disabled
85.En_Trp_Send Enabled permissive signal controlled by
Enabled
the device operating
Enabling/disabling sending
Disabled
85.En_PilotTrp_Send Enabled permissive signal controlled by
Enabled
pilot protection operating
Enabling/disabling sending
Disabled
85.En_52b_Send Enabled permissive signal controlled by
Enabled
CB open position
Enabling/disabling sending
Disabled permissive signal of CB echo
85.En_52b_Echo Enabled
Enabled logic controlled by CB open
position
Disabled Enabling/disabling pilot distance
85.Z.En Enabled
Enabled protection
Disabled Enabling/disabling unblocking
85.En_Unblocking1 Disabled
Enabled scheme
Phase-to-phase
Phase-to- Option of PLC channel for pilot
85.Opt_Ch1 Phase-to-
ground channel 1
ground
Pickup time delay of unblocking
85.t_Unblocking1 0.000~10.000 0.001 s 0.100
scheme for pilot channel 1
Time delay for blocking scheme
85.t_DPU_Blocking1 0.000~1.000 0.001 s 0.100 of pilot distance protection
operation
Pickup time delay of current
85.t_DPU_CR1 0.000~1.000 0.001 s 0.025
reversal logic
Dropout time delay of current
85.t_DDO_CR1 0.000~1.000 0.001 s 0.025
reversal logic
Disabled Enabling/disabling zone
85.ZX.En Enabled
Enabled extension of pilot distance

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 3 Protection Functions

Name Range Step Unit Default Description

protection
Pickup time delay for zone
85.t_DPU_ZX 0.000~10.000 0.001 s 0.000 extension of pilot distance
protection

3.9 Pilot Directional Earth-fault Protection (85)

Directional earth fault protection needs to coordinate with downstream protection with definite or inverse
time delay so it cannot clear an internal fault quickly. Pilot directional earth-fault protection takes use of
directional earth fault elements on both ends, it can detect high resistance fault and maintain high-speed 3
operation.

Pilot protection requires communication channel to exchange the protection information at both
ends. The channel may be dedicated or multiplexed channel through optical fiber or any other
communication media. Pilot directional earth-fault protection can be used independently, for
example, no distance protection is equipped with the device but fast operation is required for the
whole line, or it is used as backup protection of pilot distance protection to enhance the sensitivity
for an earth fault with high fault resistance.

Pilot directional earth-fault protection uses zero-sequence current and zero-sequence direction to
execute logic judgement, so the reliability of zero-sequence current directly affects the reliability of
pilot directional earth-fault protection. Because pole discrepancy state, CT circuit failure, VT circuit
failure, etc. will block pilot directional earth-fault protection, the function test of pilot directional earth-
fault protection should be executed under CB closed position due to CB position participating logic
discrimination of pole discrepancy state.

The direction discrimination and weak infeed depend on zero-sequence direction element or
negative-sequence direction element. The settings relevant to zero/negative-sequence direction
elements belong to earth fault protection and negative-sequence overcurrent protection
respectively. Hence, these settings should be also set correctly according the actural system
parameters even if earth fault protection and negative-sequence overcurrent protection are
disabled, so as to ensure that pilot directional earth-fault protection will not be affected.

3.9.1 Functions Description

Sending permissive signal (or terminating sending signal) to the opposite end is controlled by the
forward direction element. Current reversal logic is available for parallel line operation and CB echo
logic is provided once pilot directional earth fault protection is enabled. Current reversal logic is
only used for permissive scheme. For blocking scheme, current reversal need not be considered
because there is a settable time delay in pilot directional earth-fault protection.

Pilot directional earth-fault protection can be enabled or disabled by enabling signal, blocking signal
and the setting, as shown in Figure 3.9-1.

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 3 Protection Functions

SIG 85-x.DEF.Enable &

85-x.DEF.On
EN [85.DEF.En]
&
SIG 85-x.DEF.Block >=1 85-x.DEF.Blocked

SIG Fail_Device
&
85-x.DEF.Valid

Figure 3.9-1 Logic of enabling pilot directional earth-fault protection

3 SET [85.Opt_Mode]=Blocking &

SIG 85-x.Recv1

& >=1
&
SIG 85-x.Abnor_Ch1

SIG 85-x.Unblocking1 Valid

SET [85.Opt_Mode]=PUTT >=1

EN [85.DEF.En_IndepCh]

SET [85.Opt_Mode]=Blocking &

>=1
& 85-x.Valid_Recv_DEF
SIG 85-x.Recv2 & >=1

SIG 85-x.Abnor_Ch2

SIG 85-x.Unblocking2 Valid

Figure 3.9-2 Logic of receiving signal

Pilot directional earth-fault protection comprises permissive scheme and blocking scheme. It can
share pilot channel 1 (the setting [85.DEF.En_IndepCh] is set as "Disabled") with pilot distance
protection, or uses independent pilot channel 2 (the setting [85.DEF.En_IndepCh] is set as
"Enabled") by the setting [85.DEF.En_IndepCh]. For underreach mode, pilot directional earth-fault
always adopts independent pilot channel 2. The logic of receiving signal is shown in Figure 3.9-2.

3.9.1.1 Permissive Transfer Trip (PTT)

Pilot protection with permissive scheme receives permissive signal from the device of remote end,
so as to combine with local discrimination condition to accelerate tripping, so it has high security.

Operation of forward directional earth fault element is used to send permissive signal to the remote
end when the protection is enabled and will release tripping signal upon receiving permissive signal
from the remote end with further guarded by no operation of reverse directional earth fault element.

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 3 Protection Functions

This ensures the security of the protection.

The following figure shows the schematic of permissive transfer trip.

85-x.DEF.FwdDir

85-x.DEF.RevDir
M
EM A Fault B EN

N
85-x.DEF.RevDir

85-x.DEF.FwdDir

3
Relay A
85-x.DEF.FwdDir & &
[85.DEF.t_DPU] 85-x.Op_DEF 85-x.Op_DEF [85.DEF.t_DPU]
85-x.DEF.FwdDir
Relay B

Figure 3.9-3 Simple schematic of permissive scheme

1. Independent channel mode

SIG Relay Trip &

EN [85.En_Trp_Send]
>=1
SIG 85.Op_DEF & 0 [85.DEF.t_DPU]+150ms >=1

EN [85.En_PilotTrp_Send]

SIG 85-x.ExTrp 0 150ms

EN [85.En_52b_Echo]

SIG 52b_PhA
& >=1
& & &
SIG 52b_PhB & 85-x.Send2
[85.DEF.t_DPU]+150ms 0
SIG 52b_PhC

SIG 85-x.Valid_Recv2 &

EN [85.DEF.En_IndepCh]

SIG FD.Pkp &

SET [85.Opt_Mode]=PUTT >=1
& &
SET [85.Opt_Mode]=POTT & [85.DEF.t_DPU] 0 &
85-x.Op_DEF
SIG 85-x.DEF.Valid

SIG 85-x.DEF.FwdDir &

12ms &
SIG 85-x.DEF.RevDir

SIG Current reversal blocking

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2. Shared channel mode

SIG Relay Trip &

EN [85.En_Trp_Send]
>=1
SIG 85.Op_DEF & 0 100ms >=1

EN [85.En_PilotTrp_Send]

SIG 85-x.ExTrp 0 150ms

EN [85.En_52b_Echo]

3 SIG 52b_PhA
& &
& >=1

SIG 52b_PhB &

200ms 0
SIG 52b_PhC

SIG 85-x.Valid_Recv1 &

EN [85.DEF.En_IndepCh]
&
SIG FD.Pkp 85-x.Send1

SET [85.Opt_Mode]=POTT &

&
& 8ms 0 &
SIG 85-x.DEF.Valid
85-x.Op_DEF
SIG 85-x.DEF.FwdDir &
&
SIG 85-x.DEF.RevDir

SIG Current reversal blocking

Figure 3.9-4 Logic of pilot directional earth-fault protection (permissive scheme)

For current reversal blocking, please refer to section 3.9.1.4 for detail.

3.9.1.2 Blocking

Permissive scheme has high security, but it relies on pilot channel seriously. Pilot directional earth-
fault protection will not operate when there is an internal fault with abnormal channel. Blocking
scheme could be considered as an alternative.

Blocking scheme sends blocking signal when fault detector picks up and zero-sequence forward
element does not operate or both zero-sequence forward element and zero-sequence reverse
element do not operate. Pilot directional earth-fault protection will operate if forward directional
zero-sequence overcurrent element operates and not receiving blocking signal.

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85-x.DEF.FwdDir

85-x.DEF.RevDir
M
EM A Fault B EN

N
85-x.DEF.RevDir

85-x.DEF.FwdDir

Relay A Relay B
FD.Pkp FD.Pkp

85-x.DEF.RevDir &
& &
& 85-x.DEF.RevDir
3
85-x.DEF.FwdDir 85-x.DEF.FwdDir

& &
& 85-x.Op_DEF 85-x.Op_DEF &
[85.DEF.t_DPU] [85.DEF.t_DPU]

Figure 3.9-5 Simple schematic of blocking

1. Independent channel mode

EN [85.En_Trp_Send] &

SIG Relay Trip

>=1
SIG 85.Op_DEF & 0 [85.DEF.t_DPU]+150ms >=1

EN [85.En_PilotTrp_Send]

SIG 85-x.ExTrp 0 150ms

EN [85.En_52b_Send]

SIG 52b_PhA
& >=1
&
SIG 52b_PhB

SIG 52b_PhC

SIG 85-x.DEF.FwdDir &

12ms &
SIG 85-x.DEF.RevDir
&
85-x.Send2
&
SIG 85-x.Valid_Recv2 &

EN [85.DEF.En_IndepCh]
&
SIG FD.Pkp [85.DEF.t_DPU] 0 85-x.Op_DEF

SET [85.Opt_Mode]=Blocking &

SIG 85-x.DEF.Valid

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2. Shared channel mode

EN [85.En_Trp_Send] &
>=1
SIG Relay Trip 0 100ms >=1
SIG 85.Op_DEF &

EN [85.En_PilotTrp_Send]

SIG 85-x.ExTrp 0 150ms

EN [85.En_52b_Send]
3 SIG 52b_PhA
&
& >=1
SIG 52b_PhB

SIG 52b_PhC

&
SIG 85-x.DEF.FwdDir & 85-x.Send1

SIG 85-x.DEF.RevDir
&
SIG 85-x.Valid_Recv1 &

EN [85.DEF.En_IndepCh]
&
SIG FD.Pkp [85.t_DPU_Blocking1] 0 85-x.Op_DEF

SET [85.Opt_Mode]=Blocking &

SIG 85-x.DEF.Valid

Figure 3.9-6 Logic of pilot directional earth-fault protection (Blocking)

When DEF shares pilot channel 1 with pilot distance protection, time delay of pilot directional earth-
fault protection will change from the setting [85.DEF.t_DPU] to the setting [85.t_DPU_Blocking1].

Because the time delay of pilot directional earth-fault protection has enough margin for current
reversal, so blocking scheme should not consider the current reversal condition.

For blocking scheme, pilot directional earth-fault protection will operate when there is an internal
fault with abnormal channel, however, it is possible that pilot directional earth-fault protection issues
an undesired trip when there is an external fault with abnormal channel.

3.9.1.3 Unblocking

Permissive scheme will operate only when it receives permissive signal from the remote end.
However, it may not receive permissive signal from the remote end when pilot channel fails. For
this case, pilot directional earth-fault protection can adopt unblocking scheme. Under normal
conditions, the signaling equipment works in the pilot frequency, and when the device operates to
send permissive signal, the signaling equipment will be switched to high frequency. While the
channel is blocked, the signaling equipment will receive neither pilot frequency signal nor high

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frequency signal. The signaling equipment will provide a contact to the device as unblocking signal.
When the device receives unblocking signal from the signaling equipment, it will recognize channel
failure, and unblocking signal will be taken as permissive signal temporarily.

The unblocking scheme can only be used together with permissive scheme.

EN [85.En_Unblocking2] &
&
SIG 85-x.Unblocking2 & 85-x.Unblocking2 Valid

[85.t_Unblocking2] 0

SIG 85-x.DEF.FwdDir 3
Figure 3.9-7 Logic of pilot directional earth-fault protection (Unblocking)

3.9.1.4 Current Reversal

The reach of directional earth-fault protection is difficult to define. There may have problem for pilot
direction earth-fault protection applied on parallel line arrangement due to current reversal
phenomenon.

When there is a fault in one of the parallel lines, the direction of the fault current may change during
the sequence tripping of the circuit breaker at both ends as shown in Figure 3.9-8: When a fault
occurs on line C–D near breaker D, the fault current through line A-B to D will flow from A to B.
When breaker D is tripped, but breaker C is not tripped, the fault current in line A-B will then flow
from B to A. This process is the current reversal.

M N M N
Strong Weak
A B A B
source source
EM EN EM EN

C D C D

Direction of fault current Direction of fault current

flow before CB‘D’open flow after CB‘D’open

Figure 3.9-8 Current reversal

As shown above, the device A detects a forward fault while the device B detects a reverse fault
before break D is tripped. However, the device A detects a reverse fault while the device B detects
a forward fault after breaker D is tripped. There is a competition between pickup and drop off of
pilot zones in the device A and the device B when the fault measured by the device A changes from
the forward direction into reverse direction and vice versa for the device B. There may be mal-
operation for the device in line A-B if the forward direction of the device B has operated but the
forward direction of the device A drops off slightly slower or the forward direction of the device B
has operated but the forward direction information of the device A is still received due to the channel
delay (the permissive signal is received).

In general, the following two methods shall be adopted to solve the problem of current reversal:

1. The fault shall be measured by means of the reverse element of the device B. Once the reverse

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 3 Protection Functions

element of the device B operates, the send signals and the tripping circuit will be blocked for
a period of time after a short time delay. This method can effectively solve the problem of
competition between the device A and the device B, but there shall be a precondition. The
reverse element of the device B must be in cooperation with the forward element of the device
A, i.e. in case of a fault in adjacent lines, if the forward element of the device A operates, and
the reverse element of the device B must also operate. Once the bilateral cooperation fails,
the anticipated function cannot be achieved. In addition, the blocking time for sending signals
and the tripping circuit after the reverse element of the device B operates shall be set in
combination with the channel time delay.

2. Considering the pickup and drop off time difference of distance elements and the channel time
3 delay between the device A and the device B, the maloperation due to current reversal shall
be eliminated by setting the time delay. The reverse direction element of the device is not
required for this method, the channel time delay and the tripping time of adjacent breaker shall
be taken into account comprehensively.

This protection device adopts the second method to eliminate the maloperation due to current
reversal.

SIG 85-x.DEF.FwdDir &

t1 t2 Current reversal blocking
SIG Signal received conditon

Figure 3.9-9 Logic of current reversal blocking

t1: pickup time delay of current reversal

t2: dropoff time delay of current reversal

When adopting independent pilot channel 2, t1 and t2 are the settings [85.t_DPU_CR2] and
[85.t_DDO_CR2] respectively, which should be considered individually from channel 1.

When sharing pilot channel 1 with pilot distance protection, t1 and t2 are the settings
[85.t_DPU_CR1] and [85.t_DDO_CR1] respectively.

Referring to above figure, when signal from the remote end is received without the operation of the
forward element of pilot directional earth-fault protection, the current reversal blocking logic is
enabled after t1. t1 shall be set the shortest possible but allowing sufficient time for the operation
of forward element of pilot directional earth-fault protection, generally set as 25ms.

Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked.
The logic will be disabled by either the dropoff of signal or the operation of forward element of pilot
directional earth-fault protection. t2 is required to avoid maloperation for the case that the forward
element of pilot directional earth-fault protection of device B picks up before the signal from device
A drops off. Considering the channel propagation delay and the pickup and drop-off time difference
of the forward element of pilot directional earth-fault protection with margin, t2 is generally set
between 25ms~40ms.

Because the time delay of pilot directional earth-fault protection has an enough margin to current
reversal, current reversal blocking only used for permissive scheme not blocking scheme.

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3.9.1.5 CB Echo

When CB Echo logic is applied for DEF, the device will initiate sending a pulse of permissive signal
if signal receive condition is met during CB is in open position.

SIG FD.Pkp

SIG 52b_PhA
&
>=1
SIG 52b_PhB

SIG 52b_PhC

SIG 85-x Valid_Recv_DEF

SIG 85-x.DEF.Valid
& &
[85.DEF.t_DPU]+150ms 0 & 3
85-x Send_DEF
EN [85.DEF.En_IndepCh]

EN [85.En_52b_Echo]

Figure 3.9-10 Simplified CB Echo logic for POTT

3.9.2 Function Block Diagram

85

85-x.DEF.Enable 85-x.DEF.On

85-x.DEF.Block 85-x.DEF.Bloked

85-x.Abnor_Ch1 85-x.DEF.Valid

85-x.Abnor_Ch2 85-x.Op_DEF

85-x.Rcv1 85-x.Send1

85-x.Rcv2 85-x.Send2

85-x.ExTrp 85.Op_DEF

85-x.Unblocking1 85-x.DEF.FwdDir

85-x.Unblocking2 85-x.DEF.RevDir

3.9.3 I/O Signals

Table 3.9-1 Input signals of pilot directional earth-fault protection

No. Input Signal Description

1 85-x.DEF.Enable Input signal of enabling pilot directional earth-fault protection x (x=1 or 2)
2 85-x.DEF.Block Input signal of blocking pilot directional earth-fault protection x (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot directional
3 85-x.Abnor_Ch1
earth-fault protection x (x=1 or 2)
Input signal of indicating that pilot channel 2 is abnormal for pilot directional
4 85-x.Abnor_Ch2
earth-fault protection x (x=1 or 2)
5 85-x.Recv1 Input signal of receiving permissive signal via channel 1 for pilot directional earth-

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 3 Protection Functions

fault protection x (x=1 or 2)

Input signal of receiving permissive signal via channel 2 for pilot directional earth-
6 85-x.Recv2
fault protection x (x=1 or 2)
Input signal of initiating sending permissive signal from external tripping signal
7 85-x.ExTrp
(x=1 or 2)
8 85-x.Unblocking1 Unblocking signal 1 for pilot directional earth-fault protection x (x=1 or 2)
9 85-x.Unblocking2 Unblocking signal 2 for pilot directional earth-fault protection x (x=1 or 2)

Table 3.9-2 Output signals of pilot directional earth-fault protection

No. Output Signal Description

3 1 85-x.DEF.On Pilot directional earth-fault protection x is enabled. (x=1 or 2)

2 85-x.DEF.Blocked Pilot directional earth-fault protection x is blocked. (x=1 or 2)
3 85-x.DEF.Valid Pilot directional earth-fault protection x is valid. (x=1 or 2)
4 85-x.Op_DEF Pilot directional earth-fault protection x operates. (x=1 or 2)
Output signal of sending permissive signal 1 for pilot directional earth-fault
5 85-x.Send1 protection x when pilot directional earth-fault protection sharing pilot channel 1
with pilot distance protection (x=1 or 2)
Output signal of sending permissive signal 2 for pilot directional earth-fault
6 85-x.Send2 protection x when pilot directional earth-fault protection adopting independent
pilot channel 2 (x=1 or 2)
General pilot directional earth-fault protection operates. It is OR operation
7 85.Op_DEF
between 85-1.Op_DEF and 85-2.Op_DEF
8 85-x.DEF.FwdDir Forward direction signal of pilot directional earth-fault protection x (x=1 or 2)
9 85-x.DEF.RevDir Reverse direction signal of pilot directional earth-fault protection x (x=1 or 2)

3.9.4 Settings
Table 3.9-3 Settings of pilot directional earth-fault protection

Name Range Step Unit Default Description

Disabled Enabling/disabling pilot directional
85.DEF.En Enabled
Enabled earth-fault protection
Enabling/disabling pilot directional
earth-fault protection operate to block
AR
Disabled
85.DEF.En_BlkAR Enabled Disabled: selective phase tripping and
Enabled
not blocking AR
Enabled: three-phase tripping and
blocking AR
Enabling/disabling independent
channel for pilot directional earth-fault
Disabled protection
85.DEF.En_IndepCh Enabled
Enabled Disabled: pilot directional earth-fault
protection sharing same channel with
pilot distance protection

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Name Range Step Unit Default Description

Enabled: pilot directional earth-fault
adopting independent pilot channel
Disabled Enabling/disabling unblocking scheme
85.En_Unblocking2 Disabled
Enabled for pilot DEF via pilot channel 2
Pickup time delay of unblocking
85.t_Unblocking2 0.000~10.000 0.001 s 0.200
scheme for pilot channel 2
Zero-sequence current setting of pilot
85.DEF.3I0_Set (0.050~40.000)×In 0.001 A 0.200
directional earth-fault protection
Time delay of pilot directional earth-fault
85.DEF.t_DPU 0.000~10.000 0.001 s 0.150
protection 3
Time delay pickup for current reversal
logic when pilot directional earth-fault
85.t_DPU_CR2 0.000~1.000 0.001 s 0.025
protection adopts independent pilot
channel 2
Time delay dropoff for current reversal
logic when pilot directional earth-fault
85.t_DDO_CR2 0.000~1.000 0.001 s 0.025
protection adopts independent pilot
channel 2

3.10 DPFC Distance Protection (21D)

When there is a fault happens to the power grid and the fault is within the protected range, distance
protection can isolate the fault with a certain time delay. DPFC distance protection, as an
independent fast protection, can quickly operate to isolate the fault from the power grid and
enhance the stability of power grid.

3.10.1 Functions Description

The power system is normally treated as a balanced symmetrical three-phase network. When a
fault occurs in the power system, by applying the principle of superposition, the load current and
voltage can be calculated in the system prior to the fault and the pure fault component can be
calculated by fault current or voltage subtracted by pre-fault load current or voltage. DPFC distance
protection concerns change of current and voltage at power frequency, therefore, DPFC distance
protection is not influenced by load current.

As an independent fast protection, DPFC distance protection is mainly used to clear close up fault
of long line quickly, its protected range can set as 60%~70% of the whole line.

Because DPFC distance protection only reflects the fault component and is not influenced by
current change due to load variation and power swing, power swing blocking (PSB) function is not
required. Moreover, there is no transient overreaching due to infeed current from the remote power
supply because it is not influenced by load current.

DPFC distance protection may not overreach, and its protected zone will be inverse-proportion
reduced with system impedance behind it, i.e. the protected zone will be less than setting if the

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 3 Protection Functions

system impedance is greater. The protected zone will be close to setting value if the system
impedance is smaller. Therefore, DPFC distance protection is usually used for long transmission
line with large power source and it is recommended to disable DPFC distance protection for short
line or the line with weak power source.

ZZD

M F N
Z
EM EN
∆I

3 ZS ZK

jX

Zzd
Zk

Φ
R
Zs+Zk
-Zs

Figure 3.10-1 Operation characteristic for forward fault

Where:

ZZD: the setting of DPFC distance protection

ZS: total impedance between local system and device location

ZK: measurement impedance

Φ: positive-sequence sensitive angle, i.e. [21L1.phi1_Reach]

Figure 3.10-1 shows the operation characteristic of DPFC distance protection on R-X plane when
a fault occurs in forward direction, which is the circle with the –Zs as the center and the│Zs+Zzd│
as the radius. When measured impedance Zk is in the circle, DPFC distance protection will operate.
DPFC distance protection has a larger capability of enduring fault resistance than distance
protection using positive-sequence as polarized voltage.

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ZZD

F M N
Z
EM EN
∆I
ZK
Z′S

jX

3
Z's

Zzd

Φ R

-Zk

Figure 3.10-2 Operation characteristic for reverse fault

Z'S：total impedance between remote system and protective device location

Figure 3.10-2 shows the operation characteristic of the DPFC distance element on R-X plane when
a fault occurs in reverse direction, which is the circle with the Z′S as the center and the│Z′S-Zzd│as
the radius. The region of operation is in the quadrant 1 but the measured impedance -Zk is always
in the quadrant 3, the DPFC distance protection will not operate. DPFC distance protection can be
enabled or disabled by the setting, enabling signal and blocking signal.

3.10.2 Function Block Diagram

21D

21D.Enable 21D.Op

21D.Block 21D.Blocked

21D.Valid

21D.Op

3.10.3 I/O Signals

Table 3.10-1 Input signals of DPFC distance protection

No. Input Signal Description

1 21D.Enable Input signal of enabling DPFC distance protection

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2 21D.Block Input signal of blocking DPFC distance protection

Table 3.10-2 Output signals of DPFC distance protection

No. Output Signal Description

1 21D.On DPFC distance protection is enabled.
2 21D.Blocked DPFC distance protection is blocked.
3 21D.Valid DPFC distance protection is valid.
4 21D.Op DPFC distance protection operates.

3.10.4 Logic
3 SIG 21D.Enable &
21D.On
EN [21D.En]
&
SIG 21D.Block >=1 21D.Blocked

SIG Fail_Device
&
21D.Valid

SIG 21D.Valid
&
SIG FD.Pkp

EN [Prot.En_VT]

SIG Manual closing signal

>=1 &
SIG 3-pole reclosing signal 21D.Op

SET [21D.Z_Set]<0.5Ω/In

SET ZØ<[21D.Z_Set] &

>=1
SIG UP<0.85Un &
SET ZØØ <[21D.Z_Set] &

SIG UPP<0.85Unn

SIG PD signal

Figure 3.10-3 Logic of DPFC distance protection

Pole open signal blocks DPFC distance element of corresponding phase-

to-earth and phase-to-phase DPFC distance protection, and healthy phases
(operation phases) are not affected. For example, if phase A open is
confirmed, DPFC distance element of phase A, phase AB and phase AC are
blocked.

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3.10.5 Settings
Table 3.10-3 Settings of DPFC distance protection

Name Range Step Unit Default Remark

Impedance setting of DPFC distance
21D.Z_Set (0.000~4Unn)/In 0.001 Ω 5.000
protection
Impedance setting of DPFC distance
21D.Z_Overreach (0.000~4Unn)/In 0.001 Ω 10.000
protection with overreaching characteristic
Disabled
21D.En Enabled Enabling/disabling DPFC distance protection
Enabled

3
3.11 Distance Protection (21L)

The distance protection function is designed to meet the requirement for the application of
transmission line or underground cable. The reach of distance protection is definite, and distance
protection is easy to coordinate with protections of the adjacent equipment. Distance protection
includes three independent phase-to-phase measuring loops as well as three independent phase-
to-ground measuring loops. Both mho and quadrilateral characteristics are available for different
application. In addition, load encroachment, power swing blocking and releasing, and faulty phase
selection functions are also provided.

3.11.1 Functions Description

Up to 8 zones distance protection are supplied, including 1 zone distance protection with fixed
forward direction, 5 zones distance protection with settable direction, 1 zone pilot distance
protection with fixed forward direction and 1 zone pilot distance protection with fixed reverse
direction. Each zone includes three independent phase-to-phase measuring loops as well as three
independent phase-to-ground measuring loops. Phase-to-ground distance element should be
compensated by zero-sequence current of local line. Zone 2~6 can select forward direction, reverse
direction and non direction.

Load encroachment can distinguish effectively between heavily loaded line and faulty line, and the
risk of encroachment of the load impedance into the tripping characteristics of the distance
protection can be excluded.

Power swing blocking and releasing can prevent distance protection from undesired operation
during power swing, even if measured impedance reaches into the operation area of distance
protection. Moreover, distance protection can operate reliably when a fault occurs during power
swing.

Based on distance protection characteristics, faulty phase can be identified correctly. It is beneficial
for the faulty phase selection which is important to the line which uses phase-segregated circuit
breaker and provides valid information for 1-pole AR and fault location. When receiving manual
closing signal or 3-pole reclosing signal, the operation characteristic of phase-to-phase distance
element (quadrilateral & mho) will always shift in reverse direction. It is ensured to enclose the
origin of impedance and without dead zone for three-phase fault.

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 3 Protection Functions

The distance protection can be controlled by zero-sequence direction element or negative-

sequence direction element. The settings relevant to zero/negative-sequence direction elements
belong to earth fault protection and negative-sequence overcurrent protection respectively. Hence,
these settings should be also set correctly according the actural system parameters even if earth
fault protection and negative-sequence overcurrent protection are disabled, so as to ensure that
distance protection will not be affected.

3.11.2 Quadrilateral Distance Protection

For forward direction or reverse direction close up fault, the voltage of faulty phase is 0, and the
measured impedance of faulty phase is located in the origin of R-X plane. Positive-sequence
3 voltage is used as polarized voltage to distinguish between forward direction fault and reverse
direction fault. As shown in Figure 3.11-1 and Figure 3.11-2, line OA and line OE are named
direction line which has good direction characteristics with positive-sequence voltage as the
polarized voltage.

1. Phase comparison equation of forward direction distance element is:

𝑈̇1
−𝛽 ≤ 𝐴𝑟𝑔 ≤ 90° + 𝛼
𝐼̇

2. Phase comparison equation of reverse direction distance element is:

𝑈̇1
180° − 𝛽 ≤ 𝐴𝑟𝑔 ≤ 270° + 𝛼
𝐼̇

⚫ For phase-to-ground distance element, taking phase-A as an example

𝑈̇1 is positive-sequence voltage, 𝑈̇1 = 𝑈̇𝐴1

𝐼 ̇ is phase current compensated by zero-sequence current, 𝐼 ̇ = 𝐼𝐴̇ + 𝐾0 × 3𝐼0̇

K0 is zero-sequence compensation coefficient.

⚫ For phase-to-phase distance element, taking phase-AB as an example

𝑈̇1 is positive-sequence voltage, 𝑈̇1 = 𝑈̇𝐴𝐵1

𝐼 ̇ is phase current compensated by zero-sequence current, 𝐼 ̇ = 𝐼𝐴𝐵

̇

jX

B Z_Set
θ D
C θ2
Dꞌ
Dꞌꞌ
A
α
φ φ
R
R_Offset O β R_Set
E

Figure 3.11-1 Quadrilateral forward direction distance element

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jX
E
R_Set β O R_Offset
R
φ φ
α
A
Dꞌꞌ
Dꞌ C
θ2 θ
B
D Z_Set

Figure 3.11-2 Quadrilateral reverse direction distance element 3

jX

B Z_Set
D
C

φ φ φ
R
R_Offset R
φ O

A
Z_Offset E

Figure 3.11-3 Quadrilateral non direction distance element

Where:

Z_Set is the impedance setting.

R_Set is the resistance setting.

Z_Set is the offset impedance setting.

R_Set is the offset resistance setting.

α is the angle of directional line OA in the second quadrant.

β is the angle of directional line OE in the fourth quadrant.

θ is downward offset angle of the reactance line, which is used to prevent distance protection from
overreaching.

θ2 is downward offset angle of the adaptive zero-sequence reactance line, which is used to prevent
distance protection from overreaching. θ2 can be adjusted adaptively and only used in phase-to-
ground distance protection.

φ is line positive-sequence characteristic angle, which is shared by phase-to-ground distance

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 3 Protection Functions

element and phase-to-phase distance element

In order to improve the reliability of distance protection and prevent phase-to-ground distance
protection from overreaching in the case of fault resistance, the phase-to-ground distance
protection provides an adaptive zero-sequence reactance line. The adaptive zero-sequence
reactance line does not need to be set, and can adjust the downward angle according to the fault
situation to prevent distance protection from overreaching. This function takes effect only after
being configured by PCS-Studio. It is applicable to scenarios where a larger RCA needs to be
configured to avoid various types of overreaching. The adaptive adjustment of the downward angle
ensures that distance protection not only has a strong ability for the fault with high resisance but
also has no the risk of overreaching.
3 For forward direction or reverse direction close up three-phase fault, positive-sequence voltage is
almost 0, so the dead zone of distance protection for a close up three-phase fault must be
eliminated. Memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltage adopts 2 cycles pre-fault positive-sequence voltage.

When the memory fades out, the operating characteristics will be shifted toward forward direction
or reverse direction, as shown in Figure 3.11-4 and Figure 3.11-5.

jX

B Z_Set
θ θ2 D
C
Dꞌ
Dꞌꞌ

A α
φ φ
O R
R_Offset β R_Set
ZShift
E

Figure 3.11-4 Shift impedance characteristics of forward direction

jX

B Z_Set
θ θ2 D
C
A Dꞌ
Dꞌꞌ

α ZShift
E φ
R_Offset φ R
β R_Set
O

Figure 3.11-5 Shift impedance characteristics of reverse direction

For reverse direction distance element, the similar treatment as forward direction distance element
can be adopted, by rotating the operation characteristics of forward direction distance element 180°,

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the operating characteristics of reverse direction distance element can be gained.

3.11.3 Mho Distance Protection

For forward direction or reverse direction close up fault, the voltage of faulty phase is almost 0, and
the measured impedance of faulty phase is located in the origin of R-X plane. Positive-sequence
voltage is used as polarized voltage to distinguish between forward direction fault and reverse
direction fault.

Phase comparison equation of forward direction distance element and reverse direction distance
element is:

−90° ≤ 𝐴𝑟𝑔
𝑈̇𝑂𝑃∅
≤ 90° 3
𝑈̇𝑃∅

𝑈̇𝑃∅ is the polarized positive-sequence voltage, i.e., 𝑈̇𝑃∅ = −𝑈̇1∅

𝑈̇𝑂𝑃∅ is the operating voltage.

⚫ For forward direction characteristics: 𝑈̇𝑂𝑃∅ = 𝑈̇ − 𝐼 ̇ × 𝑍

1) For phase-to-ground distance element:

𝑈̇ is phase voltage

𝐼 ̇ is phase current compensated by zero-sequence current

Taking phase-A as an example: 𝑈̇𝑂𝑃𝐴 = 𝑈̇𝐴 − (𝐼𝐴̇ + 𝐾0 × 3𝐼0̇ ) × 𝑍

2) For phase-to-phase distance element:

𝑈̇ is phase-to-phase voltage

𝐼 ̇ is phase-to-phase current

Taking phase-AB as an example: 𝑈̇𝑂𝑃𝐴𝐵 = 𝑈̇𝐴𝐵 − 𝐼𝐴𝐵

̇ ×𝑍

⚫ For reverse direction characteristics: 𝑈̇𝑂𝑃∅ = 𝑈̇ + 𝐼 ̇ × 𝑍

1) For phase-to-ground distance element:

𝑈̇ is phase voltage

𝐼 ̇ is phase current compensated by zero-sequence current

Taking phase-A as an example: 𝑈̇𝑂𝑃𝐴 = 𝑈̇𝐴 + (𝐼𝐴̇ + 𝐾0 × 3𝐼0̇ ) × 𝑍

2) For phase-to-phase distance element:

𝑈̇ is phase-to-phase voltage

𝐼 ̇ is phase-to-phase current

Taking phase-AB as an example: 𝑈̇𝑂𝑃𝐴𝐵 = 𝑈̇𝐴𝐵 + 𝐼𝐴𝐵

̇ ×𝑍

⚫ For non-direction characteristics 𝑈̇𝑃∅ = 𝑈̇ + 𝐼 ̇ × 𝑍𝑂𝐹𝐹𝑆𝐸𝑇

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1) For phase-to-ground distance element:

𝑈̇ is phase voltage

𝐼 ̇ is phase current compensated by zero-sequence current

Taking phase-A as an example: 𝑈̇𝑃𝐴 = 𝑈̇𝐴 + (𝐼𝐴̇ + 𝐾0 × 3𝐼0̇ ) × 𝑍𝑂𝐹𝐹𝑆𝐸𝑇

2) For phase-to-phase distance element:

𝑈̇ is phase-to-phase voltage

𝐼 ̇ is phase-to-phase current
3 Taking phase-AB as an example: 𝑈̇𝑃𝐴𝐵 = 𝑈̇𝐴𝐵 + 𝐼𝐴𝐵
̇ × 𝑍𝑂𝐹𝐹𝑆𝐸𝑇

Non direction distance element adopts offset characteristics and does not use positive-sequence
voltage as polarized voltage, and operation voltage is as same as that of forward direction distance
element.

jX

Z
θ
C
θ2
D
D'

R
O

Figure 3.11-6 Mho forward direction distance element

jX

φ R

D'

D θ2
θ
Z

Figure 3.11-7 Mho reverse direction distance element

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jX

Z_Set

φ
R
φ O

Z_Offset

Figure 3.11-8 Mho non-direction distance element

3
Where:

Z_Set is the impedance setting.

Z_Offset is the offset impedance setting.

θ is downward offset angle of the reactance line, which is used to prevent distance protection from
overreaching.

θ2 is downward offset angle of the adaptive zero-sequence reactance line, which is used to prevent
distance protection from overreaching. θ2 can be adjusted adaptively and only used in phase-to-
ground distance protection.

φ is line positive-sequence characteristic angle, which is shared by phase-to-ground distance

element and phase-to-phase distance element.

In order to improve the reliability of distance protection and prevent phase-to-ground distance
protection from overreaching in the case of fault resistance, the phase-to-ground distance
protection provides an adaptive zero-sequence reactance line. The adaptive zero-sequence
reactance line does not need to be set, and can adjust the downward angle according to the fault
situation to prevent distance protection from overreaching. This function takes effect only after
being configured by PCS-Studio. It is applicable to scenarios where a larger RCA needs to be
configured to avoid various types of overreaching. The adaptive adjustment of the downward angle
ensures that distance protection not only has a strong ability for the fault with high resisance but
also has no the risk of overreaching.

In order to improve the performance of mho distance protection against high resistance fault, phase
shift θ2 is applied to polarized voltage in phase-to-ground distance element and phase-to-phase
distance element. Their impedance shift characteristics towards quadrant 1 is shown in Figure
3.11-9·.

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jX

Z_Set

θ2
φ

R
O

3 Figure 3.11-9 Shift mho impedance characteristics

For the fault in forward direction, the operating characteristics of phase-to-ground distance element
is shown in Figure 3.11-10. Operating characteristics on R-X plane is a circle with line connecting
ends of Z_Set and -2ZS/3 as the diameter. The origin is enclosed in the circle.

jX

Z_Set

R
O

-2Zs/3

Figure 3.11-10 Phase-to-ground operating characteristics for forward fault

Where:

Z_Set is the impedance setting.

ZS is total impedance between local system and protective device location

φ is positive-sequence sensitive angle.

For the fault in forward direction, the operating characteristics of phase-to-phase distance element
is shown in Figure 3.11-11. Operating characteristics on R-X plane is a circle with line connecting
ends of Z_Set and -ZS/2 as the diameter. The origin is enclosed in the circle.

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jX

Z_Set

φ
R
O

-Zs/2

Figure 3.11-11 Phase-to-phase operating characteristics for forward fault 3

For the fault in reverse direction, the operating characteristics is shown in Figure 3.11-12. This
characteristics is a circle with line connecting ends of Z_Set and Z'S as the diameter.

ZꞋs

jX

Z_Set

O R

Figure 3.11-12 Operating characteristics for reverse fault

Where:

Z'S is total impedance between remote system and protective device location.

For reverse direction distance element, its operating characteristics can be gained by rotating the
operating characteristics of forward direction distance element 180°.

jX

Z_Set

φ
O
R

C2

Zs C1

Figure 3.11-13 Operating characteristics of three-phase close up fault

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For forward direction or reverse direction close up three-phase fault, positive-sequence voltage is
also 0, so the dead zone of distance protection for a close up three-phase fault must be eliminated.
Memorized positive-sequence voltage is adopted as polarized voltage when the positive-sequence
voltage drops down to 15%Un or below. The memorized positive-sequence voltages adopts 2
cycles pre-fault positive-sequence voltage. When the memory fades out, the operating
characteristics will be shifted toward forward direction or reverse direction.

For the fault in forward direction, as shown in Figure 3.11-13, C1 is the operating characteristics
before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is enclosed in the impedance circle.

3 For the fault in reverse direction, as shown in Figure 3.11-14, C1 is the operating characteristics
before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is not enclosed in the impedance circle.

ZꞋs

jX

C1
Z_Set

C2
φ
O
R

Figure 3.11-14 Operating characteristics of three-phase close up fault

The distance protection with such design thoroughly eliminates the dead zone when three-phase
close up fault occurs. It also has favourable directivity and will not operate for a reverse three-phase
fault at busbar.

3.11.4 Zero-sequence Current Compensation

For three-phase transmission line, the faulty phase is affected by the current of non-faulty phase
due to the mutual inductance among phase-to-phase conductors.

ZL

ZM
IA

IB ZM

IC
UC UB UA

Figure 3.11-15 Phase-to-phase mutual inductance

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Where:

𝑍𝐿 is line impedance

𝑍𝑀 is line mutual impedance

For metallic fault:

𝑈̇𝐴 = 𝐼𝐴̇ × 𝑍𝐿 + 𝐼𝐵̇ × 𝑍𝑀 + 𝐼𝐶̇ × 𝑍𝑀 = 𝐼𝐴̇ × (𝑍𝐿 − 𝑍𝑀 ) + (𝐼𝐴̇ + 𝐼𝐵̇ + 𝐼𝐶̇ ) × 𝑍𝑀

For three-phase symmetric line:

𝑍𝐿1 = 𝑍𝐿 − 𝑍𝑀

𝑍𝐿0 = 𝑍𝐿 + 2𝑍𝑀
3
𝑍𝐿1 is line positive-sequence impedance

𝑍𝐿0 is line zero-sequence impedance

𝑍𝐿0 − 𝑍𝐿1
𝑍𝑀 =
3

𝑍 −𝑍 𝑍𝐿0 −𝑍𝐿1
Hence, 𝑈̇𝐴 = 𝐼𝐴̇ × 𝑍𝐿1 + (𝐼𝐴̇ + 𝐼𝐵̇ + 𝐼𝐶̇ ) × 𝐿0 3 𝐿1 = (𝐼𝐴̇ + 3𝐼0̇ × 3×𝑍 ) × 𝑍𝐿1
𝐿1

Zero-sequence compensation coefficient 𝐾0

𝑍𝐿0 − 𝑍𝐿1
𝐾0 =
3 × 𝑍𝐿1

𝑈̇𝐴 = (𝐼𝐴̇ + 𝐾0 × 3𝐼0̇ ) × 𝑍𝐿1

The device provides zero-sequence compensation coefficient to fulfill zero-sequence current

compensation.

For parallel double-circuit lines, due to mutual inductance of zero-sequence current from the
adjacent line, phase-to-ground characteristics of distance protection will be affected.

ZL1

Z
I
3I0I ZM0

II
3I0II

Figure 3.11-16 Zero-sequence mutual inductance for double-circuit lines

Where:

3𝐼0𝐼 is residual current of line I.

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3𝐼0𝐼𝐼 is residual current of line II.

𝑍𝑀0 is mutual zeros-sequence current between line I and line II.

When phase-A earth fault happens to line I , phase-A voltage is:

𝑈̇𝐴 = (𝐼𝐴̇ + 𝐾0 × 3𝐼0̇ ) × 𝑍𝐿1 + 3𝐼0𝐼𝐼

̇ × 𝑍𝑀0

Due to mutual inductance of zero-sequence current from the adjacent line, the error item
̇ × 𝑍𝑀0 is imported. According to the actual application, 𝐾0 and the setting range of distance
3𝐼0𝐼𝐼
protection shall be adjusted reasonably to avoid undesired operation.
3 3.11.5 Load Encroachment

When distance protection is used to protect long, heavily loaded lines, the risk of encroachment of
the load impedance into the tripping characteristics of the distance protection may exist. A load
encroachment characteristics for all zones is used to exclude the risk of unwanted fault detected
by distance protection during heavy load flow. As shown in Figure 3.11-17, if the measured
impedance locates in the load area, distance protection will be blocked.

jX

φLoad φLoad
Load Area Load Area
R
O
RLoad RLoad

Figure 3.11-17 Distance element with load encroachment

Two settings are equipped to exclude the encroachment of the load impedance:

RLoad: the minimum load resistance

φLoad: the load area angle

These values are common for all zones, and independent settings are provided to phase-to-ground
and phase-to-phase characteristics.

3.11.6 Power Swing Blocking and Releasing

When power swing occurs on the power system, the impedance measured by the distance
measuring element may vary from the load impedance area into the operating zone of the distance
element. The distance measuring element may operate due to the power swing occurs at many
points of interconnected power systems. To keep the stability of whole power system, tripping due
to operation of the distance measuring element during a power swing is generally not allowed.
Distance protection adopts power swing blocking releasing to avoid maloperation resulting from

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power swing. In another word, distance protection is blocked all along under the normal condition
and power swing when the respective logic settings are enabled. Only when fault (internal fault or
power swing with internal fault) is detected, power swing blocking for distance protection is released
by PSBR element.

Power swing blocking for distance element will be released if any of the following PSBR elements
operates. Each distance zone element has respective setting for selection this function.

⚫ Fault detector PSBR element (FD PSBR)

⚫ Unsymmetrical fault PSBR element (UF PSBR)

⚫ Symmetrical fault PSBR element (SF PSBR)

3
1. Fault detector PSBR element

If any of the following condition is matched, FD PSBR will operate for 160ms.

Positive-sequence current is lower than the setting [21L.I_PSBR] before general fault detector
element operates.

As shown in figure below, assuming that normal load impedance locates at position 1 and the
impedance locates at position 2 when positive-sequence current is lower than the setting
[21L.I_PSBR], it means FD operates between point 1 and point 2 if operation condition for FD
PSBR mentioned above is fulfilled (point 3 as an example), and then FD PSBR will operate for
160ms.

[21.I_PSBR]
FD
Normal load
impedance
Point 1
Point 2

Point 3

2. Unsymmetrical fault PSBR element

The operation criterion:

I0+I2>m×I1

The “m”, an empirical value, is internal fixed coefficient which can ensure UF PSBR operation
during power swing with internal unsymmetrical fault, while no operation during power swing or
power swing with external fault.

This decision mainly utilizes the "discrepancy" that there is no negative-sequence or zero-sequence
current during power swing, and there are negative-sequence and zero-sequence currents in case
of asymmetric fault. In addition, value of m is used to differentiate internal asymmetric fault and
external asymmetric fault in case of power swing.

⚫ In case of power swing or both power swing and external fault, asymmetric fault discriminating

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element will not operate and distance protection will be blocked:

In case of power swing but no fault, I0 and I2 are near zero, but I1 is very large. Asymmetric fault
discriminating element will not operate.

In case of both power swing and external fault, if center of power swing is in scope of protection,
both phase-to-phase and grounding impedance relays may operate. At this time, selection of value
of m is used to ensure no operation of asymmetric fault discriminating element, blocking of distance
protection, and no incorrect operation without selectivity. If power swing center is not on this line,
distance protection will not operate incorrectly without selectivity due to power swing.

⚫ In case of internal asymmetric fault, asymmetric fault discriminating element operates and
3 distance protection will be release to clear internal fault:

In case of both power swing and internal fault, if at the instant of short circuit, system electric
potential angle is not laid out, asymmetric fault discriminating element will operate at once. If at the
instant of short circuit, system electric potential angle is laid out, asymmetric fault discriminating
element will operate when system angle gradually decreases, or local side tripping may be
activated after immediate operation of opposite side asymmetric fault discriminating element and
releasing of distance protection tripping. In case of normal internal asymmetric phase-to-phase or
grounding fault in the system, relatively large zero-sequence or negative-sequence component will
exist. At this time, the above equation is true and distance protection will be released.

3. Symmetrical fault PSBR element

If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD PSBR
nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is provided for this
case specially. This detection is based on measuring the voltage at power swing center, during
power swing, U1cosΦ will constantly change periodically.

UOS=U1×COSΦ

Where:

Φ: the angle between positive sequence voltage and current

U1: the positive sequence voltage

As shown in the figure below, assume system connection impedance angle of 90°, current vector
will be perpendicular to the line connecting EM and EN, and have the same phase as power swing
center voltage. During normal operation of system or power swing, U1cosΦ just reflects positive-
sequence voltage of power swing center. In case of 3-phase short circuit, U1cosΦ is voltage drop
on arc resistor, transition resistance is arc resistance, and voltage drop on arc resistor is less than
5%UN. In actual system, line impedance angle is not 90°. Through compensation of angle Φ, power
swing center voltage can be measured accurately. After compensation, power swing center voltage
is U1cos(Φ＋90o－ΦL), where ΦL is line impedance angle.

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I
EM U EN
UOS

During power swing, power swing center voltage U1cosΦ has the following characteristics: When
electric potential phase angle difference between power supplies at two sides is 180 o, U1cosΦ＝0
and change rate dU1cosΦ/dt is the maximum. When this phase angle difference is near 0o, power
swing center voltage change rate dU1cosΦ/dt is the minimum. During short circuit, U1cosΦ remains 3
unchanged and dU1cosΦ/dt＝0. However, in early stage of short circuit when normal state enters
short circuit state, dU1cosΦ/dt is very large. Therefore, use of dU1cosΦ/dt solely to differentiate
power swing and short circuit is not complete.

For these reasons, the method to release distance protection on condition that power swing center
voltage U1cosΦ is less than a setting and after a short delay can be used as symmetric fault
discriminating element. This element can accurately differentiate power swing and 3-phase short
circuit fault, and constitute a complete power swing blocking scheme with other elements. The
element to open distance protection if U1cosΦ is less than a certain setting and after a delay is
easy to realize and has short delay, and can trip fault more quickly and accurately trip 3-phase
short circuit fault during power swing.

The criterion of SF PSBR element comprises the following two parts:

⚫ when -0.03UN<UOS<0.08UN, the SF PSBR element will operate after 150ms.

⚫ when -0.1UN<UOS<0.25UN, the SF PSBR element will operate after 500ms.

The second criterion is a backup of the first criterion allowing longer monitoring period of voltage
variation. To reduce the time delay for SF PSBR element during power swing, the change rate of
voltage at power swing center is also used which can release SF PSBR element quickly for the
fault occurred during power swing. The typical release time is less than 60ms.

3.11.7 Faulty Phase Selection

The realization of phase-segregated tripping and fault location depends on the faulty phase selection.
Each zone of distance protection contains three phase-to-ground measuring elements and three phase-
to-phase measuring elements, so non-faulty phase maybe operates when there is a fault. For example,
for near-end phase A fault, phase A distance element operates, while phase AB and phase CA distance
element are also possible to operate. Therefore, the faulty phase selection of distance protection cannot
only depend on the operating phase of distance protection. For single-phase fault, three phase-to-
ground distance elements, three phase-to-phase distance elements and the angle relation between I 0
and I2A can effectively distinguish faulty phase.

Zero-sequence current is used to distinguish between earth fault and phase-to-phase fault. For earth
fault, associating the angle relation between I0 and I2A, the operating phase of distance protection can

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determine faulty phase. For phase-to-phase fault, the faulty phase is detected by the operating phase
and the relative relationship among the different distance elements.

⚫ For single-phase earth fault

I2
1) −30° < 𝐴𝑟𝑔 < 30° phase-A fault region is selected
I0

I2
2) 90° < 𝐴𝑟𝑔 < 150° phase-C fault region is selected
I0

I2
3) 210° < 𝐴𝑟𝑔 < 270° phase-B fault region is selected
3 I0

I2/I0

CG
30˚
30˚
30˚ AG
30˚
I2/I0
30˚
30˚
BG

I2/I0

Figure 3.11-18 Faulty phase selection based on I2 and I0

For single-phase earth fault, after confirming the fault region, the faulty phase is determined by the
distance element. For example, the logic of faulty phase selection for AG fault is shown as below.

SIG Phase-A distance element &

SIG Phase-BC distance element

&
SIG Region AG AG fault

SIG Grounded fault condition

Figure 3.11-19 Logic of faulty phase selection for AG fault

⚫ For two-phases earth fault

I2
1) −90° < 𝐴𝑟𝑔 < 30° phase-BC fault region is selected
I0

I2
2) 30° < 𝐴𝑟𝑔 < 150° phase-AB fault region is selected
I0

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I2
3) 150° < 𝐴𝑟𝑔 < 270° phase-CA fault region is selected
I0

I2/I0

ABG

30˚ 90˚
30˚ BCG
90˚ I2/I0
90˚
30˚
3
CAG

I2/I0

Figure 3.11-20 Faulty phase selection based on I2 and I0

For two-phases earth fault, after confirming the fault region, the faulty phases are determined by the
distance elements. For example, the logic of faulty phase selection for ACG fault is shown as below.

SIG Phase-AC distance element &

SIG Phase-B distance element

&
SIG Region CAG ACG fault

SIG Grounded fault condition

Figure 3.11-21 Logic of faulty phase selection for ACG fault

⚫ For phase-to-phase fault

For phase-to-phase fault, zero-sequence current is not existed, so the faulty phases are determined by
the distance elements. For example, the logic of faulty phase selection for AB fault and for ABC fault
are shown as below.

SIG Zab<Zbc &

SIG Zab<Zca
&
SIG Phase-AB distance element AB fault

SIG Phase-C distance element

SIG Phase-A distance element

&
SIG Phase-B distance element ABC fault

SIG Phase-C distance element

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Figure 3.11-22 Logic of faulty phase selection for AB fault and ABC fault

3.11.8 Time Delay Characteristics

For distance protection with time delay, for example, zone 2, the time delay of phase-to-ground
distance element is shared by phase A, phase B and phase C, and the time delay of phase-to-
phase distance element is shared by phase AB, phase BC and phase CA.

When there is a transferring fault, operating time of distance protection with time delay is subject
to the beginning of the first fault. For example:

T=0ms: there is phase A earth fault in the range of zone 2.

3 T=100ms: phase A earth fault is transferred into phase B earth fault.

T=150ms: the circuit breaker of phase A is open.

If the time delay of zone 2 of phase-to-ground distance element is set as 400ms, zone 2 of phase-
to-ground distance element will operate at T=400ms not T=500ms. However, time delay of each
zone of distance protection is independent.

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3.11.9 Function Block Diagram

21L

21L.Enable 21L.On

21L.Block 21L.Blocked

21Li.Enable 21L.Valid

21Li.Block 21Li.On

21Li.ZG.Enable 21Li.Op

21Li.ZG.Block 21Li.Op.PhA
3
21Li.ZP.Enable 21Li.Op.PhB

21Li.ZP.Block 21Li.Op.PhC

21Li.En_ShortDly 21Li.ZG.StA

21Li.Blk_ShortDly 21Li.ZG.StB

21Li.En_PSBR 21Li.ZG.StC

21Li.Blk_PSBR 21Li.ZP.StAB

21Li.ZP.StBC

21Li.ZP.StCA

21L.PilotFwd.ZG.StA

21L.PilotFwd.ZG.StB

21L.PilotFwd.ZG.StC

21L.PilotFwd.ZP.StAB

21L.PilotFwd.ZP.StBC

21L.PilotFwd.ZP.StCA

21L.PilotRev.ZG.StA

21L.PilotRev.ZG.StB

21L.PilotRev.ZG.StC

21L.PilotRev.ZP.StAB

21L.PilotRev.ZP.StBC

21L.PilotRev.ZP.StCA

3.11.10 I/O Signals

Table 3.11-1 Input signals of distance protection

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No. Input Signal Description

1 21L.Enable Input signal of enabling distance protection
2 21L.Block Input signal of blocking distance protection
3 21Li.Enable Input signal of enabling zone i of distance protection (i=1~6)
4 21Li.Block Input signal of blocking zone i of distance protection (i=1~6)
5 21Li.ZG.Enable Input signal of enabling zone i of phase-to-ground distance element (i=1~6)
6 21Li.ZP.Enable Input signal of enabling zone i of phase-to-phase distance element (i=1~6)
7 21Li.ZG.Block Input signal of blocking zone i of phase-to-ground distance element (i=1~6)
8 21Li.ZP.Block Input signal of blocking zone i of phase-to-phase distance element (i=1~6)
9 21Li.Enable_ShortDly Input signal of enabling zone i of distance protection with short time delay (i=2~6)
3 10 21Li.Block_ShortDly Input signal of blocking zone i of distance protection with short time delay (i=2~6)
Input signal of enabling power swing blocking releasing for zone i of distance
11 21Li.Enable_PSBR
protection (i=1~6)
Input signal of blocking power swing blocking releasing for zone i of distance
12 21Li.Block_PSBR
protection (i=1~6)

Table 3.11-2 Output signals of distance protection

No. Output Signal Description

1 21L.On Distance protection is enabled.
2 21L.Blocked Distance protection is blocked.
3 21L.Valid Distance protection is valid.
4 21Li.On Zone i of distance protection is enabled. (i=1~6)
5 21Li.Op Zone i of distance protection operates (i=1~6)
6 21Li.Op_PhA Zone i of distance protection operates (Phase A, i=1~6)
7 21Li.Op_PhB Zone i of distance protection operates (Phase B, i=1~6)
8 21Li.Op_PhC Zone i of distance protection operates (Phase C, i=1~6)
9 21Li.ZG.StA Zone i of distance protection starts. (Phase A, i=1~6)
10 21Li.ZG.StB Zone i of distance protection starts. (Phase B, i=1~6)
11 21Li.ZG.StC Zone i of distance protection starts. (Phase C, i=1~6)
12 21Li.ZP.StAB Zone i of distance protection starts. (Phase AB, i=1~6)
13 21Li.ZP.StBC Zone i of distance protection starts. (Phase BC, i=1~6)
14 21Li.ZP.StAC Zone i of distance protection starts. (Phase AC, i=1~6)
15 21L.PilotFwd.ZG.StA Forward pilot zone of distance protection starts. (Phase A)
16 21L.PilotFwd.ZG.StB Forward pilot zone of distance protection starts. (Phase B)
17 21L.PilotFwd.ZG.StC Forward pilot zone of distance protection starts. (Phase C)
18 21L.PilotFwd.ZP.StAB Forward pilot zone of distance protection starts. (Phase AB)
19 21L.PilotFwd.ZP.StBC Forward pilot zone of distance protection starts. (Phase BC)
20 21L.PilotFwd.ZP.StCA Forward pilot zone of distance protection starts. (Phase CA)
21 21L.PilotRev.ZG.StA Reverse pilot zone of distance protection starts. (Phase A)
22 21L.PilotRev.ZG.StB Reverse pilot zone of distance protection starts. (Phase B)
23 21L.PilotRev.ZG.StC Reverse pilot zone of distance protection starts. (Phase C)
24 21L.PilotRev.ZP.StAB Reverse pilot zone of distance protection starts. (Phase AB)
25 21L.PilotRev.ZP.StBC Reverse pilot zone of distance protection starts. (Phase BC)

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 3 Protection Functions

26 21L.PilotRev.ZP.StCA Reverse pilot zone of distance protection starts. (Phase CA)

3.11.11 Logic

SIG 21L.Enable 21L.On

&
SIG 21L.Block >=1 21L.Blocked

SIG Fail_Device
&
SIG 21L.Valid 21L.Valid
&
SIG 21Li.Enable

SIG 21Li.Block
3
EN [21Li.ZG.En]
& &
& 21Li.ZG.Enabled
SIG 21Li.ZG.Enable

SIG 21Li.ZG.Block >=1

EN [21Li.ZP.En]
& 21Li.On
&
SIG 21Li.ZP.Enable

SIG 21Li.ZP.Block

SIG VTS.Alm
&
>=1 21Li.ZP.Enabled
SIG Prot.BI_En_VT &

EN [Prot.En_VT]

Figure 3.11-23 Logic of enabling distance protection (i=1~6)

SIG 21Li.Enable_ShortDly &

SIG 21Li.Block_ShortDly
&
EN [21Li.En_ShortDly] 21Li.Enabled_ShortDly

SIG 21Li.On

Figure 3.11-24 Logic of enabling short time delay (i=2~6)

PCS-902S Line Distance Relay 3-79

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 3 Protection Functions

SIG 21L1.ZG.Enabled
&
SIG FD.Pkp Flag.21L1.ZG

EN [21L1.ZG.En_3I0] >=1

SET 3I0>[FD.ROC.3I0_Set]

EN [21L1.ZG.En_NeuDir_Blk] &
& &
SET 50/51G.RevDir.Op 21L1.Flg_PSBR_ZG

EN [21L1.ZG.En_NegDir_Blk] &
3
SET 50/51Q.RevDir.Op

SIG 21L1.ZG.StA
&
SET Ia>0.04In

SIG 21L.LoadEnchPG.StA

SIG 21L1.ZG.StB
& >=1
SET Ib>0.04In

SIG 21L.LoadEnchPG.StB

SIG 21L1.ZG.StC
&
SET Ic>0.04In

SIG 21L.LoadEnchPG.StC

Figure 3.11-25 Logic of zone 1 of distance protection (phase-to-ground)

"21L1.ZG.StA" means that zone 1 of phase-to-ground distance element starts. (phase A)

"21L1.ZG.StB" means that zone 1 of phase-to-ground distance element starts. (phase B)

"21L1.ZG.StC" means that zone 1 of phase-to-ground distance element starts. (phase C)

"21L.LoadEnchPG.StA" means that phase-to-ground measured impedance is inside the load area.
(phase A)

"21L.LoadEnchPG.StB" means that phase-to-ground measured impedance is inside the load area.
(phase B)

"21L.LoadEnchPG.StC" means that phase-to-ground measured impedance is inside the load area.
(phase C)

"Flag.21L1.ZG" means that measured impedance of zone 1 of phase-to-ground distance element

is inside the operation area.

3-80 PCS-902S Line Distance Relay

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 3 Protection Functions

SIG 21L1.ZP.Enabled
&
SIG FD.Pkp Flag.21L1.ZP

EN [21L1.ZP.En_NegDir_Blk] &

SIG 50.51G.RevDir.Op

SIG 21L1.ZP.StAB
&
SET Iab>0.04In

SIG 21L.LoadEnchPP.StAB

SIG 21L1.ZP.StBC
& >=1
&
21L1.Flg_PSBR_ZP
3
SET Ibc>0.04In

SIG 21L.LoadEnchPP.StBC

SIG 21L1.ZP.StCA
&
SET Ica>0.04In

SIG 21L.LoadEnchPP.StCA

Figure 3.11-26 Logic of zone 1 of distance protection (phase-to-phase)

"21L1.ZP.StAB" means that zone 1 of phase-to-phase distance element starts. (phase AB)

"21L1.ZP.StBC" means that zone 1 of phase-to-phase distance element starts. (phase BC)

"21L1.ZP.StCA" means that zone 1 of phase-to-phase distance element starts. (phase CA)

"21L.LoadEnchPP.StAB" means that phase-to-phase measured impedance is inside the load area.
(phase AB)

"21L.LoadEnchPP.StBC" means that phase-to-phase measured impedance is inside the load area.
(phase BC)

"21L. LoadEnchPP.StCA" means that phase-to-phase measured impedance is inside the load
area. (phase CA)

"Flag.21L1.ZP" means that measured impedance of zone 1 of phase-to-phase distance element

is inside the operation area.

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 3 Protection Functions

SIG 21Li.ZG.Enabled
&
SIG FD.Pkp Flag.21Li.ZG

EN [21Li.ZG.En_3I0] >=1

SET 3I0>[FD.ROC.3I0_Set]

EN [21Li.ZG.En_NeuDir_Blk]

&
SET [21Li.DirMode]=Forward & & 21Li.Flg_PSBR_ZG
>=1
SIG 50/51G.RevDir.Op
3 SET [21Li.DirMode]=Reverse &

SIG 50/51G.FwdDir.Op

EN [21Li.ZG.En_NegDir_Blk]
&
SET [21Li.DirMode]=Forward & &
>=1
SIG 50/51Q.RevDir.Op

SET [21Li.DirMode]=Reverse &

SIG 50/51Q.FwdDir.Op

SIG 21Li.ZG.StA
&
SET Ia>0.04In

SIG 21L.LoadEnchPG.StA

SIG 21Li.ZG.StB
& >=1
SET Ib>0.04In

SIG 21L.LoadEnchPG.StB

SIG 21Li.ZG.StC
&
SET Ic>0.04In

SIG 21L.LoadEnchPG.StC

Figure 3.11-27 Logic of distance protection (phase-to-ground, i=2~6)

"21Li.ZG.StA" means that zone i of phase-to-ground distance element starts. (phase A)

"21Li.ZG.StB" means that zone i of phase-to-ground distance element starts. (phase B)

"21Li.ZG.StC" means that zone i of phase-to-ground distance element starts. (phase C)

"Flag.21Li.ZG" means that measured impedance of zone i of phase-to-ground distance element is

inside the operation area.

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 3 Protection Functions

SIG 21Li.ZP.Enabled
&
SIG FD.Pkp Flag.21Li.ZP

EN [21Li.ZP.En_NegDir_Blk]

SET [21Li.DirMode]=Forward & &

>=1 &
SIG 50/51Q.RevDir.Op 21Li.Flg_PSBR_ZP

SET [21Li.DirMode]=Reverse &

SIG 50/51Q.FwdDir.Op

SIG 21Li.ZP.StAB
3
&
SET Iab>0.04In

SIG 21L.LoadEnchPP.StAB

SIG 21Li.ZP.StBC
& >=1
SET Ibc>0.04In

SIG 21L.LoadEnchPP.StBC

SIG 21Li.ZP.StCA
&
SET Ica>0.04In

SIG 21L.LoadEnchPP.StCA

Figure 3.11-28 Logic of distance protection (phase-to-phase, i=2~6)

"21Li.ZP.StAB" means that zone i of phase-to-phase distance element starts. (phase AB)

"21Li.ZP.StBC" means that zone i of phase-to-phase distance element starts. (phase BC)

"21Li.ZP.StCA" means that zone i of phase-to-phase distance element starts. (phase CA)

"Flag.21Li.ZP" means that measured impedance of zone i of phase-to-phase distance element is

inside the operation area.

SIG 21L1.Rls_PSBR & 21L1.ZG.Op

[21L1.ZG.t_Op] 0
SIG Flag.21L1.ZG >=1
21L1.Op
&
[21L1.ZP.t_Op] 0
SIG Flag.21L1.ZP 21L1.ZP.Op

Figure 3.11-29 Logic of distance protection operating (zone 1)

PCS-902S Line Distance Relay 3-83

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 3 Protection Functions

[21Li.ZG.t_Op] 0 >=1
SIG 21Li.Rls_PSBR & 21Li.ZG.Op
&
SIG Flag.21Li.ZG [21Li.ZG.t_ShortDly] 0 >=1
21Li.Op

[21Li.ZP.t_Op] 0 >=1
& 21Li.ZP.Op
&
SIG Flag.21Li.ZP [21Li.ZP.t_ShortDly] 0

SIG 21Li.Enabled_ShortDly

3 Figure 3.11-30 Logic of distance protection operating (zone i, i=2~6)

SIG 21Li.Flg_PSBR_ZG >=1

21Li.Flg_PSBR
SIG 21Li.Flg_PSBR_ZP

SIG 21Li.En_PSBR &

21Li.Enable_PSBR
SIG 21Li.Blk_PSBR

SIG FD.Pkp &

SIG 21Li.Flg_PSBR

SIG 21Li.Enable_PSBR &

EN [21Li.En_PSBR]
>=1
SIG -0.03Un<U1cosΦ<0.08Un 150ms 0 &
>=1 21Li.Rls_PSBR
SIG -0.1Un<U1cosΦ<0.25Un 500ms 0

>=1
&
SIG |I0|+|I2|>m×I1

SIG 21Li.Flg_PSBR

SET I1>[21L.I_PSBR] 0 3s & &

0 160ms >=1
SIG FD.Pkp

Figure 3.11-31 Logic of PSBR (i=1~6)

"21Li.Rls_PSBR" is the releasing signal of power swing blocking element for zone i of distance
protection.

"21Li.Flg_PSBR_ZG" is the operating condition of power swing blocking element for zone i of
phase-to-ground distance element.

"21Li.Flg_PSBR_ZP" is the operating condition of power swing blocking element for zone i of
phase-to-phase distance element.

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 3 Protection Functions

3.11.12 Settings
Table 3.11-3 Settings of distance protection

Name Range Step Unit Default Description

The angle of directional line in the
second quadrant for quadrilateral
21L.Ang_Alpha 5~30 1 ° 15
phase-to-ground distance
element
The angle of directional line in the
fourth quadrant for quadrilateral

3
21L.Ang_Beta 5~30 1 ° 15
phase-to-ground distance
element
Phase-to-ground angle setting of
load trapezoid characteristics, it
should be set according to the
21L.LoadEnch.ZG.phi 5~50 1 ° 12
maximum load area angle
(φLoad_Max), φLoad_Max+5° is
recommended.
Phase-to-ground resistance
setting of load trapezoid
characteristics, it should be set
21L.LoadEnch.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 40.000
according to the minimum load
resistance, 70%~90% minimum
load resistance is recommended.
Phase-to-phase angle setting of
load trapezoid characteristics, it
should be set according to the
21L.LoadEnch.ZP.phi 5~50 1 ° 12
maximum load area angle
(φLoad_Max), φLoad_Max+5° is
recommended.
Phase-to-phase resistance
setting of load trapezoid
characteristics, it should be set
21L.LoadEnch.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 40.000
according to the minimum load
resistance, 70%~90% minimum
load resistance is recommended.
Current setting for power swing
21L.I_PSBR (0.050~40.000)×In 0.001 A 1.000
blocking releasing
Mho Characteristics option of phase-
21L.ZG.Opt_Characteristic Mho
Quad to-ground distance element
Mho Characteristics option of phase-
21L.ZP.Opt_Characteristic Mho
Quad to-phase distance element
Forward Direction option for zone i of
21Li.DirMode Forward
Reverse distance protection (i=2~6)

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 3 Protection Functions

Name Range Step Unit Default Description

Non_Directional
Real component of zero-
sequence compensation
21Li.Real_K0 -4.000~4.000 0.001 0.660
coefficient for zone i of distance
protection (i=1~6)
Imaginary component of zero-
sequence compensation
21Li.Imag_K0 -4.000~4.000 0.001 0.000
coefficient for zone i of distance
protection (i=1~6)

3 Phase angle of positive-

21Li.phi1_Reach 30~89 1 ° 78 sequence impedance for zone i
of distance protection (i=1~6)
Downward offset angle of the
reactance line for zone i of phase-
21Li.ZG.RCA 0~45 1 ° 12
to-ground distance element
(i=1~6)
Impedance setting of zone i of
21Li.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 phase-to-ground distance
element (i=1~6)
Shift impedance setting of zone i
21Li.ZG.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element (i=2~6)
Resistance setting of zone i of
21Li.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-ground
distance element (i=1~6)
Shift resistance setting of zone i
21Li.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element (i=1~6)
Phase shift of zone i of phase-to-
21Li.ZG.phi_Shift 0~30 1 ° 0
ground distance element (i=1~6)
Time delay of zone i of phase-to-
21Li.ZG.t_Op 0.000~10.000 0.001 s 0.200
ground distance element (i=1~6)
Short time delay of zone i of
21Li.ZG.t_ShortDly 0.000~10.000 0.001 s 0.100 phase-to-ground distance
element (i=2~6)
Enabling/disabling zone i of
Disabled
21Li.ZG.En Enabled phase-to-ground distance
Enabled
element (i=1~6)
Enabling/disabling zone i of
Disabled phase-to-ground distance
21Li.ZG.En_BlkAR Disabled
Enabled element operating to block AR
(i=1~6)
21Li.ZG.En_3I0 Disabled Enabled Enabling/disabling zone i of

3-86 PCS-902S Line Distance Relay

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 3 Protection Functions

Name Range Step Unit Default Description

Enabled phase-to-ground distance
element controlled by residual
current fault detector element
(i=1~6)
Enabling/disabling zone i of
phase-to-ground distance
Disabled
21Li.ZG.En_NeuDir_Blk Enabled element blocked by direction
Enabled
control element of earth fault
protection (i=1~6)
Enabling/disabling zone i of 3
phase-to-ground distance
Disabled element blocked by direction
21Li.ZG.En_NegDir_Blk Enabled
Enabled control element of negative-
sequence overcurrent protection
(i=1~6)
Enabling/disabling phase-to-
Disabled ground load trapezoid
21Li.LoadEnch.ZG.En Enabled
Enabled characteristics for zone i of
distance protection (i=1~6)
Downward offset angle of the
reactance line for zone i of phase-
21Li.ZP.RCA 0~45 1 ° 12
to-phase distance element
(i=1~6)
Impedance setting of zone i of
21Li.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 phase-to-phase distance element
(i=1~6)
Shift impedance setting of zone i
21Li.ZP.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element (i=2~6)
Resistance setting of zone i of
21Li.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-phase
distance element (i=1~6)
Shift resistance setting of zone i
21Li.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element (i=1~6)
Phase shift of zone i of phase-to-
21Li.ZP.phi_Shift 0~30 1 ° 0
phase distance element (i=1~6)
Time delay of zone i of phase-to-
21Li.ZP.t_Op 0.000~10.000 0.001 s 0.200
phase distance element (i=1~6)
Short time delay of zone i of
21Li.ZP.t_ShortDly 0.000~10.000 0.001 s 0.100 phase-to-phase distance element
(i=2~6)
21Li.ZP.En Disabled Enabled Enabling/disabling zone i of

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 3 Protection Functions

Name Range Step Unit Default Description

Enabled phase-to-phase distance element
(i=1~6)
Enabling/disabling zone i of
Disabled
21Li.ZP.En_BlkAR Disabled phase-to-phase distance element
Enabled
operating to block AR (i=1~6)
Enabling/disabling zone i of
phase-to-phase distance element
Disabled
21Li.ZP.En_NegDir_Blk Enabled blocked by direction control
Enabled
element of negative-sequence

3 overcurrent protection (i=1~6)

Enabling/disabling phase-to-
Disabled phase load trapezoid
21Li.LoadEnch.ZP.En Enabled
Enabled characteristics for zone i of
distance protection (i=1~6)
Enabling/disabling fixed
Disabled
21Li.En_ShortDly Disabled accelerate zone i of distance
Enabled
protection (i=2~6)
Enabling/disabling zone i of
Disabled
21Li.En_PSBR Enabled distance protection controlled by
Enabled
PSBR (i=1~6)
Enabling/disabling zone i of
Disabled
21Li.En_ReacLine Disabled distance protection controlled by
Enabled
the reactance line (i=1~6)

The first 9 settings are shared by pilot distance zone.

Table 3.11-4 Settings of pilot distance zone

Name Range Step Unit Default Description

Real component of zero-
sequence compensation
21L.PilotFwd.Real_K0 -4.000~4.000 0.001 0.660
coefficient for forward pilot
distance zone
Imaginary component of
zero-sequence
21L.PilotFwd.Imag_K0 -4.000~4.000 0.001 0.000
compensation coefficient for
forward pilot distance zone
Phase angle of positive-
21L.PilotFwd.phi1_Reach 30~89 1 ° 78 sequence impedance for
forward pilot distance zone
Downward offset angle of the
21L.PilotFwd.ZG.RCA 0~45 1 ° 12
reactance line for forward

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 3 Protection Functions

Name Range Step Unit Default Description

pilot distance zone (phase-to-
ground)
Impedance setting of forward
21L.PilotFwd.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
ground)
Resistance setting of
quadrilateral forward pilot
21L.PilotFwd.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
ground)
Shift resistance setting of 3
quadrilateral forward pilot
21L.PilotFwd.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
ground)
Enabling/disabling forward
pilot distance zone controlled
Disabled
21L.PilotFwd.ZG.En_3I0 Enabled by residual current fault
Enabled
detector element (phase-to-
ground)
Enabling/disabling forward
pilot distance zone blocked
Disabled
21L.PilotFwd.ZG.En_NeuDir_Blk Enabled by direction control element
Enabled
of earth fault protection
(phase-to-ground)
Enabling/disabling forward
pilot distance zone blocked
Disabled by direction control element
21L.PilotFwd.ZG.En_NegDir_Blk Enabled
Enabled of negative-sequence
overcurrent protection
(phase-to-ground)
Enabling/disabling load
Disabled trapezoid characteristics for
21L.PilotFwd.LoadEnch.ZG.En Enabled
Enabled forward pilot distance zone
(phase-to-ground)
Downward offset angle of the
reactance line for forward
21L.PilotFwd.ZP.RCA 0~45 1 ° 12
pilot distance zone (phase-to-
phase)
Impedance setting of forward
21L.PilotFwd.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
phase)
Resistance setting of
21L.PilotFwd.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral forward pilot
distance zone (phase-to-

PCS-902S Line Distance Relay 3-89

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 3 Protection Functions

Name Range Step Unit Default Description

phase)
Shift resistance setting of
quadrilateral forward pilot
21L.PilotFwd.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
phase)
Enabling/disabling forward
pilot distance zone blocked
Disabled by direction control element
21L.PilotFwd.ZP.En_NegDir_Blk Enabled
Enabled of negative-sequence

3 overcurrent protection
(phase-to-phase)
Enabling/disabling load
Disabled trapezoid characteristics for
21L.PilotFwd.LoadEnch.ZP.En Enabled
Enabled forward pilot distance zone
(phase-to-phase)
Enabling/disabling forward
Disabled
21L.PilotFwd.En_PSBR Enabled pilot distance zone controlled
Enabled
by PSBR
Enabling/disabling forward
Disabled
21L.PilotFwd.En_ReacLine Disabled pilot distance zone controlled
Enabled
by the reactance line
Real component of zero-
sequence compensation
21L.PilotRev.Real_K0 -4.000~4.000 0.001 0.660
coefficient for reverse pilot
distance zone
Imaginary component of
zero-sequence
21L.PilotRev.Imag_K0 -4.000~4.000 0.001 0.000
compensation coefficient for
reverse pilot distance zone
Phase angle of positive-
21L.PilotRev.phi1_Reach 30~89 1 ° 78 sequence impedance for
reverse pilot distance zone
Downward offset angle of the
reactance line for reverse
21L.PilotRev.ZG.RCA 0~45 1 ° 12
pilot distance zone (phase-to-
ground)
Impedance setting of reverse
21L.PilotRev.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
ground)
Resistance setting of
quadrilateral reverse pilot
21L.PilotRev.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
ground)

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 3 Protection Functions

Name Range Step Unit Default Description

Shift resistance setting of
quadrilateral reverse pilot
21L.PilotRev.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
ground)
Enabling/disabling reverse
pilot distance zone controlled
Disabled
21L.PilotRev.ZG.En_3I0 Enabled by residual current fault
Enabled
detector element (phase-to-
ground)
Enabling/disabling load 3
Disabled trapezoid characteristics for
21L.PilotRev.LoadEnch.ZG.En Enabled
Enabled reverse pilot distance zone
(phase-to-ground)
Downward offset angle of the
reactance line for reverse
21L.PilotRev.ZP.RCA 0~45 1 ° 12
pilot distance zone (phase-to-
phase)
Impedance setting of reverse
21L.PilotRev.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
phase)
Resistance setting of
quadrilateral reverse pilot
21L.PilotRev.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
phase)
Shift resistance setting of
quadrilateral reverse pilot
21L.PilotRev.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
phase)
Enabling/disabling load
Disabled trapezoid characteristics for
21L.PilotRev.LoadEnch.ZP.En Enabled
Enabled reverse pilot distance zone
(phase-to-phase)
Enabling/disabling reverse
Disabled
21L.PilotRev.En_PSBR Enabled pilot distance zone controlled
Enabled
by PSBR
Enabling/disabling reverse
Disabled
21L.PilotRev.En_ReacLine Disabled pilot distance zone controlled
Enabled
by the reactance line

3.12 Series Compensation

Series compensation is applied to long distance transmission lines to improve power system

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stability and increases the power transfer capability of transmission lines and so on. However,
series compensation has also brought a series of new problems to the operation and protection of
transmission line. Series compensation destroys the uniformity of transmission line impedance,
because it is a centralized capacitive reactance, make the phase relationship between voltages
and currents be changed, which has influence on the protection functions.

In general, it is relatively good to the protection functions that the series compensation is equipped
in middle of transmission line, but not convenient to operation maintenance. It is convenient to
operation maintenance that the series compensation is equipped in both ends of transmission line,
but has strong influence on the protection function.

3 3.12.1 Series Compensation System Introduction

Series compensation is a technique of compensating the circuit inductance by connecting

capacitors in series. The series complement system can be divided into two types: fixed series
compensation (FSC) and controllable series compensation (CSC). FSC is mainly used in the actual
project. Its structure is shown in Figure 3.12-1.

C
+ -

MOV

GAP

Figure 3.12-1 The schematic diagram of series compensation system

1. Series capacitor bank (C)

Series capacitor bank is composed of several capacitors in series and parallel, which is the core
component of series compensation system. In general, the compensation degree of series
compensation system is about 30%~40%.

2. Metal-oxide varistors (MOV)

MOV is the main protection element of the series capacitor bank. Because MOV has the nonlinear
characteristics of voltage-current, when the fault current is large, MOV will conduct timely to reduce
the voltage at both ends of series capacitor bank to prevent the series capacitor bank from being
broken down due to the high voltage.

3. Spark gap (GAP)

The shunt GAP is used to protect series capacitor bank and MOV. When MOV's current and energy

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exceed the threshold, GAP will discharge and bypass series capacitor bank and MOV.

4. Bypass circuit breaker (S)

The bypass circuit breaker is mainly used to control the switching state of series capacitor bank
and decide whether to put series compensation system into service. Because GAP itself does not
have the ability to extinguish the arc, in order to enhance the GAP's ability to extinguish the arc, a
bypass circuit breaker is added in series compensation system to extinguish the arc by shorting
GAP and protect series compensation system.

5. Damping circuit (D)

The damping circuit is composed of resistance and inductance in parallel, during GAP discharge,
the discharge current rising too fast and easy to achieve bigger current value, in order to prevent
3
the damage to other devices by the discharge current, so the damping circuit is added to suppress
the rising velocity of GAP's discharge current, so as to reduce the risk of the damage to the device.

3.12.2 Functions Description

3.12.2.1 Series Compensation System Influence

1. Distance Protection overreach

The series capacitor is a centralized capacitive reactance, and shortens the physical distance of
transmission line, which results that the measurement impedance of underreaching distance
protection may be beyond the whole line, so as to cause maloperation for external fault. As shown
in Figure 3.12-2, when the series capacitor is put into service, the series capacitor will make the
short-circuit impedance step mutation if the short-circuit fault occurs.

-jXC

ZL1 ZL2

jX

-jXC
ZL1
ZL2

Figure 3.12-2 The influence on short-circuit impedance

As shown in Figure 3.12-3, for IED 1, according to the conventional setting method, zone 1 of
distance protection should be about 80% of the whole line. If the short-circuit fault occurs after the
series capacitor, it is assumed that the fault occurs at point K, and the series capacitor leads to the
reduction of the measured impedance, the device incorrectly considers it as internal fault and

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misoperate. Therefore, the influence from the series capacitor should be considered when calculate
the setting of zone 1 of distance protection.

1 2 3 K 4
EM EN

M Q N

Figure 3.12-3 Equivalent circuit of series compensated line

2. Voltage reversal
3 The voltage distribution in series compensated line is briefly analyzed as follows. As shown in
Figure 3.12-4, when a metal earth fault occurs at point K, it is not considered that the series
capacitor is bypassed due to internal protection, and the voltage on side N is calculated as follows:

𝑍𝐿2 − 𝑍𝐶
𝑈̇𝑁 = × 𝐸̇𝑁
𝑍𝑁 + 𝑍𝐿2 − 𝑍𝐶

Where:

ZL2 is the line impedance from fault point K to side N.

ZC is the impedance of the series capacitor.

ZN is the system impedance on side N

EN is the potential on side N.

IM IN
K
EM EN
ZM ZN

M N
UM
UQ
EM F EN

UN

Figure 3.12-4 Equivalent circuit of internal fault in series compensated line

In series compensented line, if the fault occurs close to series compensation system, then the total
impedance between VT and the fault point is capacitve (i.e., ZC>ZL2 and ZC<ZN+ZL2), and the
voltage distribution is shown in Figure 3.12-4. At this point, the phase of measured voltage UN
reverses 180° comparing with normal phase (no series compensation), i.e., voltage reversal.

In series compensation system, those protection functions using the voltage quantity, such as,
distance protection, directional element, normal selectivity will be affected when the voltage is
reverse.

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3. Current reversal

In series compensated line, using busbar voltage as the reference, the short-circuit current may
leads the voltage, about 180°, i.e., current reversal. When the zero-sequence impedance and
negative-sequence impedance of the system is smaller than the capacitive reactance of the line,
zero-sequence and negative-sequence current measured by the device will also be reverse. When
the fault resistance is small, MOV is conducted, and the equivalent capacitive reactance of series
compensation system is reduced, the current reversal will not occur.

The current reversal generally occurs near the series capacitor connected to the large system with
large fault resistance. As shown in Figure 3.12-4, when a metal earth fault occurs at point K, it is
not considered that the series capacitor is bypassed due to internal protection, the total impedance
from the fault point to side N is capacitive when ZC>ZN+ZL2, i.e, current reversal.
3
Those protections using the current quantity, such as, distance protection, directional element,
current differential protection, normal selectivity will be affected when the current is reverse.

3.12.2.2 Prevent Distance Protection Overreaching

1. DPFC distance protection

When a fault happens to the system with series compensation, and the fault point is behind the series
capacitor, external busbar fault in forward direction as shown in Figure 3.12-5, the voltage variation of
the fault point adds ZC×I1 comparing with the system without series compensation. ZC is the impedance
of series capacitor. Assume that U|o| is pre-fault voltage of the fault point.

𝛥𝑈𝑜𝑝 = 𝑈|0| + 𝑍𝐶 × 𝐼1

So the voltage variation of setting point is greater than the threshold value, leads DPFC distance
protection to overreaching operation for external fault. In order to prevent DPFC distance protection from
overreaching, the threshold value is set as "U|0|+[U_Mov_Prot]" with a certain margin.

21D.Z_Set

UM
C

I1

ZC×I1

ΔUop U|o|

Figure 3.12-5 Voltage variation of DPFC distance protection

2. Zone 1 of distance protection

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UM C
Z1 I1

I2

UM C

Figure 3.12-6 Zone 1 overreaching during external fault in forward direction

3 As shown in Figure 3.12-6, when an external fault occurs behind the series capacitor, the series
capacitor will make the measured impedance become small if the forward direction of the device
includes the series capacitor, which will lead underreaching distance protection (zone 1 of distance
protection) to overreaching.

The device provides the setting [U_Mov_Prot], and protecting range of zone 1 of distance protection will
be adjusted in real-time based on the setting and the current (I1) flowing through where the device
located. The setting of zone 1 of distance protection is set as 70%~85% of line impedance not including
the series capacitor, the actual protecting range reduces:

[𝑈_𝑀𝑂𝑉_𝑃𝑟𝑜𝑡]
𝑍𝑠𝑐 = | |
√2 × 𝐼1

Zone 1 of distance protection and DPFC distance protection share the setting [U_Mov_Prot], which is
set based on the peak value of MOV's polarizing voltage.

The reactance compensation changes in real-time with the fault current. When the fault level is relatively
low due to the fault resistance, the fault current is relatively small and the possibility of MOV operating
is small, it is easier to overreaching, so the compensation degree is higher.

3.12.2.3 Prevent Voltage Reversal

1. DPFC distance protection

For a fault with the series capacitor in reverse direction, underreaching DPFC distance element may
maloperate when the setting value is too small. An overreaching DPFC distance element is equipped,
the setting [21D.Z_Overreach] is set to reach system impedance in remote end, and ensure no
maloperation for a short-circuit with the series capacitor in reverse direction. The logic relationship
between underreaching DPFC distance element and overreaching DPFC distance element is "AND" to
prevent DPFC distance protection from maloperation for the fault in reverse direction. Both
underreaching DPFC distance element and overreaching DPFC distance element will operate for the
fault in forward direction.

2. Zone 1 of distance protection

In the event of three-phase fault, undervolatge distance element will maybe operate. In order to ensure
that distance protection operates reliably, memorized positive-sequence voltage is selected as the
polarized voltage. However, for the series compensated line, in the case of high voltage, the voltage
reversal may cause incorrect direction judgement, so as to lead to undesired operation or miss operation.

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In order to resolve the influence of voltage reversal on distance element, memorized positive-sequence
voltage will always be adopted as polarized voltage for any cases (not only for undervoltage distance
element).

3.12.2.4 Prevent Direction Control Element Misjudging

When is an asymmetric earth fault occurs in forward direction, zero-sequence or negative-sequence

voltage used as the polarized voltage of direction element can be reversed. Taking zero-sequence circuit
as an example, when the equivalent zero-sequence impedance behind the device is capacitive,
conventional directional zero-sequence element will think it as the fault in reverse direction, as shown
in Figure 3.12-7.

XC
3

X'S0

Figure 3.12-7 Asymmetrical fault

′
When XS0 < XC and zero-sequence voltage is reverse, zero-sequence voltage should be compensated.
The compensation equation is U0′ = U0 − I0 × jX0com . The device provides the setting
[50/51G.DIR.Z0_Comp], which can be set as XC. Because line zero-sequence impedance is greater
than line positive-sequence impedance, it only compensates a little part of transmission line, so the
directionality is not lost for reverse fault.

Similarly, negative-sequence voltage should be also compensated to prevent from negative-

sequence voltage reversal. The device provides the setting [50/51Q.DIR.Z2_Comp], which can be
set as XC.

For non series compensated line, series compensation is not equipped in local end, or series
compensation is equipped in local end but the measured voltage is from busbar VT, the settings
[50/51G.DIR.Z0_Comp] and [50/51Q.DIR.Z2_Comp] can be set as "0" because no voltage reversal
happens.

There is no special treatment for direction control element of phase

overcurrent protection, so directional phase overcurrent protection is not
applicable to the series compensated line, and the direction control element
of phase overcurrent protection needs to be disabled when the device is
used for the series compensated line.

3.13 Out-of-step Protection (78)

When the disturbance happens to the power system because of some reason (such as short circuit,
fault clear, power supply injecting or separating, etc.), the phase angle difference of the electric
potential between the synchronous generators of parallel operation will change with time, and the

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voltage of each node and the current of each circuit in the system also change with time, this
phenomenon is called oscillation. The oscillation that can keep system stably and synchronously
operate is called synchronous oscillation, and that leads to lose synchronization and that the
system can't normally operate is called asynchronous oscillation.

For the power grid of loss synchronous, the voltage of each node in the tie line that synchronous
or asynchronous oscillation happens to will oscillate periodically, and where the voltage oscillation
is the most violent in each tie line is the center of synchronous or asynchronous oscillation. In
general, the voltage oscillation is more violent more close to the oscillation center. Out-of-step
center is the point where the lowest voltage appears in the tie line of asynchronous oscillation in
the process of out-of-step oscillation, i.e., the oscillation center of the tie line of asynchronous
3 oscillation. The phase angle of bus voltage difference on either side of out-of-step center will
change within 0°~180°~360° periodically. Considering the selectivity, the separation should be
performed within 2~3 out-of-step period or the corresponding time delay after the system is out of
step, otherwise the out-of-step oscillation among multiple generators may is developed, further
expanding the accident, so as to cause system separation even collapse accident. So when the
out-of-step operation time or oscillation times is greater than specified value, out-of-step protection
should operate to separate.

3.13.1 Function Description

In the event that the interconnected system is out-of-step, the system can be reduced as a dual-
machine system as shown in Figure 3.13-1.

EM U EN
I
ZLine

Figure 3.13-1 Dual-machine equivalent system

For the sake of easy analysis, assumptions have to be made as follows:

1. The potential of the two machines are EM and EN respectively, and their amplitude are both
equal to E1.

2. The equivalent impedance angle of system is 90°

Taking EN as reference vector, whose initial phase angle is 0° and angle velocity is ω. At the side
M, the initial phase angle of equivalent potential EM is α (i.e., during normal operation condition, the
system′s power angle δ is α), whose increment of the angle velocity is Δω relative to side N, so

𝐸𝑁 = 𝐸1 × 𝑐𝑜𝑠( 𝜔 × 𝑡)

𝐸𝑀 = 𝐸1 × 𝑐𝑜𝑠( (𝜔 + 𝛥𝜔) × 𝑡 + 𝛼)

Suppose the power angle between both sides of the system is

𝛿 = 𝛥𝜔 × 𝑡 + 𝛼

The equivalent system vector diagram of Figure 3.13-1 is illustrated in Figure 3.13-2.

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EM U Ucosφ EN

Uscv

E1 E1

φ
½δ

Figure 3.13-2 Dual-machine equivalent system

3
Where:

USCV is the voltage of oscillation center

U is the measured voltage by the device

As shown in Figure 3.13-2, the voltage of oscillation center USCV is:

𝛿
𝑈𝑆𝐶𝑉 = 𝑈 × 𝑐𝑜𝑠 𝜑 = 𝐸1 × 𝑐𝑜𝑠
2

In the case that the system is in synchronous condition, Δω=0, the voltage of oscillation center
maintains be unchanged, that is:

𝛼
𝑈𝑆𝐶𝑉 = 𝑐𝑜𝑠
2

Make calculus for the voltage of oscillation center,

𝑑𝑈𝑆𝐶𝑉 𝐸1 𝛿 𝑑𝛿
= − × 𝑠𝑖𝑛 ×
𝑑𝑡 2 2 𝑑𝑡

The above equation describe the relationship between the voltage change rate of oscillation center
and system slip frequency dδ/dt , which indicates the voltage variation of oscillation center is
independent of system impedance.

When the power angle is 180°, the voltage variation of oscillation center is maximum, and when
the power angle is 0°, the voltage variation of oscillation center is minimum. In the case that the
system is in out-of-step condition, the voltage of oscillation center varies periodically with the
oscillation cycle as 180°, that is:

⚫ If the value of Δω is larger than 0, namely accelerating out-of-step condition, the variation trend
of δ is 0°－360°(0°)－360°, the variation curve of oscillation center voltage is shown in Figure
3.13-3.

⚫ If the value of Δω is less than 0, namely decelerating out-of-step condition, the variation trend
of δ is 360°－0°(360°)－0°, the variation curve of oscillation center voltage is shown in Figure
3.13-4.

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t
0

-1

Figure 3.13-3 Variation curve of oscillation center voltage (Acceleration)

3 U

t
0

-1

Figure 3.13-4 Variation curve of oscillation center voltage (Deceleration)

According to the above analysis, it can be shown that there is certain functional relation between
the oscillation center voltage and power angle δ, thus the oscillation center voltage (Ucosφ) can
be used to reflect the variation of power angle. Power angle varies continuously as an electrical
quantity. As a result, the oscillation center voltage varies continuously during out-of-step
oscillation, crossing the zero point. However, sudden variation or discontinuous change is a
distinguished feature of oscillation center voltage during fault occurrence or clearance. During
synchronous oscillation, the oscillation center voltage also varies continuously but it does not
cross the zero point. Therefore, the oscillation center voltage can be used to discriminate
among out-of-step oscillation, short-circuit fault and synchronous oscillation.

The variation range of oscillation center voltage (Ucosφ) can be divided into seven zones on the
variation plane, as shown in Figure 3.13-5. From the above analysis, the variation rules of
oscillation center voltage (Ucosφ) during out-of-step oscillation are as follows:

⚫ During accelerating out-of-step condition, the variation rule of Ucosφ is

0→1→2→3→4→5→6→0

⚫ During decelerating out-of-step condition, the variation rule of Ucosφ is

0→6→5→4→3→2→1→0

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U U

1 1
0 0
1 1
2 2
3 3
t t
0 4 0 4
5 5
6 6
-1
0 0
-1

Figure 3.13-5 The variation rule of oscillation center voltage

3
If the oscillation center voltage varies as the above mentioned rules, the device consider it as out-
of-step condition and issues tripping command after the time delay (i.e., the setting [78.N_Limit]),
performing separation. The above analysis is based on the assumption that system impedance
angle is 90°, while in practical system it is not, thus angle compensation is required. As shown in
Figure 3.13-6, setting the system impedance angle is determined by the setting [78.phi1_Reach]
in the device, the angle compensation is made to the oscillation center voltage,

𝑈𝑆𝐶𝑉 = 𝑈 × 𝑐𝑜𝑠(𝜑 + 90 − [78. 𝑝ℎ𝑖1_𝑅𝑒𝑎𝑐ℎ])

I'
EM U EN
U cos 

 
2

Figure 3.13-6 Vector diagram of the oscillation center voltage

In order to locate the distance between the oscillation center and where the device is equipped,
setting impedance measurement element is used to confirm the operation range of separation
device, the operation characteristic of zone relay based on impedance discrimination is shown
in Figure 3.13-7.

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ZM ZLine ZN
EM 52 52 EN

I U

PCS-931S

ZRev ZFwd

Where:

3 ZM and ZN are respective system impedances.

ZFwd is the impedance from zone relay location to side-N system, i.e., [78.Z_Fwd]

ZRev is the impedance from zone relay location to side-M system, i.e., [78.Z_Rev]

jX

ZN

[78.Z_Fwd]

R
[78.Z_Rev]
δ O

ZM

Figure 3.13-7 Operation characteristic of zone detector element

The measured impedance is the impedance of phase-BC, zone relay meets the operation criterion
when the measured impedance is within the range of operation characteristic. Out-of-step
protection will operate when both zone relay and out-of-step relay operate.

In order to prevent out-of-step protection from being initiated under normal conditions, the device
calculates in real-time the voltage vector of two points (point A and point B) based on measured
voltage and current, so as to calculate the phase angle between two voltage (δ), which participates
in logic discrimination of out-of-step protection.

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3.13.2 Function Block Diagram

78

78.Enable 78.On

78.Block 78.Blocked

78.Clr_Counter 78.Valid

78.St

78.Op

3
3.13.3 I/O Signals
Table 3.13-1 Input signals of out-of-step protection

No. Input Signal Description

1 78.Enable Input signal of enabling out-of-step protection
2 78.Block Input signal of blocking out-of-step protection
3 78.Clr_Counter Clear the counter

Table 3.13-2 Output signals of out-of-step protection

No. Output Signal Description

1 78.On Out-of-step protection is enabled.
2 78.Blocked Out-of-step protection is blocked.
3 78.Valid Out-of-step protection is valid.
4 78.St Out-of-step protection starts.
5 78.Op Out-of-step protection operates.

3.13.4 Logic

EN [78.En] &
78.On
SIG 78.Enable
&
SIG 78.Block >=1 78.Blocked

SIG Fail_Device
&
78.Valid

Figure 3.13-8 Logic of enabling out-of-step protection

In order to prevent out-of-step protection from maloperation under normal conditions or faulty
conditions, the system will be thought as oscillation only the following conditions are all met.

1. Measured positive-sequence voltage (U1) is smaller than 0.95Un.

2. Three phase currents are all greater than 0.12In (In is rated phase current.).

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3. The change rate of power angle (dδ/dt) is within 0.2~8.

4. The power angle (δ) is greater than the minimum start angle ([78.Phi_Start]).

In order to prevent the circuit breaker from abnormality caused by too high tripping current when
the system is out of step, the device provides the maximum tripping angle [78.Phi_Trp], and the
power angle δ should be less than the setting.

SIG 78.Valid
&
SIG VTS.Alm t1 t2 78.St

SIG Ia>0.12In
&
3 SIG Ib>0.12In &
SIG Ic>0.12In
&

SIG |δ|>[78.phi_Start]

SIG U1<0.95Un &

SIG 8>dδ/dt>0.2
&
Counter>[78.N_Limit] >=1
SIG Ucosφ from + to -

SIG 78.Clr_Counter
&
Counter>[78.N_Limit]
SIG Ucosφ - to +
&
EN [78.En_Trp] 78.Op

SIG δ<[78.phi_Trp] &

>=1

SIG 78.Z_St
&

SIG 78.St

Figure 3.13-9 Logic of out-of-step protection

Where:

U1 is positive-sequence voltage.

t1 is the pickup time delay of discriminating oscillation, internal fixed value is 40ms.

t2 is the dropoff time delay of discriminating oscillation, internal fixed value is 3s.

"78.Z_st" means that the impedance characteristics of out-of-step protection meet the pickup
condition.

3.13.5 Settings
Table 3.13-3 Settings of out-of-step protection

Name Range Step Unit Default Description

78.En Disabled Enabled Enabling/disabling out-of-step protection

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Name Range Step Unit Default Description

Enabled
Disabled Enabling/disabling out-of-step protection
78.En_Trp Disabled
Enabled operate to trip
The forward impedance setting of zone detector
78.Z_Fwd (0.000~4Unn)/In 0.001 Ω 10.000
element
The reversal impedance setting of zone
78.Z_Rev (0.000~4Unn)/In 0.001 Ω 5.000
detector element
78.phi1_Reach 30~89 1 ° 78 The positive-sequence impedance angle
The minimum start angle, which generally
78.phi_Start 0~180 1 ° 60
should be greater than maximum load angle. 3
It is the maximum tripping angle after out-of-
step protection operating, which is used to
prevent the circuit breaker from incorrect
78.phi_Trp 0~180 1 ° 90
operation due to too large current during
tripping. It is generally set based on the
breaking capacity of circuit breaker.
The number setting of out-of-step cycle, and it
78.N_Limit 1~20 1 1
is set as 2~3 generally

3.14 Distance SOTF Protection (21SOTF)

When the circuit breaker is closed manually or automatically, it is possible to switch on to a

permanent fault. When the circuit breaker is switched onto the fault, the influence on power system
can be effectively decreased if main protection or fast protection can isolate the fault timely.

This is especially critical if the fault occurs in the remote end of transmission line, since main
protection would not clear the fault until the time delay of backup protection have elapsed. In this
situation, however, the fastest possible clearance is required. Distance SOTF (switch onto fault)
protection is a complementary function to distance protection. With distance SOTF protection, a
fast trip is achieved for a fault on the whole line, when the line is being energized. It shall be
responsive to all types of faults anywhere within the protected line.

3.14.1 Function Description

Distance SOTF protection shares pickup signal as initiation condition with distance protection. It is
selectable among zone 2, 3 or 4 of distance protection which is accelerated to trip by manual closing
or auto-reclosing, and they can enable or disable be controlled by power swing blocking. Distance
SOTF protection equips with independent time delay. Zone 2 of distance protection is fixedly
accelerated to trip by 1-pole AR. Zone 2 of distance protection is also accelerated to trip by pole
discrepancy condition. For single-phase fault, distance SOTF protection will accelerate to operate
if another fault happens to the healthy phase before auto-reclosing.

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3.14.2 Function Block Diagram

21SOTF

21SOTF.Enable 21SOTF.On

21SOTF.Block 21SOTF.Blocked

21SOTF.Valid

21SOTF.Op

21SOTF.Op_PDF

3
3.14.3 I/O Signals
Table 3.14-1 Input signals of distance SOTF protection

No. Input Signal Description

1 21SOTF.Enable Input signal of enabling distance SOTF protection
2 21SOTF.Block Input signal of blocking distance SOTF protection

Table 3.14-2 Output signals of distance SOTF protection

No. Output Signal Description

1 21SOTF.On Distance SOTF protection is enabled.
2 21SOTF.Blocked Distance SOTF protection is blocked.
3 21SOTF.Valid Distance SOTF protection is valid
Distance SOTF protection operates when manual closing or auto-reclosing to
4 21SOTF.Op
fault.
Distance SOTF protection operates when another fault happened under pole
5 21SOTF.Op_PDF
discrepancy conditions.

3.14.4 Logic

SIG 21SOTF.Enable &

21SOTF.On
EN [21SOTF.En]
&
SIG 21SOTF.Block >=1 21SOTF.Blocked

SIG Fail_Device
&
21SOTF.Valid

Figure 3.14-1 Logic of enabling distance SOTF protection

SIG 79.Close (3P) 0 [SOTF.t_En] 3-pole reclosing signal

SIG 79.Close (1P) 0 [SOTF.t_En] 1-pole reclosing signal

Figure 3.14-2 Logic of auto-reclosing signal

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SIG 52b_PhA
>=1
SIG 52b_PhB

SIG 52b_PhC
&
SIG FD.Pkp

SET [SOTF.Opt_Mode_ManCls]=CBPos
>=1
SET [SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos

SET [SOTF.Opt_Mode_ManCls]=All

SET [SOTF.Opt_Mode_ManCls]=ManClsBI
>=1

3
SET [SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos

SET [SOTF.Opt_Mode_ManCls]=All
& >=1
SIG FD.Pkp 0 [SOTF.t_En] Manual closing signal

SIG ManCls

SET [SOTF.Opt_Mode_ManCls]=All >=1

SET [SOTF.Opt_Mode_ManCls]=AutoInit &

SIG Ua<[SOTF.U_Ddl]
&
SIG Ub<[SOTF.U_Ddl]

SIG Uc<[SOTF.U_Ddl]

SIG FD.Pkp >=1 &

[SOTF.t_DdL] 0 Dead line
SIG VTS.Alm

SIG Ia<0.04In
&
SIG Ib<0.04In

SIG Ic<0.04In

Figure 3.14-3 Logic of manual closing signal

Distance SOTF protection can be initiated by several cases, including manual closing signal, 3-
pole reclosing, 1-pole reclosing and pole discrepancy conditions. The device provides a variety of
accelerated tripping modes by manual closing signal, which can choose circuit breaker position,
external binary signal of manual closing or dead line check.

1. Circuit breaker position (The setting [SOTF.Opt_Mode_ManCls] shall be set as "CBPos",

"ManClsBI/CBPos" or "All")

When the circuit breaker is in open position while the device does not pick up, then manual closing
signal will be kept for a certain time which is determined by the setting [SOTF.t_En], and distance
SOTF protection will be enabled.

2. External binary signal of manual closing (The setting [SOTF.Opt_Mode_ManCls] shall be set
as "ManClsBI", "ManClsBI/CBPos" or "All")

When external binary input of manual closing is energized, then manual closing signal will be kept
for a certain time which is determined by the setting [SOTF.t_En], and distance SOTF protection

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 3 Protection Functions

will be enabled.

3. Dead line check (The setting [SOTF.Opt_Mode_ManCls] shall be set as "AutoInit" or "All")

If the device does not pick up, when three-phase current is smaller than 0.04In and three-phase
voltage is smaller than the setting [SOTF.U_Ddl] with the time delay [SOTF.t_Ddl], then manual
closing signal will be kept for a certain time which is determined by the setting [SOTF.t_En], and
distance SOTF protection will be enabled.

SIG Manual closing signal

SIG 21SOTF.Valid &

3 SIG FD.Pkp
&
&
[21SOTF.t_ManCls] 0 21SOTF.Op_ManCls
EN [21SOTF.Zi.En_ManCls] &

SIG 21Li.Flg_PSBR

Figure 3.14-4 Logic of distance SOTF protection by manual closing signal (i=2~4)

SIG FD.Pkp &

&
SIG 21SOTF.Valid [21SOTF.t_3PAR] 0 >=1
21SOTF.Op_AR
SIG 3-pole reclosing signal

EN [21SOTF.Zi.En_3PAR]
& &
SIG 21Li.Flg_PSBR >=1
EN [21SOTF.Zi.En_PSBR]
&

SIG 21Li.Rls_PSBR

EN [21SOTF.Z2.En_1PAR] & &

[21SOTF.t_1PAR] 0
SIG 1-pole reclosing signal

SIG 52b_PhA 50ms 0 &

SIG 21L2.Rls_PSBR(A)

SIG 52b_PhB 50ms 0 & >=1

SIG 21L2.Rls_PSBR(B)

SIG 52b_PhC 50ms 0 &

SIG 21L2.Rls_PSBR(C)

>=1 &

SIG 21L2.Rls_PSBR

SIG 21SOTF.Valid & &

[21SOTF.t_PDF] 0 21SOTF.Op_PDF
SIG FD.Pkp

EN [21SOTF.En_PDF]

Figure 3.14-5 Logic of distance SOTF protection by 1-pole or 3-pole AR (i=2~4)

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SIG 21SOTF.Op_ManCls >=1

21SOTF.Op
SIG 21SOTF.Op_AR

Figure 3.14-6 Logic of distance SOTF protection

3.14.5 Settings
Table 3.14-3 Settings of distance SOTF protection

Name Range Step Unit Default Description

Time delay of enabling SOTF
protection (shared by distance 3
SOTF.t_En 0.200~100.000 0.001 s 0.400 SOTF protection, phase current
SOTF protection and residual
current SOTF protection)
Time delay of distance protection
21SOTF.t_ManCls 0.000~100.000 0.001 s 0.025 accelerating to trip when manual
closing
Time delay of distance protection
21SOTF.t_3PAR 0.000~100.000 0.001 s 0.025 accelerating to trip when 3-pole
reclosing
Time delay of distance protection
21SOTF.t_1PAR 0.000~100.000 0.001 s 0.025 accelerating to trip when 1-pole
reclosing
Disabled Enabling/disabling distance SOTF
21SOTF.En Enabled
Enabled protection
Enabling/disabling zone 2 of
Disabled
21SOTF.Z2.En_ManCls Enabled distance SOTF protection for
Enabled
manual closing
Enabling/disabling zone 3 of
Disabled
21SOTF.Z3.En_ManCls Disabled distance SOTF protection for
Enabled
manual closing
Enabling/disabling zone 4 of
Disabled
21SOTF.Z4.En_ManCls Disabled distance SOTF protection for
Enabled
manual closing
Enabling/disabling zone 2 of
Disabled
21SOTF.Z2.En_3PAR Enabled distance SOTF protection for 3-pole
Enabled
reclosing
Enabling/disabling zone 3 of
Disabled
21SOTF.Z3.En_3PAR Disabled distance SOTF protection for 3-pole
Enabled
reclosing
Enabling/disabling zone 4 of
Disabled
21SOTF.Z4.En_3PAR Disabled distance SOTF protection for 3-pole
Enabled
reclosing

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 3 Protection Functions

Name Range Step Unit Default Description

Enabling/disabling zone 2
Disabled controlled by PSB of distance
21SOTF.Z2.En_PSBR Enabled
Enabled SOTF protection for 3-pole
reclosing
Enabling/disabling zone 3
Disabled controlled by PSB of distance
21SOTF.Z3.En_PSBR Enabled
Enabled SOTF protection for 3-pole
reclosing
Enabling/disabling zone 4

3 21SOTF.Z4.En_PSBR
Disabled
Enabled
controlled by PSB of distance
Enabled SOTF protection for 3-pole
reclosing
Enabling/disabling zone 2 of
Disabled
21SOTF.Z2.En_1PAR Enabled distance SOTF protection for 1-pole
Enabled
reclosing
Time delay of distance protection
21SOTF.t_PDF 0.000~100.000 0.001 s 0.025 operating under pole discrepancy
conditions
Enabling/disabling distance SOTF
Disabled
21SOTF.En_PDF Disabled protection under pole discrepancy
Enabled
conditions
Undervoltage setting of deadline
SOTF.U_Ddl 0.000~100.000 0.001 V 30.000
detection
SOTF.t_Ddl 0.200~100.000 0.001 s 15.000 Time delay of deadline detection
Option of manual SOTF mode
ManClsBI: initiated by input signal
of manual closing
ManClsBI CBPos: initiated by CB position
CBPos ManClsBI/CBPos: initiated by
SOTF.Opt_Mode_ManCls ManClsBI/CBPos CBPos either input signal of manual closing
AutoInit or CB position
All AutoInit: initiated by no voltage
detection
All: initiated by both binary input
and no voltage detection

3.15 Phase Overcurrent Protection (50/51P)

Phase overcurrent protection is widely used in power systems. It can be used as main protection
of the feeder, and can also be used as backup protection for power equipment such as transformers,
reactors, and motors. When a fault occurs in the system, a fault current will be generated and phase
overcurrent protection can reflect the increase of the fault current.

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3.15.1 Function Description

The device can provide six stages of phase overcurrent protection with independent logic. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics. The
dropout characteristics can be set as instantaneous dropout, definite-time dropout or inverse-time
dropout. It can be chosen whether it is blocked by voltage control element or harmonic control
element. The direction control element can be set as no direction, forward direction and reverse
direction. Phase overcurrent protection picks up when the current exceeds the setting, and
operates after a certain time delay. Once the fault disappears, phase overcurrent protection will
dropout.

Phase overcurrent protection can operate to trip or alarm. For some specific applications, phase 3
overcurrent protection needs to be blocked by the external signal, so the device provides an input
signal to be used to block phase overcurrent protection.

EN [50/51Pi.En] &
50/51Pi.On
SIG 50/51Pi.Enable

&
SIG 50/51Pi.Block >=1 50/51Pi.Blocked

SIG Fail_Device
&
50/51Pi.Valid

Figure 3.15-1 Logic of enabling phase overcurrent protection

The pickup logic of phase overcurrent protection is shown in Figure 3.15-2:

SET Ia>0.95×[50/51Pi.I_Set]
>=1
SET Ib>0.95×[50/51Pi.I_Set] &
0 500ms &
SET Ic>0.95×[50/51Pi.I_Set]
50/51Pi.Pkp
SIG 50/51Pi.On

SIG 50/51Pi.Valid
&
FD.Pkp
SET [50/51Pi.Opt_Trp/Alm]=Alm

Figure 3.15-2 Pickup logic of phase overcurrent protection

3.15.1.1 Voltage Control Element

When a fault occurs at the remote end of a feeder, the fault current is relatively small, so the voltage
control element can be adopted to increase the sensitivity for this kind of fault. It can be enabled or
disabled via the setting [50/51Pi.En_Volt_Blk] (i=1~6). If VT circuit supervision is enabled and the
setting [50/51P.En_VTS_Blk] is set as "Enabled", the device will issue an alarm signal "VTS.Alm"
when VT circuit fails, and voltage control element will be blocked. If voltage control element is not
enabled, phase overcurrent protection will not be affected by VT circuit failure. The corresponding

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 3 Protection Functions

relationship between each phase and voltage control element is as follows.

Voltage criterion Phase A Phase B Phase C

Uab<[50/51P.VCE.Upp] Uab<[50/51P.VCE.Upp] Ubc<[50/51P.VCE.Upp]
Phase-to-phase
Uca<[50/51P.VCE.Upp] Ubc<[50/51P.VCE.Upp] Uca<[50/51P.VCE.Upp]
Negative-sequence U2>[50/51P.VCE.U2] U2>[50/51P.VCE.U2] U2>[50/51P.VCE.U2]
Zero-sequence U0_Cal>[50/51P.VCE.3U0] U0_Cal>[50/51P.VCE.3U0] U0_Cal>[50/51P.VCE.3U0]

The relationship among phase-to-phase criterion, negative-sequence criterion and zero-sequence

criterion is "OR". The logic of voltage control element is shown in Figure 3.15-3.

3 EN [50/51P.En_VTS_Blk] &

>=1

SIG VTS.Alm
>=1
SIG Uab, Ubc, Uca & 50/51P.VCE.Op
criterion
Voltage

SIG U2, U0_Cal

SIG Prot.BI_En_VT &

EN [Prot.En_VT]

Figure 3.15-3 Logic of voltage control element

3.15.1.2 Direction Control Element

Ua

[50/51P.DIR.phi_Min_Fwd]

Non-operating Ia
area

[50/51P.DIR.phi_Max_Rev] Operating area in

forward direction

[50/51P.DIR.RCA]

Operating area in
reverse direction

[50/51P.DIR.phi_Max_Fwd]

[50/51P.DIR.phi_Min_Rev] Non-operating
area

Figure 3.15-4 Operating characteristics of the direction element

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In order to ensure the selectivity of phase overcurrent protection, direction control element is also
available. The setting [50/51Pi.Opt_Dir] (i=1~6) is used to select the direction characteristics for
each stage of phase overcurrent protection: no direction, forward direction and reverse direction
are selectable.

The polarized voltage is selectable by the setting [50/51P.Opt_PolarizedVolt]. Takes the phase A
fault as an example, if the setting [50/51P.DIR.Opt_PolarizedVolt] is set as "Up", its operating
characteristics is shown in Figure 3.15-4. The principle of phase B and phase C is the same. The
operation boundary of the forward direction element can be set by [50/51P.DIR.phi_Min_Fwd] and
[50/51P.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be set
by [50/51P.DIR.phi_Min_Rev] and [50/51P.DIR.phi_Max_Rev]. When positive-sequence voltage
or phase-to-phase voltage is used as polarized voltage, the operating characteristics is also the 3
similar.

The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode. They are used to judge the fault in forward direction. If the system phase
sequence is "ACB", the angle difference under positive-sequence voltage polarization mode and
phase-to-phase voltage polarization mode is different, comparing with system phase sequence
"ABC".

1. Direction criterion (system phase sequence: ABC)

⚫ Polarization mode: positive-sequence voltage polarized

Faulty phase Operating current Polarized voltage Angle difference

Phase A Ia U1 Angle(U1)-Angle(Ia)-RCA
Phase B Ib U1 Angle(U1)-Angle(Ib)-RCA-120º
Phase C Ic U1 Angle(U1)-Angle(Ic)-RCA+120º

⚫ Polarization mode: phase-to-phase voltage polarized

Faulty phase Operating current Polarized voltage Angle difference

Phase A Ia Ubc Angle(Ubc)-Angle(Ia)-RCA+90º
Phase B Ib Uca Angle(Uca)-Angle(Ib)-RCA+90º
Phase C Ic Uab Angle(Uab)-Angle(Ic)-RCA+90º

⚫ Polarization mode: phase-to-ground voltage polarized

Faulty phase Operating current Polarized voltage Angle difference

Phase A Ia Ua Angle(Ua)-Angle(Ia)-RCA
Phase B Ib Ub Angle(Ub)-Angle(Ib)-RCA
Phase C Ic Uc Angle(Uc)-Angle(Ic)-RCA

⚫ Polarization mode: negative-sequence voltage polarized

Faulty phase Operating current Polarized voltage Angle difference

Phase A I2 U2 Angle(U2)-Angle(I2)-RCA+180º
Phase B I2 U2 Angle(U2)-Angle(I2)-RCA+180º
Phase C I2 U2 Angle(U2)-Angle(I2)-RCA+180º

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 3 Protection Functions

2. Direction criterion (system phase sequence: ACB)

⚫ Polarization mode: positive-sequence voltage polarized

Faulty phase Operating current Polarized voltage Angle difference

Phase A Ia U1 Angle(U1)-Angle(Ia)-RCA
Phase B Ib U1 Angle(U1)-Angle(Ib)-RCA+120º
Phase C Ic U1 Angle(U1)-Angle(Ic)-RCA-120º

⚫ Polarization mode: phase-to-phase voltage polarized

Faulty phase Operating current Polarized voltage Angle difference

3 Phase A Ia Ubc Angle(Ubc)-Angle(Ia)-RCA+270º

Phase B Ib Uca Angle(Uca)-Angle(Ib)-RCA+270º
Phase C Ic Uab Angle(Uab)-Angle(Ic)-RCA+270º

In order to improve the reliability of direction control element, negative-sequence direction criterion
is provided for direction control element and used to judge the fault in reversal direction, which is
enabled in fixed and used integrated with the polarization modes mentioned above. Negative-
sequence direction criterion is shown in the table below.

Negative-sequence direction criterion

Operating current Polarized voltage Angle difference
I2 U2 Angle(U2)-Angle(I2)-RCA+180º

Therefore, the criteria of three-phase direction control element are as follows:

Direction control element

Direction element Operating condition
Angle_A forward direction operates and Angle_I2 reverse direction does not
Phase A forward direction
operates.
Angle_A reverse direction operates and Angle_I2 forward direction does not
Phase A reverse direction
operates.
Angle_B forward direction operates and Angle_I2 reverse direction does not
Phase B forward direction
operates.
Angle_B forward direction operates and Angle_I2 forward direction does not
Phase B reverse direction
operates.
Angle_C forward direction operates and Angle_I2 reverse direction does not
Phase C forward direction
operates.
Angle_C forward direction operates and Angle_I2 forward direction does not
Phase C reverse direction
operates.

The calculation of direction control element needs to judge the voltage threshold and the current
threshold. The direction judgement can be executed only when the operating current is greater than
the setting [50/51P.DIR.I_Min]. For different polarization mode, the selected operating current is
different, the specific principles are shown as the table blow. The memorized characteristics of the
direction control element can eliminate the dead zone for close up three-phase short-circuit fault.

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Polarized voltage Operating current

Phase-to-phase voltage Phase current
Phase-to-ground voltage Phase current
Positive-sequence voltage Phase current
Negative-sequence voltage Negative-sequence current

When the polarized voltage is less than the minimum operating voltage setting [50/51P.DIR.U_Min],
positive-sequence voltage before two cycles is used to judge the direction. The polarized voltage
will not be used to judge the direction until it is greater than [50/51P.DIR.U_Min].

The logic of forward direction element and reverse direction element are shown in Figure 3.15-5.

EN [50/51P.En_VTS_Blk] &
3

>=1

SIG VTS.Alm

SIG Three-phase currents & >=1

Forward direction

SIG Three-phase voltages

&
criterion

50/51P.FwdDir.Op
SIG Memorized U1

SET [50/51P.Opt_PolarizedVolt]

SIG Prot.BI_En_VT &

EN [Prot.En_VT]

SET Iop>[50/51P.DIR.I_Min]

EN [50/51P.En_VTS_Blk] &

>=1

SIG VTS.Alm

SIG Three-phase currents & >=1

Reverse direction

SIG Three-phase voltages

&
criterion

50/51P.RevDir.Op
SIG Memorized U1

SET [50/51P.Opt_PolarizedVolt]

SIG Prot.BI_En_VT &

EN [Prot.En_VT]

SET Iop>[50/51P.DIR.I_Min]

Figure 3.15-5 Logic of forward and reverse direction element

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 3 Protection Functions

Iop: the operating current

Memorized U1 is positive-sequence memorized voltage, it is 2-cycles positive-sequence voltage

before the polarized voltage is less than the minimum operating voltage setting [50/51P.DIR.U_Min]
and is derived from the three-phase voltage.

3.15.1.3 Harmonic Control Element

When the transformer is energized with no-load, the inrush current may be generated, which may
cause the maloperation of phase overcurrent protection. Because secondary harmonic component
is high in the inrush current but the secondary harmonic component is low in the fault current,
harmonic control element based on the secondary harmonic component is added to prevent phase
3 overcurrent protection from maloperation due to inrush current. For harmonic control element, the
harmonic blocking mode can be selected through the setting [50/51P.HMB.Opt_Blk], it can support
phase blocking, cross blocking, and maximum phase blocking. The corresponding relationship is
shown in the following table.

Harmonic blocking criterion

Harmonic blocking mode
Phase A Phase B Phase C
Ia2/Ia1> Ib2/Ib1> Ic2/Ic1>
PhaseBlk (phase blocking)
[50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2]
CrossBlk (cross blocking) (Ia2/Ia1) or (Ib2/Ib1) or (Ic2/Ic1)>[50/51P.HMB.K_Hm2]
MaxPhaseBlk (maximum phase Max(Ia2, Ib2, Ic2)/Ia1> Max(Ia2, Ib2, Ic2)/Ib1> Max(Ia2, Ib2, Ic2)/Ic1>
blocking) [50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2]

When the fundamental current is greater than the setting [50/51P.HMB.I_Rls], the corresponding
phase will be unblocked by harmonic control element. The logic of harmonic control element is
shown in Figure 3.15-6.

SET Imax>[50/51P.HMB.I_Rls]

SIG Ia1, Ib1, Ic1

&
50/51P.HMB.Op
Harmonic
criterion

SIG Ia2, Ib2, Ic2

SET [50/51P.HMB.Opt_Blk]

Figure 3.15-6 Logic of harmonic control element

Ia1, Ib1, Ic1 are the fundamental current.

Ia2, Ib2, Ic2 are the secondary harmonic current.

Imax is the maximum phase current.

3.15.1.4 Operating Characteristics

Phase overcurrent protection can operate instantaneously or with a fixed time delay. It can also
operate with inverse-time characteristics, and its characteristics curve complies with the standards
IEC 60255-3 and ANSI C37.112. Phase overcurrent protection can support definite-time
characteristics, IEC & ANSI standard inverse-time characteristics and user-defined inverse-time
characteristics, which are determined by the setting [50/51Pi.Opt_Curve] (i=1~6). The relationship

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between the setting and the characteristics curve is shown in the table below.

50/51Pi.Opt_Curve Time Characteristics k α c tr

ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite time - - - -
ANSILTE ANSI Long time extremely inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long time very inverse 28.55 2.0 0.712 13.46
ANSILT
IECN
ANSI Long time inverse
IEC Normal inverse
0.086
0.14
0.02
0.02
0.185
0
4.6
-
3
IECV IEC Very inverse 13.5 1.0 0 -
IECI IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short time inverse 0.05 0.04 0 -
IECLT IEC Long time inverse 120.0 1.0 0 -
IECDefTime IEC Definite time - - - -
UserDefine Programmable

When the setting [50/51Pi.Opt_Curve] is set as "UserDefine", it means that user-defined inverse-
time characteristics is selected. These settings [50/51Pi.K], [50/51Pi.C] and [50/51Pi.Alpha] are
valid, and the inverse-time operating curve is determined by the three settings.

⚫ Instantaneous characteristics

When I>[50/51Pi.I_Set], phase overcurrent protection operates instantaneously.

⚫ Definite-time characteristics

[50/51Pi.t_Op]

I
[50/51Pi.I_Set]

Figure 3.15-7 Definite-time operating curve of phase overcurrent protection

When I>[50/51Pi.I_Set], phase overcurrent protection operates with a time delay [50/51Pi.t_Op],
and the operating characteristics curve is as shown in Figure 3.15-7.

⚫ Inverse-time characteristics

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When I>[50/51Pi.I_Set], phase overcurrent protection begins to accumulate, and the operating time
is affected by the applied current I. The operating time will decrease with the current increasing,
but the operating time shall not less than the setting [50/51Pi.tmin] (i=1~6). The inverse-time
operating characteristics equation is:

[50/51𝑃𝑖. 𝐾]
𝑡= [50/51Pi.Alpha]
+ [50/51Pi. C] × [50/51Pi. TMS]
𝐼
( ) −1
{ [50/51Pi. I_Set] }

I is the measured current.

3 The inverse-time operating characteristics curve is shown Figure 3.15-8.

[50/51Pi.tmin]

I
[50/51Pi.I_Set] ID

Figure 3.15-8 Inverse-time operating curve of phase overcurrent protection

When the applied current is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overcurrent protection is shown in the following equation.

𝑇0
1
∫ 𝑑𝑡 = 1
𝑡(𝐼)
0

T0 is the operating time of the protection element.

t(I) is the theoretical operating time when the current is I.

3.15.1.5 Dropout Characteristics

The supported dropout characteristics of phase overcurrent protection include instantaneous,

definite-time and ANSI inverse-time characteristics. When the operating characteristics curve is
selected as definite-time, IEC inverse-time or user-defined inverse-time characteristics, the dropout
characteristic curve can only be selected as instantaneous or definite-time characteristics, and the
alarm signal "Fail_Settings" will be issued and the device will be blocked if ANSI inverse-time
characteristics is selected. When the operating characteristics curve is selected as ANSI inverse-
time characteristics, the dropout characteristic curve can be selected as instantaneous, definite-

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time and ANSI inverse-time characteristics.

⚫ Instantaneous characteristics

When I<0.95×[50/51Pi.I_Set], phase overcurrent protection drops out instantaneously.

⚫ Definite-time characteristics

When I<0.95×[50/51Pi.I_Set], phase overcurrent protection drops out with a time delay
[50/51Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among start
signal, operating signal and the counter is as shown in Figure 3.15-9.

Start time

3
I>[50/51Pi.I_Set]

50/51Pi.St

50/51Pi.Op

[50/51Pi.t_Op] Phase overcurrent

protection operating

Operating counter

[50/51Pi.t_DropOut]
[50/51Pi.t_DropOut] [50/51Pi.t_DropOut]
Dropout time
Dropout time

Figure 3.15-9 Definite-time dropout characteristics of phase overcurrent protection

⚫ Inverse-time characteristics

When I>[50/51Pi.I_Set], phase overcurrent protection begins to accumulate, the accumulated

value after tP (Assuming tP is less than the theoretical operating time) is calculated according to the
following equation.

𝑡𝑃
1
𝐼𝑡𝑝 = ∫ 𝑑𝑡
𝑡(𝐼)
0

If I<0.95×[50/51Pi.I_Set], phase overcurrent protection begins to drop out, and the dropout
characteristics meets the following equations.

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 3 Protection Functions

𝑡𝑅
1
𝐼𝑡𝑝 = ∫ 𝑑𝑡
𝑡𝑅 (𝐼)
0

𝑡𝑟
𝑡𝑅 (𝐼) = 2 × [50/51Pi. TMS]
𝐼
1−( )
{ [50/51Pi. I_Set] }

tR is the dropout time.

tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
3 phase overcurrent protection operates.

I is the measured current.

tr

I
[50/51Pi.I_Set]

Figure 3.15-10 Inverse-time dropout curve of phase overcurrent protection

If 0.95×[50/51Pi.I_Set]<I<[50/51Pi.I_Set], the counter will neither accumulate nor drop out. The
inverse-time dropout characteristics curve is shown in Figure 3.15-10.

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Start time

I>[50/51Pi.I_Set]

50/51Pi.St

50/51Pi.Op

[50/51Pi.t_Op]
Phase overcurrent protection operating 3

Operating counter

Dropout time Coefficient (tr)

Dropout time
Dropout time

Figure 3.15-11 Inverse-time dropout characteristics of phase overcurrent protection

The sequence diagram of inverse-time dropout characteristics among start signal, operating signal
and the counter is shown in Figure 3.15-11.

3.15.2 Function Block Diagram

50/51P

50/51Pi.Enable 50/51Pi.On

50/51Pi.Block 50/51Pi.Blocked

50/51Pi.Valid

50/51Pi.St

50/51Pi.StA

50/51Pi.StB

50/51Pi.StC

50/51Pi.Op

50/51Pi.Op.PhA

50/51Pi.Op.PhB

50/51Pi.Op.PhC

50/51Pi.Alm

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3.15.3 I/O Signal

Table 3.15-1 Input signals of phase overcurrent protection

No. Input signal Description

1 50/51Pi.Enable Input signal of enabling stage i of phase overcurrent protection (i=1~6)
2 50/51Pi.Block Input signal of blocking stage i of phase overcurrent protection (i=1~6)

Table 3.15-2 Output signals of phase overcurrent protection

No. Output signal Description

1 50/51Pi.On Stage i of phase overcurrent protection is enabled. (i=1~6)
3 2 50/51Pi.Blocked Stage i of phase overcurrent protection is blocked. (i=1~6)
3 50/51Pi.Valid Stage i of phase overcurrent protection is valid. (i=1~6)
4 50/51Pi.St Stage i of phase overcurrent protection starts. (i=1~6)
5 50/51Pi.StA Stage i of phase overcurrent protection starts. (Phase A, i=1~6)
6 50/51Pi.StB Stage i of phase overcurrent protection starts. (Phase B, i=1~6)
7 50/51Pi.StC Stage i of phase overcurrent protection starts. (Phase C, i=1~6)
8 50/51Pi.Op Stage i of phase overcurrent protection operates. (i=1~6)
9 50/51Pi.Op.PhA Stage i of phase overcurrent protection operates. (Phase A, i=1~6)
10 50/51Pi.Op.PhB Stage i of phase overcurrent protection operates. (Phase B, i=1~6)
11 50/51Pi.Op.PhC Stage i of phase overcurrent protection operates. (Phase C, i=1~6)
12 50/51Pi.Alm Stage i of phase overcurrent protection alarms. (i=1~6)

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3.15.4 Logic

SET Ia>[50/51Pi.I_Set]

SIG 50/51P.VCE.Op >=1 &

EN [50/51Pi.En_Volt_Blk]

SIG 50/51P.FwdDir.Op.PhA

selection
Direction
SIG 50/51P.RevDir.Op.PhA

SIG [50/51Pi.Opt_Dir] 50/51Pi.StA

&
SIG 50/51P.HMB.Op.PhA & & Timer
t
3
&
t
EN [50/51Pi.En_Hm_Blk] 50/51Pi.Op.PhA

SIG 50/51Pi.Pkp

SET [50/51Pi.Opt_Trp/Alm]=Trp
&
50/51Pi.Alm.PhA
SET [50/51Pi.Opt_Trp/Alm]=Alm

SIG 50/51Pi.StA
>=1
SIG 50/51Pi.StB 50/51Pi.St

SIG 50/51Pi.StC

SIG 50/51Pi.Op.PhA
>=1
SIG 50/51Pi.Op.PhB 50/51Pi.Op

SIG 50/51Pi.Op.PhC

SIG 50/51Pi.Alm.PhA
>=1
SIG 50/51Pi.Alm.PhB 50/51Pi.Alm

SIG 50/51Pi.Alm.PhC

Figure 3.15-12 Logic of phase overcurrent protection

3.15.5 Settings
Table 3.15-3 Settings of phase overcurrent protection

Name Range Step Unit Default Description

Low voltage setting
50/51P.VCE.Upp 10.000~100.000 0.001 V 70.000 of voltage control
element
Negative-sequence
voltage setting of
50/51P.VCE.U2 2.000~57.000 0.001 V 8.000
voltage control
element
Zero-sequence
50/51P.VCE.3U0 2.000~57.000 0.001 V 8.000
voltage setting of

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Name Range Step Unit Default Description

voltage control
element
The characteristic
50/51P.DIR.RCA -180~179 1 ° 45 angle of direction
control element
The negative-
sequence
50/51P.DIR.RCA_NegOC -180~179 1 ° 45 characteristic angle
of direction control

3 element
The minimum
boundary in forward
50/51P.DIR.phi_Min_Fwd 10~90 1 ° 90 direction of phase
overcurrent
protection
The maximum
boundary in forward
50/51P.DIR.phi_Max_Fwd 10~90 1 ° 90 direction of phase
overcurrent
protection
The minimum
boundary in reverse
50/51P.DIR.phi_Min_Rev 10~90 1 ° 90 direction of phase
overcurrent
protection
The maximum
boundary in reverse
50/51P.DIR.phi_Max_Rev 10~90 1 ° 90 direction of phase
overcurrent
protection
The voltage
polarization mode of
direction control
element
U2: negative-
U2
sequence voltage is
Upp
50/51P.DIR.Opt_PolarizedVolt Upp used as polarized
Up
voltage
U1
Upp: phase-to-phase
voltage is used as
polarized voltage
Up: phase-to-ground
voltage is used as

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Name Range Step Unit Default Description

polarized voltage
U1: positive-
sequence voltage is
used as polarized
The minimum
operating current
50/51P.DIR.I_Min (0.050~1.000)×In 0.001 A 0.050
setting of direction
control element
The minimum

50/51P.DIR.U_Min 1.000~10.000 0.001 V 4.000

operating voltage 3
setting of direction
control element
Enabling/disabling
phase overcurrent
protection is blocked
Disabled by VT circuit failure
50/51P.En_VTS_Blk Disabled
Enabled when VT circuit
supervision is
enabled and VT
circuit fails
The coefficient of
second harmonics of
50/51P.HMB.K_Hm2 0.100~1.000 0.001 0.200
harmonic control
element
The current setting of
50/51P.HMB.I_Rls (2.000~30.000)×In 0.001 A 20.000 releasing harmonic
control element
The option of
harmonic blocking
mode
PhaseBlk: phase
PhaseBlk
blocking
50/51P.HMB.Opt_Blk CrossBlk PhaseBlk
CrossBlk: cross
MaxPhaseBlk
blocking
MaxPhaseBlk:
maximum phase
blocking
The current setting
for stage i of phase
50/51Pi.I_Set (0.050~40.000)×In 0.001 A 15.000
overcurrent
protection (i=1~6)
The operating time
50/51Pi.t_Op 0.000~100.000 0.001 s 0.100
delay for stage i of

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Name Range Step Unit Default Description

phase overcurrent
protection (i=1~6)
The dropout time
delay for stage i of
50/51Pi.t_DropOut 0.000~100.000 0.001 s 0.000
phase overcurrent
protection (i=1~6)
Enabling/disabling
stage i of phase
Disabled overcurrent
50/51Pi.En_Volt_Blk Disabled
3 Enabled protection controlled
by voltage control
element (i=1~6)
The option direction
Non_Directional characteristic for
50/51Pi.Opt_Dir Forward Non_Directional stage i of phase
Reverse overcurrent
protection (i=1~6)
Enabling/disabling
stage i of phase
Disabled overcurrent
50/51Pi.En_Hm_Blk Disabled
Enabled protection controlled
by harmonic control
element (i=1~6)
Enabling/disabling
Disabled stage i of phase
50/51Pi.En Enabled
Enabled overcurrent
protection (i=1~6)
Enabling/disabling
stage i of phase
overcurrent
protection operate to
Trp
50/51Pi.Opt_Trp/Alm Trp trip or alarm (i=1~6)
Alm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
The option of
ANSIV
operating
ANSIN
characteristics curve
50/51Pi.Opt_Curve ANSIM IECDefTime
for stage i of phase
ANSIDefTime
overcurrent
ANSILTE
protection (i=1~6)
ANSILTV

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Name Range Step Unit Default Description

ANSILT
IECN
IECV
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of dropout
3
characteristics curve
for stage i of phase
overcurrent
protection (i=1~6)
Inst: instantaneous
Inst
dropout
50/51Pi.Opt_Curve_DropOut DefTime Inst
characteristics
IDMT
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage i of
50/51Pi.TMS 0.040~20.000 0.001 1.000 inverse-time phase
overcurrent
protection (i=1~6)
The minimum
operating time for
stage i of inverse-
50/51Pi.tmin 0.000~10.000 0.001 s 0.020
time phase
overcurrent
protection (i=1~6)
The constant “K” for
stage i of customized
50/51Pi.K 0.0010~120.0000 0.0001 0.1400 inverse-time phase
overcurrent
protection (i=1~6)
The constant “α” for
stage i of customized
50/51Pi.Alpha 0.0100~3.0000 0.0001 0.0200
inverse-time phase
overcurrent

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Name Range Step Unit Default Description

protection (i=1~6)
The constant “C” for
stage i of customized
50/51Pi.C 0.0000~1.2000 0.0001 0.0000 inverse-time phase
overcurrent
protection (i=1~6)

3.16 Phase Current SOTF Protection (50PSOTF)

3 When the circuit breaker is closed manually or automatically, it is possible to switch on to a

permanent fault. When the circuit breaker is switched onto an existing earth fault in the remote end
of transmission line, phase overcurrent protection only operates to isolate the fault with a time delay,
which will affect the power system seriously. In this situation, however, the fastest possible
clearance is required. Phase current SOTF protection is a complementary function. Phase current
SOTF protection shall be enabled for a certain time which is determined by the setting [SOTF.t_En]
via either manual closing or auto-reclosing.

3.16.1 Function Description

Phase current SOTF protection will operate to trip three-phase circuit breaker with a time delay of
[50PSOTF.t_Op] when manual closing or auto-reclosing. For in-line transformer application, large
inrush current generated during manual closing and auto-reclosing will lead to an undesired
operation of phase current SOTF protection. Second harmonic blocking can be selected by the
setting [50PSOTF.En_Hm2_Blk] to prevent maloperation due to inrush current.

When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.HMB.K_Hm2], second harmonic blocking element
operates to block phase current SOTF protection if the setting [50PSOTF.En_Hm2_Blk] is set as
"Enabled". Its operation criterion:

IP_2nd=[50/51P.HMB.K_Hm2]×IP Equation 3.16-1

Where:

IP_2nd is second harmonic of phase current

IP is fundamental component of phase current.

If fundamental component of any phase current is lower than the minimum operating current (0.1In),
then second harmonic calculation is not carried out and harmonic blocking element does not
operate. In order to improve the reliability, phase current SOTF protection can select phase voltage
element, phase-to-phase voltage element, zero-sequence voltage element and negative-sequence
voltage element as auxiliary criterion.

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3.16.2 Function Block Diagram

50PSOTF

50PSOTF.Enable 50PSOTF.On

50PSOTF.Block 50PSOTF.Blocked

50PSOTF.Valid

50PSOTF.Op

50PSOTF.St

50PSOTF.StA 3
50PSOTF.StB

50PSOTF.StC

3.16.3 I/O Signals

Table 3.16-1 Input signals of phase current SOTF protection

No. Input Signal Description

1 50PSOTF.Enable Input signal of enabling phase current SOTF protection
2 50PSOTF.Block Input signal of blocking phase current SOTF protection

Table 3.16-2 Output signals of phase current SOTF protection

No. Output Signal Description

1 50PSOTF.On Phase current SOTF protection is enabled.
2 50PSOTF.Blocked Phase current SOTF protection is blocked.
3 50PSOTF.Valid Phase current SOTF protection is valid.
4 50PSOTF.Op Phase current SOTF protection operates.
5 50PSOTF.St Phase current SOTF protection starts.
6 50PSOTF.StA Phase current SOTF protection starts. (Phase A)
7 50PSOTF.StB Phase current SOTF protection starts. (Phase B)
8 50PSOTF.StC Phase current SOTF protection starts. (Phase C)

3.16.4 Logic
SIG 50PSOTF.Enable &
50PSOTF.On
EN [50PSOTF.En]
&
SIG 50PSOTF.Block >=1 50PSOTF.Blocked

SIG Fail_Device
&
50PSOTF.Valid

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SIG 3-pole AR signal

>=1
SIG 1-pole AR signal

SIG Manual closing signal

SET Ia>[50PSOTF.I_Set]
>=1
SET Ib>[50PSOTF.I_Set]

SET Ic>[50PSOTF.I_Set]

SIG I3P 2nd Hm Detect & &

EN [50PSOTF.En_Hm2_Blk]

SET Ua<[50PSOTF.Up_Set]
>=1

3
SET Ub<[50PSOTF.Up_Set] &
SET Uc<[50PSOTF.Up_Set]

EN [50PSOTF.En_Up_UV]

SET Uab<[50PSOTF.Upp_Set]
>=1 >=1
SET Ubc<[50PSOTF.Upp_Set] &
SET Uca<[50PSOTF.Upp_Set]

EN [50PSOTF.En_Upp_UV]

SET U2>[50PSOTF.U2_Set] & >=1

>=1
EN [50PSOTF.En_U2_OV]

SET 3U0>[50PSOTF.3U0_Set] &

EN [50PSOTF.En_3U0_OV]

EN [50PSOTF.En_Up_UV] >=1

EN [50PSOTF.En_Upp_UV]
>=1
EN [50PSOTF.En_U2_OV]
50PSOTF.St
EN [50PSOTF.En_3U0_OV]
&
[50PSOTF.t_Op] 0 50PSOTF.Op
SIG 50PSOTF.Valid

Figure 3.16-1 Logic of phase current SOTF protection

3.16.5 Settings
Table 3.16-3 Settings of phase current SOTF protection

Name Range Step Unit Default Description

Current setting of phase current
50PSOTF.I_Set (0.050~40.000)×In 0.001 A 1.000
SOTF protection
Time delay for phase current SOTF
50PSOTF.t_Op 0.000~100.000 0.001 s 0.100
protection
Voltage setting for phase
50PSOTF.Up_Set 0.000~200.000 0.001 V 1.000
undervoltage supervision logic
Voltage setting for phase-phase
50PSOTF.Upp_Set 0.000~200.000 0.001 V 1.000
undervoltage supervision logic
Voltage setting for negative-
50PSOTF.U2_Set 0.000~200.000 0.001 V 1.000 sequence overvoltage supervision
logic

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Name Range Step Unit Default Description

Voltage setting for zero-sequence
50PSOTF.3U0_Set 0.000~200.000 0.001 V 1.000
overvoltage supervision logic
Enabling/disabling phase
Disabled
50PSOTF.En_Up_UV Enabled undervoltage supervision logic for
Enabled
phase current SOTF protection
Enabling/disabling phase-phase
Disabled
50PSOTF.En_Upp_UV Enabled undervoltage supervision logic for
Enabled
phase current SOTF protection
Enabling/disabling negative-

50PSOTF.En_U2_OV
Disabled
Enabled
sequence overvoltage supervision 3
Enabled logic for phase current SOTF
protection
Enabling/disabling zero-sequence
Disabled
50PSOTF.En_3U0_OV Enabled overvoltage supervision logic for
Enabled
phase current SOTF protection
Disabled Enabling/disabling phase current
50PSOTF.En Enabled
Enabled SOTF protection
Enabling/disabling second harmonic
Disabled
50PSOTF.En_Hm2_Blk Enabled blocking for phase overcurrent SOTF
Enabled
protection

3.17 Earth Fault Protection (50/51G)

Under normal conditions, three phases of the power system is symmetrical, its zero-sequence
current and voltage are zero theoretically. Most of the faults are asymmetrical, so various
protections reflect sequence component principle can be fulfilled based on the fault's asymmetrical
characteristics. Earth fault protection has been widely used in power systems, it can be applied for
the fault as long as there is zero-sequence current, including single-phase earth fault and phase-
to-phase short-circuit earth fault etc..

3.17.1 Function Description

The device can provide six stages of earth fault protection with independent logic. Each stage can
be independently set as definite-time characteristics or inverse-time characteristics. It can be
chosen whether it is blocked by harmonic control element. The direction control element can be set
as no direction, forward direction and reverse direction. The zero-sequence current used by earth
fault protection always adopts calculated zero-sequence current.

Earth fault protection can operate to trip or alarm. For some specific applications, earth fault
protection needs to be blocked by the external signal, so the device provides an input signal to be
used to block earth fault protection.

When CT circuit is abnormal or the position of three-phases circuit breaker are discrepant, earth
fault protection should be blocked. By default, they have been fulfilled by the connection to the

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"function blocked input" signal of earth fault protection (50/51Gi.Block). in the configuration page
"UserPage_Common" by PCS-Studio. (refer to "Section 4 Protection Function Configuration in
Application Manual")

SIG 52b_PhA
>=1
SIG 52b_PhB &
SIG 52b_PhC

&

>=1
3 SIG CB1.CTS.Alm
output to
50/51Gi.Block

SIG CB2.CTS.Alm

Figure 3.17-1 Blocking scheme configuration

EN [50/51Gi.En] &
50/51Gi.On
SIG 50/51Gi.Enable
&
SIG 50/51Gi.Block >=1 50/51Gi.Blocked

SIG Fail_Device
&
50/51Gi.Valid

Figure 3.17-2 Logic of enabling earth fault protection

The pickup logic of earth fault protection is shown in Figure 3.17-3.

SET 3I0>0.95×[50/51Gi.3I0_Set] & 50/51Gi.Pkp

0 500ms &
SIG 50/51Gi.On &
FD.Pkp
SIG 50/51Gi.Valid

SET [50/51Gi.Opt_Trp/Alm]=Alm

Figure 3.17-3 Pickup logic of earth fault protection

3.17.1.1 Direction Control Element

In order to ensure the selectivity of earth fault protection, direction control element can be available.
The setting [50/51Gi.Opt_Dir] (i=1~6) is used to select the direction characteristics for each stage
of earth fault protection: no direction, forward direction and reverse direction are selectable.

The polarized voltage is selectable by the setting [50/51G.DIR.Opt_PolarizedVolt]. If the setting

[50/51G.DIR.Opt_PolarizedVolt] is set as "3U0", its operating characteristics is shown in Figure
3.17-4. When negative-sequence voltage is used as polarized voltage, the operating characteristics
is also the similar.

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-U0

[50/51G.DIR.phi_Min_Fwd]

Non-operating I0
area

Operating area in
[50/51G.DIR.phi_Max_Rev] forward direction

[50/51G.DIR.RCA]

Operating area in
reverse direction 3

[50/51G.DIR.phi_Max_Fwd]
Non-operating
area
[50/51G.DIR.phi_Min_Rev]

Figure 3.17-4 Operating characteristics of direction control element

The operation boundary of the forward direction element can be set by [50/51G.DIR.phi_Min_Fwd]
and [50/51G.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51G.DIR.phi_Min_Rev] and [50/51G.DIR.phi_Max_Rev]. The following table shows the
relationship among the operating current, the polarized voltage and the polarization mode.

⚫ Polarization mode: zero-sequence voltage polarized

Operating current Polarized voltage Angle difference

Calculated residual current: 3I0_Cal -3U0 Angle(-3U0)-Angle(3I0_Cal)-RCA

⚫ Polarization mode: negative-sequence voltage polarized

Operating current Polarized voltage Angle difference

I2 U2 Angle(U2)-Angle(I2)-RCA+180º

The logic of forward direction element and reverse direction element are shown in Figure 3.17-5.

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EN [50/51G.En_VTS_Blk] &

>=1

SIG VTS.Alm

SIG 3I0_Cal (internally calculate)

& >=1

direction
Forward
criterion
SIG 3U0_Cal (internally calculate)

3 EN [Prot.En_VT] &

SIG Prot.BI_En_VT
&
SET Iop>[50/51G.DIR.3I0_Min] 50/51G.FwdDir.Op

SET Upo>[50/51G.DIR.3U0_Min]

EN [50/51G.En_VTS_Blk] &

>=1

SIG VTS.Alm

SIG 3I0_Cal (internally calculate)

& >=1
direction
Reverse
criterion

SIG 3U0_Cal (internally calculate)

EN [Prot.En_VT] &

SIG Prot.BI_En_VT
&
SET Iop>[50/51G.DIR.3I0_Min] 50/51G.RevDir.Op

SET Upo>[50/51G.DIR.3U0_Min]

Figure 3.17-5 Logic of forward and reverse direction element

Iop: the operating current

Upo: the polarized voltage

The direction element calculation needs to judge the current threshold and voltage threshold. The
direction judgement can not be executed unless the operating current is greater than the setting
[50/51G.DIR.3I0_Min], and the polarized voltage is greater than the setting [50/51G.DIR.3U0_Min].

3.17.1.2 Harmonic Control Element

Harmonic control element based on zero-sequence current can be used to prevent earth fault
protection from maloperation due to inrush current. Calculated zero-sequence current is adopted.
When the percentage of the second harmonic component to fundamental component in residual
current is greater than the setting [50/51G.HMB.K_Hm2], harmonic control element operates to

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block earth fault protection if the corresponding setting [50/51Gi.En_Hm_Blk] is set as "Enabled"
(i=1~6). When the fundamental component of zero-sequence current is greater than the setting
[50/51G.HMB.I_Rls], earth fault protection will be unblocked by harmonic control element. The logic
of harmonic control element is shown in Figure 3.17-6. 3I0_2nd is secondary harmonic component
of residual current.

SET 3I0>[50/51G.HMB.I_Rls]

SIG 3I0_Cal (internally calculate)

&
50/51G.HMB.Op

Harmonic
criterion
SET 3I0_2nd/3I0>[50/51G.HMB.K_Hm2]
3
Figure 3.17-6 Logic of harmonic control element

3.17.1.3 Operating Characteristics

Earth fault protection can operate instantaneously or with a fixed time delay. It can also operate
with inverse-time characteristics, and its characteristics curve complies with the standards IEC
60255-3 and ANSI C37.112. Earth fault protection can support definite-time characteristics, IEC &
ANSI standard inverse-time characteristics and user-defined inverse-time characteristics, which
are determined by the setting [50/51Gi.Opt_Curve] (i=1~6). The relationship between the setting
and the characteristics curve is shown in the table below.

50/51Gi.Opt_Curve Time Characteristic k α c tr

ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite time - - - -
ANSILTE ANSI Long time extremely inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long time very inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long time inverse 0.086 0.02 0.185 4.6
IECN IEC Normal inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -
IECI IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short time inverse 0.05 0.04 0 -
IECLT IEC Long time inverse 120.0 1.0 0 -
IECDefTime IEC Definite time - - - -
UserDefine Programmable

When the setting [50/51Gi.Opt_Curve] is set as "UserDefine", it means that user-defined inverse-
time characteristics is selected. These settings [50/51Gi.K], [50/51Gi.C] and [50/51Gi.Alpha] are
valid, and the inverse-time operating curve is determined by the three settings.

⚫ Instantaneous characteristics

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When 3I0>[50/51Gi.3I0_Set], earth fault protection operates immediately.

⚫ Definite-time characteristics

3 [50/51Gi.t_Op]

I0
[50/51Gi.3I0_Set]

Figure 3.17-7 Definite-time operating curve of earth fault protection

When 3I0>[50/51Gi.3I0_Set], earth fault protection operates with a time delay [50/51Gi.t_Op], and
the operating characteristics curve is as shown in Figure 3.17-7.

⚫ Inverse-time characteristics

The inverse-time operating characteristics curve is shown Figure 3.17-8.

[50/51Gi.tmin]

I0
[50/51Gi.3I0_Set] ID

Figure 3.17-8 Inverse-time operating curve of earth fault protection

When 3I0>[50/51Gi.3I0_Set], earth fault protection begins to accumulate, and the operating time
is affected by the applied current 3I0. The operating time will decrease with the current increasing,
but the operating time shall not less than the setting [50/51Gi.tmin] (i=1~6). The inverse-time
operating characteristics equation is:

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[50/51Gi. K]
𝑡= [50/51Gi.Alpha]
+ [50/51Gi. C] × [50/51Gi. TMS]
3𝐼0
( ) −1
{ [50/51Gi. 3I0_Set] }

3I0 is the measured residual current.

When the applied residual current is not a fixed value, but changes with the time, the operating
behavior of inverse-time earth fault protection is shown in the following equation.

𝑇0
1
∫ 𝑑𝑡 = 1
0
𝑡(3𝐼0 ) 3
T0 is the operating time of the protection element.

t(3I0) is the theoretical operating time when the current is 3I0.

3.17.1.4 Dropout Characteristics

The supported dropout characteristics of earth fault protection include instantaneous, definite-time
and ANSI inverse-time characteristics. When the operating characteristics curve is selected as
definite-time, IEC inverse-time or user-defined inverse-time characteristics, the dropout
characteristic curve can only be selected as instantaneous or definite-time characteristics, and the
alarm signal "Fail_Settings" will be issued and the device will be blocked if ANSI inverse-time
characteristics is selected. When the operating characteristics curve is selected as ANSI inverse-
time characteristics, the dropout characteristic curve can be selected as instantaneous, definite-
time and ANSI inverse-time characteristics.

⚫ Instantaneous characteristics

When 3I0<0.95×[50/51Gi.3I0_Set], earth fault protection drops out immediately.

⚫ Definite-time characteristics

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Start time

3I0>[50/51Gi.3I0_Set]

50/51Gi.St

3 50/51Gi.Op

[50/51Gi.t_Op] Earth fault protection

operating

Operating counter

[50/51Gi.t_DropOut]
[50/51Gi.t_DropOut] [50/51Gi.t_DropOut]
Dropout time
Dropout time

Figure 3.17-9 Definite-time dropout characteristics of earth fault protection

When 3I0<0.95×[50/51Gi.3I0_Set], earth fault protection drops out with a time delay
[50/51Gi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among start
signal, operating signal and the counter is as shown in Figure 3.17-9.

⚫ Inverse-time characteristics

The inverse-time dropout characteristics curve is shown in Figure 3.17-10.

tr

I0
[50/51Gi.3I0_Set]

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Figure 3.17-10 Inverse-time dropout curve of earth fault protection

When 3I0<0.95×[50/51Gi.3I0_Set], earth fault protection begins to accumulate, the accumulated

value after tP (Assuming tP is less than the theoretical operating time) is calculated according to the
following equation.

𝑡𝑃
1
𝐼𝑡𝑝 = ∫ 𝑑𝑡
𝑡(3𝐼0 )
0

If 3I0<0.95×[50/51Gi.3I0_Set], earth fault protection begins to drop out, and the dropout
characteristics meets the following equations.

𝑡𝑅
3
1
𝐼𝑡𝑝 = ∫ 𝑑𝑡
𝑡𝑅 (3𝐼0 )
0

𝑡𝑟
𝑡𝑅 (3𝐼0) = 2 × [50/51Gi. TMS]
3𝐼0
1−( )
{ [50/51Gi. 3I0_Set] }

tR is the dropout time.

tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
earth fault protection operates.

3I0 is the measured residual current.

If 0.95×[50/51Gi.3I0_Set]<3I0<[50/51Gi.3I0_Set], the counter will neither accumulate nor drop out.

The sequence diagram of inverse-time dropout characteristics among start signal, operating signal
and the counter is shown in Figure 3.17-11.

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Start time

3I0>[50/51Gi.3I0_Set]

50/51Gi.St

50/51Gi.Op

3 [50/51Gi.t_Op]
Earth fault protection operating

Operating counter

Dropout time Coefficient (tr)

Dropout time
Dropout time

Figure 3.17-11 Inverse-time dropout characteristics of earth fault protection

3.17.2 Function Block Diagram

50/51G

50/51Gi.Enable 50/51Gi.On

50/51Gi.Block 50/51Gi.Blocked

50/51Gi.Valid

50/51Gi.St

50/51Gi.Op

50/51Gi.Alm

3.17.3 I/O Signal

Table 3.17-1 Input signals of earth fault protection

No. Input signal Description

1 50/51Gi.Enable Input signal of enabling stage i of earth fault protection (i=1~6)
2 50/51Gi.Block Input signal of blocking stage i of earth fault protection (i=1~6)

Table 3.17-2 Output signals of earth fault protection

No. Output signal Description

1 50/51Gi.On Stage i of earth fault protection is enabled. (i=1~6)
2 50/51Gi.Blocked Stage i of earth fault protection is blocked. (i=1~6)

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No. Output signal Description

3 50/51Gi.Valid Stage i of earth fault protection is valid. (i=1~6)
4 50/51Gi.St Stage i of earth fault protection starts. (i=1~6)
5 50/51Gi.Op Stage i of earth fault protection operates. (i=1~6)
6 50/51Gi.Alm Stage i of earth fault protection alarms. (i=1~6)

3.17.4 Logic

SET 3I0>[50/51Gi.3I0_Set]

SIG 50/51G.FwdDir.Op 50/51Gi.St

selection &
Direction
SIG 50/51G.RevDir.Op & Timer
t
3
SET [50/51Gi.Opt_Dir] t

SIG 50/51G.HMB.Op &

EN [50/51Gi.En_Hm_Blk]

SIG 50/51Gi.Pkp
&
50/51Gi.Op
SET [50/51Gi.Opt_Trp/Alm]=Trp

&
50/51Gi.Alm
SET [50/51Gi.Opt_Trp/Alm]=Alm

Figure 3.17-12 Logic diagram of earth fault protection

3.17.5 Settings
Table 3.17-3 Settings of earth fault protection

Name Range Step Unit Default Description

The characteristic
50/51G.DIR.RCA -180~179 1 ° 45 angle of direction
control element
The minimum
boundary in forward
50/51G.DIR.phi_Min_Fwd 10~90 1 ° 90
direction of earth
fault protection
The maximum
boundary in forward
50/51G.DIR.phi_Max_Fwd 10~90 1 ° 90
direction of earth
fault protection
The minimum
boundary in reverse
50/51G.DIR.phi_Min_Rev 10~90 1 ° 90
direction of earth
fault protection
50/51G.DIR.phi_Max_Rev 10~90 1 ° 90 The maximum

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Name Range Step Unit Default Description

boundary in reverse
direction of earth
fault protection
The voltage
polarization mode of
direction control
element
3U0: zero-sequence
3U0
50/51G.DIR.Opt_PolarizedVolt 3U0 voltage is used as
U2
3 polarized
U2: negative-
sequence voltage is
used as polarized
voltage
The minimum
operating current
50/51G.DIR.3I0_Min (0.050~1.000)×In 0.001 A 0.050
setting of direction
control element
The minimum
operating voltage
50/51G.DIR.3U0_Min 1.000~10.000 0.001 V 4.000
setting of direction
control element
The compensation
setting of zero-
sequence
50/51G.DIR.Z0_Comp (0.000~4Unn)/In 0.001 Ω 0.000
impedance of
direction control
element
Enabling/disabling
earth fault protection
is blocked by VT
Disabled
50/51G.En_VTS_Blk Disabled circuit failure when
Enabled
VT circuit supervision
is enabled and VT
circuit fails
The coefficient of
second harmonics of
50/51G.HMB.K_Hm2 0.100~1.000 0.001 0.200
harmonic control
element
The current setting of
50/51G.HMB.I_Rls (2.000~30.000)×In 0.001 A 20.000 releasing harmonic
control element
50/51Gi.3I0_Set (0.050~40.000)×In 0.001 A 15.000 The zero-sequence

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Name Range Step Unit Default Description

current setting for
stage i of earth fault
protection (i=1~6)
The operating time
delay for stage i of
50/51Gi.t_Op 0.000~100.000 0.001 s 0.100
earth fault protection
(i=1~6)
The dropout time
delay for stage i of
50/51Gi.t_DropOut 0.000~100.000 0.001 s 0.000
earth fault protection 3
(i=1~6)
The option direction
Non_Directional
characteristic for
50/51Gi.Opt_Dir Forward Non_Directional
stage i of earth fault
Reverse
protection (i=1~6)
Enabling/disabling
stage i of earth fault
Disable
50/51Gi.En_Hm_Blk Disabled protection controlled
Enabled
by harmonic control
element (i=1~6)
Enabling/disabling
Disabled
50/51Gi.En Enabled stage i of earth fault
Enabled
protection (i=1~6)
Enabling/disabling
stage i of earth fault
protection operate to
Trp trip or alarm (i=1~6)
50/51Gi.Opt_Trp/Alm Trp
Alm Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM The option of
ANSIDefTime operating
ANSILTE characteristics curve
50/51Gi.Opt_Curve IECDefTime
ANSILTV for stage i of earth
ANSILT fault protection
IECN (i=1~6)
IECV
IECI
IECE

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Name Range Step Unit Default Description

IECST
IECLT
IECDefTime
UserDefine
The option of dropout
characteristics curve
for stage i of earth
fault protection
(i=1~6)

3 Inst
Inst: instantaneous
dropout
50/51Gi.Opt_Curve_DropOut DefTime Inst
characteristics
IDMT
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage i of
50/51Gi.TMS 0.040~20.000 0.001 1.000 inverse-time earth
fault protection
(i=1~6)
The minimum
operating time for
50/51Gi.tmin 0.000~10.000 0.001 s 0.020 stage i of inverse-
time earth fault
protection (i=1~6)
The constant “K” for
stage i of customized
50/51Gi.K 0.0010~120.0000 0.0001 0.1400 inverse-time earth
fault protection
(i=1~6)
The constant “α” for
stage i of customized
50/51Gi.Alpha 0.0100~3.0000 0.0001 0.0200 inverse-time earth
fault protection
(i=1~6)
The constant “C” for
stage i of customized
50/51Gi.C 0.0000~1.2000 0.0001 0.0000 inverse-time earth
fault protection
(i=1~6)

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3.18 Residual Current SOTF Protection (50GSOTF)

When the circuit breaker is closed manually or automatically, it is possible to switch on to a

permanent fault. When the circuit breaker is switched onto an existing earth fault in the remote end
of transmission line, earth fault protection only operates to isolate the fault with a time delay, which
will affect the power system seriously. In this situation, however, the fastest possible clearance is
required. Residual current SOTF protection is a complementary function. Residual current SOTF
protection shall be enabled for a certain time which is determined by the setting [SOTF.t_En] via
either manual closing or auto-reclosing.

3.18.1 Function Description 3

Residual current SOTF protection will operate to trip three-phase circuit breaker with a time delay
of [50GSOTF.t_Op_1P] via 1-pole auto-reclosing. Residual current SOTF protection will operate to
trip three-phase circuit breaker with a time delay of [50GSOTF.t_Op_3P] via manual closing or 3-
pole auto-reclosing.

For in-line transformer application, large inrush current generated during manual closing and auto-
reclosing will lead to an undesired operation of residual current SOTF protection. Second harmonic
blocking can be selected by the setting [50GSOTF.En_Hm2_Blk] to prevent maloperation due to
inrush current. When the percentage of second harmonic component to fundamental component
of residual current is greater than the setting [50/51G.HMB.K_Hm2], second harmonic blocking
element operates to block residual overcurrent SOTF element if the setting
[50GSOTF.En_Hm2_Blk] is set as "Enabled". Its operation criterion:

I0_2nd=[50/51G.HMB.K_Hm2]×I0 Equation 3.18-1

Where:

I0_2nd is second harmonic of residual current

I0 is fundamental component of residual current.

If fundamental component of residual current is lower than the minimum operating current (0.1In)
then second harmonic calculation is not carried out and harmonic blocking element does not
operate.

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3.18.2 Function Block Diagram

50GSOTF

50GSOTF.Enable 50GSOTF.On

50GSOTF.Block 50GSOTF.Blocked

50GSOTF.Valid

50GSOTF.Op

50GSOTF.St

3
3.18.3 I/O Signals
Table 3.18-1 Input signals of residual current SOTF protection

No. Input Signal Description

1 50GSOTF.Enable Input signal of enabling residual current SOTF protection
2 50GSOTF.Block Input signal of blocking residual current SOTF protection

Table 3.18-2 Output signals of residual current SOTF protection

No. Output Signal Description

1 50GSOTF.On Residual current SOTF protection is enabled.
2 50GSOTF.Blocked Residual current SOTF protection is blocked.
3 50GSOTF.Valid Residual current SOTF protection is valid.
4 50GSOTF.Op Residual current SOTF protection operates.
5 50GSOTF.St Residual current SOTF protection starts.

3.18.4 Logic

SIG 50GSOTF.Enable &

50GSOTF.On
EN [50GSOTF.En]
&
SIG 50GSOTF.Block >=1 50GSOTF.Blocked

SIG Fail_Device
&
50GSOTF.Valid

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SIG I3P 2nd Hm Detect &

SET [50/51G1.En_Hm2_Blk]

SIG 3-pole AR signal >=1

&
SIG Manual closing signal [50GSOTF.t_Op_3P] 0

SET 3I0>[50GSOTF.3I0_Set]
& >=1
SIG FD.ROC.Pkp & 50GSOTF.Op
[50GSOTF.t_Op_1P] 0
SIG 50GSOTF.Enable

SIG 1-pole AR signal

>=1

3
50GSOTF.St

Figure 3.18-1 Logic of residual current SOTF protection

3.18.5 Settings
Table 3.18-3 Settings of residual current SOTF protection

Name Range Step Unit Default Description

Current setting of residual current
50GSOTF.3I0_Set (0.050~40.000)×In 0.001 A 1.000
SOTF protection
Time delay for residual current
50GSOTF.t_Op_1P 0.000~100.000 0.001 s 0.060
SOTF protection when 1 pole closed
Time delay for residual current
50GSOTF.t_Op_3P 0.000~100.000 0.001 s 0.100
SOTF protection when 3 pole closed
Disabled Enabling/disabling residual current
50GSOTF.En Enabled
Enabled SOTF protection
Enabling/disabling residual current
Disabled
50GSOTF.En_Hm2_Blk Disabled SOTF protection blocked by
Enabled
harmonic

3.19 Negative-sequence Overcurrent Protection (50/51Q)

When a phase-to-phase fault occurs in the system, the fault current is small, and phase current
criterion may not detect the fault. At this time, negative-sequence overcurrent protection is sensitive
to the fault and can be used. Negative-sequence overcurrent (NOC) protection can also be used
to detect pole disagreement operation or unbalanced load.

3.19.1 Function Description

The device can provide two stages of negative-sequence overcurrent protection with independent
logic. Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. For parallel lines or a ring network line, the flow direction of negative-sequence
current may be different. Considering the selectivity of negative-sequence overcurrent protection,
the direction control element can be set as no direction, forward direction and reverse direction.

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Negative-sequence overcurrent protection can operate to trip or alarm. For some specific
applications, negative-sequence overcurrent protection needs to be blocked by the external signal,
so the device provides an input signal to be used to block negative-sequence overcurrent protection.

When CT circuit is abnormal or the position of three-phases circuit breaker are discrepant,
negative-sequence overcurrent protection should be blocked. By default, they have been fulfilled
by the connection to the "function blocked input" signal of earth fault protection (50/51Qi.Block). in
the configuration page "UserPage_Common" by PCS-Studio. (refer to "Section 4 Protection
Function Configuration in Application Manual")

SIG 52b_PhA

3 SIG 52b_PhB
>=1
&
SIG 52b_PhC

&

>=1 output to
SIG CB1.CTS.Alm 50/51Qi.Block

SIG CB2.CTS.Alm

Figure 3.19-1 Blocking scheme configuration

EN [50/51Qi.En] &
50/51Qi.On
SIG 50/51Qi.Enable
&
SIG 50/51Qi.Block >=1 50/51Qi.Blocked

SIG Fail_Device
&
50/51Qi.Valid

Figure 3.19-2 Logic of enabling negative-sequence overcurrent protection

The pickup logic of negative-sequence overcurrent protection is shown in Figure 3.19-3.

SET I2>0.95×[50/51Qi.I2_Set] & 50/51Qi.Pkp

0 500ms &
SIG 50/51Qi.On &
FD.Pkp
SIG 50/51Qi.Valid

SET [50/51Qi.Opt_Trp/Alm]=Alm

Figure 3.19-3 Pickup logic of negative-sequence overcurrent protection

3.19.1.1 Direction Control Element

In order to ensure the selectivity of negative-sequence overcurrent protection, direction control

element can be available. The setting [50/51Qi.Opt_Dir] (i=1 or 2) is used to select the direction

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characteristics for each stage of negative-sequence overcurrent protection: no direction, forward

direction and reverse direction are selectable. The direction control element selects negative-
sequence voltage as the polarized voltage, its operating characteristics is shown in Figure 3.19-4.

The operation boundary of the forward direction element can be set by [50/51Q.DIR.phi_Min_Fwd]
and [50/51Q.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51Q.DIR.phi_Min_Rev] and [50/51Q.DIR.phi_Max_Rev].

-U2

[50/51Q.DIR.phi_Min_Fwd]
3
Non-operating I2
area
[50/51Q.DIR.phi_Max_Rev]
Operating area in
forward direction

[50/51Q.DIR.RCA]

Operating area in
reverse direction

[50/51Q.DIR.phi_Max_Fwd]
Non-operating
area

[50/51Q.DIR.phi_Min_Rev]

Figure 3.19-4 Operating characteristics of direction control element

The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode. Polarization mode adopts negative-sequence voltage polarized.

Operating current Polarized voltage Angle difference

I2 -U2 Angle=Angle(-U2)-Angle(I2)-RCA

The direction element calculation needs to judge the current threshold and voltage threshold. The
direction judgement can not be executed unless the operating current is greater than the setting
[50/51Q.DIR.I2_Min], and the polarized voltage is greater than the setting [50/51Q.DIR.U2_Min].
The logic of forward direction element and reverse direction element are shown in Figure 3.19-5.

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EN [50/51Q.En_VTS_Blk] &

>=1

SIG VTS.Alm
& >=1
SIG I2

direction
Forward
criterion
SIG U2

3 EN [Prot.En_VT] &

SIG Prot.BI_En_VT
&
SET Iop>[50/51Q.DIR.I2_Min] 50/51Q.FwdDir.Op

SET Upo>[50/51Q.DIR.U2_Min]

EN [50/51Q.En_VTS_Blk] &

>=1

SIG VTS.Alm
& >=1
SIG I2
direction
Reverse
criterion

SIG U2

EN [Prot.En_VT] &

SIG Prot.BI_En_VT
&
SET Iop>[50/51Q.DIR.I2_Min] 50/51Q.RevDir.Op

SET Upo>[50/51Q.DIR.U2_Min]

Figure 3.19-5 Logic of forward and reverse direction element

Iop: the operating current

Upo: the polarized voltage

3.19.1.2 Operating Characteristics

Negative-sequence overcurrent protection can operate instantaneously or with a fixed time delay.
It can also operate with inverse-time characteristics, and its characteristics curve complies with the
standards IEC 60255-3 and ANSI C37.112. Negative-sequence overcurrent protection can support
definite-time characteristics, IEC & ANSI standard inverse-time characteristics and user-defined
inverse-time characteristics, which are determined by the setting [50/51Qi.Opt_Curve] (i=1 or 2).
The relationship between the setting and the characteristics curve is shown in the table below.

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50/51Qi.Opt_Curve Time Characteristic k α c tr

ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite time - - - -
ANSILTE ANSI Long time extremely inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long time very inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long time inverse 0.086 0.02 0.185 4.6
IECN IEC Normal inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 - 3
IECI IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short time inverse 0.05 0.04 0 -
IECLT IEC Long time inverse 120.0 1.0 0 -
IECDefTime IEC Definite time - - - -
UserDefine Programmable

When the setting [50/51Qi.Opt_Curve] is set as "UserDefine", it means that user-defined inverse-
time characteristics is selected. These settings [50/51Qi.K], [50/51Qi.C] and [50/51Qi.Alpha] are
valid, and the inverse-time operating curve is determined by the three settings.

⚫ Instantaneous characteristics

When I2>[50/51Qi.I2_Set], negative-sequence overcurrent protection operates immediately.

⚫ Definite-time characteristics

When I2>[50/51Qi.I2_Set], negative-sequence overcurrent protection operates with a time delay

[50/51Qi.t_Op], the operating characteristics curve is as shown in Figure 3.19-6.

[50/51Qi.t_Op]

I2
[50/51Qi.I2_Set]

Figure 3.19-6 Definite-time operating curve of NOC protection

⚫ Inverse-time characteristics

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When I2>[50/51Qi.I2_Set], negative-sequence overcurrent protection begins to accumulate, and

the operating time is affected by the applied current I2. The operating time will decrease with the
current increasing, but the operating time shall not less than the setting [50/51Qi.tmin] (i=1 or 2).
The inverse-time operating characteristics equation is:

[50/51Qi. K]
𝑡= [50/51Qi.Alpha]
+ [50/51Qi. C] × [50/51Qi. TMS]
𝐼2
( ) −1
{ [50/51Qi. I2_Set] }

I2 is the measured negative-sequence current.

3 The inverse-time operating characteristics curve is shown Figure 3.19-7.

[50/51Qi.tmin]

I2
[50/51Qi.I2_Set] ID

Figure 3.19-7 Inverse-time operating curve of NOC protection

When the applied negative-sequence current is not a fixed value, but changes with the time, the
operating behavior of inverse-time negative-sequence overcurrent protection is shown in the
following equation.

𝑇0
1
∫ 𝑑𝑡 = 1
𝑡(𝐼2 )
0

T0 is the operating time of the protection element.

t(I2) is the theoretical operating time when the current is I2.

3.19.1.3 Dropout Characteristics

The supported dropout characteristics of negative-sequence overcurrent protection include

instantaneous, definite-time and ANSI inverse-time characteristics. When the operating
characteristics curve is selected as definite-time, IEC inverse-time or user-defined inverse-time
characteristics, the dropout characteristic curve can only be selected as instantaneous or definite-
time characteristics, and the alarm signal "Fail_Settings" will be issued and the device will be

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blocked if ANSI inverse-time characteristics is selected. When the operating characteristics curve
is selected as ANSI inverse-time characteristics, the dropout characteristic curve can be selected
as instantaneous, definite-time and ANSI inverse-time characteristics.

⚫ Instantaneous characteristics

When I2<0.95×[50/51Qi.I2_Set], negative-sequence overcurrent protection drops out immediately.

⚫ Definite-time characteristics

When I2<0.95×[50/51Qi.I2_Set], negative-sequence overcurrent protection drops out with a time

delay [50/51Qi.t_DropOut], and the sequence diagram of definite-time dropout characteristic
among start signal, operating signal and the counter is as shown in Figure 3.19-8.
3
Start time

I2>[50/51Qi.I2_Set]

50/51Qi.St

50/51Qi.Op

[50/51Qi.t_Op] Negative-sequence overcurrent

protection operating

Operating counter

[50/51Qi.t_DropOut]
[50/51Qi.t_DropOut] [50/51Qi.t_DropOut]
Dropout time
Dropout time

Figure 3.19-8 Definite-time dropout characteristics of NOC protection

⚫ Inverse-time characteristics

When I2<0.95×[50/51Qi.I2_Set], negative-sequence overcurrent protection begins to accumulate,

the accumulated value after tP (Assuming tP is less than the theoretical operating time) is calculated
according to the following equation.

𝑡𝑃
1
𝐼𝑡𝑝 = ∫ 𝑑𝑡
𝑡(𝐼2 )
0

If I2<0.95×[50/51Qi.I2_Set], negative-sequence overcurrent protection begins to drop out, and the

dropout characteristics meets the following equations.

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𝑡𝑅
1
𝐼𝑡𝑝 − ∫ 𝑑𝑡 = 0
𝑡𝑅 (𝐼2 )
0

𝑡𝑟
𝑡𝑅 (𝐼2 ) = 2 × [50/51Qi. I2_Set]
𝐼2
1−( )
{ [50/51Qi. TMS] }

tR is the dropout time.

tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
3 negative-sequence overcurrent protection operates.

I2 is the measured negative-sequence current.

If 0.95×[50/51Qi.I2_Set]<I2<[50/51Qi.I2_Set], the counter will neither accumulate nor drop out.

The inverse-time dropout characteristics curve is shown in Figure 3.19-9.

tr

I2
[50/51Qi.I2_Set]

Figure 3.19-9 Inverse-time dropout curve of NOC protection

The sequence diagram of inverse-time dropout characteristics among start signal, operating signal
and the counter is shown in Figure 3.19-10.

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Start time

I2>[50/51Qi.I2_Set]

50/51Qi.St

50/51Qi.Op

[50/51Qi.t_Op]
Negative-sequence overcurrent
protection operating 3

Operating counter

Dropout time Coefficient (tr)

Dropout time
Dropout time

Figure 3.19-10 Inverse-time dropout characteristics of NOC protection

3.19.2 Function Block Diagram

50/51Q

50/51Qi.Enable 50/51Qi.On

50/51Qi.Block 50/51Qi.Blocked

50/51Qi.Valid

50/51Qi.St

50/51Qi.Op

50/51Qi.Alm

3.19.3 I/O Signal

Table 3.19-1 Input signals of negative-sequence overcurrent protection

No. Input signal Description

1 50/51Qi.Enable Input signal of enabling stage i of negative-sequence overcurrent protection (i=1~2)
2 50/51Qi.Block Input signal of blocking stage i of negative-sequence overcurrent protection (i=1~2)

Table 3.19-2 Output signals of negative-sequence overcurrent protection

No. Output signal Description

1 50/51Qi.On Stage i of negative-sequence overcurrent protection is enabled. (i=1~2)
2 50/51Qi.Blocked Stage i of negative-sequence overcurrent protection is blocked. (i=1~2)

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No. Output signal Description

3 50/51Qi.Valid Stage i of negative-sequence overcurrent protection is valid. (i=1~2)
4 50/51Qi.St Stage i of negative-sequence overcurrent protection starts. (i=1~2)
5 50/51Qi.Op Stage i of negative-sequence overcurrent protection operates. (i=1~2)
6 50/51Qi.Alm Stage i of negative-sequence overcurrent protection alarms. (i=1~2)

3.19.4 Logic

SET I2>[50/51Qi.I2_Set]
50/51Qi.St
SIG 50/51Q.FwdDir.Op
&
selection & Timer
Direction
3 SIG 50/51Q.RevDir.Op
t
t
SET [50/51Qi.Opt_Dir]

SIG 50/51Qi.Pkp

SIG 52b_PhA >=1

SIG 52b_PhB &

&

SIG 52b_PhC
&
50/51Qi.Op
SET [50/51Qi.Opt_Trp/Alm]=Trp

&
50/51Qi.Alm
SET [50/51Qi.Opt_Trp/Alm]=Alm

Figure 3.19-11 Logic of negative-sequence overcurrent protection

3.19.5 Settings
Table 3.19-3 Settings of negative-sequence overcurrent protection

Name Range Step Unit Default Description

The characteristic
50/51Q.DIR.RCA -180~179 1 ° 45 angle of direction
control element
The minimum
boundary in forward
50/51Q.DIR.phi_Min_Fwd 10~90 1 ° 90 direction of negative-
sequence overcurrent
protection
The maximum
boundary in forward
50/51Q.DIR.phi_Max_Fwd 10~90 1 ° 90
direction of negative-
sequence overcurrent

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Name Range Step Unit Default Description

protection
The minimum
boundary in reverse
50/51Q.DIR.phi_Min_Rev 10~90 1 ° 90 direction of negative-
sequence overcurrent
protection
The maximum
boundary in reverse
50/51Q.DIR.phi_Max_Rev 10~90 1 ° 90 direction of negative-
sequence overcurrent 3
protection
The minimum
operating current
50/51Q.DIR.I2_Min (0.050~1.000)×In 0.001 A 0.050
setting of direction
control element
The minimum
operating voltage
50/51Q.DIR.U2_Min 1.000~10.000 0.001 V 4.000
setting of direction
control element
The compensation
setting of negative-
50/51Q.DIR.Z2_Comp (0.000~4Unn)/In 0.001 Ω 0.000 sequence impedance
of direction control
element
Enabling/disabling
negative-sequence
overcurrent protection
Disabled
50/51Q.En_VTS_Blk Disabled is blocked by VT circuit
Enabled
failure when VT circuit
supervision is enabled
and VT circuit fails
The negative-
sequence current
setting for stage i of
50/51Qi.I2_Set (0.050~40.000)×In 0.001 A 15.000
negative-sequence
overcurrent protection
(i=1 or 2)
The operating time
delay for stage i of
50/51Qi.t_Op 0.030~100.000 0.001 s 0.100 negative-sequence
overcurrent protection
(i=1 or 2)
50/51Qi.t_DropOut 0.000~100.000 0.001 s 0.000 The dropout time delay

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Name Range Step Unit Default Description

for stage i of negative-
sequence overcurrent
protection (i=1 or 2)
The option direction
Non_Directional characteristic for stage
50/51Qi.Opt_Dir Forward Non_Directional i of negative-sequence
Reverse overcurrent protection
(i=1 or 2)
Enabling/disabling

3 50/51Qi.En
Disabled
Enabled
stage i of negative-
Enabled sequence overcurrent
protection (i=1 or 2)
Enabling/disabling
stage i of negative-
sequence overcurrent
Trp protection operate to
50/51Qi.Opt_Trp/Alm Trp
Alm trip or alarm (i=1 or 2)
Trp: for tripping
purpose
Alm: for alarm purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of operating
ANSILTV
characteristics curve
ANSILT
50/51Qi.Opt_Curve IECDefTime for stage i of negative-
IECN
sequence overcurrent
IECV
protection (i=1 or 2)
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of dropout
characteristics curve
Inst for stage i of negative-
50/51Qi.Opt_Curve_DropOut DefTime Inst sequence overcurrent
IDMT protection (i=1 or 2)
Inst: instantaneous
dropout characteristics

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Name Range Step Unit Default Description

DefTime: definite-time
dropout characteristics
IDMT: inverse-time
dropout characteristics
Time multiplier setting
for stage i of inverse-
50/51Qi.TMS 0.040~20.000 0.001 1.000 time negative-
sequence overcurrent
protection (i=1 or 2)
The minimum 3
operating time for
stage i of inverse-time
50/51Qi.tmin 0.000~10.000 0.001 s 0.020
negative-sequence
overcurrent protection
(i=1 or 2)
The constant “K” for
stage i of customized
50/51Qi.K 0.0010~120.0000 0.0001 0.1400 inverse-time negative-
sequence overcurrent
protection (i=1 or 2)
The constant “α” for
stage i of customized
50/51Qi.Alpha 0.0100~3.0000 0.0001 0.0200 inverse-time negative-
sequence overcurrent
protection (i=1 or 2)
The constant “C” for
stage i of customized
50/51Qi.C 0.0000~1.2000 0.0001 0.0000 inverse-time negative-
sequence overcurrent
protection (i=1 or 2)

3.20 Phase Overvoltage Protection (59P)

In the power system, some abnormal conditions can generate high voltage, which may damage
the insulation performance of transformers, capacitors, motors and transmission lines, resulting in
equipment damage. Phase overvoltage protection can effectively detect the overvoltage that may
be generated in the system.

3.20.1 Function Description

The device can provide two stages of phase overvoltage protection with independent logic. When
a high voltage occurs in the system, phase overvoltage protection will operate to isolate the fault
from the system after a time delay if the voltage is greater than the setting. In addition, phase

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overvoltage protection also provides the alarm function to notify that there is the overvoltage in the
system and find the cause timely to prevent from further deterioration of the fault. Each stage of
phase overvoltage protection can be independently set as definite-time characteristics or inverse-
time characteristics. The dropout characteristics can be set as instantaneous dropout and definite-
time dropout.

Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [59Pi.Opt_Up/Upp]. "1-out-of-3" or "3-out-of-3" logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages) Phase overvoltage protection can operate to trip or alarm. For some specific
applications, phase overvoltage protection needs to be blocked by the external signal, so the device
3 provides an input signal to be used to block phase overvoltage protection. In addition, if the VT is
out of service, phase overvoltage protection will be disabled.

EN [59Pi.En] &
59Pi.On
SIG 59Pi.Enable

SIG 59Pi.Block
&
>=1 59Pi.Blocked
SIG Fail_Device

SIG Prot.BI_En_VT & &

59Pi.Valid
EN [Prot.En_VT]

Figure 3.20-1 Logic of enabling phase overvoltage protection

The pickup logic of phase overvoltage protection is shown in Figure 3.20-2.

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SET [59Pi.Opt_Up/Upp]=Upp

SET Uab>U_DropOut
>=1
SET Ubc>U_DropOut &
SET Uca>U_DropOut

SET [59Pi.Opt_1P/3P]=1P
&
SET [59Pi.Opt_1P/3P]=3P >=1 Phase-phase voltage criterion

SET Uab>U_DropOut
&
&
SET Ubc>U_DropOut
3
SET Uca>U_DropOut

SET Ua>U_DropOut
>=1
SET Ub>U_DropOut &
SET Uc>U_DropOut

SET [59Pi.Opt_1P/3P]=1P

SET [59Pi.Opt_1P/3P]=3P >=1

SET Ua>U_DropOut
&
&
SET Ub>U_DropOut

SET Uc>U_DropOut
&
Phase voltage criterion
SET [59Pi.Opt_Up/Upp]=Up

SIG Phase-phase voltage criterion >=1

&
SIG Phase voltage criterion 0 500ms &
x.59Pi.Pkp
SIG 59Pi.On

SIG 59Pi.Valid
&
FD.Pkp
SET [59Pi.Opt_Trp/Alm]=Alm

Figure 3.20-2 Pickup logic of phase overvoltage protection

U_DropOut is the dropout voltage value, i.e. [59Pi.K_DropOut]×[59Pi.U_Set]

3.20.1.1 Operating Characteristics

Phase overvoltage protection can operate with a fixed time delay. It can also operate with inverse-
time characteristics, and its characteristics curve complies with the standards IEC 60255-3 and
ANSI C37.112. Phase overvoltage protection can support definite-time characteristics, IEC & ANSI
standard inverse-time characteristics and user-defined inverse-time characteristics, which are
determined by the setting [59Pi.Opt_Curve] (i=1 or 2).

The relationship between the setting and the characteristics curve is shown in the table below.

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59Pi.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite time - - -
IECDefTime IEC Definite time - - -
UserDefine UserDefine
InvTime_U Voltage inverse 1 1 0

When the setting [59Pi.Opt_Curve] is set as "ANSIDefTime" or "IECDefTime", the operating

characteristics is definite-time phase overvoltage protection.

When the setting [59Pi.Opt_Curve] is set as "UserDefine", it means that user-defined inverse-time
characteristics is selected. These settings [59Pi.K], [59Pi.C] and [59Pi.Alpha] are valid, and the
3 inverse-time operating curve is determined by the three settings.

When the setting [59Pi.Opt_Curve] is set as "InvTime_U", the settings [59Pi.K], [59Pi.C] and
[59Pi.Alpha] are useless.

⚫ Definite-time characteristics

When U>[59Pi.U_Set], phase overvoltage protection operates with a time delay [59Pi.t_Op], the
operating characteristics curve is as shown in Figure 3.20-3.

[59Pi.t_Op]

U
[59Pi.U_Set]

Figure 3.20-3 Definite-time operating curve of phase overvoltage protection

⚫ Inverse-time characteristics

When U>[59Pi.U_Set], phase overvoltage protection begins to accumulate, and the operating time
is affected by the applied voltage U. The operating time will decrease with the voltage increasing,
but the operating time shall not less than the setting [59Pi.tmin] (i=1 or 2).

The inverse-time operating characteristics equation is:

[59Pi. K]
𝑡= [59Pi.Alpha]
+ [59Pi. C] × [59Pi. TMS]
𝑈
( ) −1
{ [59Pi. U_Set] }

U is the measured voltage.

The inverse-time operating characteristics curve is shown Figure 3.20-4.

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[59Pi.tmin]

[59Pi.U_Set] UD
U 3
Figure 3.20-4 Inverse-time operating curve of phase overvoltage protection

When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overvoltage protection is shown in the following equation.

𝑇0
1
∫ 𝑑𝑡 = 1
𝑡(𝑈)
0

T0 is the operating time of the protection element.

t(U) is the theoretical operating time when the voltage is U.

3.20.1.2 Dropout Characteristics

The supported dropout characteristics of phase overvoltage protection include instantaneous and
definite-time characteristics.

⚫ Instantaneous characteristics

When U<[59Pi.K_DropOut]×[59Pi.U_Set], phase overvoltage protection drops out immediately.

⚫ Definite-time characteristics

When U<[59Pi.K_DropOut]×[59Pi.U_Set], phase overvoltage protection drops out with a time delay
[59Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among start
signal, operating signal and the counter is as shown in Figure 3.20-5.

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Start time

U>[59Pi.U_Set]

59Pi.St

3 59Pi.Op

[59Pi.t_Op] Phase overvoltage

protection operating

Operating counter

[59Pi.t_DropOut]
[59Pi.t_DropOut] [59Pi.t_DropOut]
Dropout time
Dropout time

Figure 3.20-5 Definite-time dropout characteristics of phase overvoltage protection

3.20.2 Function Block Diagram

59P

59Pi.Enable 59Pi.On

59Pi.Block 59Pi.Blocked

59Pi.Valid

59Pi.St

59Pi.StA

59Pi.StB

59Pi.StC

59Pi.Op

59Pi.Op.PhA

59Pi.Op.PhB

59Pi.Op.PhC

59Pi.Alm

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3.20.3 I/O Signal

Table 3.20-1 Input signals of phase overvoltage protection

No. Input signal Description

1 59Pi.Enable Input signal of enabling stage i of phase overvoltage protection (i=1~2)
2 59Pi.Block Input signal of blocking stage i of phase overvoltage protection (i=1~2)

Table 3.20-2 Output signals of phase overvoltage protection

No. Output signal Description

1 59Pi.On Stage i of phase overvoltage protection is enabled. (i=1~2)
2 59Pi.Blocked Stage i of phase overvoltage protection is blocked. (i=1~2) 3
3 59Pi.Valid Stage i of phase overvoltage protection is valid. (i=1~2)
4 59Pi.St Stage i of phase overvoltage protection starts. (i=1~2)
5 59Pi.StA Stage i of phase overvoltage protection starts. (Phase A, i=1~2)
6 59Pi.StB Stage i of phase overvoltage protection starts. (Phase B, i=1~2)
7 59Pi.StC Stage i of phase overvoltage protection starts. (Phase C, i=1~2)
8 59Pi.Op Stage i of phase overvoltage protection operates. (i=1~2)
9 59Pi.Op.PhA Stage i of phase overvoltage protection operates. (Phase A, i=1~2)
10 59Pi.Op.PhB Stage i of phase overvoltage protection operates. (Phase B, i=1~2)
11 59Pi.Op.PhC Stage i of phase overvoltage protection operates. (Phase C, i=1~2)
12 59Pi.Alm Stage i of phase overvoltage protection alarms. (i=1~2)

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3.20.4 Logic

SET [59Pi.Opt_Up/Upp]=Upp

SET Uab>[59Pi.U_Set]
>=1
SET Ubc>[59Pi.U_Set] &
SET Uca>[59Pi.U_Set]

SET [59Pi.Opt_1P/3P]=1P
&
SET [59Pi.Opt_1P/3P]=3P >=1 >=1
SET Uab>[59Pi.U_Set]
&
&
3 SET Ubc>[59Pi.U_Set]

SET Uca>[59Pi.U_Set]

SET [59Pi.Opt_Up/Upp]=Up

SET Ua>[59Pi.U_Set]
>=1
SET Ub>[59Pi.U_Set] &
SET Uc>[59Pi.U_Set]

SET [59Pi.Opt_1P/3P]=1P
&
SET [59Pi.Opt_1P/3P]=3P >=1
SET Ua>[59Pi.U_Set]
&
& 59Pi.St
SET Ub>[59Pi.U_Set]
& Timer
SET Uc>[59Pi.U_Set] t
&
t
SIG 59Pi.Pkp 59Pi.Op

SET [59Pi.Opt_Trp/Alm]=Trp

&
59Pi.Alm
SET [59Pi.Opt_Trp/Alm]=Alm

Figure 3.20-6 Logic of phase overvoltage protection

3.20.5 Settings
Table 3.20-3 Settings of phase overvoltage protection

Name Range Step Unit Default Description

The option of the calculation
voltage used by stage i of
Up phase overvoltage protection
59Pi.Opt_Up/Upp Upp
Upp (i=1 or 2)
Up: phase voltage
Upp: phase-to-phase voltage
The option of the voltage
3P criterion used by stage i of
59Pi.Opt_1P/3P 3P
1P phase overvoltage protection
(i=1 or 2)

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Name Range Step Unit Default Description

3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The voltage setting for stage i
59Pi.U_Set 57.700~200.000 0.001 V 115.000 of phase overvoltage
protection (i=1 or 2)
The dropout coefficient for
59Pi.K_DropOut 0.930~1.000 0.001 0.980 stage i of phase overvoltage
protection (i=1 or 2)
The operating time delay for
59Pi.t_Op 0.100~100.000 0.001 s 1.000 stage i of phase overvoltage 3
protection (i=1 or 2)
The dropout time delay for
59Pi.t_DropOut 0.000~100.000 0.001 s 0.000 stage i of phase overvoltage
protection (i=1 or 2)
Enabling/disabling stage i of
Disabled
59Pi.En Enabled phase overvoltage protection
Enabled
(i=1 or 2)
Enabling/disabling stage i of
phase overvoltage protection
Trp operate to trip or alarm (i=1 or
59Pi.Opt_Trp/Alm Trp
Alm 2)
Trp: for tripping purpose
Alm: for alarm purpose
ANSIDefTime The option of operating
IECDefTime characteristics curve for stage
59Pi.Opt_Curve IECDefTime
UserDefine i of phase overvoltage
InvTime_U protection (i=1 or 2)
The option of dropout
characteristics curve for stage
i of phase overvoltage
Inst protection (i=1 or 2)
59Pi.Opt_Curve_DropOut Inst
DefTime Inst: instantaneous dropout
characteristics
DefTime: definite-time dropout
characteristics
Time multiplier setting for
stage i of inverse-time phase
59Pi.TMS 0.040~20.000 0.001 1.000
overvoltage protection (i=1 or
2)
The minimum operating time
for stage i of inverse-time
59Pi.tmin 0.000~10.000 0.001 s 0.020
phase overvoltage protection
(i=1 or 2)

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Name Range Step Unit Default Description

The constant “K” for stage i of
customized inverse-time
59Pi.K 0.0010~120.0000 0.0001 1.0000
phase overvoltage protection
(i=1 or 2)
The constant “C” for stage i of
customized inverse-time
59Pi.Alpha 0.0100~3.0000 0.0001 1.0000
phase overvoltage protection
(i=1 or 2)
The constant “α” for stage i of

3 59Pi.C 0.0000~1.0000 0.0001 0.0000

customized inverse-time
phase overvoltage protection
(i=1 or 2)

3.21 Residual Overvoltage Protection (59G)

If an earth fault happens to the feeder in the grounding system via high resistance, the residual
current changes little and is difficult to detect. However, the amplitude of the residual voltage
changes significantly and can be used to detect the earth fault. In addition, the transformer is
grounded via the gap in the neutral point, the residual voltage increases once a fault occurs, so
residual overvoltage protection can also be used as backup protection of the transformer. The
residual voltage is calculated internally by the device using three-phase voltage.

3.21.1 Function Description

The device can provide two stages of residual overvoltage protection with independent logic. When
the residual voltage is greater than the setting, residual overvoltage protection will operate to isolate
the fault from the system after a time delay. In addition, residual overvoltage protection also
provides the alarm function to notify that there is an earth fault leading to residual voltage
generation, and find the cause timely to prevent from further deterioration of the fault.

EN [59Gi.En] &
59Gi.On
SIG 59Gi.Enable

SIG 59Gi.Block
&
>=1 59Gi.Blocked
SIG Fail_Device

SIG Prot.BI_En_VT & &

59Gi.Valid
EN [Prot.En_VT]

Figure 3.21-1 Logic of enabling residual overvoltage protection

Residual overvoltage protection supports definite-time characteristics. The dropout characteristics

can be set as instantaneous dropout and definite-time dropout. Residual overvoltage protection
can operate to trip or alarm. For some specific applications, residual overvoltage protection needs

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to be blocked by the external signal, so the device provides an input signal to be used to block
residual overvoltage protection. In addition, if the VT is out of service, residual overvoltage
protection will be disabled.

The pickup logic of residual overvoltage protection is shown in Figure 3.21-2.

SET 3U0_Cal>[59Gi.K_DropOut]×[59Gi.3U0_Set] &

0 500ms &
SIG 59Gi.On 59Gi.Pkp

SIG 59Gi.Valid
&
FD.Pkp

3
SET [59Gi.Opt_Trp/Alm]=Alm

Figure 3.21-2 Pickup logic of residual overvoltage protection

3.21.1.1 Operating Characteristics

When 3U0>[59Gi.3U0_Set], residual overvoltage protection operates with a time delay [59Gi.t_Op],
the operating characteristics curve is as shown in Figure 3.21-3.

[59Gi.t_Op]

U0
[59Gi.3U0_Set]

Figure 3.21-3 Definite-time operating curve of residual overvoltage protection

3.21.1.2 Dropout Characteristics

The supported dropout characteristics of residual overvoltage protection include instantaneous and
definite-time characteristics.

⚫ Instantaneous characteristics

When 3U0<[59Gi.K_DropOut]×[59Gi.3U0_Set], residual overvoltage protection drops out

immediately.

⚫ Definite-time characteristics

When 3U0<[59Gi.K_DropOut]×[59Gi.3U0_Set], residual overvoltage protection drops out with a

time delay [59Gi.t_DropOut], and the sequence diagram of definite-time dropout characteristic
among start signal, operating signal and the counter is as shown in Figure 3.21-4.

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Start time

3U0>[59Gi.3U0_Set]

59Gi.St

3 59Gi.Op

[59Gi.t_Op] Residual overvoltage

protection operating

Operating counter

[59Gi.t_DropOut]
[59Gi.t_DropOut] [59Gi.t_DropOut]
Dropout time
Dropout time

Figure 3.21-4 Definite-time dropout characteristics of residual overvoltage protection

3.21.2 Function Block Diagram

59G

59Gi.Enable 59Gi.On

59Gi.Block 59Gi.Blocked

59Gi.Valid

59Gi.St

59Gi.Op

59Gi.Alm

3.21.3 I/O Signal

Table 3.21-1 Input signals of residual overvoltage protection

No. Input signal Description

1 59Gi.Enable Input signal of enabling stage i of residual overvoltage protection (i=1~2)
2 59Gi.Block Input signal of blocking stage i of residual overvoltage protection (i=1~2)

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Table 3.21-2 Output signals of residual overvoltage protection

No. Output signal Description

1 59Gi.On Stage i of residual overvoltage protection is enabled. (i=1~2)
2 59Gi.Blocked Stage i of residual overvoltage protection is blocked. (i=1~2)
3 59Gi.Valid Stage i of residual overvoltage protection is valid. (i=1~2)
4 59Gi.St Stage i of residual overvoltage protection starts. (i=1~2)
5 59Gi.Op Stage i of residual overvoltage protection operates. (i=1~2)
6 59Gi.Alm Stage i of residual overvoltage protection alarms. (i=1~2)

3.21.4 Logic

59Gi.St
3
SET 3U0_Cal>[59Gi.3U0_Set] &
[59Gi.t_Op] 0
SIG 59Gi.Pkp
&
59Gi.Op
SET [59Gi.Opt_Trp/Alm]=Trp

&
59Gi.Alm
SET [59Gi.Opt_Trp/Alm]=Alm

Figure 3.21-5 Logic of residual overvoltage protection

3.21.5 Settings
Table 3.21-3 Settings of residual overvoltage protection

Name Range Step Unit Default Description

The voltage setting for stage i of residual
59Gi.3U0_Set 1.000~200.000 0.001 V 50.000
overvoltage protection (i=1 or 2)
The dropout coefficient for stage i of residual
59Gi.K_DropOut 0.930~1.000 0.001 0.980
overvoltage protection (i=1 or 2)
The operating time delay for stage i of residual
59Gi.t_Op 0.100~100.000 0.001 s 1.000
overvoltage protection (i=1 or 2)
The dropout time delay for stage i of residual
59Gi.t_DropOut 0.000~100.000 0.001 s 0.000
overvoltage protection (i=1 or 2)
Disabled Enabling/disabling stage i of residual
59Gi.En Enabled
Enabled overvoltage protection (i=1 or 2)
Enabling/disabling stage i of residual
overvoltage protection operate to trip or alarm
Trp
59Gi.Opt_Trp/Alm Trp (i=1 or 2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose

3.22 Negative-sequence Overvoltage Protection (59Q)

When the system has a broken-conductor, reverse phase sequence or inter-phase voltage

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imbalance, negative-sequence voltage increases, and negative-sequence overvoltage protection

can reflect the system imbalance fault. It is used to protect the equipment from insulation
breakdown or premature aging due to the overvoltage. Negative-sequence overvoltage (NOV)
protection can also be used to alarm for prompting users the system voltage state is abnormal at
this moment.

3.22.1 Function Description

The device provides two stages of negative-sequence overvoltage protection. If negative-sequence

voltage is greater than the setting, negative-sequence overvoltage protection will operate.
Negative-sequence overvoltage protection is with independent definite-time characteristics and
3 definite-time or instantaneous dropout characteristics.

EN [59Qi.En] &
59Qi.On
SIG 59Qi.Enable

SIG 59Qi.Block
&
>=1 59Qi.Blocked
SIG Fail_Device

SIG Prot.BI_En_VT & &

59Qi.Valid
EN [Prot.En_VT]

Figure 3.22-1 Logic of enabling negative-sequence overvoltage protection

Negative-sequence overvoltage protection can operate to trip or alarm. For some special
application, negative-sequence overvoltage protection needs to be blocked by the external signal,
so the device provides an input signal to be used to block negative-sequence overvoltage
protection. In addition, if the VT is out of service, negative-sequence overvoltage protection will be
disabled. The pickup logic of negative-sequence overvoltage protection is shown in Figure 3.22-2.

SET U2>[59Qi.U2_Set]×[59Qi.K_DropOut] & 59Qi.Pkp

0 500ms &
SIG 59Qi.On &
FD.Pkp
SIG 59Qi.Valid

SET [59Qi.Opt_Trp/Alm]=Alm

Figure 3.22-2 Pickup logic of negative-sequence overvoltage protection

3.22.1.1 Operation Characteristics

When U2>[59Qi.U2_Set], negative-sequence overvoltage protection operates with a time delay

[59Qi.t_Op], the operating characteristics curve is as shown in Figure 3.22-3.

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[59Qi.t_Op]

U2
[59Qi.U2_Set]
3
Figure 3.22-3 Definite-time operating curve of NOV protection

3.22.1.2 Dropout Characteristics

The supported dropout characteristics of negative-sequence overvoltage protection include

instantaneous and definite-time characteristics.

⚫ Instantaneous characteristics

When U2<[59Qi.K_DropOut]×[59Qi.U2_Set], negative-sequence overvoltage protection drops out

immediately.

⚫ Definite-time characteristics

Start time

U2>[59Qi.U2_Set]

59Qi.St

59Qi.Op

[59Qi.t_Op] Negative-sequence overvoltage

protection operating

Operating counter

[59Qi.t_DropOut]
[59Qi.t_DropOut] [59Qi.t_DropOut]
Dropout time
Dropout time

Figure 3.22-4 Definite-time dropout characteristics of NOV protection

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When U2<[59Qi.K_DropOut]×[59Qi.U2_Set], negative-sequence overvoltage protection drops out

with a time delay [59Qi.t_DropOut], and the sequence diagram of definite-time dropout
characteristic among start signal, operating signal and the counter is as shown in Figure 3.22-4.

3.22.2 Function Block Diagram

59Q

59Qi.Enable 59Qi.On

59Qi.Block 59Qi.Blocked

3 59Qi.Valid

59Qi.St

59Qi.Op

59Qi.Alm

3.22.3 I/O Signals

Table 3.22-1 Input signals of negative-sequence overvoltage protection

No. Input Signal Description

1 59Qi.Enable Input signal of enabling stage i of negative-sequence overvoltage protection (i=1 or 2)
2 59Qi.Block Input signal of blocking stage i of negative-sequence overvoltage protection (i=1 or 2)

Table 3.22-2 Output signals of negative-sequence overvoltage protection

No. Output Signal Description

1 59Qi.On Stage i of negative-sequence overvoltage protection is enabled. (i=1 or 2)
2 59Qi.Blocked Stage i of negative-sequence overvoltage protection is blocked. (i=1 or 2)
3 59Qi.Valid Stage i of negative-sequence overvoltage protection is valid. (i=1 or 2)
4 59Qi.St Stage i of negative-sequence overvoltage protection starts. (i=1 or 2)
5 59Qi.Op Stage i of negative-sequence overvoltage protection operates. (i=1 or 2)
6 59Qi.Alm Stage i of negative-sequence overvoltage protection alarms. (i=1 or 2)

3.22.4 Logic

59Qi.St
SET U2>[59Qi.U2_Set] &
[59Qi.t_Op] 0
SIG 59Qi.Pkp
&
59Qi.Op
SET [59Qi.Opt_Trp/Alm]=Trp

&
59Qi.Alm
SET [59Qi.Opt_Trp/Alm]=Alm

Figure 3.22-5 Logic of negative-sequence overvoltage protection

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3.22.5 Settings
Table 3.22-3 Settings of negative-sequence overvoltage protection

Name Range Step Unit Default Description

The voltage setting for stage i of negative-
59Qi.U2_Set 2.000~100.000 0.001 V 15.000
sequence overvoltage protection (i=1 or 2)
The dropout coefficient for stage i of negative-
59Qi.K_DropOut 0.930~1.000 0.001 0.980
sequence overvoltage protection (i=1 or 2)
The operating time delay for stage i of negative-
59Qi.t_Op 0.100~100.000 0.001 s 1.000
sequence overvoltage protection (i=1 or 2)

59Qi.t_DropOut 0.000~100.000 0.001 s 0.000

The dropout time delay for stage i of negative- 3
sequence overvoltage protection (i=1 or 2)
Disabled Enabling/disabling stage i of negative-
59Qi.En Enabled
Enabled sequence overvoltage protection (i=1 or 2)
Enabling/disabling stage i of negative-
sequence overvoltage protection operate to trip
Trp
59Qi.Opt_Trp/Alm Trp or alarm (i=1 or 2)
Alm
Trp: for tripping purpose
Alm: for alarm purpose

3.23 Phase Undervoltage Protection (27P)

In the power system, some abnormal conditions will lead to low voltage. Electric equipment such
as motors cannot operate for a long time under the rated voltage and need to be isolated from the
system timely. In addition, the voltage decreasing may be related to the shortage of system reactive
power. Shedding some reactive loads through phase undervoltage protection can improve the
voltage level of the system.

3.23.1 Function Description

The device can provide two stages of phase undervoltage protection with independent logic. When
the voltage drops in the system and it is lower than the setting, phase undervoltage protection will
operate to isolate the fault from the system after a time delay. In addition, phase undervoltage
protection also provides the alarm function to notify that there is a voltage drop in the system and
find the cause timely to prevent from further deterioration of the fault. Each stage of phase
undervoltage protection can be independently set as definite-time characteristics or inverse-time
characteristics. The dropout characteristics can be set as instantaneous dropout and definite-time
dropout.

Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [27Pi.Opt_Up/Upp]. "1-out-of-3" or "3-out-of-3" logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages). The circuit breaker position with/without the current condition can be as an
auxiliary criterion for phase undervoltage protection, which can be configured via the setting
[27Pi.Opt_LogicMode].

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EN [27Pi.En] &
27Pi.On
SIG 27Pi.Enable

SIG 27Pi.Block
&
>=1 27Pi.Blocked
SIG Fail_Device

SIG Prot.BI_En_VT & &

27Pi.Valid
EN [Prot.En_VT]

3 Figure 3.23-1 Logic of enabling phase undervoltage protection

Phase undervoltage protection can operate to trip or alarm. For some specific applications, phase
undervoltage protection needs to be blocked by the external signal, so the device provides an input
signal to be used to block phase undervoltage protection. In addition, if the VT is out of service,
phase undervoltage protection will be disabled.

The pickup logic of phase overvoltage protection is shown in Figure 3.23-2. U_DropOut is the
dropout voltage value, i.e. [27Pi.K_DropOut]×[27Pi.U_Set].

SET [27Pi.Opt_1P/3P]=3P
&
SET [27Pi.Opt_Up/Upp]=Upp

SET Uab<[U_DropOut]
&
SET Ubc<[U_DropOut]

SET Uca<[U_DropOut]
>=1
&
SET [27Pi.Opt_1P/3P]=1P

SET Uab<[U_DropOut]
>=1
SET Ubc<[U_DropOut]

SET Uca<[U_DropOut]

SET [27Pi.Opt_1P/3P]=3P
&
SET [27Pi.Opt_Up/Upp]=Up

SET Ua<[U_DropOut]
&
SET Ub<[U_DropOut] >=1
SET Uc<[U_DropOut]
>=1 Voltage criterion
&
SET [27Pi.Opt_1P/3P]=1P

SET Ua<[U_DropOut]
>=1
SET Ub<[U_DropOut]

SET Uc<[U_DropOut]

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SET [27Pi.Opt_LogicMode]=None

SET [27Pi.Opt_LogicMode]=Curr

SIG Ia>0.04In
&
SIG Ib>0.04In
& >=1

SIG Ic>0.04In

SET [27Pi.Opt_LogicMode]=CBPos &

SIG CB closed position

>=1
& >=1
3
>=1 Auxiliary criterion
SET [27Pi.Opt_LogicMode]=CurrOrCBPos
&
&

SET [27Pi.Opt_LogicMode]=CurrAndCBPos

SIG Voltage criterion

& 27Pi.Pkp
SIG Auxiliary criterion 0 500ms &
&
SIG VTS.Alm & FD.Pkp
&
EN [27Pi.En_VTS_Blk]

SIG 27Pi.On

SIG 27Pi.Valid

SET [27Pi.Opt_Trp/Alm]=Alm

Figure 3.23-2 Pickup logic of phase undervoltage protection

3.23.1.1 Operating Characteristics

Phase undervoltage protection can operate with a fixed time delay. It can also operate with inverse-
time characteristics, and its characteristics curve complies with the standards IEC 60255-3 and
ANSI C37.112. Phase overvoltage protection can support definite-time characteristics, IEC & ANSI
standard inverse-time characteristics and user-defined inverse-time characteristics, which are
determined by the setting [27Pi.Opt_Curve] (i=1 or 2). The relationship between the setting and the
characteristics curve is shown in the table below.

27Pi.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite time - - -
IECDefTime IEC Definite time - - -
UserDefine UserDefine
InvTime_U Voltage inverse 1 1 0

When the setting [27Pi.Opt_Curve] is set as "ANSIDefTime" or "IECDefTime", the operating

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characteristics is definite-time phase undervoltage protection. When the setting [27Pi.Opt_Curve]

is set as "UserDefine", it means that user-defined inverse-time characteristics is selected. These
settings [27Pi.K], [27Pi.C] and [27Pi.Alpha] are valid, and the inverse-time operating curve is
determined by the three settings. When the setting [27Pi.Opt_Curve] is set as "InvTime_U", the
settings [27Pi.K], [27Pi.C] and [27Pi.Alpha] are useless.

⚫ Definite-time characteristics

When U<[27Pi.U_Set], phase undervoltage protection operates with a time delay [27Pi.t_Op], the
operating characteristics curve is as shown in Figure 3.23-3.

3 t

[27Pi.t_Op]

U
[27Pi.U_Set]

Figure 3.23-3 Definite-time operating curve of phase undervoltage protection

⚫ Inverse-time characteristic

When U<[27Pi.U_Set], phase undervoltage protection begins to accumulate, and the operating
time is affected by the applied voltage U. The operating time will decrease with the voltage
decreasing, but the operating time shall not less than the setting [27Pi.tmin] (i=1 or 2).

[27Pi.tmin]

U
UD [27Pi.U_Set]

Figure 3.23-4 Inverse-time operating curve of phase undervoltage protection

The inverse-time operating characteristics equation is:

[27Pi. K]
𝑡= [27Pi.Alpha]
+ [27Pi. C] × [27Pi. TMS]
𝑈
1−( )
{ [27Pi. U_Set] }

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U is the measured voltage.

When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase undervoltage protection is shown in the following equation.

𝑇0
1
∫ 𝑑𝑡 = 1
𝑡(𝑈)
0

T0 is the operating time of the protection element.

t(U) is the theoretical operating time when the voltage is U.

The inverse-time operating characteristics curve is shown Figure 3.23-4. 3

3.23.1.2 Dropout Characteristics

The supported dropout characteristics of phase undervoltage protection include instantaneous and
definite-time characteristics.

⚫ Instantaneous characteristics

When U>[27Pi.K_DropOut]×[27Pi.U_Set], phase undervoltage protection drops out immediately.

⚫ Definite-time characteristics

Start time

U<[27Pi.U_Set]

27Pi.St

27Pi.Op

[27Pi.t_Op] Phase undervoltage

protection operating

Operating counter

[27Pi.t_DropOut]
[27Pi.t_DropOut] [27Pi.t_DropOut]
Dropout time
Dropout time

Figure 3.23-5 Definite-time dropout characteristics of phase undervoltage protection

When U>[27Pi.K_DropOut]×[27Pi.U_Set], phase undervoltage protection drops out with a time

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delay [27Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among
start signal, operating signal and the counter is as shown in Figure 3.23-5.

3.23.2 Function Block Diagram

27P

27Pi.Enable 27Pi.On

27Pi.Block 27Pi.Blocked

27Pi.Valid

3 27Pi.St

27Pi.StA

27Pi.StB

27Pi.StC

27Pi.Op

27Pi.Op.PhA

27Pi.Op.PhB

27Pi.Op.PhC

27Pi.Alm

3.23.3 I/O Signal

Table 3.23-1 Input signals of phase undervoltage protection

No. Input signal Description

1 27Pi.Enable Input signal of enabling stage i of phase undervoltage protection (i=1 or 2)
2 27Pi.Block Input signal of blocking stage i of phase undervoltage protection (i=1 or 2)

Table 3.23-2 Output signals of phase undervoltage protection

No. Output signal Description

1 27Pi.On Stage i of phase undervoltage protection is enabled. (i=1 or 2)
2 27Pi.Blocked Stage i of phase undervoltage protection is blocked. (i=1 or 2)
3 27Pi.Valid Stage i of phase undervoltage protection is valid. (i=1 or 2)
4 27Pi.St Stage i of phase undervoltage protection starts. (i=1 or 2)
5 27Pi.StA Stage i of phase undervoltage protection starts. (Phase A, i=1 or 2)
6 27Pi.StB Stage i of phase undervoltage protection starts. (Phase B, i=1 or 2)
7 27Pi.StC Stage i of phase undervoltage protection starts. (Phase C, i=1 or 2)
8 27Pi.Op Stage i of phase undervoltage protection operates. (i=1 or 2)
9 27Pi.Op.PhA Stage i of phase undervoltage protection operates. (Phase A, i=1 or 2)
10 27Pi.Op.PhB Stage i of phase undervoltage protection operates. (Phase B, i=1 or 2)
11 27Pi.Op.PhC Stage i of phase undervoltage protection operates. (Phase C, i=1 or 2)

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No. Output signal Description

12 27Pi.Alm Stage i of phase undervoltage protection alarms. (i=1 or 2)

3.23.4 Logic

SET [27Pi.Opt_1P/3P]=3P
&
SET [27Pi.Opt_Up/Upp]=Upp

SET Uab<[27Pi.U_Set]
&
SET Ubc<[27Pi.U_Set]
>=1
SET Uca<[27Pi.U_Set]
& 3
SET [27Pi.Opt_1P/3P]=1P

SET Uab<[27Pi.U_Set]
>=1
SET Ubc<[27Pi.U_Set]

SET Uca<[27Pi.U_Set]

SET [27Pi.Opt_1P/3P]=3P
&
SET [27Pi.Opt_Up/Upp]=Up

SET Ua<[27Pi.U_Set]
&
SET Ub<[27Pi.U_Set] >=1
SET Uc<[27Pi.U_Set]
>=1 Voltage criterion
&
SET [27Pi.Opt_1P/3P]=1P

SET Ua<[27Pi.U_Set]
>=1
SET Ub<[27Pi.U_Set]

SET Uc<[27Pi.U_Set]

SIG Voltage criterion 27Pi.St

&
SIG Auxiliary criterion & Timer
t
SIG VTS.Alm & t
&
EN [27Pi.En_VTS_Blk]

SIG 27Pi.On

SIG 27Pi.Pkp
&
27Pi.Op
SET [27Pi.Opt_Trp/Alm]=Trp

&
27Pi.Alm

SET [27Pi.Opt_Trp/Alm]=Alm

Figure 3.23-6 Logic of phase undervoltage protection

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3.23.5 Settings
Table 3.23-3 Settings of phase undervoltage protection

Name Range Step Unit Default Description

The option of the calculation
voltage used by stage i of
Up phase undervoltage protection
27Pi.Opt_Up/Upp Upp
Upp (i=1 or 2)
Up: phase voltage
Upp: phase-to-phase voltage

3 The option of the voltage

criterion used by stage i of
3P phase undervoltage protection
27Pi.Opt_1P/3P 3P
1P (i=1 or 2)
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of auxiliary criterion
mode for stage i of phase
undervoltage protection (i=1 or
2)
None: no check
None
Curr: check current condition
Curr
CBPos: check normally open
27Pi.Opt_LogicMode CBPos Curr
auxiliary contact
CurrOrCBPos
CurrOrCBPos: check current
CurrAndCBPos
condition or normally open
auxiliary contact
CurrAndCBPos: check current
condition and normally open
auxiliary contact
The voltage setting for stage i
27Pi.U_Set 5.000~120.000 0.001 V 80.000 of phase undervoltage
protection (i=1 or 2)
The dropout coefficient for
27Pi.K_DropOut 1.000~1.200 0.001 1.030 stage i of phase undervoltage
protection (i=1 or 2)
The operating time delay for
27Pi.t_Op 0.100~100.000 0.001 s 1.000 stage i of phase undervoltage
protection (i=1 or 2)
The dropout time delay for
27Pi.t_DropOut 0.000~100.000 0.001 s 0.000 stage i of phase undervoltage
protection (i=1 or 2)
Disabled Enabling/disabling stage i of
27Pi.En_VTS_Blk Disabled
Enabled phase undervoltage protection

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Name Range Step Unit Default Description

is blocked by VT circuit failure
when VT circuit supervision is
enabled and VT circuit fails
(i=1 or 2)
Enabling/disabling stage i of
Disabled
27Pi.En Enabled phase undervoltage protection
Enabled
(i=1 or 2)
Enabling/disabling stage i of
phase undervoltage protection

27Pi.Opt_Trp/Alm
Trp
Trp
operate to trip or alarm (i=1 or 3
Alm 2)
Trp: for tripping purpose
Alm: for alarm purpose
ANSIDefTime The option of operating
IECDefTime characteristics curve for stage
27Pi.Opt_Curve IECDefTime
UserDefine i of phase undervoltage
InvTime_U protection (i=1 or 2)
The option of dropout
characteristics curve for stage
i of phase undervoltage
Inst protection (i=1 or 2)
27Pi.Opt_Curve_DropOut Inst
DefTime Inst: instantaneous dropout
characteristics
DefTime: definite-time dropout
characteristics
Time multiplier setting for
stage i of inverse-time phase
27Pi.TMS 0.040~20.000 0.001 1.000
undervoltage protection (i=1 or
2)
The minimum operating time
for stage i of inverse-time
27Pi.tmin 0.030~10.000 0.001 s 0.030
phase undervoltage protection
(i=1 or 2)
The constant “K” for stage i of
customized inverse-time
27Pi.K 0.0010~120.0000 0.0001 0.1400
phase undervoltage protection
(i=1 or 2)
The constant “α” for stage i of
customized inverse-time
27Pi.Alpha 0.0100~3.0000 0.0001 0.0200
phase undervoltage protection
(i=1 or 2)
The constant “C” for stage i of
27Pi.C 0.0000~1.0000 0.0001 0.0000
customized inverse-time

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Name Range Step Unit Default Description

phase undervoltage protection
(i=1 or 2)

3.24 Overfrequency Protection (81O)

Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The increase of frequency indicates that
the output power of the system is much larger than that of the load. When the system frequency is
greater than the predefined setting, the overfrequency protection will operate for removing some
3 part of active power supplies from the system.

3.24.1 Function Description

The device can provide four stages of overfrequency protection. If the system frequency is greater
than the setting, overfrequency protection will operate to remove some part of active power supplies
from the system. Overfrequency protection is with independent definite-time characteristics and
with instantaneous dropout characteristics.

Overfrequency protection can operate to trip or alarm. For some specific applications,
overfrequency protection needs to be blocked by the external signal, so the device provides an
input signal to be used to block overfrequency protection.

EN [81Oi.En] &
81Oi.On
SIG 81Oi.Enable
&
SIG 81Oi.Block >=1 81Oi.Blocked

SIG Fail_Device
&
81Oi.Valid

Figure 3.24-1 Logic of enabling overfrequency protection

The pickup logic of overfrequency protection is shown in Figure 3.24-2.

SET f>[81Oi.f_Set] &

&
SET Upp_min>[81.Upp_Blk] 0 500ms &
81Oi.Pkp
SIG 81Oi.On

SIG 81Oi.Valid
&
FD.Pkp
SET [81Oi.Opt_Trp/Alm]=Alm

Figure 3.24-2 Pickup logic of overfrequency protection

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3.24.1.1 Operation Characteristics

Overfrequency protection supports definite-time characteristics complied with IEC 60255-3 and
ANSI C37.112. If the system frequency is greater than the setting [81Oi.f_Set], overfrequency
protection will operate with a time delay [81Oi.t_Op]. The operating characteristics curve of
overfrequency protection is shown in Figure 3.24-3.

3
[81Oi.t_Op]

f
[81Oi.f_Set]

Figure 3.24-3 Definite-time operating curve of overfrequency protection

3.24.1.2 Dropout Characteristics

Overfrequency protection is with instantaneous dropout characteristics. If the system frequency is

less than the setting [81Oi.f_Set], overfrequency protection will drop out immediately.

3.24.2 Function Block Diagram

81O

81Oi.Enable 81Oi.On

81Oi.Block 81Oi.Blocked

81Oi.Valid

81Oi.St

81Oi.Op

81Oi.Alm

3.24.3 I/O Signals

Table 3.24-1 Input signals of overfrequency protection

No. Input Signal Description

1 81Oi.Enable Input signal of enabling stage i of overfrequency protection (i=1~4)
2 81Oi.Block Input signal of blocking stage i of overfrequency protection (i=1~4)

Table 3.24-2 Output signals of overfrequency protection

No. Output Signal Description

1 81Oi.On Stage i of overfrequency protection is enabled. (i=1~4)

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2 81Oi.Blocked Stage i of overfrequency protection is blocked. (i=1~4)

3 81Oi.Valid Stage i of overfrequency protection is valid. (i=1~4)
4 81Oi.St Stage i of overfrequency protection starts. (i=1~4)
5 81Oi.Op Stage i of overfrequency protection operates. (i=1~4)
6 81Oi.Alm Stage i of overfrequency protection alarms. (i=1~4)

3.24.4 Logic

SET f>[81Oi.f_Set] & 81Oi.St

&
SET Upp_min>[81.Upp_Blk] [81Oi.t_Op] 0

3 SIG 81Oi.Pkp
&
81Oi.Alm
SET [81Oi.Opt_Trp/Alm]=Alm

&
81Oi.Op
SET [81Oi.Opt_Trp/Alm]=Trp

Figure 3.24-4 Logic of overfrequency protection

3.24.5 Settings
Table 3.24-3 Settings of overfrequency protection

Name Range Step Unit Default Description

The phase-to-phase voltage setting used to
81.Upp_Blk 10.000~150.000 0.001 V 70.000
block overfrequency protection
The frequency setting for stage i of
81Oi.f_Set 50.000~65.000 0.001 Hz 52.000
overfrequency protection (i=1~4)
The time delay for stage i of overfrequency
81Oi.t_Op 0.000~100.000 0.001 s 0.300
protection (i=1~4)
Disabled Enabling/disabling stage i of overfrequency
81Oi.En Enabled
Enabled protection (i=1~4)
Enabling/disabling stage i of overfrequency
Trp protection operate to trip or alarm (i=1~4)
81Oi.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

3.25 Underfrequency Protection (81U)

Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The decrease of frequency indicates that
the output power of the system is much less than that of the load. When the system frequency is
less than the predefined setting, the underfrequency protection will operate for shedding some part
of loads from the system.

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3.25.1 Function Description

The device can provide four stages of underfrequency protection. If the system frequency is less
than the setting, underfrequency protection will operate to shedding some part of loads from the
system. Underfrequency protection is with independent definite-time characteristics and with
instantaneous dropout characteristics.

Underfrequency protection can operate to trip or alarm. For some specific applications,
underfrequency protection needs to be blocked by the external signal, so the device provides an
input signal to be used to block underfrequency protection.

&
3
EN [81Ui.En]
81Ui.On
SIG 81Ui.Enable
&
SIG 81Ui.Block >=1 81Ui.Blocked

SIG Fail_Device
&
81Ui.Valid

Figure 3.25-1 Logic of enabling underfrequency protection

The pickup logic of underfrequency protection is shown in Figure 3.25-2.

SET f<[81Ui.f_Set] &

&
SET Upp_min>[81.Upp_Blk] 0 500ms &
81Ui.Pkp
SIG 81Ui.On

SIG 81Ui.Valid
&
FD.Pkp
SET [81Ui.Opt_Trp/Alm]=Alm

Figure 3.25-2 Pickup logic of underfrequency protection

3.25.1.1 Operation Characteristics

The operating characteristics curve of underfrequency protection is shown in Figure 3.25-3.

[81Ui.t_Op]

f
[81Ui.f_Set]

Figure 3.25-3 Definite-time operating curve of underfrequency protection

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Underfrequency protection supports definite-time characteristics complied with IEC 60255-3 and
ANSI C37.112. If the system frequency is less than the setting [81Ui.f_Set], underfrequency
protection will operate with a time delay [81Ui.t_Op].

3.25.1.2 Dropout Characteristics

Underfrequency protection is with instantaneous dropout characteristics. If the system frequency

is less than the setting [81Oi.f_Set], underfrequency protection will drop out immediately.

3.25.2 Function Block Diagram

81U
3 81Ui.Enable 81Ui.On

81Ui.Block 81Ui.Blocked

81Ui.Valid

81Ui.St

81Ui.Op

81Ui.Alm

3.25.3 I/O Signals

Table 3.25-1 Input signals of underfrequency protection

No. Input Signal Description

1 81Ui.Enable Input signal of enabling stage i of underfrequency protection (i=1~4)
2 81Ui.Block Input signal of blocking stage i of underfrequency protection (i=1~4)

Table 3.25-2 Output signals of underfrequency protection

No. Output Signal Description

1 81Ui.On Stage i of underfrequency protection is enabled. (i=1~4)
2 81Ui.Blocked Stage i of underfrequency protection is blocked. (i=1~4)
3 81Ui.Valid Stage i of underfrequency protection is valid. (i=1~4)
4 81Ui.St Stage i of underfrequency protection starts. (i=1~4)
5 81Ui.Op Stage i of underfrequency protection operates. (i=1~4)
6 81Ui.Alm Stage i of underfrequency protection alarms. (i=1~4)

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3.25.4 Logic

SET f<[81Ui.f_Set] & 81Ui.St

&
SET Upp_min>[81.Upp_Blk] [81Ui.t_Op] 0

SIG 81Ui.Pkp
&
81Ui.Alm
SET [81Ui.Opt_Trp/Alm]=Alm

&
81Ui.Op
SET [81Ui.Opt_Trp/Alm]=Trp

Figure 3.25-4 Logic of underfrequency protection

3
3.25.5 Settings
Table 3.25-3 Settings of underfrequency protection

Name Range Step Unit Default Description

The phase-to-phase voltage setting used to
81.Upp_Blk 10.000~150.000 0.001 V 70.000
block underfrequency protection
The frequency setting for stage i of
81Ui.f_Set 45.000~60.000 0.001 Hz 48.000
underfrequency protection (i=1~4)
The time delay for stage i of underfrequency
81Ui.t_Op 0.000~100.000 0.001 s 0.300
protection (i=1~4)
Disabled Enabling/disabling stage i of underfrequency
81Ui.En Enabled
Enabled protection (i=1~4)
Enabling/disabling stage i of underfrequency
Trp protection operate to trip or alarm (i=1~4)
81Ui.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

3.26 Frequency Rate-of-change Protection (81R)

Frequency rate-of-change reflects the balance of the generator′s output power and the active power
of the load. It can reflect the increase of active load power and the decrease of frequency. When
the frequency changes too fast, it is generally considered that the system has a fault, and the
frequency rate-of-change protection can operate in such a situation.

3.26.1 Function Description

The device can provide four stages of frequency rate-of-change protection. If the system frequency
rate-of-change is greater than the setting, frequency rate-of-change protection will operate.
Frequency rate-of-change protection is with independent definite-time characteristics and with
instantaneous dropout characteristics.

Frequency rate-of-change protection can operate to trip or alarm. For some specific applications,

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frequency rate-of-change protection needs to be blocked by the external signal, so the device
provides an input signal to be used to block frequency rate-of-change protection.

EN [81Ri.En] &
81Ri.On
SIG 81Ri.Enable
&
SIG 81Ri.Block >=1 81Ri.Blocked

SIG Fail_Device
&
81Ri.Valid

3
Figure 3.26-1 Logic of enabling frequency rate-of-change protection

The pickup logic of frequency rate-of-change protection is shown in Figure 3.26-2.

SIG [81Ri.df/dt_Set]>0
&
SET df/dt>[81Ri.df/dt_Set] >=1
SET Upp_min>[81.Upp_Blk]

SIG [81Ri.df/dt_Set]<0
&
SET df/dt<[81Ri.df/dt_Set]

SET Upp_min>[81.Upp_Blk]
&
0 500ms &
SIG 81Ri.On 81Ri.Pkp

SIG 81Ri.Valid
&
FD.Pkp
SET [81Ri.Opt_Trp/Alm]=Alm

Figure 3.26-2 Pickup logic of frequency rate-of-change protection

3.26.1.1 Operation Characteristics

The operating characteristics curve of frequency rate-of-change protection is shown in Figure

3.26-3.

[81Ri.t_Op]

-df/dt df/dt
-[81Ri.df/dt_Set] 0 [81Ri.df/dt_Set]

Figure 3.26-3 Definite-time operating curve of frequency rate-of-change protection

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Frequency rate-of-change protection supports definite-time characteristics complied with IEC

60255-3 and ANSI C37.112. If the absolute value of the system frequency rate-of-change is greater
than the absolute value of the setting [81Ri.df/dt_Set], frequency rate-of-change protection will
operate with a time delay [81Ri.t_Op].

3.26.1.2 Dropout Characteristics

Frequency rate-of-change protection is with instantaneous dropout characteristics. If the absolute

value of the system frequency rate-of-change is less than the absolute value of the setting
[81Ri.df/dt_Set], frequency rate-of-change protection will drop out immediately.

3.26.2 Function Block Diagram

3
81R

81Ri.Enable 81Ri.On

81Ri.Block 81Ri.Blocked

81Ri.Valid

81Ri.St

81Ri.Op

81Ri.Alm

3.26.3 I/O Signals

Table 3.26-1 Input signals of frequency rate-of-change protection

No. Input Signal Description

1 81Ri.Enable Input signal of enabling stage i of frequency rate-of-change protection (i=1~4)
2 81Ri.Block Input signal of blocking stage i of frequency rate-of-change protection (i=1~4)

Table 3.26-2 Output signals of frequency rate-of-change protection

No. Output Signal Description

1 81Ri.On Stage i of frequency rate-of-change protection is enabled. (i=1~4)
2 81Ri.Blocked Stage i of frequency rate-of-change protection is blocked. (i=1~4)
3 81Ri.Valid Stage i of frequency rate-of-change protection is valid. (i=1~4)
4 81Ri.St Stage i of frequency rate-of-change protection starts. (i=1~4)
5 81Ri.Op Stage i of frequency rate-of-change protection operates. (i=1~4)
6 81Ri.Alm Stage i of frequency rate-of-change protection alarms. (i=1~4)

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3.26.4 Logic

SIG [81Ri.df/dt_Set]>0
&
SET df/dt>[81Ri.df/dt_Set] &
SET Upp_min>[81.Upp_Blk]

SIG f>[81Ri.f_Pkp]

SIG [81Ri.df/dt_Set]<0
& >=1
SET df/dt<[81Ri.df/dt_Set] &

3
SET Upp_min>[81.Upp_Blk]
81Ri.St
SIG f<[81Ri.f_Pkp]
&
[81Ri.t_Op] 0
SIG 81Ri.Pkp
&
81Ri.Alm
SET [81Ri.Opt_Trp/Alm]=Alm

&
81Ri.Op
SET [81Ri.Opt_Trp/Alm]=Trp

Figure 3.26-4 Logic of frequency rate-of-change protection

3.26.5 Settings
Table 3.26-3 Settings of frequency rate-of-change protection

Name Range Step Unit Default Description

The phase-to-phase voltage setting used to
81.Upp_Blk 10.000~150.000 0.001 V 70.000
block frequency rate-of-change protection
The frequency rate-of-change setting for
81Ri.df/dt_Set -5.000~5.000 0.001 Hz/s 0.500 stage i of frequency rate-of-change
protection (i=1~4)
The time delay for stage i of frequency rate-
81Ri.t_Op 0.100~100.000 0.001 s 0.100
of-change protection (i=1~4)
The pickup frequency setting for stage i of
81Ri.f_Pkp 45.000~65.000 0.001 Hz 50.000
frequency rate-of-change protection (i=1~4)
Disabled Enabling/disabling stage i of frequency rate-
81Ri.En Enabled
Enabled of-change protection (i=1~4)
Enabling/disabling stage i of frequency rate-
of-change protection operate to trip or alarm
Trp
81Ri.Opt_Trp/Alm Trp (i=1~4)
Alm
Trp: for tripping purpose
Alm: for alarm purpose

3.27 Reverse Power Protection (32R)

If a power supply failure occurs on the feeder, the synchronous motors become generators due to

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the inertia of their load and the induction motors become generators. The aim of reverse power
protection is to detect the inverse flow of energy and to ensure that the motor does not feed the
fault which has appeared on the network.

3.27.1 Function Description

The device can provide two stages of reverse power protection. If the reverse power is detected
and it is greater than the setting, reverse power protection will operate. Reverse power protection
is with independent definite-time operating characteristics and with instantaneous dropout
characteristics. Reverse power protection can operate to trip or alarm. For some specific
applications, reverse power protection needs to be blocked by the external signal, so the device
provides an input signal to be used to block reverse power protection. 3
EN [32Ri.En] &
32Ri.On
SIG 32Ri.Enable
&
SIG 32Ri.Block >=1 32Ri.Blocked

SIG Fail_Device
&
32Ri.Valid

Figure 3.27-1 Logic of enabling reverse power protection

The pickup logic of reverse power protection is shown in Figure 3.27-2.

SET |P|>0.95×[32Ri.P_Set] &

SIG P<0

SET U1<[32Ri.U1_VCE] &

>=1 & 32Ri.Pkp
SET I1<[32Ri.I1_CCE] 0ms 500ms &
SET U2>[32Ri.U2_VCE]
&
FD.Pkp
SIG 32Ri.On

SIG 32Ri.Valid

SET [32Ri.Opt_Trp/Alm]=Alm

Figure 3.27-2 Pickup logic of reverse power protection

The power value is positive sequence power, P1 = 3×U1×I1×cosθ (θ is the phase angle between
positive-sequence voltage and positive-sequence current).

"I1" is the positive-sequence current.

"U1" is the positive-sequence voltage.

"U2" is the negative-sequence voltage.

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3.27.1.1 Operation Characteristics

Reverse power protection supports definite-time characteristics complied with IEC 60255-3 and
ANSI C37.112. If the power value is less than “0”, and the absolute power value is greater than the
setting [32Ri.P_Set], reverse power protection will operate with a time delay [32Ri.t_Op]. The
operating characteristics curve of reverse power protection is shown in Figure 3.27-3.

[32Ri.t_Op]

P1
[32Ri.P_Set] 0

Figure 3.27-3 Definite-time operating curve of reverse power protection

3.27.1.2 Dropout Characteristics

Reverse power protection is with instantaneous dropout characteristic. When the power is greater
than "0" or the power is less than the setting [32Ri.P_Set] multiplied by 0.95, reverse power
protection drops out immediately.

3.27.2 Function Block Diagram

32R

32Ri.Enable 32Ri.On

32Ri.Block 32Ri.Blocked

32Ri.Valid

32Ri.St

32Ri.Op

32Ri.Alm

3.27.3 I/O Signals

Table 3.27-1 Input signals of reverse power protection

No. Input Signal Description

1 32Ri.Enable Input signal of enabling stage i of reverse power protection (i=1 or 2)
2 32Ri.Block Input signal of blocking stage i of reverse power protection (i=1 or 2)

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Table 3.27-2 Output signals of reverse power protection

No. Output Signal Description

1 32Ri.On Stage i of reverse power protection is enabled. (i=1 or 2)
2 32Ri.Blocked Stage i of reverse power protection is blocked. (i=1 or 2)
3 32Ri.Valid Stage i of reverse power protection is valid. (i=1 or 2)
4 32Ri.St Stage i of reverse power protection starts. (i=1 or 2)
5 32Ri.Op Stage i of reverse power protection operates. (i=1 or 2)
6 32Ri.Alm Stage i of reverse power protection alarms. (i=1 or 2)

3.27.4 Logic
3
SET |P|>[32Ri.P_Set] &

SIG P<0

SET U1<[32Ri.U1_VCE] & 32Ri.St

>=1 &
SIG I1<[32Ri.I1_CCE] [32Ri.t_Op] 0

SIG U2>[32Ri.U2_VCE]

SIG 32Ri.Pkp
&
32Ri.Op
SET [32Ri.En_Alm]=Trp

&
32Ri.Alm
SET [32Ri.En_Alm]=Alm

Figure 3.27-4 Logic of reverse power protection

3.27.5 Settings
Table 3.27-3 Settings of reverse power protection

Name Range Step Unit Default Description

The positive-sequence voltage setting used to
32Ri.U1_VCE 5.000~60.000 0.001 V 5.000 block stage i of reverse power protection (i=1or
2)
The positive-sequence current setting used to
32Ri.I1_CCE 0.010~1.000 0.001 p.u. 0.100 block stage i of reverse power protection (i=1or
2)
The negative-sequence voltage setting used
32Ri.U2_VCE 8.000~60.000 0.001 V 8.000 to block stage i of reverse power protection
(i=1or 2)
The power setting for stage i of reverse power
32Ri.P_Set 0.100~10.000 0.001 p.u. 0.150
protection (i=1or 2)
The operating time delay for stage i of reverse
32Ri.t_Op 0.010~100.000 0.001 s 0.100
power protection (i=1or 2)

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Name Range Step Unit Default Description

Disabled Enabling/disabling stage i of reverse power
32Ri.En Enabled
Enabled protection (i=1 or 2)
Enabling/disabling stage i of reverse power
Trp protection operate to trip or alarm (i=1 or 2)
32Ri.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

3.28 Thermal Overload Protection (49P)

3 When the protected component (line or cable) operates under overload condition for a long time,
the continuous heat accumulation will cause the protected component's temperature increasing.
The insulation of the protected component will be damaged and the aging of the protected
component will be accelerated. If the temperature reaches too high values, the protected
component might be damaged. A thermal overload will often not be detected by other protection
functions and the introduction of the thermal overload protection can allow the protected circuit to
operate closer to the thermal limits. The increasing utilization of the power system closer to the
thermal limits has generated a need of a thermal overload protection for power lines.

3.28.1 Function Description

The device provides two methods to fulfill thermal overload protection, one is to calculate thermal
accumulation according the actual measured current, and the other is to calculate the protected
component's temperature according to the environmental medium temperature plus the
temperature difference.

1. Calculate thermal accumulation based on thermal model

Thermal overload protection calculates the overtemperature from the phase currents based on a
thermal model of the protected component (I2t characteristics) with the settable time constants
according to the IEC60255-8 standard. Two stages overload protection are available, each stage
can operate for alarm purpose and for trip purpose. An alarm level gives early warning to allow
operators to take action well before the line is tripped. Thermal accumulation can be cleared by
external input signal via the signal "49P1.Clr". There are two types of characteristics, cold start
characteristic and hot start characteristic. The corresponding equations are shown as below.

1. Cold start characteristic:

𝐼 [49Pi.Alpha_Cold]
𝑇 = 𝜏 × 𝑙𝑛
𝐼 [49Pi.Alpha_Cold] − (𝐾 × [49𝑃𝑖. 𝐼𝑏_𝑆𝑒𝑡])[49𝑃𝑖.𝐴𝑙𝑝ℎ𝑎_𝐶𝑜𝑙𝑑]

2. Hot start characteristic:

[49Pi.Alpha_Cold]
𝐼 [49Pi.Alpha_Cold] − 𝐼𝑃
𝑇 = 𝜏 × 𝑙𝑛
𝐼 [49Pi.Alpha_Cold] − (𝐾 × [49𝑃𝑖. 𝐼𝑏_𝑆𝑒𝑡])[49𝑃𝑖.𝐴𝑙𝑝ℎ𝑎_𝐶𝑜𝑙𝑑]

T is the theoretical operating time.

𝜏 is the thermal time constant of the protected component, the setting [49Pi.Tau]. When the current

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is smaller than 0.04In, the thermal time constant adopts the value of [49Pi.Tau] × [49Pi.C_Disspt].

I is the equivalent heating current, i.e. actual measured current.

IP is the steady-state load current prior to the overload for a duration which would result in constant
thermal level (duration is greater than several time constant τ), which is memory current. For cold
start characteristic, it is zero.

k is thermal overload coefficient, the setting [49Pi.K_Alm] or [49Pi.K_Trp].

ln is natural logarithm.

3
IP
The characteristic curve of thermal overload model is shown in Figure 3.28-1. (P = )
[49Pi.Ib_Set]

P=0
P=0.6

I
KIB

Figure 3.28-1 Characteristic curve of thermal overload model

The device adopts the hot start characteristics. The calculation is carried out when Ip=0, so the
value of Ip is not required to be set. The tripping output of thermal overload protection is controlled
by the current, even if the value of thermal accumulation is greater than the setting [49Pi.K_Trp],
thermal overload protection drops off instantaneously when the current disappears. The alarm
output of thermal overload protection is not controlled by the current, and only if the value of thermal
accumulation is greater than the setting [49Pi.K_Alm], the alarm signal will be issued. The alarm
signal can be used to block AR.

EN [49Pi.En_Trp] >=1
&
EN [49Pi.En_Alm] 49Pi.On

SIG 49Pi.Enable
&
SIG 49Pi.Block >=1 49Pi.Blocked

SIG Fail_Device
&
49Pi.Valid

Figure 3.28-2 Logic of enabling thermal overload protection

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SIG Max(Ia, Ib, Ic)

SET [49Pi.Ib_Set]
&
0 500ms &
SIG 49Pi.On 49Pi.Pkp/FD.Pkp

SIG 49Pi.Valid

Figure 3.28-3 Pickup logic of thermal overload protection

SIG 49Pi.Pkp
&
3 SIG Ia 49Pi.StA

& Timer
SET [49Pi.Ib_Set] t
49Pi.Alm.PhA
t
EN [49Pi.En_Alm]

& Timer
t
49Pi.Op.PhA
t
EN [49Pi.En_Trp]

SIG 49Pi.Clr

Figure 3.28-4 Logic of thermal overload protection (phase A)

SIG 49Pi.StA
>=1
SIG 49Pi.StB 49Pi.St

SIG 49Pi.StC

SIG 49Pi.Alm.PhA
>=1
SIG 49Pi.Alm.PhB 49Pi.Alm

SIG 49Pi.Alm.PhC

SIG 49Pi.Op.PhA
>=1
SIG 49Pi.Op.PhB 49Pi.Op

SIG 49Pi.Op.PhC

Figure 3.28-5 Logic of thermal overload protection

2. Calculate the protected component's temperature

T=T1+T_Diff

T is the protected component's temperature.

T1 is the environmental medium temperature.

T_Diff is the temperature difference between the protected component's temperature and the
environmental medium temperature.

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T1 can be acquired by external transducer (for example, Pt100) or GOOSE signal. T_Diff can be
calculated according to the measured current, and it is changed with the current. When the current
is increased from 0 to I, the temperature accumulation complies with the following equation.

𝐼 −𝑡
𝑇_𝐷𝑖𝑓𝑓 = [49𝑃𝑖. 𝐾_𝑇_𝐷𝑖𝑓𝑓] × ( )[49Pi.Alpha_Cold] × (1 − 𝑒 [49𝑃𝑖.𝑇𝑎𝑢] )
[49𝑃𝑖. 𝐼𝑏_𝑆𝑒𝑡]

Finally, the stable temperature difference:

𝐼
𝑇_𝐷𝑖𝑓𝑓 = [49𝑃𝑖. 𝐾_𝑇_𝐷𝑖𝑓𝑓] × ( )[49Pi.Alpha_Cold]
[49𝑃𝑖. 𝐼𝑏_𝑆𝑒𝑡]

I is the measured current.

3
Based on the calculated protected component's temperature, the user can compare it with user-
defined temperature threshold value to trip or alarm with/without the time delay by PCS-Studio. If
the second method is not used, the corresponding settings should be set as default value.

3.28.2 Function Block Diagram

49P

49Pi.Clr 49Pi.Accu_A

49Pi.Enable 49Pi.Accu_B

49Pi.Block 49Pi.Accu_C

49Pi.T_Diff_A

49Pi.T_Diff_B

49Pi.T_Diff_C

49Pi.St

49Pi.StA

49Pi.StB

49Pi.StC

49Pi.Op

49Pi.Op.PhA

49Pi.Op.PhB

49Pi.Op.PhC

49Pi.On

49Pi.Blocked

49Pi.Valid

49Pi.Alm

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3.28.3 I/O Signals

Table 3.28-1 Input signals of thermal overload protection

No. Input Signal Description

1 49Pi.Clr Input signal of clear thermal accumulation
2 49Pi.Enable Input signal of enabling thermal overload protection
3 49Pi.Block Input signal of blocking thermal overload protection

Table 3.28-2 Output signals of thermal overload protection

No. Output Signal Description

3 1 49Pi.Accu_A The thermal accumulation (Phase A)
2 49Pi.Accu_B The thermal accumulation (Phase B)
3 49Pi.Accu_C The thermal accumulation (Phase C)
The calculated temperature difference between the protected component's
4 49Pi.T_Diff_A
temperature and the environmental medium temperature (Phase A)
The calculated temperature difference between the protected component's
5 49Pi.T_Diff_B
temperature and the environmental medium temperature (Phase B)
The calculated temperature difference between the protected component's
6 49Pi.T_Diff_C
temperature and the environmental medium temperature (Phase C)
7 49Pi.St Thermal overload protection starts.
8 49Pi.StA Thermal overload protection starts. (Phase A)
9 49Pi.StB Thermal overload protection starts. (Phase B)
10 49Pi.StC Thermal overload protection starts. (Phase C)
11 49Pi.Op Thermal overload protection operates.
12 49Pi.Op.PhA Thermal overload protection operates. (Phase A)
13 49Pi.Op.PhB Thermal overload protection operates. (Phase B)
14 49Pi.Op.PhC Thermal overload protection operates. (Phase C)
15 49Pi.On Thermal overload protection is enabled.
16 49Pi.Blocked Thermal overload protection is blocked.
17 49Pi.Valid Thermal overload protection is valid.
18 49Pi.Alm Thermal overload protection alarms.

3.28.4 Settings
Table 3.28-3 Settings of thermal overload protection

Name Range Step Unit Default Description

Base current setting for stage i of
49Pi.Ib_Set 0.050~200.000 0.001 A 15.000
thermal overload protection (i=1 or 2)
The tripping factor setting of thermal
49Pi.K_Trp 1.000~3.000 0.001 1.200 capacity for stage i of thermal
overload protection (i=1, 2)
The alarm factor setting of thermal
49Pi.K_Alm 1.000~3.000 0.001 1.100 capacity for stage i of thermal
overload protection (i=1, 2)

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Name Range Step Unit Default Description

The time constant setting of the
49Pi.Tau 0.100~100.000 0.001 min 1.000 thermal model for stage i of thermal
overload protection (i=1 or 2)
The convertor coefficient from the
current to the temperature for stage i
49Pi.K_T_Diff 0.000~200.000 0.001 30.000
of thermal overload protection (i=1 or
2)
The cooling mode setting for stage i
of thermal overload protection (i=1 or

49Pi.Alpha_Cold 1.000~2.000 0.001 2.000

2) 3
Usually, for different cooling mode
Natural cooling: 1.6
Forced cooling: 2
The time constant of heat dissipation
for stage i of thermal overload
protection (i=1 or 2)
49Pi.C_Disspt 0.100~10.000 0.001 1.000 When the equivalent heating current
is lower than 0.04In, the thermal time
constant adopts the value of
[49Pi.Tau]×[49Pi.C_Disspt].
Enabling/disabling stage i of thermal
Disabled
49Pi.En_Trp Disabled overload protection operate to trip
Enabled
(i=1 or 2)
Enabling/disabling stage i of thermal
Disabled
49Pi.En_Alm Disabled overload protection operate to alarm
Enabled
(i=1 or 2)
The option to maintain or dissipate
Maintain the data in case of SV measurement
49Pi.Opt_Accu_CurreLos Dissipate
Dissipate abonormality for stage i of thermal
overload protection

3.29 Undercurrent Protection (37)

Undercurrent protection can isolate the fault from the system by detecting the smaller load current
when the load is lost, the capacitor is in loss of voltage and the motor is running without any load.

3.29.1 Function Description

The device can provide one stage of undercurrent protection for tripping purpose or alarm purpose.
For different protected equipment, single-phase criterion or three-phase criterion can be selected.
The circuit breaker position and the load current also can be taken as the enabling conditions of
undercurrent protection. Undercurrent protection is with definite-time operating characteristics and
instantaneous dropout characteristics. Undercurrent protection can operate to trip or alarm. For

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 3 Protection Functions

some specific applications, undercurrent protection needs to be blocked by the external signal, so
the device provides an input signal to be used to block undercurrent protection.

EN [37.En] &
37.On
SIG 37.Enable
&
SIG 37.Block >=1 37.Blocked

SIG Fail_Device
&
37.Valid

3
Figure 3.29-1 Logic of enabling undercurrent protection

SIG Ia<1.10×[37.I_Set]
>=1
SIG Ib<1.10×[37.I_Set] &
SIG Ic<1.10×[37.I_Set]
>=1
Current criterion
SET [37.Opt_1P/3P]=1P

SIG Ia<1.10×[37.I_Set]
&
SIG Ib<1.10×[37.I_Set] &
SIG Ic<1.10×[37.I_Set]

SET [37.Opt_1P/3P]=3P

SET [37.Opt_LogicMode]=None

SET [37.Opt_LogicMode]=Curr & >=1

>=1
SIG Ip>0.04In Auxiliary criterion

SET [37.Opt_LogicMode]=CBPos &

SIG CB closed position

>=1
&
>=1
SET [37.Opt_LogicMode]=CurrOrCBPos

&
&

SET [37.Opt_LogicMode]=CurrAndCBPos

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SIG Current criterion

& 37.Pkp
SIG Auxiliary criterion 0 500ms &
SIG 37.On
&
FD.Pkp
SIG 37.Valid

SET [37.Opt_Trp/Alm]=Alm

Figure 3.29-2 Pickup logic of undercurrent protection

"1-out-of-3" or "3-out-of-3" logic can be selected for the protection criterion. (1-out-of-3 means any
of three phase currents, 3-out-of-3 means all three phase currents). The circuit breaker position
with/without the current condition can be as an auxiliary criterion for undercurrent protection, which
3
can be configured via the setting [37.Opt_LogicMode]. The pickup logic of undercurrent protection
is shown in Figure 3.29-2.

3.29.1.1 Operation Characteristics

Undercurrent protection supports definite-time characteristics complied with IEC 60255-3 and ANSI
C37.112. If the load current is less than the setting [37.I_Set], undercurrent protection will operate
with a time delay [37.t_Op].

The operating characteristics curve of undercurrent protection is shown in Figure 3.29-3.

[37.t_Op]

[37.T_Set]
I

Figure 3.29-3 Definite-time operating curve of undercurrent protection

3.29.1.2 Dropout Characteristics

Undercurrent protection is with instantaneous dropout characteristics. If the load current is greater
than the setting [37.I_Set] multiplied by 1.10, undercurrent protection will drop out immediately.

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3.29.2 Function Block Diagram

37

37.Enable 37.On

37.Block 37.Blocked

37.Valid

37.St

37.StA

3 37.StB

37.StC

37.Op

37.Op.PhA

37.Op.PhB

37.Op.PhC

37.Alm

3.29.3 I/O Signals

Table 3.29-1 Input signals of undercurrent protection

No. Input Signal Description

1 37.Enable Input signal of enabling undercurrent protection
2 37.Block Input signal of blocking undercurrent protection

Table 3.29-2 Output signals of undercurrent protection

No. Output Signal Description

1 37.On Undercurrent protection is enabled.
2 37.Blocked Undercurrent protection is blocked.
3 37.Valid Undercurrent protection is valid.
4 37.St Undercurrent protection starts.
5 37.StA Undercurrent protection starts. (Phase A)
6 37.StB Undercurrent protection starts. (Phase B)
7 37.StC Undercurrent protection starts. (Phase C)
8 37.Op Undercurrent protection operates.
9 37.Op.PhA Undercurrent protection operates. (Phase A)
10 37.Op.PhB Undercurrent protection operates. (Phase B)
11 37.Op.PhC Undercurrent protection operates. (Phase C)
12 37.Alm Undercurrent protection alarms.

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3.29.4 Logic

SIG Ia<[37.I_Set]
>=1
SIG Ib<[37.I_Set] &
SIG Ic<[37.I_Set]
>=1

SET [37.Opt_1P/3P]=1P

SIG Ia<[37.I_Set]
&
SIG Ib<[37.I_Set] &
SIG Ic<[37.I_Set]

SET [37.Opt_1P/3P]=3P
3
& 37.St
SIG Auxiliary criterion &
[37.t_Op] 0
SIG 37.On

SIG 37.Pkp
&
37.Op
SET [37.Opt_Trp/Alm]=Trp

&
37.Alm
SET [37.Opt_Trp/Alm]=Alm

Figure 3.29-4 Logic of undercurrent protection

3.29.5 Settings
Table 3.29-3 Settings of undercurrent protection

Name Range Step Unit Default Description

The current setting of undercurrent
37.I_Set (0.100~1.000)×In 0.001 A 0.500
protection
The time delay of undercurrent
37.t_Op 0.100~100.000 0.001 s 0.100
protection
The option of the current criterion
1P used by undercurrent protection
37.Opt_1P/3P 3P
3P 3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of auxiliary criterion
mode for undercurrent protection
None: no check
None
Curr: check current condition
Curr
CBPos: check normally open
37.Opt_LogicMode CBPos CurrAndCBPos
auxiliary contact
CurrOrCBPos
CurrOrCBPos: check current
CurrAndCBPos
condition or normally open auxiliary
contact
CurrAndCBPos: check current

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 3 Protection Functions

Name Range Step Unit Default Description

condition and normally open
auxiliary contact
Disabled Enabling/disabling undercurrent
37.En Enabled
Enabled protection
Enabling/disabling undercurrent
Trp protection operate to trip or alarm
37.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

3 3.30 Breaker Failure Protection (50BF)

When a fault happens to the power system, the device will operate to trip the circuit breaker, and
the fault will be isolated by opening the circuit breaker. If the circuit breaker fails to open within the
certain time due to some reasons (for example, low tripping pressure), the fault may cause system
stability being destroyed or electrical equipment being damaged. Breaker failure protection is
adopted to issue a backup tripping command to trip adjacent circuit breakers, and isolate the fault
as requested by the device.

According to the tripping information from the device and the auxiliary information (the current and
the circuit breaker position) of target circuit breaker, breaker failure protection constitutes the
criterion to discriminate whether the target circuit fails to open. If the criterion is confirmed, breaker
failure protection will operate to trip the target circuit breaker with the time delay
[CBx.50BF.t_ReTrp], trip it again with the time delay [CBx.50BF.t1_Op] and trip the adjacent circuit
breakers with the time delay [CBx.50BF.t2_Op]. As a special backup protection, breaker failure
protection can quickly isolate the fault, reduce the affected range by the fault, keep system stability
and prevent generators, transformers and other primary equipment from seriously damaged.

For double circuit breakers mode, the device will provide independent
breaker failure protection for CB1 and CB2 respectively. Both breaker failure
protections have the same logic. The difference is that the prefix “CBx.” is
added to all signals and settings for circuit breaker No.x (x=1 or 2).

3.30.1 Function Description

Breaker failure protection can be current-based, contact-based or an adaptive combination of these

two conditions. Contact check criteria can be used where the fault current through the breaker is
small. The current check criterion and the contact check criterion can be flexibly set by the settings
[CBx.50BF.Opt_LogicMode]. When both criterions are enabled, the current check criterion is prior
to the contact check criterion.

3.30.1.1 Current Check Criterion

The current check criterion includes three kinds of current elements: phase overcurrent element,

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zero-sequence overcurrent element and negative-sequence overcurrent element.

1. Phase overcurrent element

𝐼𝜑 > [𝐶𝐵𝑥. 50𝐵𝐹. 𝐼_𝑆𝑒𝑡]

φ = A, B or C

The phase overcurrent element can be enabled or disabled by the setting [CBx.50BF.En_Ip]. For
single-phase initiating logic, if corresponding phase current is larger than the setting
[CBx.50BF.I_Set], the current check criterion based on phase overcurrent element meets the
condition. For three-phase initiating logic, if any phase current is larger than the setting
[CBx.50BF.I_Set], the current check criterion based on phase overcurrent element meets the
condition.
3
2. Zero-sequence overcurrent element

3𝐼0 > [𝐶𝐵𝑥. 50𝐵𝐹. 3𝐼0_𝑆𝑒𝑡]

3I0 is calculated residual current

The zero-sequence overcurrent element can be enabled or disabled by the setting

[CBx.50BF.En_3I0_1P] via single-phase initiating signal or [CBx.50BF.En_3I0_3P] via three-phase
initiating signal. The zero-sequence overcurrent element can improve the reliability and the
sensitivity. if residual current is larger than the setting [CBx.50BF.3I0_Set], the current check
criterion based on zero-sequence overcurrent element meets the condition.

3. Negative-sequence overcurrent element

𝐼2 > [𝐶𝐵𝑥. 50𝐵𝐹. 𝐼2_𝑆𝑒𝑡]

I2 is negative-sequence current

The negative-sequence overcurrent element can be enabled or disabled by the setting

[CBx.50BF.En_I2_3P]. The negative-sequence overcurrent element can improve the reliability and
the sensitivity. If negative-sequence current is larger than the setting [CBx.50BF.I2_Set], the current
check criterion based on negative-sequence overcurrent element meets the condition.

3.30.1.2 Contact Check Criterion

For single-phase initiating logic, if corresponding phase circuit breaker is in closed position, the
contact check criterion meets the condition. For three-phase initiating logic, if any phase circuit
breaker is in closed position, the contact check criterion meets the condition.

3.30.1.3 Operating Characteristics

For breaker failure protection, phase-segregated re-trip, two phases inter-trip three phases, three-
phase re-trip and two time delays are available.

1. Phase-segregated re-trip

For phase-segregated tripping system, breaker failure protection provides phase-segregated re-
trip function. When breaker failure protection receives initiating signal of phase-segregated tripping

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and the current check criterion or the contact check criterion meets the condition, the device will
issue phase-segregated tripping command to re-trip the target circuit breaker with the time delay
[CBx.50BF.t_ReTrp]. In order to avoid undesired operating of breaker failure protection and reduce
the affected range, phase-segregated re-trip does not block AR.

When the re-tripping is initiated by two-phase failure, two phase inter-trip three-phases operates to
trip three-phase circuit breaker. When the re-tripping is initiated by three-phase failure, three-phase
re-trip operates to trip three-phase circuit breaker.

2. Three-phase re-trip

For non phase-segregated tripping system, breaker failure protection provides three-phases re-trip
3 function. When breaker failure protection receives initiating signal of three-phases tripping and the
current check criterion or the contact check criterion meets the condition, the device will issue three-
phases tripping command to re-trip the target circuit breaker with the time delay
[CBx.50BF.t_ReTrp]. In order to avoid undesired operating of breaker failure protection and reduce
the affected range, three-phase re-trip does not block AR.

3. First time delay

As similar as three-phase re-trip, the device will operate to re-trip the target circuit breaker again
with the time delay [CBx.50BF.t1_Op] when the relevant operating criterion is satisfied. It can be
enabled by the setting [CBx.50BF.En_t1].

4. Second time delay

As similar as three-phase re-trip, the device will operate to trip the adjacent circuit breakers with
the time delay [CBx.50BF.t2_Op] when the relevant operating criterion is satisfied. It can be enabled
by the setting [CBx.50BF.En_t2].

In addition, breaker failure protection provides an independent initiating function via the circuit
breaker position. The input signal "CBx.50BF.ExTrp_WOI" is energized, normally closed auxiliary
contact of the circuit breaker is chosen to trigger the timer of breaker failure protection. When the
initiating signal of breaker failure protection is energized for longer than 10s, an alarm signal
"CBx.50BF.Alm_Init" will be issued, and will drop out with a time delay of 10s.

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3.30.2 Function Block Diagram

50BF

CBx.50BF.Enable CBx.50BF.On

CBx.50BF.Block CBx.50BF.Blocked

CBx.50BF.ExTrpA CBx.50BF.Valid

CBx.50BF.ExTrpB CBx.50BF.St

CBx.50BF.ExTrpC CBx.50BF.StA

CBx.50BF.ExTrp3P CBx.50BF.StB 3
CBx.50BF.ExTrp_WOI CBx.50BF.StC

CBx.50BF.52b_PhA CBx.50BF.Op_ReTrpA

CBx.50BF.52b_PhB CBx.50BF.Op_ReTrpB

CBx.50BF.52b_PhC CBx.50BF.Op_ReTrpC

CBx.50BF.Op_ReTrp3P

CBx.50BF.Op_t1

CBx.50BF.Op_t2

CBx.50BF.Alm_Init

3.30.3 I/O Signals

Table 3.30-1 Input signals of breaker failure protection

No. Input Signal Description

1 CBx.50BF.Enable Input signal of enabling breaker failure protection
2 CBx.50BF.Block Input signal of blocking breaker failure protection
3 CBx.50BF.ExTrpA Input signal of initiating breaker failure protection (phase-A)
4 CBx.50BF.ExTrpB Input signal of initiating breaker failure protection (phase-B)
5 CBx.50BF.ExTrpC Input signal of initiating breaker failure protection (phase-C)
6 CBx.50BF.ExTrp3P Input signal of initiating breaker failure protection (three-phases)
Input signal of initiating breaker failure protection with the position check of
7 CBx.50BF.ExTrp_WOI
the circuit breaker
8 CBx.50BF.52b_PhA Input signal of CB open position (phase-A)
9 CBx.50BF.52b_PhB Input signal of CB open position (phase-B)
10 CBx.50BF.52b_PhC Input signal of CB open position (phase-C)

Table 3.30-2 Output signals of breaker failure protection

No. Output Signal Description

1 CBx.50BF.On Breaker failure protection is enabled.
2 CBx.50BF.Blocked Breaker failure protection is blocked.

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3 CBx.50BF.Valid Breaker failure protection is valid.

4 CBx.50BF.StA Breaker failure protection starts (phase-A).
5 CBx.50BF.StB Breaker failure protection starts (phase-B).
6 CBx.50BF.StC Breaker failure protection starts (phase-C).
7 CBx.50BF.St Breaker failure protection starts. (three-phases)
8 CBx.50BF.Op_ReTrpA Breaker failure protection operates to re-trip phase-A circuit breaker.
9 CBx.50BF.Op_ReTrpB Breaker failure protection operates to re-trip phase-B circuit breaker.
10 CBx.50BF.Op_ReTrpC Breaker failure protection operates to re-trip phase-C circuit breaker.
11 CBx.50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phases circuit breaker.
12 CBx.50BF.Op_t1 Breaker failure protection operates with the time delay [CBx.50BF.t1_Op].
3 13 CBx.50BF.Op_t2 Breaker failure protection operates with the time delay [CBx.50BF.t2_Op].
14 CBx.50BF.Alm_Init The initiating signal of breaker failure protection is abnormal.

3.30.4 Logic

EN [CBx.50BF.En] &
CBx.50BF.On
SIG CBx.50BF.Enable
&
SIG CBx.50BF.Block >=1 CBx.50BF.Blocked

SIG Fail_Device
&
CBx.50BF.Valid

Figure 3.30-1 Logic of enabling breaker failure protection

EN [CBx.50BF.En_InTrp_Init] &
CBx.50BF.InTrpA
SIG CBx.BFI_A

&
CBx.50BF.InTrpB
SIG CBx.BFI_B

&
CBx.50BF.InTrpC
SIG CBx.BFI_C

Figure 3.30-2 Breaker failure initiating logic by internal tripping

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SIG CBx.50BF.InTrpA 10s 10s

>=1
SIG CBx.50BF.InTrpB 10s 10s

SIG CBx.50BF.InTrpC 10s 10s

SIG CBx.50BF.ExTrpA 10s 10s

>=1
SIG CBx.50BF.ExTrpB 10s 10s

SIG CBx.50BF.ExTrpC 10s 10s >=1

>=1
SIG CBx.50BF.ExTrp3P 10s 10s

3
SIG CBx.50BF.ExTrp_WOI 10s 10s
&
EN [CBx.50BF.En_Alm_Init] CBx.50BF.Alm_Init

SIG CBx.50BF.Valid

Figure 3.30-3 Logic of breaker failure initiating signal abnormality

EN [CBx.50BF.En_3I0_1P] >=1
&
SET 3I0>[CBx.50BF.3I0_Set]

SET IA (B, C) >[CBx.50BF.I_Set]

&

SET [CBx.50BF.Opt_LogicMode]=Curr

SET [CBx.50BF.Opt_LogicMode]=CBPos & >=1

Current/Contact check
(A, B, C)
SIG CBx.50BF.52b_PhA (B, C)

SET [CBx.50BF.Opt_LogicMode]=CurrAndCBPos &

EN [CBx.50BF.En_3I0_1P] >=1
& >=1
SET 3I0>[CBx.50BF.3I0_Set] &
SET IA (B, C) >[CBx.50BF.I_Set]
&

SIG CBx.50BF.52b_PhA (B, C)

Figure 3.30-4 Logic of current/contact check (phase-segregated)

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SET [CBx.50BF.Opt_LogicMode]=Curr &

SET [CBx.50BF.Opt_LogicMode]=CBPos &

SIG CBx.50BF.52b_PhA
& >=1
SIG CBx.50BF.52b_PhB Current/Contact check

SIG CBx.50BF.52b_PhC

SIG IA>[CBx.50BF.I_Set]
&
>=1 >=1
3 SIG IB>[CBx.50BF.I_Set]

&
SIG IC>[CBx.50BF.I_Set]
&

SET [CBx.50BF.Opt_LogicMode]=CurrAndCBPos

Figure 3.30-5 Logic of current/contact check (three-phase)

SIG CBx.50BF.Valid &

&
SIG CBx.50BF.Alm_Init

EN [CBx.50BF.En_ReTrp]
&
SIG Current/Contact check (A) & [CBx.50BF.t_ReTrp] 0 CBx.50BF.Op_ReTrpA

CBx.50BF.StA

&
SIG Current/Contact check (B) & [CBx.50BF.t_ReTrp] 0 CBx.50BF.Op_ReTrpB

CBx.50BF.StB
&
SIG Current/Contact check (C) & [CBx.50BF.t_ReTrp] 0 CBx.50BF.Op_ReTrpC

CBx.50BF.StC
SIG CBx.50BF.ExTrpA >=1
>=2 &
>=1 [CBx.50BF.t_ReTrp] 0 CBx.50BF.Op_ReTrp3P
SIG CBx.50BF.InTrpA

SIG CBx.50BF.ExTrpB >=1 & >=1

>=1 CBx.50BF.St
SIG CBx.50BF_InTrpB
>=1

SIG CBx.50BF.ExTrpC >=1

SIG CBx.50BF_InTrpC
&
SIG Current/Contact check

EN [CBx.50BF.En_Ip]
&
[CBx.50BF.t1_Op] 0 CBx.50BF.Op_t1
EN [CBx.50BF.En_t1]

&
[CBx.50BF.t2_Op] 0 CBx.50BF.Op_t2
EN [CBx.50BF.En_t2]

Figure 3.30-6 Logic of breaker failure protection (phase-segregated)

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SIG CBx.50BF.Valid &

SIG CBx.50BF.Alm_Init
&
EN [CBx.50BF.En_ReTrp] [CBx.50BF.t_ReTrp] 0 CBx.50BF.Op_ReTrp3P

SIG CBx.50BF.ExTrp3P
&
SIG Current/Contact check

EN [CBx.50BF.En_Ip]

SIG CBx.50BF.ExTrp3P
&
EN [CBx.50BF.En_3I0_3P] &
>=1
3
SET 3I0>[CBx.50BF.3I0_Set]
& >=1 &
EN [CBx.50BF.En_I2_3P] & [CBx.50BF.t1_Op] 0 CBx.50BF.Op_t1

SET I2>[CBx.50BF.I2_Set]

SIG CBx.50BF.ExTrp_WOI
& >=1
EN [CBx.50BF.En_CB_Ctrl] CBx.50BF.St

SIG CBx.50BF.52b_PhA
&
SIG CBx.50BF.52b_PhB

SIG CBx.50BF.52b_PhC

EN [CBx.50BF.En_t1]
&
[CBx.50BF.t2_Op] 0 CBx.50BF.Op_t2
EN [CBx.50BF.En_t2]

Figure 3.30-7 Logic of breaker failure protection (three-phase)

3.30.5 Settings
Table 3.30-3 Settings of breaker failure protection

Name Range Step Unit Default Description

The phase current setting of
CBx.50BF.I_Set (0.050~40.000)×In 0.001 A 1.000
breaker failure protection
The zero-sequence current
CBx.50BF.3I0_Set (0.050~40.000)×In 0.001 A 1.000 setting of breaker failure
protection
The negative-sequence current
CBx.50BF.I2_Set (0.050~40.000)×In 0.001 A 1.000 setting of breaker failure
protection
The re-trip time delay of breaker
CBx.50BF.t_ReTrp 0.000~20.000 0.001 s 0.050
failure protection
The first time delay of breaker
CBx.50BF.t1_Op 0.000~20.000 0.001 s 0.100
failure protection
The second time delay of breaker
CBx.50BF.t2_Op 0.000~20.000 0.001 s 0.200
failure protection
Disabled Enabling/disabling breaker failure
CBx.50BF.En Enabled
Enabled protection
CBx.50BF.En_ReTrp Disabled Enabled Enabling/disabling re-trip function

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 3 Protection Functions

Name Range Step Unit Default Description

Enabled of breaker failure protection
Disabled Enabling/disabling first time delay
CBx.50BF.En_t1 Disabled
Enabled of breaker failure protection
Disabled Enabling/disabling second time
CBx.50BF.En_t2 Disabled
Enabled delay of breaker failure protection
Enabling/disabling zero-
Disabled sequence overcurrent element of
CBx.50BF.En_3I0_1P Disabled
Enabled breaker failure protection via
single-phase initiating signal

3 Enabling/disabling phase
Disabled overcurrent element of breaker
CBx.50BF.En_Ip Disabled
Enabled failure protection via three-
phases initiating signal
Enabling/disabling zero-
Disabled sequence overcurrent element of
CBx.50BF.En_3I0_3P Disabled
Enabled breaker failure protection via
three-phases initiating signal
Enabling/disabling negative-
Disabled sequence overcurrent element of
CBx.50BF.En_I2_3P Disabled
Enabled breaker failure protection via
three-phases initiating signal
Enabling/disabling breaker failure
Disabled
CBx.50BF.En_CB_Ctrl Disabled protection be initiated by normally
Enabled
closed contact of circuit breaker
Enabling/disabling abnormality
Disabled
CBx.50BF.En_Alm_Init Disabled check of breaker failure initiating
Enabled
signal
Breaker failure check mode
None: no check
None Curr: check the current
Curr CBPos: check the normally open
CBx.50BF.Opt_LogicMode Curr
CBPos auxiliary contact
CurrAndCBPos CurrAndCBPos: check the
current and normally open
auxiliary contact
Enabling/disabling breaker failure
Disabled
CBx.50BF.En_InTrp_Init Enabled protection be initiated by internal
Enabled
tripping

3.31 Stub Differential Protection (87STB)

Stub differential protection is mainly designed for one and a half breakers arrangement. When line

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disconnector is open and transmission line is put into maintenance, line VT is no voltage. Distance
protection is disabled, and stub differential protection is enabled. It is used to protect stub section
among two circuit breakers and line disconnector. Usually, stub differential protection is enabled
automatically by normally closed auxiliary contact of line disconnector. When CT ratio at both sides
is inconsistent, CT ratio of CB2 will be converted on the basis of CT ratio of CB2.

52

CT

3
CT

52
PCS-931S

52

Figure 3.31-1 Application for one-and-half circuit breakers

3.31.1 Function Description

3.31.1.1 Stub Differential Element

Stub differential element is composed of percentage differential principle. Stub differential element can
be controlled by normally closed auxiliary contact of line disconnector to enabled or disabled. The
normally closed auxiliary contact of line disconnector is closed when line disconnector is open. The
operation criterion is:
• •
|𝐼𝜑1 + 𝐼𝜑2 | > [87𝑆𝑇𝐵. 𝐼_𝑃𝑘𝑝]
{• • • •
|𝐼𝜑1 + 𝐼𝜑2 | > [87𝑆𝑇𝐵. 𝑆𝑙𝑜𝑝𝑒] × |𝐼𝜑1 − 𝐼𝜑2 |

• •
𝐼𝜑1, 𝐼𝜑2 are secondary phase currents corresponding to both circuit breakers, are formed by phase

A, B, C

3.31.1.2 Differential Current Alarm

Under normal conditions, when stub differential protection is enabled, the device will issue the
alarm signal [87STB.Alm_Diff] with a time delay of 10s if the following operation criterion is met.
When the abnormality disappears, the alarm signal drops off with a time delay of 10s.

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 3 Protection Functions
• •
|𝐼𝜑1 + 𝐼𝜑2 | > [87𝑆𝑇𝐵. 𝐼_𝐴𝑙𝑚]
{• • • •
|𝐼𝜑1 + 𝐼𝜑2 | > 0.15 × |𝐼𝜑1 − 𝐼𝜑2|

3.31.1.3 Disconnector Position Alarm

The device will issue the alarm signal [87STB.Alm_89b_DS] with the time delay of 10s if the signal
[87STB.89b_DS] is energized and the line is live, and the alarm signal will drop off with the time
delay of 10s after the abnormality disappears. When the alarm signal of disconnector position
appears, the disconnector position is considered as invalid stub differential protection and
differential current alarm will be blocked.
3 3.31.1.4 CT Saturation

When there is an external fault, transient CT saturation may be happened. In order to prevent stub
differential protection from undesired operation due to the serious saturation, the floating
technology of adaptive restraint current is adopted.

3.31.2 Function Block Diagram

87STB

87STB.Enable 87STB.On

87STB.Block 87STB.Blocked

87STB.89b_DS 87STB.Valid

87STB.89b_DS_Rmt 87STB.Active

87STB.Op

87STB.St

87STB.StA

87STB.StB

87STB.StC

87STB.Op.PhsA

87STB.Op.PhsB

87STB.Op.PhsC

87STB.Alm_Diff

87STB.Alm_89b_DS

3.31.3 I/O Signals

Table 3.31-1 Input signals of stub differential protection

No. Input Signal Description

1 87STB.Enable Input signal of enabling stub differential protection

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2 87STB.Block Input signal of blocking stub differential protection

3 87STB.89b_DS Normally closed auxiliary contact of line disconnector
4 87STB.89b_DS_Rmt Normally closed auxiliary contact of line disconnector in the opposite end.

Table 3.31-2 Output signals of stub differential protection

No. Output Signal Description

1 87STB.On Stub differential protection is enabled.
2 87STB.Blocked Stub differential protection is blocked.
3 87STB.Valid Stub differential protection is valid.
4 87STB.Active Stub differential protection is on service.
5 87STB.Op Stub differential protection operates. 3
6 87STB.St Stub differential protection starts.
7 87STB.StA Stub differential protection starts. (phase-A)
8 87STB.StB Stub differential protection starts. (phase-B)
9 87STB.StC Stub differential protection starts. (phase-C)
10 87STB.Op.PhA Stub differential protection operates. (phase-A)
11 87STB.Op.PhB Stub differential protection operates. (phase-B)
12 87STB.Op.PhC Stub differential protection operates. (phase-C)
13 87STB.Alm_Diff The alarm signal of differential current abnormality
14 87STB.Alm_89b_DS The alarm signal of disconnector position abnormality

3.31.4 Logic

EN [87STB.En] &
87STB.On
SIG 87STB.Enable
&
SIG 87STB.Block >=1 87STB.Blocked

SIG Fail_Device
&
87STB.Valid

Figure 3.31-2 Logic of enabling stub differential protection

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SIG 87STB.Valid &

SIG 87STB.89b_DS
>=1
& 87STB.Active

SIG 87STB.89b_DS_Rmt
&
SET IDiffA >[87STB.I_Alm] &

SIG IDiffA >0.15×IBiasA

& >=1
SET IDiffB >[87STB.I_Alm] & &
3 SIG IDiffB >0.15×IBiasB
10s 10s 87STB.Alm_Diff

&
SET IDiffC >[87STB.I_Alm] &

SIG IDiffC >0.15×IBiasC

EN [87STB.En_Diff_Alm]

SIG 87STB.Valid &

SIG 87STB.89b_DS
>=1
& 87STB.Active

>=1
SIG 87STB.89b_DS_Rmt 87STB.St

SIG 87STB.Alm_Diff >=1 &

87STB.StA
EN [87STB.En_CTS_Blk]
[87STB.t_Op] 87STB.Op.PhA
SET IDiffA >[87STB.I_Pkp] & &
87STB.StB
SET IDiffA >[87STB.Slope]×IBiasA
[87STB.t_Op] 87STB.Op.PhB
SET IDiffB >[87STB.I_Pkp] & &
87STB.StC
SET IDiffB >[87STB.Slope]×IBiasB
[87STB.t_Op] 87STB.Op.PhC
SET IDiffC >[87STB.I_Pkp] &
>=1
87STB.Op
SET IDiffC >[87STB.Slope]×IBiasC

SIG IDiff >0.06In &

10s 10s 87STB.Alm_89b_DS
SIG 87STB.89b_DS

Figure 3.31-3 Logic of stub differential protection

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3.31.5 Settings
Table 3.31-3 Settings of stub differential protection

Name Range Step Unit Default Description

Pickup current setting of stub differential
87STB.I_Pkp (0.050~40.000)×In 0.001 A 1.200
protection
Current setting of differential current
87STB.I_Alm (0.050~40.000)×In 0.001 A 0.100
alarm
87STB.Slope 0.300~1.000 0.001 0.500 Slope of current differential protection
87STB.t_Op 0.000~200.000 0.001 s 0.020 Time delay of stub differential protection

87STB.En
Disabled
Enabled
Enabling/disabling stub differential 3
Enabled protection
Disabled Enabling/disabling differential current
87STB.En_Diff_Alm Enabled
Enabled alarm function
Disabled Enabling/disabling stub differential
87STB.En_CTS_Blk Disabled
Enabled protection controlled by CT circuit failure

3.32 Dead Zone Protection (50DZ)

Generally, fault current is very large when multi-phase fault occurs between CT and circuit breaker
(i.e. dead zone) and it will have a greater impact on the system. Breaker failure protection can
operate after a longer time delay, in order to clear the dead zone fault quickly and improve the
system stability, dead zone protection with shorter time delay (compared with breaker failure
protection) is adopted.

For double circuit breakers mode, the device will provide independent dead
zone protection for CB1 and CB2 respectively. Both dead zone protections
have the same logic. The difference is that the prefix “CBx.” is added to all
signals and settings for circuit breaker No.x (x=1 or 2).

3.32.1 Function Description

For some wiring arrangement (for example, circuit breaker is located between CT and the line), if
fault occurs between CT and circuit breaker, line protection can operate to trip circuit breaker quickly,
but the fault have not been cleared since local circuit breaker is tripped. Here dead zone protection
is needed in order to trip relevant circuit breaker.

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3.32.2 Function Block Diagram

50DZ

CBx.50DZ.Enable CBx.50DZ.On

CBx.50DZ.Block CBx.50DZ.Blocked

CBx.50DZ.Init CBx.50DZ.Valid

CBx.50DZ.St

CBx.50DZ.Op

3 CBx.50DZ.Alm_Init

3.32.3 I/O Signals

Table 3.32-1 Input signals of dead zone protection

No. Input Signal Description

1 CBx.50DZ.Enable Input signal of enabling dead zone protection
2 CBx.50DZ.Block Input signal of blocking dead zone protection
3 CBx.50DZ.Init Input signal of initiating dead zone protection

Table 3.32-2 Output signals of dead zone protection

No. Output Signal Description

1 CBx.50DZ.On Dead zone protection is enabled.
2 CBx.50DZ.Blocked Dead zone protection is blocked.
3 CBx.50DZ.Valid Dead zone protection is valid.
4 CBx.50DZ.St Dead zone protection starts.
5 CBx.50DZ.Op Dead zone protection operates.
6 CBx.50DZ.Alm_Init The initiating signal of dead zone protection is abnormal.

3.32.4 Logic

EN [CBx.50DZ.En] &
CBx.50DZ.On
SIG CBx.50DZ.Enable
&
SIG CBx.50DZ.Block >=1 CBx.50DZ.Blocked

SIG Fail_Device
&
CBx.50DZ.Valid

Figure 3.32-1 Logic of enabling dead zone protection

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SIG CBx.50DZ.Init [CBx.50DZ.t_Op+5s] 10 CBx.50DZ.Alm_Init

&
>=1
SET [CBx.50DZ.En_Alm_Init] CBx.50DZ.Init_Valid

&

SIG CBx.50DZ.Valid

SIG CBx.52b_PhA
&
SIG CBx.52b_PhB 3
SIG CBx.52b_PhC
CBx.50DZ.St
SET Ia>[CBx.50DZ.I_Set]
&
>=1 & [CBx.50DZ.t_Op] 0 CBx.50DZ.Op
SET Ib>[CBx.50DZ.I_Set]

SET Ic>[CBx.50DZ.I_Set]

SIG CBx.50DZ.Init_Valid >=1

SIG CBx.Trp

Figure 3.32-2 Logic of dead zone protection

3.32.5 Settings
Table 3.32-3 Settings of dead zone protection

Name Range Step Unit Default Description

The phase current setting of dead
CBx.50DZ.I_Set (0.050~40.000)×In 0.001 A 1.000
zone protection
CBx.50DZ.t_Op 0.000~30.000 0.001 s 0.100 Time delay of dead zone protection
Disabled Enabling/disabling dead zone
CBx.50DZ.En Enabled
Enabled protection

Disabled Enabling/disabling abnormality

CBx.50DZ.En_Alm_Init Disabled check of initiating signal for dead
Enabled
zone protection

3.33 Broken Conductor Protection (46BC)

Broken-conductor fault is difficult to be detected because there are no obvious fault characteristics
except for negative-sequence current, so negative-sequence overcurrent protection can be
considered to detect broken-conductor fault. However, under heavy load condition, negative-
sequence current is relatively large due to the unbalanced load, but negative-sequence current
because of broken-conductor fault under light load condition is relatively small. Hence, it is difficult
to set negative-sequence current protection reasonably so that it can suitable for both heavy load
condition and light load condition. Broken conductor protection based on the ratio of negative-

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sequence current to positive sequence current can be used to detect the broken-conductor fault.

3.33.1 Function Description

Broken-conductor fault mainly is single-phase broken or two-phases broken. The network of single-
phase broken is similar to that of two-phases earthing fault, positive-sequence, negative-sequence
and zero-sequence network is connected in parallel, I2/I1= Z0/(Z0+Z2), generally, zero-sequence
impedance is larger than positive-sequence impedance, i.e. I2/I1>0.5. The network of two-phases
broken is similar to that of single-phase earthing fault, positive-sequence, negative-sequence and
zero-sequence network is connected in series, so I2/I1=1.

According to the ratio of negative-sequence current to positive-sequence current (I2/I1), it is used

3 to judge whether there is a broken-conductor fault. Negative-sequence current under normal
conditions (i.e. the unbalanced current) is due to CT error and unbalanced load, so the ratio of
negative-sequence current to positive-sequence current (amplitude) is relative steady. The value
with margin can then be used as the setting of broken conductor protection. It is mainly used to
detect broken-conductor fault and CT circuit failure as well.

3.33.2 Function Block Diagram

46BC

46BC.Enable 46BC.On

46BC.Block 46BC.Blocked

46BC.Valid

46BC.St

46BC.Op

46BC.Alm

3.33.3 I/O Signals

Table 3.33-1 Input signals of broken conductor protection

No. Input Signal Description

1 46BC.Enable Input signal of enabling broken conductor protection
2 46BC.Block Input signal of blocking broken conductor protection

Table 3.33-2 Output signals of broken conductor protection

No. Output Signal Description

1 46BC.On Broken conductor protection is enabled.
2 46BC.Blocked Broken conductor protection is blocked.
3 46BC.Valid Broken conductor protection is valid.
4 46BC.St Broken conductor protection starts.
5 46BC.Op Broken conductor protection operates.
6 46BC.Alm Broken conductor protection alarms.

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3.33.4 Logic

EN [46BC.En] &
46BC.On
SIG 46BC.Enable
&
SIG 46BC.Block >=1 46BC.Blocked

SIG Fail_Device
&
46BC.Valid

Figure 3.33-1 Logic of enabling broken conductor protection 3

SIG 46BC.Valid

SET Ia>[46BC.I_Min]
>=1 &
SET Ib>[46BC.I_Min] 46BC.St

SET Ic>[46BC.I_Min]
[46BC.t_Op] 0ms &
SET I2/I1>[46BC.I2/I1_Set]
46BC.Op
SET [46BC.Opt_Trp/Alm]=Trp

&
46BC.Alm
SET [46BC.Opt_Trp/Alm]=Alm

Figure 3.33-2 Logic of broken conductor protection

3.33.5 Settings
Table 3.33-3 Settings of broken conductor protection

Name Range Step Unit Default Description

Minimum operating current setting of
46BC.I_Min (0.050~40.000)×In 0.001 A 1.000
broken conductor protection
Ratio setting (negative-sequence current
46BC.I2/I1_Set 0.000~5.000 0.001 0.500 to positive-sequence current) of broken
conductor protection
46BC.t_Op 0.000~100.000 0.001 s 1.000 Time delay of broken conductor protection
Disabled Enabling/disabling broken conductor
46BC.En Enabled
Enabled protection
Enabling/disabling broken conductor
Trp protection operate to trip or alarm
46BC.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

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3.34 Pole Discrepancy Protection (62PD)

The pole discrepancy of circuit breaker may occur during operation of a breaker with segregated
operating gears for the three phases. The reason could be an interruption in the tripping/closing
circuits, or mechanical failure. When there is loading, zero-sequence current or negative-sequence
current will be generated in the power system, which will result in overheat of the generator or the
motor, so a pole discrepancy can only be tolerated for a limited period. Pole discrepancy protection
is required to eliminate the fault.

3
For double circuit breakers mode, the device will provide independent pole
discrepancy protection for CB1 and CB2 respectively. Both pole
discrepancy protections have the same logic. The difference is that the
prefix “CBx.” is added to all signals and settings for circuit breaker No.x (x=1
or 2).

3.34.1 Function Description

Pole discrepancy protection determines three-phase breaker pole discrepancy condition by its
phase segregated CB auxiliary contacts. In order to improve the reliability of pole discrepancy
protection, zero-sequence current element or negative-sequence current element can be selected
as auxiliary criterion.

3.34.2 Function Block Diagram

62PD

CBx.62PD.Enable CBx.62PD.On

CBx.62PD.Block CBx.62PD.Blocked

CBx.62PD.Init CBx.62PD.Valid

CBx.62PD.St

CBx.62PD.Op

CBx.62PD.Alm_Init

3.34.3 I/O Signals

Table 3.34-1 Input signals of pole discrepancy protection

No. Input Signal Description

1 CBx.62PD.Enable Input signal of enabling pole discrepancy protection
2 CBx.62PD.Block Input signal of blocking pole discrepancy protection
3 CBx.62PD.Init Input signal of initiating pole discrepancy protection

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Table 3.34-2 Output signals of pole discrepancy protection

No. Output Signal Description

1 CBx.62PD.On Pole discrepancy protection is enabled.
2 CBx.62PD.Blocked Pole discrepancy protection is blocked.
3 CBx.62PD.Valid Pole discrepancy protection is valid.
4 CBx.62PD.St Pole discrepancy protection starts.
5 CBx.62PD.Op Pole discrepancy protection operates.
6 CBx.62PD.Alm_Init The initiating signal of pole discrepancy protection is abnormal.

3.34.4 Logic
3
EN [CBx.62PD.En] &
CBx.62PD.On
SIG CBx.62PD.Enable
&
SIG CBx.62PD.Block >=1 CBx.62PD.Blocked

SIG Fail_Device
&
CBx.62PD.Valid

Figure 3.34-1 Logic of enabling pole discrepancy protection

SIG CBx.62PD.Init [CBx.62PD.t_Op+5s] 10s CBx.62PD.Alm_Init

&

EN [CBx.62PD.En_Init_Alm]
>=1
& CBx.62PD.Init_Valid

SIG CBx.62PD.Valid

EN [CBx.62PD.En_3I0/I2_Ctrl] CBx.62PD.St
>=1 &
SET 3I0>[CBx.62PD.3I0_Set] >=1 [CBx.62PD.t_Op] 0 CBx.62PD.Op

SET I2>[CBx.62PD.I2_Set]

SIG CBx.62PD.Init_Valid

Figure 3.34-2 Logic of pole discrepancy protection

For the initiating signal of pole discrepancy protection ("CBx.62PD.Init"), it can be fulfilled by
configuring the position contacts of phase-segregated circuit breaker. For line protection, it has
been configured internally. In order to prevent pole discrepancy protection from operation during 1-
pole AR initiation, the output of 1-pole AR initiation can be used to block pole discrepancy protection.

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3.34.5 Settings
Table 3.34-3 Settings of pole discrepancy protection

Name Range Step Unit Default Description

Residual current setting of pole
CBx.62PD.3I0_Set (0.050~40.000)×In 0.001 A 1.000
discrepancy protection
Negative-sequence current setting
CBx.62PD.I2_Set (0.050~40.000)×In 0.001 A 1.000
of pole discrepancy protection
Time delay of pole discrepancy
CBx.62PD.t_Op 0.000~600.000 0.001 s 1.000
protection

3 CBx.62PD.En
Disabled
Enabled
Enabling/disabling pole
Enabled discrepancy protection
Enabling/disabling residual current
Disabled criterion and negative-sequence
CBx.62PD.En_3I0/I2_Ctrl Enabled
Enabled current criterion for pole
discrepancy protection
Enabling/disabling abnormality
Disabled
CBx.62PD.En_Init_Alm Disabled check of initiating signal for pole
Enabled
discrepancy protection

3.35 Flashover Protection (50F)

During the synchronization process of generator-transformer unit, a flashover in the circuit breaker
is possible when the voltage on both sides of the circuit breaker is in opposite direction. In general,
the circuit breaker flashover only occurs on one or two phases, so three-phase circuit breaker
flashover can be ignored. The circuit breaker flashover will cause damage to the circuit breaker
itself, and even cause a burst. Therefore, flashover protection is provided for this fault.

For double circuit breakers mode, the device will provide independent
flashover protection for CB1 and CB2 respectively. Both flashover
protections have the same logic. The difference is that the prefix “CBx.” is
added to all signals and settings for circuit breaker No.x (x=1 or 2).

3.35.1 Function Description

The circuit breaker flashover mainly occurs in the parallel process of the circuit breaker, which is
caused by the decrease of insulation capacity of the circuit breaker. The circuit breaker flashover
is generally periodic, flashover protection is in service within 5 cycles during closing the circuit
breaker. Flashover protection provides two time delays, the first time delay is used for generator's
field suppression, and the second time delay is used to initiate breaker failure protection. The
criterion is:

1. Three-phase circuit breaker are all in the open position.

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2. Negative-sequence current, residual current or phase current is greater than the

corresponding setting.

3.35.2 Function Block Diagram

50F

CBx.50F.Enable CBx.50F.On

CBx.50F.Block CBx.50F.Blcked

CBx.50F.52b CBx.50F.Valid

CBx.50F.St 3
CBx.50F.Op_t1

CBx.50F.Op_t2

3.35.3 I/O Signals

Table 3.35-1 Input signals of flashover protection

No. Input Signal Description

1 CBx.50F.Enable Input signal of enabling flashover protection
2 CBx.50F.Block Input signal of blocking flashover protection
3 CBx.50F.52b Input signal of CB open position

Table 3.35-2 Output signals of flashover protection

No. Output Signal Description

1 CBx.50F.On Flashover protection is enabled.
2 CBx.50F.Blocked Flashover protection is blocked.
3 CBx.50F.Valid Flashover protection is valid.
4 CBx.50F.St Flashover protection starts.
5 CBx.50F.Op_t1 Flashover protection operates with the time delay [CBx.50F.t1_Op].
6 CBx.50F.Op_t2 Flashover protection operates with the time delay [CBx.50F.t2_Op].

3.35.4 Logic

EN [CBx.50F.En] &
CBx.50F.On
SIG CBx.50F.Enable
&
SIG CBx.50F.Block >=1 CBx.50F.Blocked

SIG Fail_Device
&
CBx.50F.Valid

Figure 3.35-1 Logic of enabling flashover protection

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SIG CBx.50F.Valid

EN [CBx.50F.En_I0]
&
SET 3I0>[CBx.50F.3I0_Set]

SIG CBx.50F.52b &

& >=1 CBx.50F.St
EN [CBx.50F.En_I2]
[CBx.50F.t1_Op] 0 CBx.50F.Op_t1
SET I2>[CBx.50F.I2_Set]
& [CBx.50F.t2_Op] 0 CBx.50F.Op_t2
EN [CBx.50F.En_Ip]

3 SET Ia>[CBx.50F.I_Set]
>=1
SET Ib>[CBx.50F.I_Set]

SET Ic>[CBx.50F.I_Set]

Figure 3.35-2 Logic of falshover protection

3.35.5 Settings
Table 3.35-3 Settings of pole discrepancy protection

Name Range Step Unit Default Description

Phase current setting of flashover
CBx.50F.I_Set (0.050~40.000)×In 0.001 A 1.000
protection
Residual current setting of flashover
CBx.50F.3I0_Set (0.050~40.000)×In 0.001 A 1.000
protection
Negative-sequence current setting of
CBx.50F.I2_Set (0.050~40.000)×In 0.001 A 1.000
flashover protection
CBx.50F.t1_Op 0.000~30.000 0.001 s 0.040 First time delay of flashover protection
CBx.50F.t2_Op 0.000~30.000 0.001 s 0.060 Second time delay of flashover protection
Disabled
CBx.50F.En Enabled Enabling/disabling flashover protection
Enabled
Disabled Enabling/disabling phase current criterion
CBx.50F.En_Ip Disabled
Enabled for flashover protection
Disabled Enabling/disabling residual current criterion
CBx.50F.En_3I0 Disabled
Enabled for flashover protection
Disabled Enabling/disabling negative-sequence
CBx.50F.En_I2 Enabled
Enabled current criterion for flashover protection

3.36 Transfer Trip (TT)

When breaker failure protection, dead zone protection or overvoltage protection, etc. of the
opposite end operates, it is required that the device at the local end operates quickly. The device
provides transfer trip to fulfill the application, including phase-segregated and non-phase-
segregated input signals used to initiate transfer trip, which can receive transfer trip signals from
the opposite end. After receiving transfer trip signal from the opposite end, simultaneous tripping

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at both ends can be ensured.

3.36.1 Function Description

The device provides phase-segregated transfer trip and three-phases transfer trip, which can be
controlled by local fault detector by the settings [TT.En_FD_Ctrl].

1. Phase-segregated transfer trip

⚫ [TT.Init_A]

⚫ [TT.Init_B]

⚫ [TT.Init_C] 3
2. Three-phases transfer trip

⚫ [TT.Init_3P]

These input signals are always supervised, and the device will issue an alarm [TT.Alm] and block
transfer trip once the binary input is energized for longer than the setting [TT.t_Op]+5s and drop off
after resumed to normal with a time delay of 10s. Both phase-segregated transfer trip and three-
phase transfer trip operate to block AR if the setting [TT.En_BlkAR] is set as "Enabled".

3.36.2 Function Block Diagram

TT

TT.Enable TT.On

TT.Block TT.Blocked

TT.Init_3P TT.Valid

TT.Init_A TT.Alm

TT.Init_B TT.Op_3P

TT.Init_C TT.Op_A

TT.Op_B

TT.Op_C

TT.BlkAR

3.36.3 I/O Signals

Table 3.36-1 Input signals of transfer trip

No. Input Signal Description

1 TT.Enable Input signal of enabling transfer trip
2 TT.Block Input signal of blocking transfer trip
3 TT.Init_3P Input signal of initiating transfer trip (Three phases)
4 TT.Init_A Input signal of initiating transfer trip (Phase A)

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5 TT.Init_B Input signal of initiating transfer trip (Phase B)

6 TT.Init_C Input signal of initiating transfer trip (Phase C)

Table 3.36-2 Output signals of transfer trip

No. Output Signal Description

1 TT.On Transfer trip is enabled.
2 TT.Blocked Transfer trip is blocked.
3 TT.Valid Transfer trip is valid.
4 TT.Alm The initiating signal of transfer trip is abnormal.
5 TT.Op_3P Transfer trip operates. (Three phases)
3 6 TT.Op_A Transfer trip operates. (Phase A)
7 TT.Op_B Transfer trip operates. (Phase B)
8 TT.Op_C Transfer trip operates. (Phase C)
9 TT.BlkAR Transfer trip operates to block AR.

3.36.4 Logic

EN [TT.En] &
TT.On
BI TT.Enable
&
BI TT.Block >=1 TT.Blocked

SIG Fail_Device
&
TT.Valid

Figure 3.36-1 Logic of enabling transfer trip

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SIG TT.Init_3P [TT.t_Op]+5s 10s

SIG TT.Init_A [TT.t_Op]+5s 10s >=1

>=1 TT.Alm
SIG TT.Init_B [TT.t_Op]+5s 10s

SIG TT.Init_C [TT.t_Op]+5s 10s

SIG 52b_PhA
&
SIG 52b_PhB >=1
SIG 52b_PhC

EN [TT.En_CB_Ctrl]

SIG TT.Alm 3
EN [TT.En_FD_Ctrl] >=1 &

SIG Local fault detector

SIG TT.Valid
&
[TT.t_Op] 0 TT.Op_3P
SIG TT.Init_3P

&
[TT.t_Op] 0 TT.Op_A
SIG TT.Init_A

&
[TT.t_Op] 0 TT.Op_B
SIG TT.Init_B

&
[TT.t_Op] 0 TT.Op_C
SIG TT.Init_C
>=1
&
TT.BlkAR
EN [TT.En_BlkAR]

Figure 3.36-2 Logic of transfer trip

3.36.5 Settings
Table 3.36-3 Settings of transfer trip

Name Range Step Unit Default Description

TT.t_Op 0.000~100.000 0.001 s 0.005 Time delay of transfer trip
Disabled
TT.En Enabled Enabling/disabling transfer trip
Enabled
Disabled Enabling/disabling transfer trip controlled by local
TT.En_FD_Ctrl Enabled
Enabled fault detector element

Disabled Enabling/disabling transfer trip operate to block

TT.En_BlkAR Enabled
Enabled AR

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 3 Protection Functions

Name Range Step Unit Default Description

Disabled Enabling/disabling transfer trip controlled by CB
TT.En_CB_Ctrl Enabled
Enabled position

3.37 Trip Logic (TRP)

For any enabled protection tripping elements, their operation signal will convert to appropriate
tripping signals through trip logics and then trigger output contacts by configuration.

3
For double circuit breakers mode, the device will provide independent trip
logic for CB1 and CB2 respectively. Both trip logics have the same logic.
The difference is that the prefix “CBx.” is added to all signals for circuit
breaker No.x (x=1 or 2). For trip logic settings, only the setting [En_Trp3P]
will be added the prefix “CBx.” for circuit breaker No.x, which means that
both circuit breakers corresponding to the same line protection can be set
different trip mode.

3.37.1 Function Description

Trip logic gathers signals from phase selection and protection tripping elements and then converts
the operation signal from protection tripping elements to appropriate tripping signals. The device
can implement phase-segregated tripping or three-phase tripping, and may output the contact of
blocking AR and the contact of initiating breaker failure protection.

After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp]
at least. When the time delay is expired, for phase-segregated tripping, the tripping signal will drop
off immediately if the faulty current of corresponding phase is less than 0.04In (In is secondary
rated current), otherwise the tripping signal will be always kept until the faulty current of
corresponding phase is less than 0.04In. For three-phase tripping, the tripping signal will drop off
immediately if three-phase currents are all less than 0.04In, otherwise the tripping signal will be
always kept until three-phase currents are all less than 0.04In.

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3.37.2 Function Block Diagram

TRP

CBx.Enable CBx.TRP.On

CBx.Block CBx.TrpA

CBx.PrepTrp3P CBx.TrpB

CBx.TrpC

CBx.Trp

CBx.Trp3P 3
CBx.BFI_A

CBx.BFI_B

CBx.BFI_C

CBx.BFI

TRP

Line.Enable Line.Trp3P_PSFail

Line.Block Line.PSFail_BlkAR

3.37.3 I/O Signals

Table 3.37-1 Input signals of trip logic

No. Input Signal Description

1 CBx.Enable Input signal of enabling trip logic of circuit breaker No.x
2 CBx.Block Input signal of blocking trip logic of circuit breaker No.x
Input signal of permitting three-phase tripping, When this signal is valid, three-
3 CBx.PrepTrp3P
phase tripping will be adopted for any kind of faults.
4 Line.Enable Input signal of enabling line trip logic
5 Line.Block Input signal of blocking line trip logic

Table 3.37-2 Output signals of trip logic

No. Output Signal Description

1 CBx.TRP.On Tripping logic of circuit breaker No.x is enabled.
2 CBx.TrpA Tripping phase A of circuit breaker No.x
3 CBx.TrpB Tripping phase B of circuit breaker No.x
4 CBx.TrpC Tripping phase C of circuit breaker No.x
5 CBx.Trp Tripping any phase of circuit breaker No.x
6 CBx.Trp3P Tripping three phases of circuit breaker No.x
Protection phase-A tripping signal of circuit breaker No.x configured to initiate
7 CBx.BFI_A
BFP, BFI signal shall be reset immediately after tripping signal drops off.

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 3 Protection Functions

Protection tripping signal of phase B configured to initiate BFP, BFI signal shall
8 CBx.BFI_B
be reset immediately after tripping signal drops off.
Protection tripping signal of phase C configured to initiate BFP, BFI signal shall
9 CBx.BFI_ C
be reset immediately after tripping signal drops off.
Protection tripping signal configured to initiate BFP, BFI signal shall be reset
10 CBx.BFI
immediately after tripping signal drops off.
11 Line.Trp3P_PSFail Initiating three-phase tripping due to failure in fault phase selection
12 Line.PSFail_BlkAR Blocking auto-reclosing due to failure in fault phase selection

3.37.4 Logic

3 SIG Line.Enable &

SIG Line.Block

SIG Line tripping element without FPS

>=1 &
SIG FPS (phase A) & & Line trip command (phase A)

SIG Line tripping element with FPS

SIG Ia<0.04In &

[t_Dwell_Trp] 0

SIG Line tripping element without FPS

>=1 &
SIG FPS (phase B) & & Line trip command (phase B)

SIG Line tripping element with FPS

SIG Ib<0.04In &

[t_Dwell_Trp] 0

SIG Line tripping element without FPS

>=1 &
SIG FPS (phase C) & & Line trip command (phase C)

SIG Line tripping element with FPS

SIG Ic<0.04In &

[t_Dwell_Trp] 0

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SIG Line trip command (phase A)

&
SIG Line trip command (phase B)

SIG Line trip command (phase C)

SIG Line trip command (phase A)

& >=1
SIG Line trip command (phase B) >=1
Line trip 3P command
SIG Line trip command (phase C)

SIG Line trip command (phase A)

&
SIG Line trip command (phase B)

SIG Line trip command (phase C)

3
SIG Line trip command (phase A)
&
SIG Line trip command (phase B)

SIG Line trip command (phase C)

SIG FPS (phase A)

>=1
SIG FPS (phase B)

SIG FPS (phase C)

&
SIG Line tripping element with FPS [Line.t_PhSFail] 0 Line.Trp3P_PSFail

EN [Line.En_PhSFail]

SIG CBx.Enable &

CBx.TRP.On
SIG CBx.Block

>=1

SIG Breaker tripping element

SIG Ia<0.04In
& &
SIG Ib<0.04In & CB No.x Trip Command

SIG Ic<0.04In
&

[t_Dwell_Trp] 0

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 3 Protection Functions

SIG CBx.TRP.On &

CBx.TrpA
SIG Line trip command (phase A)

&
CBx.TrpB
SIG Line trip command (phase B)

&
CBx.TrpC
SIG Line trip command (phase C)
>=1
3 &
SIG CBx.PrepTrp3P >=1

EN [CBx.En_3PTrp] &
SIG Line.Trip 3P Command
>=1 CBx.Trp3P
>=1
SIG Line.Trp3P_PSFail

SIG CB No.x Trip Command

Figure 3.37-1 Tripping logic

>=1
Except undervoltage protection, &
tripping elements of all CBx.BFI
protections all initiate BFP

SIG Initiating BFP element &

CBx.BFI_A
SIG CBx.TrpA

&
CBx.BFI_B
SIG CBx.TrpB

&
CBx.BFI_C
SIG CBx.TrpC

Figure 3.37-2 Breaker failure initiation logic

Faulty phase selection (FPS) indicates the result of fault phase selection, if multi-phase is selected,
three-phase breakers will be tripped.

Line tripping element indicates all operation signals of various line protection tripping elements,
such as distance protection, overcurrent protection, etc.

Breaker tripping element indicates all protection tripping elements concerned with circuit breaker,
such as pole discrepancy protection, etc.

Initiating BFP element indicates tripping element initiating BFP, except undervoltage protection,

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tripping elements of all protections initiate BFP.

3.37.5 Settings
Table 3.37-3 Settings of trip logic

Name Range Step Unit Default Remark

Disabled Enabling/disabling auto-reclosing
En_MPF_Blk_AR Enabled
Enabled blocked when multi-phase fault happens
Disabled Enabling/disabling auto-reclosing
En_3PF_Blk_AR Enabled
Enabled blocked when three-phase fault happens

Line.t_PhSFail 0.000~100.000 0.001 s 0.200

Time delay of confirming faulty phase
selection failure
3
Disabled Enabling/disabling faulty phase
Line.En_PhSFail Disabled
Enabled selection failure
Disabled Enabling/disabling auto-reclosing
Line.En_PhSF_Blk_AR Enabled
Enabled blocked when faulty phase selection fails
The dwell time of tripping command,
empirical value is 0.04
t_Dwell_Trp 0.000~100.000 0.001 s 0.040 The tripping contact shall drop off under
conditions of no current or protection
tripping element drop-off.
Enabling/disabling three-phase tripping
Disabled
CBx.En_Trp3P Disabled mode of circuit breaker No.x for any fault
Enabled
conditions

3.38 Automatic Reclosure (79)

To maintain the integrity of the overall electrical transmission system, the device is installed on the
transmission system to isolate faulted segments during system disturbances. Faults caused by
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on
overhead lines are the transient faults. AR are installed to restore the faulted section of the
transmission system once the fault is extinguished (providing it is a transient fault). For certain
transmission systems, AR is used to improve system stability by restoring critical transmission
paths as soon as possible. Besides overhead lines, other equipment failure, such as cables, busbar,
transformer fault and so on, are generally permanent fault, and AR is not initiated after faulty feeder
is tripped. For some mixed circuits, such as overhead line with a transformer unit, hybrid
transmission lines, etc., it is required to ensure that AR is only initiated for faults overhead line
section, or make a choice according to the situation.

For double circuit breakers mode, the device will provide independent
automatic reclosure function for CB1 and CB2 respectively. Both automatic

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 3 Protection Functions

reclosure functions have the same logic. The difference is that the prefix
“CBx.” is added to all signals and settings for circuit breaker No.x (x=1 or 2).

3.38.1 Function Description

AR can be used with either integrated device or external device. When AR is used with integrated
device, the internal protection logic can initiate AR, moreover, a tripping contact from external
device can be connected to the device via input signal to initiate integrated AR.

When AR is used as an independent device, it can be initiated by the protections′ operating signal.
The device can output some configurable output signals (such as, contact signals or digital signal,
for example, GOOSE signal) to initiate external AR or block external AR. The contact signals
3 includes phase-segregated tripping signal, single-phase tripping signal, three-phase tripping signal,
blocking AR signal and protection operating signal, etc,. According to requirement, these contacts
can be selectively connected to external AR.

According to the requirement, the device can be set as one-shot or multi-shot AR. When adopting
multi-shot AR, the AR mode of first time reclosing can be set as 1-pole AR, 3-pole AR or 1/3-pole
AR. The rest AR mode is only 3-pole AR.

3.38.1.1 Enable AR

When the setting [CBx.79.Opt_Enable] is set as "Setting&Config", AR is determined whether it is

enabled or disabled by the setting and configuration signal. Otherwise, it is only determined by the
setting. When AR is enabled, the device outputs the signal "CBx.79.On", otherwise the device
outputs the signal "CBx.79.Off". The logic of enabling AR is:

SET [CBx.79.Opt_Enable]=Setting &

>=1
EN [CBx.79.En] CBx.79.On

& CBx.79.Off
SET [CBx.79.Opt_Enable]=Setting&Config &
SIG CBx.79.Enable

SIG CBx.79.Block

Figure 3.38-1 Logic of enabling AR

3.38.1.2 AR Mode

AR mode includes 1-pole AR, 3-pole AR and 1/3-pole AR. AR mode can be selected by the settings
or configuration signals.

1-pole AR: single-phase fault initiates 1-pole AR and multi-phase fault blocks AR.

3-pole AR: any kinds of fault all initiates 3-pole AR and the device provides some settings to block
AR for multi-phase fault and three-phase fault.

1/3-pole AR: single-phase fault initiates 1-pole AR and multi-phase fault initiates 3-pole AR. The
device provides the setting to block AR for three-phase fault.

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Setting
EN [CBx.79.En_1P]
CBx.79.Mode_1P
SIG CBx.79.Sel_1P
Config
Setting
EN [CBx.79.En_3P]
CBx.79.Mode_3P
SIG CBx.79.Sel_3P
Config
Setting
EN [CBx.79.En_1P/3P]
CBx.79.Mode_1P/3P

3
SIG CBx.79.Sel_1P/3P
Config
SET [CBx.79.Opt_ValidMode]

Figure 3.38-2 Logic of AR mode selection

When the setting [CBx.79.Opt_ValidMode] is set as "Setting", AR mode is determined by the

settings, [CBx.79.En_1P], [CBx.79.En_3P] and [CBx.79.En_1P/3P].

When the setting [CBx.79.Opt_ValidMode] is set as "Config", AR mode is determined by

configuration signals, "CBx.79.Sel_1P", "CBx.79.Sel_3P", "CBx.79.Sel_1P/3P".

3.38.1.3 Synchronism Check for AR

Setting
EN [CBx.79.En_SynChk]
CBx.79.On_SynChk
SIG CBx.79.Sel_SynChk
Config
Setting
EN [CBx.79.En_SynDd_RefDd]
CBx.79.On_SynDd_RefDd
SIG CBx.79.Sel_SynDd_RefDd
Config
Setting
EN [CBx.79.En_SynLv_RefDd]
CBx.79.On_SynLv_RefDd
SIG CBx.79.Sel_SynLv_RefDd
Config
Setting
EN [CBx.79.En_SynDd_RefLv]
CBx.79.On_SynDd_RefLv
SIG CBx.79.Sel_SynDd_RefLv
Config
Setting
EN [CBx.79.En_NoChk]
CBx.79.On_NoChk
SIG CBx.79.Sel_NoChk
Config
SET [CBx.79.Opt_RSYN_ValidMode]

Figure 3.38-3 Logic of synchronism check mode selection for AR

When the synchronism check mode of auto-reclosing is independent of that of manual closing, the
device provides dedicated settings used by synchronism check for AR. The synchronism check

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 3 Protection Functions

mode can be determined by the settings or configuration signals.

When the setting [CBx.79.Opt_RSYN_ValidMode] is set as "Setting", the synchronism check mode
for AR is determined by the settings, [CBx.79.En_SynChk], [CBx.79.En_SynDd_RefDd],
[CBx.79.En_SynLv_RefDd], [CBx.79.En_SynDd_RefLv] and [CBx.79.En_NoChk].

When the setting [CBx.79.Opt_RSYN_ValidMode] is set as "Config", the synchronism check mode
for AR is determined by configuration signals, "CBx.79.Sel_SynChk",
"CBx.79.Sel_SynDd_RefDd", "CBx.79.Sel_SynLv_RefDd", "CBx.79.Sel_SynDd_RefLv" and
"CBx.79.Sel_NoChk".

SIG CBx.79.On_SynChk &

3 CBx.79.Ok_SynChk
SIG CBx.25.SynChk_OK

SIG CBx.79.On_SynDd_RefDd
&
SIG CBx.25.RefDd & CBx.79.Ok_SynDd_RefDd

SIG CBx.25.SynDd

SIG CBx.79.On_SynLv_RefDd
&
SIG CBx.25.RefDd & CBx.79.Ok_SynLv_RefDd

SIG CBx.25.SynLv

SIG CBx.79.On_SynDd_RefLv
&
SIG CBx.25.RefLv & CBx.79.Ok_SynDd_RefLv

SIG CBx.25.SynDd
>=1

>=1
SIG CBx.79.Ok_SynChk CBx.79.Ok_Chk

SIG CBx.79.On_SynChk

Figure 3.38-4 Logic of synchronism check for AR

Based on the chosen synchronism check mode for AR, the device judges whether the synchronism
condition is satisfied, and then implement reclosing. When none of the synchronism check modes
for AR is selected, the device will issue an alarm "CBx.79.Alm_RSYN_Mode".

3.38.1.4 AR Ready

AR must be ready to operate before performing reclosing. The output signal [CBx.79.Ready] means that
the auto-reclosure can perform at least one time of reclosing function, i.e., breaker open-close-open.
When the device is energized or after the settings are modified, AR cannot be ready unless the following
conditions are met:

1. AR is enabled.

2. The circuit breaker is ready, such as, normal storage energy and no low pressure signal.

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3. The duration of the circuit breaker in closed position pre-fault is greater than the setting
[CBx.79.t_CBClsd].

4. There is no the signal of blocking AR.

After AR operates, it must reset, i.e., [CBx.79.Active]=0, in addition to the above conditions for
reclosing again.

When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After the fault is cleared, the tripping signal will drop out immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [CBx.79.t_PersistTrp], AR will be blocked, as shown in Figure 3.38-5.

The input signal [CBx.79.CB_Healthy] must be energized before AR gets ready. Because most
3
circuit breakers can finish one complete process: open-closed-open, it is necessary that circuit
breaker has enough energy before reclosing. When the time delay of AR is exhausted, AR will be
blocked if the input signal [CBx.79.CB_Healthy] is still not energized within time delay
[CBx.79.t_CBReady]. If this function is not required, the input signal [CBx.79.CB_Healthy] can be
not to configure, and its state will be thought as "1" by default.

In order to block AR reliably even if the signal of manually open circuit breaker not connected to
the input signal of blocking AR, when the circuit breaker is open by manually and there is CB
position input under normal conditions, AR will be blocked with the time delay of 100ms if AR is not
initiated and no any trip signal.

SIG Any tripping signal [CBx.79.t_PersistTrp] 0

>=1
SIG CBx.79.LockOut 0 [CBx.79.t_DDO_Blk]

SIG 1-pole AR Initiation [CBx.79.t_SecFault] 0

&
SIG Any tripping signal

En [CBx.79.En_PDF_Blk]

SIG CBx.79.Mode_1P &

EN [CBx.79.Num]=1
>=1
& CBx.79.Blocked
SIG Three phase trip >=1
SIG Phase A open &

SIG Phase B open

& >=1

&

SIG Phase C open

Figure 3.38-5 Logic of AR block

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When AR is disabled, AR fails, synchrocheck fails or last shot is reached, or when the internal
blocking condition of AR is met (such as, zone 3 of distance protection operates, the device
operates for multi-phase fault, three-phase fault and so on). AR will be discharged immediately and
next AR will be disabled. When the input signal [CBx.79.LockOut] is energized, AR will be blocked
immediately. The blocking flag of AR will be also controlled by the internal blocking condition of AR.
When the blocking flag of AR is valid, AR will be blocked immediately. The logic of AR ready is
shown in Figure 3.38-6.

When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled.
The time delay [CBx.79.t_SecFault] is used to discriminate another fault which begins after 1-pole
AR initiated. AR will be blocked if another fault happens after this time delay if the setting
3 [CBx.79.En_PDF_Blk] is set as "Enabled", and 3-pole AR will be initiated if [CBx.79.En_PDF_Blk]
is set as "Disabled".

AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop out with a time delay [CBx.79.t_DDO_Blk] after blocking signal disappears.

When one-shot and 1-pole AR is enabled, AR will be blocked immediately if there are binary inputs
of multi-phase CB position is energized.

>=1
SIG CB closed position [CBx.79.t_CBClsd] 0 &
SIG CBx.79.Active >=1

SIG Any tripping signal

& &
2s 0 CBx.79.Ready
SIG CBx.79.Inprog

BI [CBx.79.CB_Healthy] 0 [CBx.79.t_CBReady]

SIG CBx.79.Blocked >=1

>=1 &
SIG CBx.79.Lockout &
SIG CBx.79.Failed
>=1
SIG CBx.79.Fail_Chk

SIG Last shot is made

SIG CBx.79.On

Figure 3.38-6 Logic of AR ready

When any protection element operates to trip, the device will output a signal [CBx.79.Active] until AR
drop out (Reset Command). Any tripping signal can be from external protection device or internal
protection element. For one-shot reclosing, if 1-pole AR mode is selected, AR will be discharged when
there is three-phase tripping signal or input signal of multi-phase open position.

When AR is enabled, the device will output the signal [CBx.79.Perm_Trp3P] if AR is not ready, or AR
mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open.

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SIG CBx.79.On

SIG CBx.79.Mode_3P

SIG CBx.79.Ready

SIG CBx.79.Trp

SIG CBx.79.Trp3P

SIG CBx.79.TrpA Logic CBx.79.Perm_Trp3P

SIG CBx.79.TrpB CBx.79.Perm_Trp1P

SIG CBx.79.TrpC
3
SIG Phase A open

SIG Phase B open

SIG Phase C open

Figure 3.38-7 Logic of tripping condition output

3.38.1.5 AR Initiation

AR can be initiated by the tripping signal of line protection or CB state.

1. AR initiated by tripping signal of line protection

AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal trip
signal or external trip signal.

When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR
is ready to reclosing ("CBx.79.Ready"=1) and the single-phase tripping signal is received, this
single-phase tripping signal will be kept in the device, and 1-pole AR will be initiated after the single-
phase tripping signal drops out. The single-phase tripping signal kept in the device will be cleared
after the completion of AR sequence (Reset Command). Its logic is shown in Figure 3.38-8.

SIG Reset Command &

>=1

SIG Single-phase Trip

&
&
SIG CBx.79.Ready 1-pole AR Initiation

SIG CBx.79.Mode_1P >=1

SIG CBx.79.Mode_1P/3P

Figure 3.38-8 1-pole AR initiation (single-phase tripping)

When selecting 3-pole AR or 1/3-pole AR, three-phase tripping signal will trigger 3-pole AR. When
AR is ready to reclosing ("CBx.79.Ready"=1) and the three-phase tripping signal is received, this
three-phase tripping signal will be kept in the device, and 3-pole AR will be initiated after the three-

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phase tripping signal drops out. The three-phase tripping signal kept in the device will be cleared
after the completion of the AR sequence (Reset Command). Its logic is shown in Figure 3.38-9.

SIG Reset Command &

>=1

SIG Three-phase Trip

&
&
SIG CBx.79.Ready 3-pole AR Initiation

SIG CBx.79.Mode_3P >=1

3
SIG CBx.79.Mode_1P/3P

Figure 3.38-9 3-pole AR initiation (three-phases tripping)

When AR mode is set as 1/3-pole AR, single-phase fault will initiate 3-pole AR if the circuit breaker
is in open position.

2. AR initiated by CB state

AR can be initiated by CB state by setting the setting [CBx.79.En_CBInit]. Under normal conditions,
when AR is ready to reclose ("CBx.79.Ready"=1), AR will be initiated if circuit breaker is open and
corresponding phase current is nil. AR initiated by CB state can be divided into initiating 1-pole AR and
3-pole AR, their logics are shown in Figure 3.38-10 and Figure 3.38-11 respectively. Usually normally
closed contact of circuit breaker is used to reflect CB state.

SIG Phase A open >=1

SIG Phase B open &

&

SIG Phase C open

&
EN [CBx.79.En_CBInit] &
1-pole AR Initiation
SIG CBx.79.Ready

SIG CBx.79.Mode_1P
>=1
SIG CBx.79.Mode_3P

SIG CBx.79.Mode_1P/3P

Figure 3.38-10 1-pole AR initiation (single-phase CB state)

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SIG Phase A open

&
SIG Phase B open

SIG Phase C open

EN [CBx.79.En_CBInit] & &

3-pole AR Initiation
SIG CBx.79.Ready

SIG CBx.79.Mode_3P >=1

SIG CBx.79.Mode_1P/3P

Figure 3.38-11 3-pole AR initiation (three-phases CB state) 3

3.38.1.6 AR Reclosing

When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, the reclosing is not
permissible unless live three-phase check is met. As far as the 3-pole AR, if the synchronism check is
enabled, the release of reclosing signal shall be subject to the result of synchronism check. After the
dead time delay of AR expires, if the synchronism check is still unsuccessful within the time delay
[CBx.79.t_wait_Chk], the signal of synchronism check failure ("CBx.79.Fail_Chk") will be output and
the AR will be blocked. If 3-pole AR with no-check is enabled, the condition of synchronism check
success ("CBx.25.RSYN_OK") will always be established. And the signal of synchronism check success
("CBx.25.RSYN_OK") from the synchronism check logic can be applied by AR inside the device or
outside the device.

CBx.79.Inprog_1P
SIG 1-pole AR Initiation >=1
CBx.79.Inprog
SIG 3-pole AR Initiation
CBx.79.Inprog_3P

[CBx.79.t_Dd_1PS1] 0 &
If 79.Inhibit_AR operates, >=1
SIG CBx.79.Inhibit then circuit of time delay AR Pulse
will be interrupted.
SIG 1-pole AR Initiation &

SIG CBx.79.Ok_3PLvChk

[CBx.79.t_Dd_3PS1] 0 &
If 79.Inhibit_AR operates,
then circuit of time delay
will be interrupted. >=1
& [CBx.79.t_Wait_Chk] 0 CBx.79.Fail_Chk
SIG 3-pole AR Initiation

SIG CBx.25.RSYN_OK

Figure 3.38-12 One-shot AR

In the process of channel abnormality, an internal fault occurs on the transmission line, backup
protection at both ends of line will operate to trip the circuit breaker of each end. The operation time of
backup protection at both ends of the line is possibly non-accordant, whilst the time delay of AR needs
to consider the arc-extinguishing and insulation recovery ability for transient fault, so the time delay of

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AR shall be considered comprehensively according to the operation time of the device at both ends.
When the communication channel of main protection is abnormal (input signal [CBx.79.PLC_Lost] is
energized), and the setting [CBx.79.En_AddDly] is set as "Enabled", then the dead time delay of AR
shall be equal to the original dead time delay of AR plus the extra time delay [CBx.79.t_AddDly], so as
to ensure the recovery of insulation intensity of fault point when reclosing after transient fault. This extra
time delay [CBx.79.t_AddDly] is only valid for the first shot AR.

SIG Any tripping signal &

>=1
SIG CBx.79.PLC_Lost &
&
3 SIG CBx.79.Active Extend AR time

EN [CBx.79.En_AddDly]

Figure 3.38-13 Extra time delay of AR

Reclosing pulse length may be set through the setting [CBx.79.t_PW]. For the circuit breaker without
anti-pump interlock, the setting [CBx.79.En_CutPulse] is available to control the reclosing pulse. When
this function is enabled, if the device operates to trip during reclosing, the reclosing pulse will drop out
immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing signal is issued, AR will
drop out with time delay [CBx.79.t_Reclaim], and can carry out next reclosing.

The reclaim timer is started when the CB closing signal is given. The reclaim timer defines a time from
the issue of the reclosing command, after which the reclosing function resets. Should a new trip occur
during this time, it is treated as a continuation of the first fault.

SIG WaitMasterValid &

0 50ms
SIG AR Pulse >=1
0 [CBx.79.t_PW] & CBx.79.Close
SIG Single-phase Trip >=1
&
SIG Three-phase Trip

EN [CBx.79.En_CutPulse]

>=1
&
SIG CBx.79.Close [CBx.79.t_Reclaim] 0 Reset Command

0 2s CBx.79.Completed

Figure 3.38-14 Reclosing output logic

The output signal "CBx.79.WaitToSlave" is usually configured to the signal "CBx.79.WaitMaster" of

slave AR. Slave AR is permissible to reclosing only if master AR is reclosed successfully.

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SIG 1-pole AR Initiation >=1

0 [CBx.79.t_Fail] >=1
SIG 3-pole AR Initiation &
CBx.79.WaitToSlave
SIG CBx.79.Failed

SET [CBx.79.Opt_Priority]=High

Figure 3.38-15 Wait to slave signal

For 1-pole AR, in order to prevent pole discrepancy protection from maloperation under pole
discrepancy conditions, the contact of "1-pole AR initiation" can be used to block pole discrepancy
protection. 3
3.38.1.7 Reclosing Failure and Success

SIG CBx.79.On
&
SIG CBx.79.Ready

SIG Any tripping command & >=1

0 100ms
SIG Last shot is made

SIG CBx.79.Inprog &

SIG CBx.79.Blocked

SIG CBx.79.WaitMaster
& >=1
SET [CBx.79.Opt_Priority]=Low [CBx.79.t_WaitMaster] 0 CBx.79.Failed

>=1
&
SIG AR Pulse [CBx.79.t_Fail] 0 &
SIG CB closed

EN [CBx.79.En_FailCheck] &
& CBx.79.Succeeded

0 [CBx.79.t_Fail]

Figure 3.38-16 Reclosing failure and success

For line fault, the fault will be cleared after the device operates to trip. When the following cases appear,
the reclosing is unsuccessful. After unsuccessful AR is confirmed, AR will be blocked.

1. If any protection element operates to trip when AR is enabled ("CBx.79.On"=1) and AR is not
ready ("CBx.79.Ready"=0), the device will output the signal " CBx.79.Failed".

2. For one-shot AR, if the tripping signal is received again within reclaim time after the reclosing
pulse is issued, the reclosing shall be considered as unsuccessful.

3. For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping signal is received again after the last reclosing pulse is issued, the reclosing shall be

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considered as unsuccessful.

4. The setting [CBx.79.En_FailCheck] is available to judge whether the reclosing is successful

by CB state, when it is set as "Enabled". If CB is still in open position with a time delay
[CBx.79.t_Fail] after the reclosing pulse is issued, the reclosing shall be considered as
unsuccessful. For this case, the device will issue a signal "CBx.79.Failed" to indicate that the
reclosing is unsuccessful, and this signal will drop out after (Reset Command). AR will be
blocked if the reclosing shall be considered as unsuccessful.

3.38.1.8 Reclosing Numbers Control

The device may be set up into one-shot or multi-shot AR. Through the setting [CBx.79.Num], the
3 maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.

1. 1-pole AR

For 1-pole AR mode, no matter what the setting [CBx.79.Num] is, the reclosing number is only one.
(Hence, the setting [CBx.79.Num] is recommended to be set as "1".) For one-shot 1-pole AR mode,
1-pole AR will be initiated only for single-phase fault and respective faulty phase selected, otherwise,
AR will be blocked. For single-phase transient fault on the line, line protection device will operate
to trip and 1-pole AR is initiated. After the dead time delay for 1-pole AR is expired, the device will
send reclosing pulse, and then AR will drop out after the time delay [CB1.79.t_Reclaim] to ready
for the next reclosing. For permanent fault, the device will operate to trip again after the reclosing
is performed, and the device will output the signal of reclosing failure "CBx.79.Failed".

2. 3-pole AR

⚫ [CBx.79.Num]=1

It means one-shot reclosing. For one-shot 3-pole AR mode, line protection device will operate to
trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the dead time
delay for 3-pole AR is expired, the device will send reclosing pulse, and then AR will drop out after
the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device
will operate to trip again after the reclosing is performed, and the device will output the signal of
reclosing failure "CBx.79.Failed".

⚫ [CBx.79.Num]>1

It means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line protection device
will operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the
dead time delay of the first reclosing is expired, the device will send reclosing pulse, and then AR
will drop out after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent
fault, the device will operate to trip again after the reclosing is performed, and then 3-pole AR is
initiated after the tripping contact drops off. After the time delay for AR is expired, the device will
send reclosing pulse. The sequence is repeated until the reclosing is successful or the maximum
permit reclosing number [CBx.79.Num] is reached.

3. 1/3-pole AR

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⚫ [CBx.79.Num]=1

It means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection device will operate to
trip when a transient fault occurs on the line and 1-pole AR will be initiated for single-phase fault
and 3-pole AR will be initiated for multi-phase fault. After respective dead time delay for AR is
expired, the device will send reclosing pulse, and then AR will drop out after the time delay
[CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will operate to
trip again after the reclosing is performed, and the device will output the signal of reclosing failure
"CBx.79.Failed".

⚫ [CBx.79.Num]>1

It means multi-shot reclosing. For multi-shot reclosing in 1/3-pole AR mode, line protection device 3
will operate to trip when a transient fault occurs on the line and AR will be initiated. After the dead
time delay of the first reclosing is expired, the device will send reclosing pulse, and then AR will
drop out after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent
fault, the device will operate to trip again after the reclosing is performed, and then 3-pole AR is
initiated after the tripping contact drops off. After the time delay for AR is expired, the device will
send reclosing pulse. The sequence is repeated until the reclosing is successful or the maximum
permit reclosing number [CBx.79.Num] is reached. Table 3.38-1 shows the number of reclose
attempts with respect to the settings and AR modes. "N-1AR" and "N-3AR" indicate the reclosing
number of 1-pole AR and 3-pole AR respectively.

Table 3.38-1 Reclosing number

1-pole AR 3-pole AR 1/3-pole AR

Setting Value
N-1AR N-3AR N-1AR N-3AR N-1AR N-3AR
1 1 0 0 1 1 1
2 1 0 0 2 1 2
3 1 0 0 3 1 3
4 1 0 0 4 1 4

4. Coordination between duplicated AR

Duplicated protection configurations are normally applied for UHV lines. If reclosing function is
integrated within line protections, the auto-reclosing function can be enabled in any or both of the
line protections without coordination.

If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent
fault, the other will block the reclosing pulse according to the latest condition of the faulty phase.
For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked immediately
to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the current is
detected in the faulty phase, the current reclosing pulse will be blocked and go into the next
reclosing pulse logic automatically. If the maximum permitted reclosing number [CBx.79.Num] is
reached, the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim].

For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After
reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter
may be cleared by the submenu “Clear Counter”. If the circuit breaker is reclosed by other devices

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 3 Protection Functions

during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.

3.38.1.9 AR Time Sequence Diagram

The following four examples indicate typical time sequence of 1-pole/3-pole AR process for
transient fault and permanent fault respectively.

Signal

Fault

3 Trip

CB 52b
CB 1P Open [CBx.79.t_Reclaim]
CBx.79.t_Reclaim

CBx.79.Active

CBx.79.Inprog

CBx.79.Inprog_1P [CBx.79.t_Dd_1PS1]

CBx.25.RSYN_OK

CBx.79.Out [CBx.79.t_PW_AR]

CBx.79.Perm_Trp3P

CBx.79.Failed

Time

Figure 3.38-17 Single-phase transient fault

Signal

Fault

Trip

CB 1P Open CB 3P Open CB 3P Open

52b

CBx.79.t_Reclaim [CBx.79.t_Reclaim]

CBx.79.Active

CBx.79.Inprog

CBx.79.Inprog_1P
[CBx.79.t_Dd_1PS1]
CBx.79.Inprog_3PS2
[CBx.79.t_Dd_3PS2]
CBx.25.RSYN_OK

CBx.79.Out [CBx.79.t_PW_AR]
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P

CBx.79.Failed 200ms

Time

Figure 3.38-18 Single-phase permanent fault

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Signal

Fault

Trip3P

CB 52b
CB 3P Open [CBx.79.t_Reclaim]
CBx.79.t_Reclaim

CBx.79.Active

CBx.79.Inprog

CBx.79.Inprog_3P [CBx.79.t_Dd_3PS1]
3
CBx.25.RSYN_OK

CBx.79.Out [CBx.79.t_PW_AR]

CBx.79.Perm_Trp3P

CBx.79.Failed

Time

Figure 3.38-19 Three-phase transient fault

Signal

Fault

Trip3P

CB 3P Open CB 3P Open CB 3P Open

52b

CBx.79.t_Reclaim [CBx.79.t_Reclaim]

CBx.79.Active

CBx.79.Inprog

CBx.79.Inprog_3P
[CBx.79.t_Dd_3PS1]
CBx.79.Inprog_3PS2
[CBx.79.t_Dd_3PS2]
CBx.25.RSYN_OK

CBx.79.Out [CBx.79.t_PW_AR]
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P

CBx.79.Failed 200ms

Time

Figure 3.38-20 Three-phase permanent fault

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3.38.2 Function Block Diagram

79

CBx.79.Enable CBx.79.Alm_RSYN_Mode

CBx.79.Block CBx.79.On_SynChk

CBx.79.Sel_SynChk CBx.79.On_SynDd_RefDd

CBx.79.Sel_SynDd_RefDd CBx.79.On_SynLv_RefDd

CBx.79.Sel_SynLv_RefDd CBx.79.On_SynDd_RefLv

3 CBx.79.Sel_SynDd_RefLv CBx.79.On_NoChk

CBx.79.Sel_NoChk CBx.79.On

CBx.79.Sel_1P CBx.79.Off

CBx.79.Sel_3P CBx.79.Close

CBx.79.Sel_1P/3P CBx.79.Ready

CBx.79.Trp CBx.79.AR_Blkd

CBx.79.Trp3P CBx.79.Active

CBx.79.TrpA CBx.79.Inprog

CBx.79.TrpB CBx.79.Inprog_1P

CBx.79.TrpC CBx.79.Inprog_3P

CBx.79.Lockout CBx.79.Inprog_3PS1

CBx.79.PLC_Lost CBx.79.Inprog_3PS2

CBx.79.WaitMaster CBx.79.Inprog_3PS3

CBx.79.CB_Healthy CBx.79.Inprog_3PS4

CBx.79.Clr_Counter CBx.79.WaitToSlave

CBx.79.Inhibit CBx.79.Perm_Trp1P

CBx.79.Perm_Trp3P

CBx.79.Status

CBx.79.Failed

CBx.79.Succeeded

CBx.79.Completed

CBx.79.Fail_Chk

CBx.79.Mode_1P

CBx.79.Mode_3P

CBx.79.Mode_1/3P

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3.38.3 I/O Signals

Table 3.38-2 Input signals of AR

No. Input Signal Description

1 CBx.79.Enable Input signal of enabling AR
2 CBx.79.Block Input signal of blocking AR
3 CBx.79.Sel_SynChk Input signal of selecting synchro-check for AR
Input signal of selecting dead synchronization voltage and dead reference
4 CBx.79.Sel_SynDd_RefDd
voltage check for AR
Input signal of selecting live synchronization voltage and dead reference
5 CBx.79.Sel_SynLv_RefDd
voltage check for AR 3
Input signal of selecting dead synchronization voltage and live reference
6 CBx.79.Sel_SynDd_RefLv
voltage check for AR
7 CBx.79.Sel_NoChk Input signal of selecting no check for AR
8 CBx.79.Sel_1P Input signal for selecting 1-pole AR mode
9 CBx.79.Sel_3P Input signal for selecting 3-pole AR mode
10 CBx.79.Sel_1P/3P Input signal for selecting 1/3-pole AR mode
11 CBx.79.Trp Input signal of any phase tripping from line protection to initiate AR
12 CBx.79.Trp3P Input signal of three-phase tripping from line protection to initiate AR
13 CBx.79.TrpA Input signal of A-phase tripping from line protection to initiate AR
14 CBx.79.TrpB Input signal of B-phase tripping from line protection to initiate AR
15 CBx.79.TrpC Input signal of C-phase tripping from line protection to initiate AR
Input signal of blocking reclosing, usually it is connected with the operating
16 CBx.79.Lockout signals of definite-time protection, transformer protection and busbar
differential protection, etc.
17 CBx.79.PLC_Lost Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master AR (when
18 CBx.79.WaitMaster
reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
19 CBx.79.CB_Healthy
perform the close function
20 CBx.79.Ok_3PLvChk Live three-phase check condition of AR is met
Input signal of inhibiting AR
21 CBx.79.Inhibit When the signal is initiated, the time delay of AR is stopped timing, and the
time delay of AR is continual to time when the signal drops out.
22 CBx.79.Clr_Counter Clear the reclosing counter

Table 3.38-3 Output signals of AR

No. Output Signal Description

1 CBx.79.Alm_RSYN_Mode The synchronism check mode for AR is abnormal.
2 CBx.79.On_SynChk Synchro-check for AR is selected.
Dead synchronization voltage and dead reference voltage check for AR is
3 CBx.79.On_SynDd_RefDd
selected.
4 CBx.79.On_SynLv_RefDd Live synchronization voltage and dead reference voltage check for AR is

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 3 Protection Functions

selected.
Dead synchronization voltage and live reference voltage check for AR is
5 CBx.79.On_SynDd_RefLv
selected.
6 CBx.79.On_NoChk No check for AR is selected.
7 CBx.79.On AR is enabled.
8 CBx.79.Off AR is disabled.
9 CBx.79.Close AR operates.
10 CBx.79.Ready AR have been ready for reclosing cycle.
11 CBx.79.Blocked AR is blocked.
12 CBx.79.Active AR logic is active.
3 13 CBx.79.Inprog AR cycle is in progress
14 CBx.79.Inprog_1P The first 1-pole AR cycle is in progress
15 CBx.79.Inprog_3P 3-pole AR cycle is in progress
16 CBx.79.Inprog_3PS1 First 3-pole AR cycle is in progress
17 CBx.79.Inprog_3PS2 Second 3-pole AR cycle is in progress
18 CBx.79.Inprog_3PS3 Third 3-pole AR cycle is in progress
19 CBx.79.Inprog_3PS4 Fourth 3-pole AR cycle is in progress
Waiting signal of AR which will be sent to slave (when reclosing multiple
20 CBx.79.WaitToSlave
circuit breakers)
21 CBx.79.Perm_Trp1P Single-phase circuit breaker will be tripped once protection device operates
22 CBx.79.Perm_Trp3P Three-phase circuit breaker will be tripped once protection device operates
AR status
0: AR is preprocessed.
23 CBx.79.Status 1: AR is ready.
2: AR is in progress.
3: AR is successful.
24 CBx.79.Failed Auto-reclosing fails
25 CBx.79.Succeeded Auto-reclosing is successful
26 CBx.79.Fail_Chk Synchrocheck for AR fails
27 CBx.79.Mode_1P Output of 1-pole AR mode
28 CBx.79.Mode_3P Output of 3-pole AR mode
29 CBx.79.Mode_1P/3P Output of 1/3-pole AR mode
30 CBx.79.Completed AR is completed.

3.38.4 Settings
Table 3.38-4 Settings of AR

Name Range Step Unit Default Description

The control option of
synchronism check mode for AR
Config Config: select synchronism
CBx.79.Opt_RSYN_ValidMode Setting
Setting check mode for AR by
configuration signals
Setting: select synchronism

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Name Range Step Unit Default Description

check mode for AR by the
settings
Disabled Enabling/disabling synchronism
CBx.79.En_SynChk Disabled
Enabled check for AR
Enabling/disabling dead
Disabled synchronization voltage and
CBx.79.En_SynDd_RefDd Disabled
Enabled dead reference voltage check for
AR
Enabling/disabling live

CBx.79.En_SynLv_RefDd
Disabled
Disabled
synchronization voltage and 3
Enabled dead reference voltage check for
AR
Enabling/disabling dead
Disabled
CBx.79.En_SynDd_RefLv Disabled synchronization voltage and live
Enabled
reference voltage check for AR
Disabled Enabling/disabling no check for
CBx.79.En_NoChk Disabled
Enabled AR
Maximum number of reclosing
CBx.79.Num 1~4 1 1
attempts
Dead time of first shot 1-pole
CBx.79.t_Dd_1PS1 0.000~600.000 0.001 s 0.800
reclosing
Dead time of first shot 3-pole
CBx.79.t_Dd_3PS1 0.000~600.000 0.001 s 0.600
reclosing
Dead time of second shot 3-pole
CBx.79.t_Dd_3PS2 0.000~600.000 0.001 s 0.600
reclosing
Dead time of third shot 3-pole
CBx.79.t_Dd_3PS3 0.000~600.000 0.001 s 0.600
reclosing
Dead time of fourth shot 3-pole
CBx.79.t_Dd_3PS4 0.000~600.000 0.001 s 0.600
reclosing
Time delay of circuit breaker in
CBx.79.t_CBClsd 0.000~600.000 0.001 s 5.000
closed position before reclosing
Time delay to wait for CB
healthy, and begin to timing
when the input signal
CBx.79.t_CBReady 0.000~600.000 0.001 s 5.000 [CBx.79.CB_Healthy] is de-
energized and if it is not
energized within this time delay,
AR will be blocked.
Maximum wait time for
CBx.79.t_Wait_Chk 0.000~600.000 0.001 s 10.000
synchronism check

CBx.79.t_Reclaim 0.000~600.000 0.001 s 15.000 Reclaim time of AR

CBx.79.t_DDO_Blk 0.000~600.000 0.001 s 5.000 Dropout time delay of blocking

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Name Range Step Unit Default Description

AR, when blocking signal for AR
disappears, AR blocking
condition drops out after this
time delay

CBx.79.t_AddDly 0.000~600.000 0.001 s 0.500 Additional time delay for AR

Maximum wait time for reclosing

CBx.79.t_WaitMaster 0.000~600.000 0.001 s 3.000 permissive signal from master
AR
Time delay of discriminating
3 another fault, and begin to times
after 1-pole AR initiated, 3-pole
CBx.79.t_SecFault 0.000~600.000 0.001 s 0.300 AR will be initiated if another fault
happens during this time delay.
AR will be blocked if another fault
happens after that.
Time delay of excessive trip
CBx.79.t_PersistTrp 0.000~600.000 0.001 s 0.200
signal to block AR
Time delay allow for CB status
CBx.79.t_Fail 0.000~600.000 0.001 s 0.200 change to conform reclosing
successfully

CBx.79.t_PW 0.000~600.000 0.001 s 0.120 Pulse width of AR closing signal

Enabling/disabling auto-
Disabled
CBx.79.En_AddDly Disabled reclosing with an additional dead
Enabled
time delay
Enabling/disabling confirm
Disabled
CBx.79.En_FailCheck Disabled whether AR is successful by
Enabled
checking CB state
Enabling/disabling auto-
Disabled reclosing blocked when a fault
CBx.79.En_PDF_Blk Disabled
Enabled occurs under pole disagreement
condition
Disabled Enabling/disabling adjust the
CBx.79.En_CutPulse Disabled
Enabled length of reclosing pulse
Disabled Enabling/disabling auto-
CBx.79.En Enabled
Enabled reclosing
Enabling/disabling AR by
external input signal besides
Setting logic setting [CBx.79.En]
CBx.79.Opt_Enable Setting
Setting&Config Setting: only the setting
Setting&Config: the setting and
configuration signal
CBx.79.En_CBInit Disabled Disabled Enabling/disabling AR be

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Name Range Step Unit Default Description

Enabled initiated by open state of circuit
breaker
Option of AR priority
None: single-breaker
None arrangement
CBx.79.Opt_Priority High None High: master AR of multi-breaker
Low arrangement
Low: slave AR of multi-breaker
arrangement
Control option of AR mode 3
Config: select AR mode by
Config
CBx.79.Opt_ValidMode Setting configuration signals
Setting
Setting: select AR mode by the
settings
Disabled Enabling/disabling 1-pole AR
CBx.79.En_1P Disabled
Enabled mode
Disabled Enabling/disabling 3-pole AR
CBx.79.En_3P Enabled
Enabled mode
Disabled Enabling/disabling 1/3-pole AR
CBx.79.En_1P/3P Disabled
Enabled mode

3.39 VT Circuit Supervision (VTS)

The purpose of VT circuit supervision is to detect whether VT circuit is normal. Because some
protection functions, such as distance protection, under-voltage protection and so on, will be
influenced by VT circuit failure, these protection functions should be disabled when VT circuit fails.

VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.

1. Line VT is used as protection VT and the protected line is out of service.

2. Only current protection functions are enabled and VT is not connected to the device.

3.39.1 Function Description

VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection
VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit
failure signal will be activated if residual voltage exceeds the threshold value, or negative-sequence
voltage exceeds the threshold value or positive-sequence voltage is lower than the threshold value.
If the device is triggered to pick up by phase overcurrent protection, earth fault protection, current
differential protection, fault detector, distance protection and breaker failure protection, the time
delay timer of VT circuit supervision will be paused until these protection functions returns to normal

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 3 Protection Functions

state.

Under normal conditions, the device detect residual voltage greater than the setting [VTS.3U0_Set]
or negative-sequence voltage greater than the setting [VTS.U2_Set] to determine single-phase or
two-phase VT circuit failure, and detect positive-sequence voltage less than the setting
[VTS.U1_Set] to determine three-phase VT circuit failure. Upon detecting abnormality on VT circuit,
an alarm will comes up with the time delay [VTS.t_DPU] and drop off with the time delay
[VTS.t_DDO] after VT circuit restored to normal. Upon abnormality detection on VT circuit, an
instantaneous alarm will be issued after a time delay of 25ms and drop off without time delay.

VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary input
3 circuit of the device. If MCB is open (i.e. [VTS.MCB_VT] is energized), the device will consider the
VT circuit is in open state and issues an alarm without a time delay. If the auxiliary contact is not
connected to the device, VT circuit supervision will be issued with time delay as mentioned in
previous paragraph.

When VT is not connected into the device, the alarm will be not issued if the setting [Prot.En_VT]
is set as "Disabled". However, the alarm is still issued if the binary input [VTS.MCB_VT] is energized,
no matter that the setting [Prot.En_VT] is set as "Enabled" or "Disabled".

3.39.2 Function Block Diagram

VTS

VTS.Enable VTS.Alm

VTS.Block VTS.InstAlm

VTS.MCB_VT

3.39.3 I/O Signals

Table 3.39-1 Input signals of VT circuit supervision

No. Input Signal Description

1 VTS.Enable Input signal of enabling VT circuit supervision
2 VTS.Block Input signal of blocking VT circuit supervision
3 VTS.MCB_VT Binary input for VT MCB auxiliary contact

Table 3.39-2 Output signals of VT circuit supervision

No. Output Signal Description

1 VTS.Alm Alarm signal to indicate VT circuit fails
2 VTS.InstAlm Instantaneous alarm signal to indicate VT circuit failure

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3.39.4 Logic

Pickup flag

SET 3U0>[VTS.3U0_Set] >=1

SET U2>[VTS.U2_Set]

SET U1<[VTS.U1_Set]
>=1
SET [VTS.Opt_VT]=Bay &
SIG 52b_PhA
>=1
& &
The device picks up triggered by specific
SIG 52b_PhB >=1 protection functions, the timer of time
SIG 52b_PhC delay will be paused.

SIG Ip>0.04In
[VTS.t_DPU] [VTS.t_DDO] &
3
EN [Prot.En_VT] &

SIG Prot.BI_En_VT >=1

&
SIG [VTS.MCB_VT] VTS.Alm

EN [VTS.En]
&
SIG VTS.Enable

SIG VTS.Block

Figure 3.39-1 Logic of VT circuit supervision (delay alarm)

Pickup flag

SET 3U0>[VTS.3U0_Set] >=1

SET U2>[VTS.U2_Set]

SET U1<[VTS.U1_Set]
>=1
SET [VTS.Opt_VT]=Bay &
SIG 52b_PhA
>=1
& &
The device picks up triggered by specific
SIG 52b_PhB >=1 protection functions, the timer of time
SIG 52b_PhC delay will be paused.
25ms 0 &
SIG Ip>0.04In

EN [Prot.En_VT] &

SIG Prot.BI_En_VT >=1

&
SIG [VTS.MCB_VT] VTS.InstAlm

EN [VTS.En]
&
SIG VTS.Enable

SIG VTS.Block

Figure 3.39-2 Logic of VT circuit supervision (instantaneous alarm)

Where:

Ip is one measured phase current, i.e. Ia or Ib or Ic.

Specific protection functions include phase overcurrent protection, earth fault protection, current
differential protection, fault detector, distance protection and breaker failure protection.

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 3 Protection Functions

If there is already a VTS alarm before the device is triggered to pick up by specific protection
functions, VTS will continue to block distance protection, that is VTS will be latched when the device
picks up. If the device is triggered to pick up by specific protection functions, and VT circuit failure
signal have been detected, then the VT circuit failure signal will be maintained (i.e., the timer of
time delay will be paused.), only when the device′s pickup state drops off, VT circuit supervision
will return to normal operation.

3.39.5 Settings
Table 3.39-3 Settings of VT circuit supervision

3 Name Range
Disabled
Step Unit Default Remark

VTS.En Enabled Enabling/disabling VT circuit supervision

Enabled
Voltage selection for protection calculation from
Bus busbar VT or line VT
VTS.Opt_VT Bus
Bay Bus: busbar VT
Bay: bay VT
VTS.t_DPU 0.200~30.000 0.001 s 1.250 Pickup time delay of VT circuit supervision
VTS.t_DDO 0.200~30.000 0.001 s 10.000 Dropoff time delay of VT circuit supervision
Positive-sequence voltage setting of VT circuit
VTS.U1_Set 0.00~100.00 0.01 V 30.00
supervision
Zero-sequence voltage setting of VT circuit
VTS.3U0_Set 0.00~100.00 0.01 V 8.00
supervision
Negative-sequence voltage setting of VT circuit
VTS.U2_Set 0.00~100.00 0.01 V 8.00
supervision

3.40 CT Circuit Supervision (CTS)

The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit.
When CT secondary circuit is abnormal, the current acquired by the device is not accurate, which
will affect protection functions related to the current. Therefore, it is necessary to monitor the CT
abnormal condition. When CT abnormality is detected, the device shall issue an alarm signal and
block the relevant protection functions.

For double circuit breakers mode, the device will provide independent CT
circuit supervision function for CB1 and CB2 respectively. Both CT circuit
supervision functions have the same logic. The difference is that the prefix
“CBx.” is added to all signals for circuit breaker No.x (x=1 or 2).

3.40.1 Function Description

Under normal conditions, CT secondary signal is continuously supervised by detecting the residual
current and voltage. If residual current is larger than the setting [CBx.CTS.3I0_Set] whereas

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residual voltage is less than the setting [CBx.CTS.3U0_Set], and any phase current is less than
0.04In, CT circuit failure is considered. The concerned protection functions are blocked and an
alarm is issued with the time delay [CBx.CTS.t_DPU] and drop out with the time delay
[CBx.CTS.t_DDO] after CT circuit is restored to normal condition.

3.40.2 Function Block Diagram

CTS

CBx.CTS.Enable CBx.CTS.On

CBx.CTS.Block CBx.CTS.Blocked

CBx.CTS.Valid
3
CBx.CTS.Alm

3.40.3 I/O Signals

Table 3.40-1 Input signals of CT circuit supervision

No. Input Signal Description

1 CBx.CTS.Enable Input signal of enabling CT circuit supervision
2 CBx.CTS.Block Input signal of blocking CT circuit supervision

Table 3.40-2 Output signals of CT circuit supervision

No. Output Signal Description

1 CBx.CTS.On CT circuit supervision is enabled.
2 CBx.CTS.Blocked CT circuit supervision is blocked.
3 CBx.CTS.Valid CT circuit supervision is valid.
4 CBx.CTS.Alm Alarm signal to indicate CT circuit fails

3.40.4 Logic

EN [CBx.CTS.En] &
CBx.CTS.On
SIG CBx.CTS.Enable
&
SIG CBx.CTS.Block >=1 CBx.CTS.Blocked

SIG Fail_Device
&
CBx.CTS.Valid

Figure 3.40-1 Logic of enabling CT circuit failure

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SIG CBx.CTS.Valid

SET 3I0>[CBx.CTS.3I0_Set]
&
& [CBx.CTS.t_DPU] [CBx.CTS.t_DDO] CBx.CTS.Alm
SET 3U0<[CBx.CTS.3U0_Set]

SIG Ia<0.04In
>=1
SIG Ib<0.04In

SIG Ic<0.04In

Figure 3.40-2 Logic of CT circuit failure

3.40.5 Settings
3
Table 3.40-3 Settings of CT circuit supervision

Name Range Step Unit Default Remark

Zero-sequence current setting of CT circuit
CBx.CTS.3I0_Set 0.00~200.00 0.01 A 0.10
supervision
Zero-sequence voltage setting of CT circuit
CBx.CTS.3U0_Set 0.00~200.00 0.01 V 30.00
supervision
CBx.CTS.t_DPU 0.000~100.000 0.001 s 10.000 Pickup time delay of CT circuit supervision
CBx.CTS.t_DDO 0.000~100.000 0.001 s 10.000 Dropoff time delay of CT circuit supervision
Disabled
CBx.CTS.En Enabled Enabling/disabling CT circuit supervision
Enabled

3.41 Impedance-Based Fault Location (FL)

The main objective of line protection is fast, selective and reliable operation for faults on a protected
line section. Besides this, information on distance to fault is very important for those involved in
operation and maintenance. Reliable information on the fault location greatly decreases the outage
of the protected lines and increases the total availability of a power system.

For a permanent fault, it is necessary to find out and eliminate the fault point and as soon as
possible so as to reduce the time of power off. Therefore, accurate fault location is very important.
This fault location function cannot be used for the transmission line with series compensation.

3.41.1 Function Description

Single-end fault location is available in the device. Fault location picks up after the device operates
to trip when there is a fault in the line. If the pickup time is greater than 25ms, fault location is
calculated with a time delay of 10ms after the device operates to trip. If the pickup time is smaller
than 25ms, fault location is calculated with a time delay of 20ms after the device operates to trip.

When the faulty phase detected there is a protection tripping and the calculation of the fault
impedance is initiated. According to the fault impedance to locate the fault point, two calculation
results are provided, which is the length of the fault point distance from the end of the device and
its percentage of the lines length.

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For parallel lines, there is a mutual coupling between each phase, and also a mutual coupling
between parallel lines. The coupling strength between parallel lines associated with the
transposition way. For parallel lines with fully transposition, positive-sequence and negative-
sequence mutual coupling is very small, and usually can be ignored. But zero-sequence mutual
coupling has a greater influence on the line, so the measured impedance must consider the effect.

3.41.1.1 Mutual Coupling Compensation

When an earth fault happens to parallel lines in the same tower, the voltage of faulty phase is
determined by both the current of local line and zero-sequence current of the adjacent line.
Therefore, there will be a larger error in the measured phase-to-ground impedance, which will affect
the result of fault location.
3
A Ia B

ZM
k

C Ic D
kZL (1-k)ZL
ZS

ZL

Figure 3.41-1 Schematic diagram of mutual coupling for parallel lines

For fault location of parallel lines, mutual coupling compensation is necessary to improve the
precision of fault location. Practically, the mutual coupling between the parallel lines is insignificant
to positive-sequence loop and negative-sequence loop and thus the mutual coupling compensation
is only for zero-sequence loop.

With the aid of sequence network, the principle of mutual coupling compensation is as below. The
equivalent sequence network for an earth fault on parallel lines with single source is shown as
Figure 3.41-2, which indicates parallel lines with an earth fault at location k on line CD.

Ia1 ZL1
ZS1
kZL1 (1-k)ZL1
Ic1

Ia2 ZL2
ZS2
kZL2 (1-k)ZL2
Ic2

Ia0 ZL0

ZS0
Z0M
kZL0 (1-k)ZL0
Ic0

Figure 3.41-2 Equivalent sequence network

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 3 Protection Functions

Where:

ZS1 is system equivalent positive-sequence impedance at the fault point.

ZS2 is system equivalent negative-sequence impedance at the fault point.

ZS0 is system equivalent zero-sequence impedance at the fault point.

The device at location C without mutual coupling compensation will have voltage U RC and current
IRC measured as shown in the expression.

𝑈𝑅𝐶 = (𝑘 × 𝑍𝐿1 × 𝐼𝑐1 + 𝑘 × 𝑍𝐿2 × 𝐼𝑐2 + 𝑘 × 𝑍𝐿0 × 𝐼𝑐0 ) + 𝑘 × 𝑍0𝑀 × 𝐼𝑎0

3 If the line is fully transposed, ZL1=ZL2, then

𝑍𝐿0 𝑍0𝑀
𝑈𝑅𝐶 = 𝑘 × 𝑍𝐿1 × [𝐼𝑐1 + 𝐼𝑐2 + ( ) × 𝐼𝑐0 + ( ) × 𝐼𝑎0 ]
𝑍𝐿1 𝑍𝐿1

𝑍𝐿0 𝑍𝐿0
𝐼𝑅𝐶 = 𝐼𝑐1 + 𝐼𝑐2 + 𝐼𝑐0 + ( − 1) × 𝐼𝑐0 = 𝐼𝑐1 + 𝐼𝑐2 + ( ) × 𝐼𝑐0
𝑍𝐿1 𝑍𝐿1

The impedance presented to the device is:

𝑍𝐿0 𝑍0𝑀
𝑈𝑅𝐶 𝑘 × 𝑍𝐿1 × [𝐼𝑐1 + 𝐼𝑐2 + (𝑍𝐿1 ) × 𝐼𝑐0 + ( 𝑍𝐿1 ) × 𝐼𝑎0 ]
𝑍𝑅𝐶 = =
𝐼𝑅𝐶 𝑍
𝐼𝑐1 + 𝐼𝑐2 + (𝑍𝐿0 ) × 𝐼𝑐0
𝐿1

𝑍0𝑀 𝐼𝑎0
𝑍𝑅𝐶 = 𝑍𝐿1 × [1 + ]
𝑍𝐿1 × 𝐼𝑐1 + 𝑍𝐿1 × 𝐼𝑐2 + 𝑍𝐿0× 𝐼𝑐0

For an earth fault, 𝐼𝑐1 = 𝐼𝑐2 = 𝐼𝑐0

𝑍0𝑀 𝐼𝑎0
𝑍𝑅𝐶 = 𝐾 × 𝑍𝐿1 × [1 + × ]
2𝑍𝐿1 + 𝑍𝐿0 𝐼𝑐0

When mutual coupling compensation enabled, then

𝑍𝐿0 𝑍𝑀0 𝑍𝐿0 𝑍𝑀0

𝐼𝑅𝐶 = 𝐼𝑐1 + 𝐼𝑐2 + 𝐼𝑐0 + ( − 1) × 𝐼𝑐0 + ( ) × 𝐼𝑎0 = 𝐼𝑐1 + 𝐼𝑐2 + ( ) × 𝐼𝑐0 + ( ) × 𝐼𝑎0
𝑍𝐿1 𝑍𝐿1 𝑍𝐿1 𝑍𝐿1

𝑍𝐿0 𝑍0𝑀
𝑈𝑅𝐶 𝑘 × 𝑍𝐿1 × [𝐼𝑐1 + 𝐼𝑐2 + (𝑍𝐿1 ) × 𝐼𝑐0 + ( 𝑍𝐿1 ) × 𝐼𝑎0 ]
𝑍𝑅𝐶 = =
𝐼𝑅𝐶 𝑍 𝑍
𝐼𝑐1 + 𝐼𝑐2 + (𝑍𝐿0 ) × 𝐼𝑐0 + ( 𝑍𝑀0 ) × 𝐼𝑎0
𝐿1 𝐿1

𝑍𝑅𝐶 = 𝑘 × 𝑍𝐿1 (Actual distance of the fault)

The residual current from the parallel line should be added to the device when considering mutual
coupling compensation for parallel lines.

3.41.1.2 Fault Location Algorithm

The device adopts single-end fault location, which only uses the measured value of the voltage and
the current at one end. The error is mainly from the effect of fault resistance of fault point and infeed
current from power source of the opposite end.

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As shown in Figure 3.41-3, when a short-circuit fault with fault resistance occurs, additional voltage
will be generated in the fault resistance by infeed current from power source of the opposite end,
which will have a great impact on the measurement result. Generally, the larger the fault resistance
is, the larger the impact will be.

UM UN
EM ZM ZF ZL-ZF ZN EN

IM IN
Bus M Bus N
IF RF

3
Figure 3.41-3 Equivalent circuit of single-phase fault with fault resistance

Where:

𝑈̇𝑀 is busbar voltage at side M.

̇ is line phase current at side M.

𝐼𝑀

𝐼0̇ is line zero-sequence current at side M.

𝐼𝐹̇ is the fault current of fault resistance.

𝐾0 is zeros-sequence compensation coefficient

𝑅𝐹 is fault resistance.

𝑈̇𝑀 = (𝐼𝑀
̇ + 𝐾0 × 3𝐼0̇ ) × 𝑍𝐹 + 𝐼𝐹̇ × 𝑅𝐹

3𝐼0̇
𝐼𝐹̇ =
𝐶𝑀0
𝑍𝑁0 + 𝑍𝐿0 − 𝑍𝐹0 Equation 3.41-1
𝐶𝑀0 =
𝑍𝑀0 + 𝑍𝑁0 + 𝑍𝐿0

𝑍𝐹0 − 𝑍𝐹1
𝐾0 =
3𝑍𝐹1

𝐶𝑀0 is zero-sequence distribution coefficient at side M.

𝑍𝑀0 is zero-sequence impedance at side M.

𝑍𝑁0 is zero-sequence impedance at side N.

𝑍𝐿0 is line zero-sequence impedance.

𝑍𝐹1 is line positive-sequence impedance from side M to fault point.

𝑍𝐹0 is line zero-sequence impedance from side M to fault point.

𝑈̇𝑀 , 𝐼𝑀
̇ and 𝐼0̇ can be measured. Because the parameters of zero-sequence impedance circuit
between the system at both sides are generally similar. 𝐶𝑀0 can be approximately thought as real

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 3 Protection Functions

number. Therefore, 𝑍𝐹1 can be calculated by Equation 3.41-1.

3𝐼0̇
𝑈̇𝑀 = (𝐼𝑀
̇ + 𝐾0 × 3𝐼0̇ ) × 𝑍𝐹1 + × 𝑅𝐹 Equation 3.41-2
𝐶𝑀0

The two ends are multiplied by conjugate complex number of İ0.

3|𝐼0 |2
𝐼0′ × 𝑈̇𝑀 = (𝐼𝑀
̇ + 𝐾0 × 3𝐼0̇ ) × 𝐼0′ × 𝑍𝐹1 + × 𝑅𝐹 Equation 3.41-3
𝐶𝑀0

Take the imaginary part of Equation 3.41-3,

𝐼𝑚[𝐼0′ × 𝑈̇𝑀 ] = 𝐼𝑚[(𝐼𝑀

̇ + 𝐾0 × 3𝐼0̇ ) × 𝐼0′ × 𝑍𝐹1 ]
3 Equation 3.41-4

The result of fault location can be obtained directly by solving ZF1 .

The distance from the location of the device to the fault point (i.e., Fault Location) is:

𝐼𝑚[𝑍𝐹1 ]
𝐹𝑎𝑢𝑙𝑡 𝐿𝑜𝑐𝑎𝑡𝑖𝑜𝑛 = × 𝐿𝑖𝑛𝑒 𝐿𝑒𝑛𝑔𝑡ℎ (𝑘𝑚)
𝑋1𝐿

𝐹𝑎𝑢𝑙𝑡 𝐿𝑜𝑐𝑎𝑡𝑖𝑜𝑛
𝐹𝑎𝑢𝑙𝑡 𝐿𝑜𝑐𝑎𝑡𝑖𝑜𝑛 (𝑃𝑒𝑟𝑐𝑒𝑛𝑡) = × 100%
𝐿𝑖𝑛𝑒 𝐿𝑒𝑛𝑔𝑡ℎ

Where:

𝑍𝐹1 is the measured impedance from the location of the device to the fault point.

𝑋1𝐿 is line positive-sequence impedance.

Line Length is the length of transmission line (km)

3.41.2 Function Block Diagram

FL

FPS_Fault Fault_Location

FD.Pkp Fault_Phase

PhSA Fault_PhaseA_Volt

PhSB Fault_PhaseB_Volt

PhSC Fault_PhaseC_Volt

Trp Fault_PhaseA_Curr

Fault_PhaseB_Curr

Fault_PhaseC_Curr

Fault_Resid_Volt

Fault_Resid_Curr

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3.41.3 I/O Signals

Table 3.41-1 Input signals of fault location

No. Input Signal Description

1 FPS_Fault Faulty phase selection
2 FD.Pkp The device picks up
3 PhSA Phase-A is selected as faulty phase
4 PhSB Phase-B is selected as faulty phase
5 PhSC Phase-C is selected as faulty phase
6 Trp Input signal of protection tripping

Table 3.41-2 Output signals of fault location

3
No. Output Signal Description
1 Fault_Location The result of fault location
2 Faulty_Phase The selected faulty phase
3 Fault_PhaseA_Volt Phase-A faulty voltage at the moment of fault location
4 Fault_PhaseB_Volt Phase-B faulty voltage at the moment of fault location
5 Fault_PhaseC_Volt Phase-C faulty voltage at the moment of fault location
6 Fault_PhaseA_Curr Phase-A faulty current at the moment of fault location
7 Fault_PhaseB_Curr Phase-B faulty current at the moment of fault location
8 Fault_PhaseC_Curr Phase-C faulty current at the moment of fault location
9 Fault_Resid_Volt Faulty residual voltage
10 Fault_Resid_Curr Faulty residual current

3.41.4 Settings
Table 3.41-3 Settings of fault location

Name Range Step Unit Default Description

Positive-sequence reactance of the whole line
X1L (0.000~4Unn)/In 0.001 Ω 10.000
(secondary value)
Positive-sequence resistance of the whole line
R1L (0.000~4Unn)/In 0.001 Ω 1.000
(secondary value)
Zero-sequence reactance of the whole line
X0L (0.000~4Unn)/In 0.001 Ω 20.000
(secondary value)
Zero-sequence resistance of the whole line
R0L (0.000~4Unn)/In 0.010 Ω 3.000
(secondary value)
Zero-sequence mutual reactance (secondary
X0M (0.000~4Unn)/In 0.001 Ω 20.000
value)
Zero-sequence mutual resistance of the whole
R0M (0.000~4Unn)/In 0.001 Ω 3.000
line (secondary value)
LineLength 0.00~6000.00 0.01 km 100.00 Total length of the whole line
Voltage setting of MOV (Metal-oxide Varistor) in
U_MOV_Prot 0.000~200.000 0.001 V 30.000
series compensated line
Disabled Enabling/disabling series capacitor
En_SerCmp Disabled
Enabled compensation

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4 Control Functions

Table of Contents

4.1 Switchgear Control .......................................................................................... 4-1

4.1.1 Function Description............................................................................................................. 4-1

4.1.2 Function Block Diagram ....................................................................................................... 4-4

4.1.3 I/O Signals ............................................................................................................................ 4-5

4.1.4 Logic ..................................................................................................................................... 4-7

4.1.5 Settings................................................................................................................................. 4-9

4
4.2 Synchronism Check (25) ............................................................................... 4-10
4.2.1 Function Description........................................................................................................... 4-11

4.2.2 Function Block Diagram ..................................................................................................... 4-13

4.2.3 I/O Signals .......................................................................................................................... 4-13

4.2.4 Logic ................................................................................................................................... 4-15

4.2.5 Settings............................................................................................................................... 4-18

4.3 Voltage Selection ........................................................................................... 4-22

4.3.1 Function Description........................................................................................................... 4-22

4.3.2 Function Block Diagram ..................................................................................................... 4-25

4.3.3 I/O Signals .......................................................................................................................... 4-25

4.3.4 Logic ................................................................................................................................... 4-26

4.3.5 Settings............................................................................................................................... 4-28

List of Figures

Figure 4.1-1 Logic of closing operation .................................................................................... 4-7

Figure 4.1-2 Logic of open operation ........................................................................................ 4-7

Figure 4.1-3 DPS synthesis logic............................................................................................... 4-8

Figure 4.1-4 DPS alarm logic...................................................................................................... 4-8

Figure 4.1-5 Trip counter triggering logic ................................................................................. 4-8

Figure 4.1-6 Interlocking logic ................................................................................................... 4-9

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Figure 4.1-7 Manual control logic .............................................................................................. 4-9

Figure 4.2-1 Relationship between reference and synchronous voltages ......................... 4-11

Figure 4.2-2 Synchronism check logic ................................................................................... 4-15

Figure 4.2-3 Synchronism check logic ................................................................................... 4-16

Figure 4.2-4 Dead check logic.................................................................................................. 4-18

Figure 4.3-1 Voltage connection 1 for double busbars ......................................................... 4-23

Figure 4.3-2 Voltage connection 2 for double busbars ......................................................... 4-23

Figure 4.3-3 Voltage connection for one-and-half circuit breakers ..................................... 4-24

Figure 4.3-4 Voltage selection for double busbars (Three-phases voltages of busbars) . 4-26

Figure 4.3-5 Voltage selection for double busbars (Single-phase voltage of busbars) .... 4-27
4
Figure 4.3-6 Voltage selection for one-and-half circuit breakers (bus CB)......................... 4-27

Figure 4.3-7 Voltage selection for one-and-half circuit breakers (tie CB) ........................... 4-28

List of Tables

Table 4.1-1 Remote/Local control mode switch logic ............................................................. 4-2

Table 4.1-2 Input signals of control function............................................................................ 4-5

Table 4.1-3 Output signals of control function......................................................................... 4-5

Table 4.1-4 DPS settings ............................................................................................................. 4-9

Table 4.1-5 Control settings ..................................................................................................... 4-10

Table 4.1-6 Interlocking settings .............................................................................................. 4-10

Table 4.2-1 Input signals of manual closing synchronism check ........................................ 4-13

Table 4.2-2 Output signals of manual closing synchronism check ..................................... 4-14

Table 4.2-3 Settings of synchronism check ........................................................................... 4-18

Table 4.3-1 Input signals of voltage selection ........................................................................ 4-25

Table 4.3-2 Output signals of voltage selection ..................................................................... 4-26

Table 4.3-3 Settings of voltage selection ................................................................................ 4-28

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 4 Control Functions

4.1 Switchgear Control

The switchgear control function is mainly used to realize operation of primary equipment such as
circuit breaker (CB), disconnect switch (DS) and earthing switch (ES). This function can be divided
into remote control and local control according to the control source location. A remote control
mainly refers to remote control commands from substation automation system (SAS) or network
control center (NCC). However, a control triggered manually from the device LCD, by a terminal
contact or by a panel handle is a local control. The switchgear control function is closely related to
interlocking, double point status (DPS), remote/local control mode switching and trip counter.

4.1.1 Function Description

A control command can realize various control signals such as the CB/DS/ES opening/closing. In
order to ensure the reliability of the control output, a locking circuit is added to each control object.
The operation is strictly in accordance with the selection, check and execution steps, to ensure that 4
the control operation can be safely and reliably implemented. In addition, the device has a hardware
self-checking and blocking function to prevent hardware damage from maloperation output. When
the device is in the remote control mode, the control command may be sent via communication
protocol. When it is in the local control mode, the local operation may be performed on the device
LCD or panel handle. A complete control process is:

1. Protocol module sends a selection command;

2. Control module responds the success or failure result of selection;

3. If the selection is successful, the protocol module sends an execution command, otherwise it
sends a cancel command;

4. Control module responds the success or failure result of execution;

5. The control operation may be open/close or up/down/stop.

When the device is in the maintenance status, it can still respond to local control commands. The
switchgear control function can cooperate with functions such as synchronism check and
interlocking criteria calculation to complete the output of the corresponding operation command. It
can realize the normal control output in one bay and the interlocking and programmable logic
configuration between bays. This device supports the following functional control module:

Module Description
CSWI Control of circuit breaker (CB), disconnector switch (DS) or earthing switch (ES)
RMTLOC Remote or local control mode
XCBR Synthesis of CB position, three-phase or phase separated
XSWI Synthesis of DS/ES position
SXCBR/SCSWI Trip counter of CB/DS/ES
RSYN Synchronism check for CB closing
CILO Interlocking logic for CB/DS/ES control
MCSWI Manual control of CB/DS/ES

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 4 Control Functions

Module Description
CHKPOS Position verification for switchgear control

The initiation of a control command may be sent to the device by the SCADA or the NCC through
communication protocol. It may also be the LCD operation of the device or the manual triggering
through configured signal. The command is sent by the CPU to the control module for processing,
and a control record is made on the CPU module according to the control result.

4.1.1.1 Remote/Local Control Mode Switch

Since the source of a control command may be SAS or NCC, or may be triggered by the device
LCD or terminal contact, it is necessary to provide a remote/local control mode switch function. The
remote/local control mode switch function determines whether the device is in the remote or the
local control permission state through the configuration of terminal contact, function key, or binary
signal. Each control object provides a remote/local input, and the control module determines the

4 current control authority to be remote or local according to the input value. By default, if the input
is not configured, any control operation is blocked.

Table 4.1-1 Remote/Local control mode switch logic

in_Remote in_Local Remote Control Local Control

NULL NULL Disable Disable
0 NULL Disable Enable
1 NULL Enable Disable
NULL 0 Enable Disable
NULL 1 Disable Enable
0 0 Disable Disable
0 1 Disable Enable
1 0 Enable Disable
1 1 Enable Enable

4.1.1.2 Double Point Status

A double point status (DPS), which usually indicates switchgear status, can be derived from 2
ordinary binary inputs. The signification of a DPS is shown in the following table. For switchgear
status, only the 2 statuses "01" and "10" indicating respectively the positions opening and closing
are valid. The other 2 statuses "00" and "11", i.e. intermediate or bad status, will cause the alarm
"xx.DPS.Alm".

DPS Bit0=0 Bit0=1

Bit1=0 DPS_INT DPS_OFF
Bit1=1 DPS_ON DPS_BAD

The unit also supports the DPS synthesis through switchgear opening and closing positions after
jittering processing. The synthetic DPS contains original SOE timestamp. The CB control function
supports phase-segregated position inputs and can synthesize these inputs into general position.
In accordance with the control object, the DPS synthesis function is divided into 2 modules: XCBR
and XSWI. The XCBR is mainly used for CB position synthesis, including phase-segregated

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 4 Control Functions

positions, while the XSWI is used DS or ES position synthesis. For the convenient use in user-
defined logic programming, this functional module derives four single-bit outputs to indicate each
DPS state. The relationship between DPS state and indication signals is:

DPS State DPS_ON DPS_OFF DPS_INT DPS_BAD

ON 1 0 0 0
OFF 0 1 0 0
INT 0 0 1 0
BAD 0 0 0 1

4.1.1.3 Trip Counter

The trip counter function takes the DPS of switchgear position as input count the trip times. For CB,
this device supports phase-segregated and general trip counter. The trip counter function is
triggered by DPS change. The counting result is stored in non-volatile memory for power-off holding.
Use the clear command from the menu in local LCD or customized binary signal to reset trip counter.
4
4.1.1.4 Interlocking

The interlocking function will influence the control operation output. When the function is enabled,
the device determines whether the control operation is permitted based on the interlocking logic
result. Each control object is equipped with an independent interlocking logic which supports
unlocking operation through a binary signal. The interlocking function is very important for the
control operation of switchgears. During the operation of primary equipment, the positions of the
relevant equipment must be correct for operation permission. For remote control, i.e. command
from SAS or NCC, this device could judge the interlocking logic depending on the message within
the command; for local control through device LCD or terminal contact, please use the
corresponding logic setting to enable/disable the interlocking function. The signal
"Sig_CILOChk_Failed" is generated when the control operation interlocking check of any control
object fails, and the signal lasts for 2s before automatically dropping off.

4.1.1.5 Manual Control

The switchgear control function supports manual control function that can be configured with a
terminal contact or binary signal to trigger the control operation. The manual control function
supports the control input configuration of selection and open/close. When the control object
selection input is configured, the signal "1" indicates that the current control object has to be
selected before a control operation; if the control object selection input is not configured, the control
command can be directly issued without judgment of selection.

4.1.1.6 Direct Control

For applications such as signal reset and function enable/disable, the control mode is generally
direct control, i.e. execution without selection before, direct control with normal security in IEC
61850. The direct control function provides remote/local switch and interlocking configurations. The
control command is usually issued directly by the SAS. It also supports the command triggered by
binary signal.

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 4 Control Functions

4.1.1.7 Switchgear Position Verification

The position verification function is provided during switchgear control process. In a control function
block of circuit breaker, disconnector or earthing switch, if the input "xx.in_En_ChkPos" is set as
"1", the CB/DS/ES position shall be verified when receiving a remote or local control command.
The verification logic complies with IEC 61850 standard is:

⚫ A control object only permits to be opened when its DPS is CLOSE

⚫ A control object only permits to be closed when its DPS is OPEN

⚫ The device shall respond control command failed with the cause of failure when its DPS is INT,
BAD or opposite (i.e. OPEN while opening or CLOSE while closing).

4.1.2 Function Block Diagram

4
CSWI: XCBR

in_Remote

in_Local

in_NO_DPS

in_NC_DPS

in_NO_DPS_A

in_NC_DPS_A

in_NO_DPS_B

in_NC_DPS_B

CSWI: XSWI
in_NO_DPS_C

in_NC_DPS_C in_Remote

in_N_Trp in_Local

in_N_Trp_A in_NO_DPS

in_N_Trp_B in_NC_DPS

in_N_Trp_C in_N_Trp

in_Rsyn in_Clr_Cnt CSWI: DONS

in_En_Opn in_En_Opn in_Remote

in_En_Cls in_En_Cls in_Local

in_Bypass_CILO in_Bypass_CILO in_En_Opn

in_ManSel in_ManSel in_En_Cls

in_ManOpn in_ManOpn in_Bypass_CILO

in_ManCls in_ManCls in_ManOpn

in_En_ChkPos in_En_ChkPos in_ManCls

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 4 Control Functions

XCBR: circuit breaker

XSWI: disconnector switch or earthing switch

DONS: direct control object

The prefix "xx" can be CB** (for circuit breaker), DS** (for disconnector
switch) or DirCtrl** for direct control object in the following lists

4.1.3 I/O Signals

Table 4.1-2 Input signals of control function

No. Input Signal Description

1
2
xx.in_Remote
xx.in_Local
Remote control mode
Local control mode
4
3 xx.in_NO_DPS Normally opened contact input for DPS opening position
4 xx.in_NC_DPS Normally closed contact input for DPS closing position
5 xx.in_NO_DPS_A Phase A normally opened contact input for DPS opening position
6 xx.in_NC_DPS_A Phase A normally closed contact input for DPS closing position
7 xx.in_NO_DPS_B Phase B normally opened contact input for DPS opening position
8 xx.in_NC_DPS_B Phase B normally closed contact input for DPS closing position
9 xx.in_NO_DPS_C Phase C normally opened contact input for DPS opening position
10 xx.in_NC_DPS_C Phase C normally closed contact input for DPS closing position
11 xx.in_N_Trp Opening command for trip counter
12 xx.in_N_Trp_A Phase A opening command for trip counter
13 xx.in_N_Trp_B Phase B opening command for trip counter
14 xx.in_N_Trp_C Phase C opening command for trip counter
15 xx.in_Clr_Cnt Clear trip counters
16 xx.in_Rsyn Pointer to the structure of synchronism check element
17 xx.in_En_Opn Opening permission for interlocking
18 xx.in_En_Cls Closing permission for interlocking
19 xx.in_Bypass_CILO Bypass for interlocking
20 xx.in_ManSel Selection for manual control
21 xx.in_ManOpn Opening for manual control
22 xx.in_ManCls Closing for manual control
23 xx.in_En_ChkPos Input signal of enabling of position verification function for switchgear control

Table 4.1-3 Output signals of control function

No. Output Signal Description

1 xx.NO_DPS DPS opening position
2 xx.NC_DPS DPS closing position
3 xx.NO_DPS_A Phase A DPS opening position
4 xx.NC_DPS_A Phase A DPS closing position

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 4 Control Functions

No. Output Signal Description

5 xx.NO_DPS_B Phase B DPS opening position
6 xx.NC_DPS_B Phase B DPS closing position
7 xx.NO_DPS_C Phase C DPS opening position
8 xx.NC_DPS_C Phase C DPS closing position
9 xx.DPS Synthetic DPS for switchgear position
10 xx.DPS_A Synthetic DPS for switchgear phase A position
11 xx.DPS_B Synthetic DPS for switchgear phase B position
12 xx.DPS_C Synthetic DPS for switchgear phase C position
13 xx.N_Trp Trip counter
14 xx.N_Trp_A Phase A trip counter
15 xx.N_Trp_B Phase B trip counter
16 xx.N_Trp_C Phase C trip counter
17 xx.Opn_Enabled Permission of opening operation
4 18 xx.Cls_Enabled Permission of closing operation
19 xx.Opn/Cls_Enabled Permission of operation (Opn_Enabled OR Cls_Enabled)
20 xx.Opn_Exec Opening operation
21 xx.Cls_Exec Closing operation
22 xx.Opn_Sel Opening selection
23 xx.Cls_Sel Closing selection
24 xx.DPS.Alm Alarm signal when DPS status is BAD or INT
25 xx.Cmd_ManSel Selection command for manual control
26 xx.Cmd_ManOpn Opening command for manual control
27 xx.Cmd_ManCls Closing command for manual control
28 xx.RSYN_ChkInprog Synchronism check is in progress
29 xx.DPS_ON Single-bit DPS state indication of ON
30 xx.DPS_OFF Single-bit DPS state indication of OFF
31 xx.DPS_INT Single-bit DPS state indication of INT
32 xx.DPS_BAD Single-bit DPS state indication of BAD
33 xx.DPS_A_ON Phase A single-bit DPS state indication of ON
34 xx.DPS_A_OFF Phase A single-bit DPS state indication of OFF
35 xx.DPS_A_INT Phase A single-bit DPS state indication of INT
36 xx.DPS_A_BAD Phase A single-bit DPS state indication of BAD
37 xx.DPS_B_ON Phase B single-bit DPS state indication of ON
38 xx.DPS_B_OFF Phase B single-bit DPS state indication of OFF
39 xx.DPS_B_INT Phase B single-bit DPS state indication of INT
40 xx.DPS_B_BAD Phase B single-bit DPS state indication of BAD
41 xx.DPS_C_ON Phase C single-bit DPS state indication of ON
42 xx.DPS_C_OFF Phase C single-bit DPS state indication of OFF
43 xx.DPS_C_INT Phase C single-bit DPS state indication of INT
44 xx.DPS_C_BAD Phase C single-bit DPS state indication of BAD
The control operation interlocking check of any control object fails, and automatic
45 Sig_CILOChk_Failed
drop-out after 2s

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 4 Control Functions

4.1.4 Logic

EN [CB**.En_CILO_Cls] >=1

SIG CB**.Cls_Enabled

SIG CB**.Cmd_ManCls >=1

&
CB** closing cmd. from device local HMI >=1 &
0 [CB**.t_PW_Cls] CB**.Cls_Exec

SIG CB** Control Mode = Remote & During this period, if the CB position
changes into open (i.e. CB**.DPS=OFF),
the output of closing execution command
CB** closing cmd. from SCADA/Gateway shall be interrupted.

SIG CB**.25.RSYN_OK
>=1
&
4
SIG CB**.25.SynChk_Enabled

SIG CB**.25.DdChk_Enabled

EN [DS**.En_CILO_Cls] >=1

SIG DS**.Cls_Enabled

SIG DS**.Cmd_ManCls >=1

& &
DS** closing cmd. from device local HMI >=1 0 [DS**.t_PW_Cls] DS**.Cls_Exec

During this period, if the D S position

changes into open (i.e. DS**.DPS=ON),
SIG DS** Control Mode = Remote & the output of closing execution command
shall be interrupted.
DS** closing cmd. from SCADA/Gateway

Figure 4.1-1 Logic of closing operation

EN [xx.En_CILO_Opn] >=1

SIG xx.Opn_Enabled

SIG xx.Cmd_ManOpn >=1

& &
xx opening cmd. from device local HMI >=1 0 [xx.t_PW_Opn] xx.Opn_Exec

During this period, if the CB or DS position

SIG xx Control Mode = Remote & changes into close (i.e. xx.DPS=ON), the
output of open execution command shall be
xx opening cmd. from SCADA/Gateway interrupted.

Figure 4.1-2 Logic of open operation

The prefix xx can be CB** (for circuit breaker) or DS** (for disconnector

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 4 Control Functions

switch) in the following figures.

SIG xx.DPS_A = OFF

>=1
SIG xx.DPS_B = OFF xx.DPS = OFF

SIG xx.DPS_C = OFF

SIG xx.DPS_A = ON
&
SIG xx.DPS_B = ON xx.DPS = ON

SIG xx.DPS_C = ON

SIG xx.DPS_A = INT

>=1
SIG xx.DPS_B = INT xx.DPS = INT

SIG xx.DPS_C = INT

4 SIG xx.DPS_A = BAD

>=1
SIG xx.DPS_B = BAD xx.DPS = BAD

SIG xx.DPS_C = BAD

Figure 4.1-3 DPS synthesis logic

SIG xx.DPS=BAD >=1

&
SIG xx.DPS= NT [xx.DPS.t_Alm] [xx.DPS.t_Alm] xx.Alm_DPS

EN [xx.DPS.En_Alm]

Figure 4.1-4 DPS alarm logic

SIG Rasing edge of xx.in_N_Trp_A & xx.N_Trp_A + 1

SIG xx.DPS_A change form ON to OFF

SIG Rasing edge of xx.in_N_Trp_B & xx.N_Trp_B + 1

&
>=1
SIG xx.DPS_B change form ON to OFF xx.N_Trp + 1

SIG Rasing edge of xx.in_N_Trp_C & xx.N_Trp_C + 1

SIG xx.DPS_C change form ON to OFF

SIG Rasing edge of xx.in_N_Trp &

SIG xx.DPS change form ON to OFF

Figure 4.1-5 Trip counter triggering logic

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 4 Control Functions

from SAS/NCC with "Interlocking"

SIG Remote control
>=1
SIG Local control Interlocking logic is activated
from LCD with "InterlockChk" >=1
&
SIG Manual control

EN [xx.En_CILO_Opn] >=1

EN [xx.En_CILO_Cls]

Figure 4.1-6 Interlocking logic

SIG xx.in_Manual_Sel not configurated &

>=1
SIG xx.in_ManOpn=1

SIG xx.in_ManSel =1 &

4
SIG xx.in_ManOpn=1
&
SIG xx.Opn_Enabled =1 xx.Cmd_ManOpn

SIG Control mode is Local

SIG xx.in_Manual_Sel not configurated &

SIG xx.in_ManCls=1
>=1
SIG xx.in_ManSel =1 &

SIG xx.in_ManCls=1
&
SIG xx.Cls_Enabled =1 xx.Cmd_ManCls

SIG Control mode is Local

Figure 4.1-7 Manual control logic

4.1.5 Settings
Table 4.1-4 DPS settings

Name Range Step Unit Default Description

The DPU (delay pick up) time of DPS, i.e. debounce
CB**.DPS.t_DPU 0~60000 1 ms 500
time (for circuit breaker No.**)
Disabled Enabling/disabling DPS alarm (for circuit breaker
CB**.DPS.En_Alm Disabled
Enabled No.**)
CB**.DPS.t_Alm 0~60000 1 ms 500 Time delay of DPS alarm (for circuit breaker No.**)
The DPU (delay pick up) time of DPS, i.e. debounce
DS**.DPS.t_DPU 0~60000 1 ms 500
time (for circuit breaker No.**)
DS**.DPS.En_Alm Disabled Disabled Enabling/disabling DPS alarm (for circuit breaker

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 4 Control Functions

Name Range Step Unit Default Description

Enabled No.**)
DS**.DPS.t_Alm 0~60000 1 ms 500 Time delay of DPS alarm (for circuit breaker No.**)

Table 4.1-5 Control settings

Name Range Step Unit Default Description

Pulse Width (PW), i.e. holding time, for opening
CB**.t_PW_Opn 0~60000 1 ms 500
output of circuit breaker No.**
Pulse Width (PW), i.e. holding time, for closing
CB**.t_PW_Cls 0~60000 1 ms 500
output of circuit breaker No.**
Pulse Width (PW), i.e. holding time, for opening
DS**.t_PW_Opn 0~60000 1 ms 500
output of disconnector switch No.**
Pulse Width (PW), i.e. holding time, for closing
DS**.t_PW_Cls 0~60000 1 ms 500
output of disconnector switch No.**
4 DirCtrl**.t_PW_Opn 0~60000 1 ms 500
Pulse Width (PW), i.e. holding time, for opening
output of direct control object No.**
Pulse Width (PW), i.e. holding time, for closing
DirCtrl**.t_PW_Cls 0~60000 1 ms 500
output of direct control object No.**

Table 4.1-6 Interlocking settings

Name Range Step Unit Default Description

Enabling/disabling open output of circuit
Disabled
CB**.En_CILO_Opn Disabled breaker No.** controlled by the interlocking
Enabled
logic
Enabling/disabling closing output of circuit
Disabled
CB**.En_CILO_Cls Disabled breaker No.** controlled by the interlocking
Enabled
logic
Disabled Enabling/disabling open output of disconnector
DS**.En_CILO_Opn Disabled
Enabled switch No.** controlled by the interlocking logic
Enabling/disabling closing output of
Disabled
DS**.En_CILO_Cls Disabled disconnector switch No.** controlled by the
Enabled
interlocking logic
Disabled Enabling/disabling open output of direct control
DirCtrl**.En_CILO_Opn Disabled
Enabled object No.** controlled by the interlocking logic
Enabling/disabling closing output of direct
Disabled
DirCtrl**.En_CILO_Cls Disabled control object No.** controlled by the
Enabled
interlocking logic

4.2 Synchronism Check (25)

The purpose of synchronism check is to ensure two systems are synchronous before they are going to
be connected. When two asynchronous systems are connected together, due to phase difference
between the two systems, larger impact will be led to the system during closing. Thus closing operation

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 4 Control Functions

is applied with the synchronism check to avoid this situation and maintain the system stability. The
synchronism check includes synchro-check and dead charge check.

For double circuit breakers mode, the device will provide independent
synchro-check function for CB1 and CB2 respectively. Both synchro-check
functions have the same logic. The difference is that the prefix “CBx.” is
added to all settings for circuit breaker No.x (x=1 or 2).

4.2.1 Function Description

4.2.1.1 Synchro-check

The comparative relationship between the voltage at reference side and the voltage at synchronous
side for synchro-check is as follow. Figure 4.2-1 shows the characteristics of synchro-check
element used for CB closing if both reference and synchronous sides are live. The element
4
operates if the voltage difference, frequency difference, slip frequency difference and phase angle
difference are all within their setting ranges.

U_Ref
U_Syn

Figure 4.2-1 Relationship between reference and synchronous voltages

The device supports two groups of frequency difference setting, voltage difference setting and
phase difference setting. When the "RSYN U/f/phi_Diff setting selection" is set as "Enabled" in
the path: Device Node→Global Config→System Config by PCS-Studio,.the user can select one
group of settings through the configuration signal "in_Set_Sel" to participate in logic judgment by
PCS-Studio. When "in_Set_Sel"=0, the first group of settings are used: [U_Diff_Set], [f_Diff_Set]
and [phi_Diff_Set]. When "in_set_Sel"=1, the second group of settings are used: [U_Diff_Set2],
[f_Diff_Set2] and [phi_Diff_Set2].

⚫ The voltage difference between the voltage at reference side and the voltage at synchronous
side is checked by the following equation

[CBx.25.U_UV]≤CBx.U_Ref≤[CBx.25.U_OV]

[CBx.25.U_UV]≤CBx.U_Syn≤[CBx.25.U_OV]

|CBx.U_Ref-CBx.U_Syn|≤[CBx.25.U_Diff_Set]

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 4 Control Functions

⚫ The frequency difference between the voltage at reference side and the voltage at
synchronous side is checked by the following equation

[CBx.25.f_UF]≤f(CBx.U_Ref)≤[CBx.25.f_OF]

[CBx.25.f_UF]≤f(CBx.U_Syn)≤[CBx.25.f_OF]

|f(CBx.U_Ref)-f(CBx.U_Syn)|≤[CBx.25.f_Diff_Set]

⚫ The rate-of-change of frequency difference between the voltage at reference side and the
voltage at synchronous side is checked by the following equation

d|f(CBx.U_Syn)-f(CBx.U_Ref)|/dt≤[CBx.25.df/dt_Set]

⚫ The phase difference between the voltage at reference side and the voltage at synchronous
side is checked by the following equation

∆δ≤[CBx.25.phi_Diff_Set]
4
4.2.1.2 Dead Check

The device compares the voltages between the reference side and the synchronous side with the
settings [CBx.25.U_LvChk] and [CBx.25.U_DdChk]. When the voltage is higher than
[CBx.25.U_LvChk], the corresponding side is regarded as live. When the voltage is lower than
[CBx.25.U_DdChk], the corresponding side is regarded as dead.

4.2.1.3 Voltage Input Channel

According to different application scenarios, the different voltage input channel needs to be
configured. For both the reference side and the synchronous side, the voltage input channel may
be single phase or three phases. In the meantime, the voltage selection logic can be adopted for
the synchronism check input channel, please refer to Section 4.3.

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4.2.2 Function Block Diagram

RSYN

in_en

in_blk

in_Ch_Ua_Ref

in_Ch_Ub_Ref

in_Ch_Uc_Ref

in_Ch_Ua_Syn

in_Ch_Ub_Syn

in_Ch_Uc_Syn

in_Blk_RSYN 4
in_Blk_DdChk

in_Blk_LvChk

in_Blk_SynChk

in_Bypass_RSYN

in_En_DdChk

in_En_SynChk

in_Set_Sel

4.2.3 I/O Signals

Table 4.2-1 Input signals of manual closing synchronism check

No. Input Signal Description

1 CBx.25.in_en Input signal of enabling manual closing synchronism check
2 CBx.25.in_blk Input signal of blocking manual closing synchronism check
3 CBx.25.in_Ch_Ua_Ref Reference voltage channel (phase A or single phase)
4 CBx.25.in_Ch_Ub_Ref Reference voltage channel (phase B)
5 CBx.25.in_Ch_Uc_Ref Reference voltage channel (phase C)
6 CBx.25.in_Ch_Ua_Syn Synchronization voltage channel (phase A or single phase)
7 CBx.25.in_Ch_Ub_Syn Synchronization voltage channel (phase B)
8 CBx.25.in_Ch_Uc_Syn Synchronization voltage channel (phase C)
9 CBx.25.in_Blk_RSYN Signal to block synchronism check logic
10 CBx.25.in_Blk_DdChk Signal to block dead charge logic
11 CBx.25.in_Blk_LvChk Signal to block live check logic
12 CBx.25.in_Blk_SynChk Signal to block synchro-check logic
13 CBx.25.in_Bypass_RSYN Signal to temporarily bypass synchronism check logic
14 CBx.25.in_En_DdChk Activate dead charge check (valid only if the setting

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 4 Control Functions

No. Input Signal Description

[CBx.25.Opt_ValidMode]=Config)
Activate synchro-check (valid only if the setting
15 CBx.25.in_En_SynChk
[CBx.25.Opt_ValidMode]=Config)
Select between the first group of frequance/voltage/phase difference setting
16 CBx.25.in_Set_Sel
and the second group of frequance/voltage/phase difference setting

Table 4.2-2 Output signals of manual closing synchronism check

No. Output Signal Description

1 CBx.25.RSYN Pointer to the structure of synchronism check element
2 CBx.25.U_Ref_Sec Reference side voltage secondary value
3 CBx.25.U_Ref_Pri Reference side voltage primary value
4 CBx.25.f_Ref Reference side frequency
5 CBx.25.U_Syn_Sec Synchronous side voltage secondary value
4 6 CBx.25.U_Syn_Pri Synchronous side voltage primary value
7 CBx.25.f_Syn Synchronous side frequency
8 CBx.25.U_Diff_Sec Voltage difference secondary value
9 CBx.25.U_Diff_Pri Voltage difference primary value
10 CBx.25.phi_Diff Phase angle difference
11 CBx.25.f_Diff Frequency difference
12 CBx.25.df/dt Frequency rate-of-change
13 CBx.25.RSYN_OK Satisfaction of synchronism check logic, i.e. SynChk_OK or DdChk_OK
14 CBx.25.SynChk_OK Satisfaction of synchro-check logic
15 CBx.25.DdChk_OK Satisfaction of dead charge check logic
16 CBx.25.Alm_Cfg_Ch Channel configuration for reference or synchronization is not correct.
17 CBx.25.SynChk_Enabled Synchro-check is enabled
18 CBx.25.DdChk_Enabled Dead charge check is enabled
19 CBx.25.U_Diff_OK Voltage difference within setting range
20 CBx.25.f_Diff_OK Frequency difference within setting range
21 CBx.25.df/dt_OK Frequency variation within setting range
22 CBx.25.phi_Diff_OK Phase difference within setting range
23 CBx.25.RefDd The reference side is dead.
24 CBx.25.RefLv The reference side is live.
25 CBx.25.SynDd The synchronous side is dead.
26 CBx.25.SynLv The synchronous side is live.
Dead charge check is blocked by dead voltage criterion, and automatic
27 CBx.25.U_Dd_Blk_DdChk
drop-out after 2s.
Dead charge check is blocked by live voltage criterion, and automatic
28 CBx.25.U_Lv_Blk_DdChk
drop-out after 2s.
Synchro-check is blocked by voltage difference criterion, and automatic
29 CBx.25.U_Diff_Blk_SynChk
drop-out after 2s.
Synchro-check is blocked by frequency difference criterion, and
30 CBx.25.f_Diff_Blk_SynChk
automatic drop-out after 2s.

4-14 PCS-902S Line Distance Relay

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 4 Control Functions

No. Output Signal Description

Synchro-check is blocked by phase difference criterion, and automatic
31 CBx.25.phi_Diff_Blk_SynChk
drop-out after 2s.
Synchro-check is blocked by frequency variation criterion, and automatic
32 CBx.25.df/dt_Blk_SynChk
drop-out after 2s.
Synchro-check is blocked by voltage circuit supervision, and automatic
33 CBx.25.VTS_Blk_SynChk
drop-out after 2s.
Synchro-check is blocked by abnormal voltage quality, and automatic
34 CBx.25.U_q_Blk_SynChk
drop-out after 2s.
Synchro-check is blocked by over-voltage, and automatic drop-out after
35 CBx.25.OV_Blk_SynChk
2s.
Synchro-check is blocked by over-frequency, and automatic drop-out
36 CBx.25.OF_Blk_SynChk
after 2s.
Synchro-check is blocked by external blocking signal, and automatic
37 CBx.25.ExtSig_Blk_SynChk
drop-out after 2s. 4
38 CBx.25.Sig_DdChk_Failed Dead charge check is blocked, and automatic drop-out after 2s.
39 CBx.25.Sig_SynChk_Failed Synchro-check check is blocked, and automatic drop-out after 2s.

4.2.4 Logic

EN [CBx.25.Opt_ValidMode]=Setting &
>=1
EN [CBx.25.En_SynChk] CBx.25.SynChk_Enabled

EN [CBx.25.Opt_ValidMode]=Config &

SIG CBx.25.in_En_SynChk

EN [CBx.25.Opt_ValidMode]=Setting &
>=1
EN [CBx.25.En_DdChk] CBx.25.DdChk_Enabled

EN [CBx.25.Opt_ValidMode]=Config &

SIG CBx.25.in_En_DdChk

SIG CBx.25.SynChk_Enabled &

Synchronism check for CB closing is disabled
SIG CBx.25.DdChk_Enabled

Figure 4.2-2 Synchronism check logic

If one of the following conditions is met, the synchro-check for CB closing is enabled.

⚫ [CBx.25.Opt_ValidMode]=Setting & [CBx.25.En_SynChk]=Enabled

⚫ [CBx.25.Opt_ValidMode]=Config & "CBx.25.En_SynChk"=1

If one of the following conditions is met, the dead charge check for CB closing is enabled.

⚫ [CBx.25.Opt_ValidMode]=Setting & [CBx.25.En_DdChk]=Enabled

PCS-902S Line Distance Relay 4-15

Date: 2023-08-01
 4 Control Functions

⚫ [CBx.25.Opt_ValidMode]=Config & "CBx.25.in_En_DdChk"=1

If none of synchro-check and dead charge check is enabled, the synchronism check for CB closing
is disabled.

SIG CBx.in_Bypass_RSYN

SIG CBx.in_Blk_RSYN >=1 >=1

& CB**.25.SynChk_OK
SIG CBx.in_Blk_SynChk

SET Δf≤[CBx.25.f_Diff_Set] >=1

EN [CBx.25.En_fDiffChk]=Disabled

SET df/dt≤[CBx.25.df/dt_Set] >=1 &

EN [CBx.25.En_df/dtChk]=Disabled

4 SET ΔU≤[CBx.25.U_Diff_Set] &

SET Δδ≤[CBx.25.phi_Diff_Set]

SET U_Ref≤[CBx.25.U_UV] >=1

>=1 &
SET U_Ref≥[CBx.25.U_OV] >=1
SET U_Syn≤[CBx.25.U_UV] >=1

SET U_Syn≥[CBx.25.U_OV]

SET f_Ref≤[CBx.25.f_UF] >=1

>=1
SET f_Ref≥[CBx.25.f_OF]

SET f_Syn≤[CBx.25.f_UF] >=1

SET f_Syn≥[CBx.25.f_OF]

SIG Cmd without synchro-check

SIG CBx.25.SynChk_Ok
>=1
& SynChk Success
SIG CBx.25.SynChk_Enabled

SIG Cmd with synchro-check

Figure 4.2-3 Synchronism check logic

4-16 PCS-902S Line Distance Relay

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 4 Control Functions

SIG CBx.in_Bypass_RSYN

SIG CBx.in_Blk_RSYN

SET [CBx.25.Opt_Mode_DdChk]

SIG CBx.in_Blk_DdChk &

SIG CBx.25.RefDd >=1

& CBx.25.DdChk_OK
&

crite ria sel ection

Dead check
SIG CBx.25.SynDd

SIG CBx.25.RefLv &

SIG CBx.25.SynLv & 4

SIG CBx.in_Blk_LvChk

SIG Cmd. without dead charge check

SIG CBx.25.DdChk_Ok
>=1
& DdChk Success
SIG CBx.25.DdChk_Enabled

SIG Cmd. with dead charge check

SIG Ua_Ref < [CBx.25.U_DdChk]

&
SIG Ub_Ref < [CBx.25.U_DdChk]

SIG Uc_Ref < [CBx.25.U_DdChk]

&
>=1
SIG U_Ref is three-phase voltage CBx.25.RefDd

SIG U_Ref < [CBx.25.U_DdChk] &

SIG U_Ref is single-phase voltage

SIG Ua_Syn < [CBx.25.U_DdChk]

&
SIG Ub_Syn < [CBx.25.U_DdChk]

SIG Uc_Syn < [CBx.25.U_DdChk]

&
>=1
SIG U_Syn is three-phase voltage CBx.25.SynDd

SIG U_Syn < [CBx.25.U_DdChk] &

SIG U_Syn is single-phase voltage

PCS-902S Line Distance Relay 4-17

Date: 2023-08-01
 4 Control Functions

SIG Ua_Ref > [CBx.25.U_LvChk]

&
SIG Ub_Ref > [CBx.25.U_LvChk]

SIG Uc_Ref > [CBx.25.U_LvChk]

&
>=1
SIG U_Ref is three-phase voltage CBx.25.RefLv

SIG U_Ref > [CBx.25.U_LvChk] &

SIG U_Ref is single-phase voltage

SIG Ua_Syn > [CBx.25.U_LvChk]

&
SIG Ub_Syn > [CBx.25.U_LvChk]

SIG Uc_Syn > [CBx.25.U_LvChk]

&
>=1
SIG U_Syn is three-phase voltage CBx.25.SynLv

4 SIG U_Syn > [CBx.25.U_LvChk] &

SIG U_Syn is single-phase voltage

Figure 4.2-4 Dead check logic

4.2.5 Settings
Table 4.2-3 Settings of synchronism check

Name Range Step Unit Default Description

Selection of decision
mode for synchronism
check
Setting: the mode
depends on the
Setting settings
CBx.25.Opt_ValidMode Setting
Config Config: the mode
depends on
configuration signals
("CBx.in_syn_chk"
and
"CBx.in_vol_chk")
Enabling/disabling
synchro-check (valid
Disabled
CBx.25.En_SynChk Enabled only if the setting
Enabled
[CBx.25.Opt_ValidMo
de]=Setting)
Enabling/disabling
Disabled dead charge check
CBx.25.En_DdChk Enabled
Enabled (valid only if the
setting

4-18 PCS-902S Line Distance Relay

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 4 Control Functions

Name Range Step Unit Default Description

[CBx.25.Opt_ValidMo
de]=Setting)
Percentage threshold
CBx.25.U_UV 0.00~100.00 0.01 % 80.00 of under voltage for
CB closing blocking
Percentage threshold
CBx.25.U_OV 100.00~170.00 0.01 % 170.00 of over voltage for CB
closing blocking
Under frequency
CBx.25.f_UF 45.000~65.000 0.001 Hz 45.000 threshold for CB
closing blocking
Over frequency
CBx.25.f_OF 45.000~65.000 0.001 Hz 65.000 threshold for CB
closing blocking 4
Ua
Ub
Selection of voltage
Uc
CBx.25.Opt_U_SynChk Ua for synchronism
Uab
check
Ubc
Uca
Threshold of voltage
difference for
CBx.25.U_Diff_Set 0.00~100.00 0.01 V 10.00
synchronism check
(first group)
Threshold of voltage
difference for
CBx.25.U_Diff_Set2 0.00~100.00 0.01 V 10.00
synchronism check
(second group)
Threshold of
frequency difference
CBx.25.f_Diff_Set 0.00~2.00 0.01 Hz 0.50
for synchronism
check (first group)
Threshold of
frequency difference
CBx.25.f_Diff_Set2 0.00~2.00 0.01 Hz 0.50
for synchronism
check (second group)
Threshold of rate-of-
Hz/ change of frequency
CBx.25.df/dt_Set 0.00~2.00 0.01 1.00
s difference for
synchronism check.
Threshold of phase
CBx.25.phi_Diff_Set 0.00~180.00 0.01 ° 15.00 difference for
synchronism check

PCS-902S Line Distance Relay 4-19

Date: 2023-08-01
 4 Control Functions

Name Range Step Unit Default Description

(first group)
Threshold of phase
difference for
CBx.25.phi_Diff_Set2 0.00~180.00 0.01 ° 15.00
synchronism check
(second group)
Compensation angle
CBx.25.phi_Comp 0.00~360.00 0.01 ° 0.00 of phase difference for
synchronism check
Selection of dead
charge check mode
SynDdRefDd:
synchronism voltage
is dead & reference
4 voltage is dead
SynLvRefDd:
synchronism voltage
is live & reference
voltage is dead
SynDdRefLv:
synchronism voltage
SynDdRefDd
is dead & reference
SynLvRefDd
voltage is live
SynDdRefLv
RefDd: reference
CBx.25.Opt_Mode_DdChk RefDd AnySideDd
voltage is dead
SynDd
SynDd: synchronism
SynLvRefDd/SynDdRefLv
voltage is dead
AnySideDd
SynLvRefDd/SynDdR
efLv: synchronism
voltage is live &
reference voltage is
dead or synchronism
voltage is dead &
reference voltage is
live
AnySideDd:
synchronism voltage
or reference voltage is
dead
Threshold for voltage
dead check
CBx.25.U_DdChk 0.00~100.00 0.01 V 17.32 When the setting
[CBx.25.Opt_U_SynC
hk] is set as "Uab",

4-20 PCS-902S Line Distance Relay

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 4 Control Functions

Name Range Step Unit Default Description

"Ubc" or "Uca", the
setting will be divided
by 1.732 to be used as
the threshold for
voltage dead check
Threshold for voltage
live check
When the setting
[CBx.25.Opt_U_SynC
hk] is set as "Uab",
CBx.25.U_LvChk 0.00~100.00 0.01 V 34.64
"Ubc" or "Uca", the
setting will be divided
by 1.732 to be used as
the threshold for 4
voltage live check
Threshold of duration
CBx.25.t_Reset 0~60 1 s 5
for synchrocheck
Circuit breaker closing
time. It is the time from
receiving closing
CBx.25.t_Close_CB 0~2000 1 ms 20
command pulse till the
CB is completely
closed.
Enabling/disabling
Disabled
CBx.25.En_f_Diff_Chk Enabled frequency difference
Enabled
check
Enabling/disabling
Disabled
CBx.25.En_df/dt_Chk Enabled frequency variation
Enabled
difference check

⚫ CBx.25.Opt_Mode_DdChk

Setting value Dead check mode

SynDdRefDd Dead check for both the reference and the synchronization sides

SynLvRefDd Live check for synchronization side and dead check for reference side

SynDdRefLv Dead check for synchronization side and live check for reference side

RefDd Dead check for reference side

SynDd Dead check for synchronization side

Live check for synchronization side and dead check for reference side, or
SynLvRefDd/SynDdRefLv
dead check for synchronization side and live check for reference side

Dead check for both the reference and the synchronization sides, live check
AnySideDd
for synchronization side and dead check for reference side, or dead check for

PCS-902S Line Distance Relay 4-21

Date: 2023-08-01
 4 Control Functions

Setting value Dead check mode

synchronization side and live check for reference side

4.3 Voltage Selection

The voltage selection function can be used to switch the reference and synchronization voltages
of synchronism check in double busbars and one-and-half circuit breakers, or to switch three-
phases voltage between double busbars used by protection calculations or measurements.

4.3.1 Function Description

By default, the device adopts the principle of proximity in built-in voltage selection logic. Moreover,
it supports customized selection logic. The default voltage selection logic is automatically disabled
if the customized voltage selection logic is correctly configured.
4 The customized selection result may be derived from any source binary signals, such as binary
inputs, isolators status and programmable logic output signals. If voltage selection logic fails, the
alarm "CBx.Alm_Invalid_Sel" will be issued and the selection output remains unchanged.

The voltage selection is used in the following scenarios:

1. Double busbars arrangement

⚫ Three-phases voltages from Bus1 VT and Bus2 VT via switching is used for protection
calculations or measurements and meanwhile used as reference side of synchronism check.
Single-phase voltage from line VT is used as synchronizing side of synchronism check.

Bus2

Bus1

DS1 DS2
Ua1
Ub1

Uc1

Ua2
Ub2 CB 52
Uc2

DS1.DPS

DS2.DPS

UL1

Line

4-22 PCS-902S Line Distance Relay

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 4 Control Functions

Figure 4.3-1 Voltage connection 1 for double busbars

⚫ The voltage from Bus 1 VT and Bus 2 VT via switching is used as synchronizing side of
synchronism check. The voltage from Line VT is used as reference side of synchronism check.

Bus2

Bus1

DS1 DS2

UB1

UB2

CB 52
DS1.DPS
4
DS2.DPS

Ua
Ub
Uc

Line

Figure 4.3-2 Voltage connection 2 for double busbars

2. One-and-half circuit breakers

⚫ For bus-side CB, the voltage from Line1 VT, Line2 VT and Bus VT of the other sie via switching
is used as reference side of synchronism check. The voltage from Bus VT of local side is used
as synchronizing side of synchronism check.

⚫ For tie CB, the voltages from Line1 VT & Bus1 VT and Line2 VT & Bus2 VT via switching are
used as synchronizing side and reference side of synchronism check respectively.

PCS-902S Line Distance Relay 4-23

Date: 2023-08-01
 4 Control Functions

Bus1

UB1
Line 1
Bus1_CB.DPS 52 Bus1_CB

Ua
Ub
Uc
DS1
DS1.DPS

Tie_CB.DPS 52 Tie_CB Line 2

4
UL2

DS2
DS2.DPS

Bus2_CB.DPS 52 Bus2_CB

UB2

Bus2

Figure 4.3-3 Voltage connection for one-and-half circuit breakers

3. For a customized voltage selection logic, the inputs "CBx.in_bus1_sel", "CBx.in_bus2_sel",

"CBx.in_line1_sel" and "CBx.in_line2_sel" are derived from binary signals, such as
switchgear positions, binary inputs, programmable logic outputs, etc. The inputted value "1"
means "Channel selected" while the inputted value "0" means "Channel not selected". Make
sure that all these customized voltage selection inputs and measurement channels are
correctly configured before put the logic into service.

4-24 PCS-902S Line Distance Relay

Date: 2023-08-01
-27
 4 Control Functions

4.3.2 Function Block Diagram

VolSwitch

in_Ch_Ua_Bus1 Ch_Ua_Ref

in_Ch_Ub_Bus1 Ch_Ub_Ref

in_Ch_Uc_Bus1 Ch_Uc_Ref

in_Ch_Ua_Bus2 Ch_Ua_Syn

in_Ch_Ub_Bus2 Ch_Ub_Syn

in_Ch_Uc_Bus2 Ch_Uc_Syn

in_Ch_Ua_Line1

in_Ch_Ub_Line1

in_Ch_Uc_Line1 4
in_Ch_Ua_Line2

in_Ch_Ub_Line2

in_Ch_Uc_Line2

in_Bus1_CB

in_Tie_CB

in_Bus2_CB

in_DS1

in_DS2

4.3.3 I/O Signals

Table 4.3-1 Input signals of voltage selection

No. Input Signal Description

1 CBx.in_Ch_Ua_Bus1 Voltage input for Bus1 (phase A)
2 CBx.in_Ch_Ub_Bus1 Voltage input for Bus1 (phase B)
3 CBx.in_Ch_Uc_Bus1 Voltage input for Bus1 (phase C)
4 CBx.in_Ch_Ua_Bus2 Voltage input for Bus2 (phase A)
5 CBx.in_Ch_Ub_Bus2 Voltage input for Bus2 (phase B)
6 CBx.in_Ch_Uc_Bus2 Voltage input for Bus2 (phase C)
7 CBx.in_Ch_Ua_Line1 Voltage input for Line1 (phase A)
8 CBx.in_Ch_Ub_Line1 Voltage input for Line1 (phase B)
9 CBx.in_Ch_Uc_Line1 Voltage input for Line1 (phase C)
10 CBx.in_Ch_Ua_Line2 Voltage input for Line2 (phase A)
11 CBx.in_Ch_Ub_Line2 Voltage input for Line2 (phase B)
12 CBx.in_Ch_Uc_Line2 Voltage input for Line2 (phase C)

PCS-902S Line Distance Relay 4-25

Date: 2023-08-01
 4 Control Functions

No. Input Signal Description

13 CBx.in_Bus1_CB DPS position for the Bus 1 side CB in one-and-half circuit breakers
14 CBx.in_Tie_CB DPS position for the tie CB in one-and-half circuit breakers
15 CBx.in_Bus2_CB DPS position for the Bus 2 side CB in one-and-half circuit breakers
DPS position for Line 1 DS in one-and-half circuit breakers or Busbar 1 in double
16 CBx.in_DS1
busbars
DPS position for Line 2 DS in one-and-half circuit breakers of Busbar 2 in double
17 CBx.in_DS2
busbars
18 CBx.in_Bus1_sel Bus1-selected input for customized programmable voltage selection logic
19 CBx.in_Bus2_sel Bus2-selected input for customized programmable voltage selection logic
20 CBx.in_Line1_sel Line1-selected input for customized programmable voltage selection logic
21 CBx.in_Line2_sel Line2-selected input for customized programmable voltage selection logic

Table 4.3-2 Output signals of voltage selection

4 No. Output Signal Description

1 CBx.VoltSel.Ch_Ua_Ref Reference voltage channel (Phase A)
2 CBx.VoltSel.Ch_Ub_Ref Reference voltage channel (Phase B)
3 CBx.VoltSel.Ch_Uc_Ref Reference voltage channel (Phase C)
4 CBx.VoltSel.Ch_Ua_Syn Synchronization voltage channel (Phase A)
5 CBx.VoltSel.Ch_Ub_Syn Synchronization voltage channel (Phase B)
6 CBx.VoltSel.Ch_Uc_SYn Synchronization voltage channel (Phase C)
Bus1 voltage channel for customized programmable voltage selection
7 CBx.VoltSel.Bus1_Sel
logic
Line1 voltage channel for customized programmable voltage selection
8 CBx.VoltSel.Line1_Sel
logic
Line2 voltage channel for customized programmable voltage selection
9 CBx.VoltSel.Line2_Sel
logic
Bus2 voltage channel for customized programmable voltage selection
10 CBx.VoltSel.Bus2_Sel
logic
11 CBx.VoltSel.Alm_Invalid_Sel Voltage selection is invalid.

4.3.4 Logic

SIG DS1.DPS=ON &

UB1_Sel
SIG DS2.DPS=OFF &
CBx.VoltSel.Alm_Invalid_Sel
SIG DS1.DPS=OFF &
UB2_Sel
SIG DS2.DPS=ON

UB1 U_Ref
Three-phase voltage of busbars for reference side
UB2

Figure 4.3-4 Voltage selection for double busbars (Three-phases voltages of busbars)

4-26 PCS-902S Line Distance Relay

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 4 Control Functions

SIG DS1.DPS=ON &

UB1_Sel
SIG DS2.DPS=OFF &
CBx.VoltSel.Alm_Invalid_Sel
SIG DS1.DPS=OFF &
UB2_Sel
SIG DS2.DPS=ON

UB1 U_Syn
Single-phase voltage of busbars for synchronous side
UB2

Figure 4.3-5 Voltage selection for double busbars (Single-phase voltage of busbars)

SIG DS1.DPS=ON UL1_Sel

SIG DS1.DPS=OFF

SIG Tie_CB.DPS=ON
&
UL2_Sel
4
SIG DS2.DPS=ON

SIG DS1.DPS=OFF
&
SIG Tie_CB.DPS=ON UB2_Sel

SIG DS2.DPS=OFF &

&
CBx.VoltSel.Alm_Invalid_Sel
SIG Bus2_CB.DPS=ON

UL1

UL2 U_Ref

UB2

UB1 U_Syn

Figure 4.3-6 Voltage selection for one-and-half circuit breakers (bus CB)

PCS-902S Line Distance Relay 4-27

Date: 2023-08-01
 4 Control Functions

SIG DS1.DPS=ON UL1_Sel

SIG DS1.DPS=OFF &

UB1_Sel
SIG Bus1_CB.DPS=ON

SIG DS2.DPS=ON UL2_Sel

SIG DS2.DPS=OFF &

UB2_Sel
SIG Bus2_CB.DPS=ON &

>=1
& CBx.VoltSel.Alm_Invalid_Sel

4 UL1 Uref

UB1

UL2 Usyn

UB2

Figure 4.3-7 Voltage selection for one-and-half circuit breakers (tie CB)

4.3.5 Settings
Table 4.3-3 Settings of voltage selection

Name Range Step Unit Default Description

Option of circuit breaker No.x
configuration, and it should be set as
"NoVoltSel" if no voltage selection is
adopted.
NoVoltSel NoVoltSel: no voltage selection
DblBusOneCB DblBusOneCB: one circuit breaker
CBx.VoltSel.Opt_CBConfig 3/2BusCB1 NoVoltSel for double busbar
3/2TieCB 3/2BusCB1: bus 1 side circuit
3/2BusCB2 breaker for one and a half breakers
3/2TieCB: line side circuit breaker for
one and a half breakers
3/2BusCB2: bus 2 side circuit
breaker for one and a half breakers

4-28 PCS-902S Line Distance Relay

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-27
 5 Measurement

5 Measurement

Table of Contents

5.1 Primary Values ................................................................................................. 5-1

5.1.1 General Values ..................................................................................................................... 5-1

5.1.2 Angle Values ......................................................................................................................... 5-2

5.1.3 Sequence Components Values ............................................................................................ 5-5

5.1.4 Power Values........................................................................................................................ 5-6

5.1.5 Harmonics ............................................................................................................................ 5-8

5.2 Secondary Values ............................................................................................ 5-9

5.2.1 General Values ..................................................................................................................... 5-9

5.2.2 Angle Values ....................................................................................................................... 5-11 5

5.2.3 Sequence Components Values .......................................................................................... 5-14

5.2.4 Power Values...................................................................................................................... 5-14

5.2.5 Harmonics .......................................................................................................................... 5-16

5.3 Function Values ............................................................................................. 5-17

5.3.1 Sum Values ........................................................................................................................ 5-17

5.3.2 ThOvLd Values ................................................................................................................... 5-18

5.3.3 Synchronism Check ........................................................................................................... 5-19

5.3.4 SCBR Values ...................................................................................................................... 5-21

5.4 Energy Metering ............................................................................................ 5-21

5.5 Power Quality................................................................................................. 5-22
5.6 Synchrophasor Measurement ...................................................................... 5-24
5.6.1 Function Description........................................................................................................... 5-24

5.6.2 Function Block Diagram ..................................................................................................... 5-26

5.6.3 PMU Values ........................................................................................................................ 5-26

5.6.4 PMU Status ........................................................................................................................ 5-28

5.6.5 PMU Settings ..................................................................................................................... 5-29

5.7 AC Analog Input Calibration ......................................................................... 5-40

PCS-902S Line Distance Relay 5-a

Date: 2023-08-01
 5 Measurement

5.7.1 Function Description........................................................................................................... 5-40

5.7.2 Settings............................................................................................................................... 5-41

List of Tables

Table 5.6-1 PMU global settings .............................................................................................. 5-29

Table 5.6-2 PMU communication settings .............................................................................. 5-30

Table 5.6-3 PMU bay settings ................................................................................................... 5-38

Table 5.6-4 PMU BI settings...................................................................................................... 5-39

Table 5.6-5 PMU label settings ................................................................................................. 5-39

Table 5.7-1 AC calibration settings .......................................................................................... 5-41

5-b PCS-902S Line Distance Relay

Date: 2023-08-01
 5 Measurement

5.1 Primary Values

Access path: MainMenuMeasurementsPrimary Values

When the "Meas" is set as "ON" in the path: Device Node→Global Config
→ Function Group → Additional function by PCS-Studio, the
measurement CT is available for the application scenario that protection CT
is independent with measurement CT.

5.1.1 General Values

No. Item Definition Unit

Single CB application

1 Prot.Ia_Pri Phase-A current (from protection CT) A

2 Prot.Ib_Pri Phase-B current (from protection CT) A

3 Prot.Ic_Pri Phase-C current (from protection CT) A 5

4 Prot.Ua_Pri Phase-A voltage kV

5 Prot.Ub_Pri Phase-B voltage kV

6 Prot.Uc_Pri Phase-C voltage kV

7 Prot.Uab_Pri Phases-AB voltage kV

8 Prot.Ubc_Pri Phases-BC voltage kV

9 Prot.Uca_Pri Phases-CA voltage kV

10 Prot.f Frequency of protection voltage Hz

11 3I0Adj.I_Pri The residual current from parallel line kV

12 UB1.Syn.U_Pri Synchronism voltage (UB1) Hz

13 UB1.Syn.f Frequency of synchronism voltage (UB1) kV

14 UL2.Syn.U_Pri Synchronism voltage (UL2) Hz

15 UL2.Syn.f Frequency of synchronism voltage (UL2) kV

16 UB2.Syn.U_Pri Synchronism voltage (UB2) Hz

17 UB2.Syn.f Frequency of synchronism voltage (UB2) kV

18 Meas.Ia_Pri Phase-A current (from measurement CT) A

19 Meas.Ib_Pri Phase-B current (from measurement CT) A

20 Meas.Ic_Pri Phase-C current (from measurement CT) A

21 Meas.Ua_Pri Phase-A voltage kV

22 Meas.Ub_Pri Phase-B voltage kV

23 Meas.Uc_Pri Phase-C voltage kV

PCS-902S Line Distance Relay 5-1

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

24 Meas.Uab_Pri Phases-AB voltage kV

25 Meas.Ubc_Pri Phases-BC voltage kV

26 Meas.Uca_Pri Phases-CA voltage kV

27 Meas.f Frequency of protection voltage Hz

Double CBs application

1 Prot.CB1.Ia_Pri Phase-A current corresponding to circuit breaker No.1 A

2 Prot.CB1.Ib_Pri Phase-B current corresponding to circuit breaker No.1 A

3 Prot.CB1.Ic_Pri Phase-C current corresponding to circuit breaker No.1 A

4 Prot.CB2.Ia_Pri Phase-A current corresponding to circuit breaker No.2 A

5 Prot.CB2.Ib_Pri Phase-B current corresponding to circuit breaker No.2 A

6 Prot.CB2.Ic_Pri Phase-C current corresponding to circuit breaker No.2 A

7 Prot.Ua_Pri Phase-A voltage kV

8 Prot.Ub_Pri Phase-B voltage kV

9 Prot.Uc_Pri Phase-C voltage kV

5 10 Prot.Uab_Pri Phases-AB voltage kV

11 Prot.Ubc_Pri Phases-BC voltage kV

12 Prot.Uca_Pri Phases-CA voltage kV

13 Prot.f Frequency of protection voltage Hz

14 3I0Adj.I_Pri The residual current from parallel line kV

15 UB1.Syn.U_Pri Synchronism voltage (UB1) Hz

16 UB1.Syn.f Frequency of synchronism voltage (UB1) kV

17 UL2.Syn.U_Pri Synchronism voltage (UL2) Hz

18 UL2.Syn.f Frequency of synchronism voltage (UL2) kV

19 UB2.Syn.U_Pri Synchronism voltage (UB2) Hz

20 UB2.Syn.f Frequency of synchronism voltage (UB2) kV

5.1.2 Angle Values

All angle values are based on the same base phase angle. This base may be the phase angle of
positive-sequence voltage or positive-sequence current and is automatically switched following
with the priority of phase angle. (U1: positive-sequence voltage, I1: positive-sequence current)

⚫ Single circuit breaker application scenario

The priority of base phase angle switching is:

1. Ang(U1)

2. Ang(I1)

⚫ Double circuit breakers application scenario

5-2 PCS-902S Line Distance Relay

Date: 2023-08-01
 5 Measurement

The priority of base phase angle switching is:

1. Bus.Ang(U1)

2. CB1.Ang(I1)

3. CB2.Ang(I1)

⚫ Double busbars application scenario

The priority of base phase angle switching is:

1. Bus1.Ang(U1)

2. Bus2.Ang(U1)

No. Item Definition Unit

Single CB application

1 Prot.Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °

2 Prot.Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °

3 Prot.Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °

4 Prot.Ang (Ua-Ia)
Phase angle between phase-A voltage and phase-A current (from
°
5
protection CT)

Phase angle between phase-B voltage and phase-B current (from

5 Prot.Ang (Ub-Ib) °
protection CT)

Phase angle between phase-C voltage and phase-C current (from

6 Prot.Ang (Uc-Ic) °
protection CT)

Phase angle between phase-A current and phase-B current (from

7 Prot.Ang (Ia-Ib) °
protection CT)

Phase angle between phase-B current and phase-C current (from

8 Prot.Ang (Ib-Ic) °
protection CT)

Phase angle between phase-C current and phase-A current

9 Prot.Ang (Ic-Ia) °
(from protection CT)

10 Prot.Ang (Ua) Phase angle of phase-A voltage °

11 Prot.Ang (Ub) Phase angle of phase-B voltage °

12 Prot.Ang (Uc) Phase angle of phase-C voltage °

13 Prot.Ang (Ia) Phase angle of phase-A current (from protection CT) °

14 Prot.Ang (Ib) Phase angle of phase-B current (from protection CT) °

15 Prot.Ang (Ic) Phase angle of phase-C current (from protection CT) °

16 3I0Adj.Ang (I) Phase angle of residual current from parallel line °

17 UB1.Syn.Ang (U) Phase angle of synchronism voltage (UB1) °

18 UL2.Syn.Ang (U) Phase angle of synchronism voltage (UL2) °

19 UB2.Syn.Ang (U) Phase angle of synchronism voltage (UB2) °

PCS-902S Line Distance Relay 5-3

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

20 Meas.Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °

21 Meas.Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °

22 Meas.Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °

Phase angle between phase-A voltage and phase-A current (from

23 Meas.Ang (Ua-Ia) °
measurement CT)

Phase angle between phase-B voltage and phase-B current (from

24 Meas.Ang (Ub-Ib) °
measurement CT)

Phase angle between phase-C voltage and phase-C current (from

25 Meas.Ang (Uc-Ic) °
measurement CT)

Phase angle between phase-A current and phase-B current (from

26 Meas.Ang (Ia-Ib) °
measurement CT)

Phase angle between phase-B current and phase-C current (from

27 Meas.Ang (Ib-Ic) °
measurement CT)

Phase angle between phase-C current and phase-A current (from

28 Meas.Ang (Ic-Ia) °
measurement CT)
5 29 Meas.Ang (Ua) Phase angle of phase-A voltage °

30 Meas.Ang (Ub) Phase angle of phase-B voltage °

31 Meas.Ang (Uc) Phase angle of phase-C voltage °

32 Meas.Ang (Ia) Phase angle of phase-A current (from measurement CT) °

33 Meas.Ang (Ib) Phase angle of phase-B current (from measurement CT) °

34 Meas.Ang (Ic) Phase angle of phase-C current (from measurement CT) °

Double CBs application

1 Prot.Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °

2 Prot.Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °

3 Prot.Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °

Phase angle between phase-A voltage and phase-A current

4 Prot.CB1.Ang (Ua-Ia) °
corresponding to circuit breaker No.1

Phase angle between phase-B voltage and phase-B current

5 Prot.CB1.Ang (Ub-Ib) °
corresponding to circuit breaker No.1

Phase angle between phase-C voltage and phase-C current

6 Prot.CB1.Ang (Uc-Ic) °
corresponding to circuit breaker No.1

Phase angle between phase-A voltage and phase-A current

7 Prot.CB2.Ang (Ua-Ia) °
corresponding to circuit breaker No.2

Phase angle between phase-B voltage and phase-B current

8 Prot.CB2.Ang (Ub-Ib) °
corresponding to circuit breaker No.2

Phase angle between phase-C voltage and phase-C current

9 Prot.CB2.Ang (Uc-Ic) °
corresponding to circuit breaker No.2

5-4 PCS-902S Line Distance Relay

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

Phase angle between phase-A current and phase-B current

10 Prot.CB1.Ang (Ia-Ib) °
corresponding to circuit breaker No.1

Phase angle between phase-B current and phase-C current

11 Prot.CB1.Ang (Ib-Ic) °
corresponding to circuit breaker No.1

Phase angle between phase-C current and phase-A current

12 Prot.CB1.Ang (Ic-Ia) °
corresponding to circuit breaker No.1

Phase angle between phase-A current and phase-B current

13 Prot.CB2.Ang (Ia-Ib) °
corresponding to circuit breaker No.2

Phase angle between phase-B current and phase-C current

14 Prot.CB2.Ang (Ib-Ic) °
corresponding to circuit breaker No.2

Phase angle between phase-C current and phase-A current

15 Prot.CB2.Ang (Ic-Ia) °
corresponding to circuit breaker No.2

16 Prot.Ang (Ua) Phase angle of phase-A voltage °

17 Prot.Ang (Ub) Phase angle of phase-B voltage °

18 Prot.Ang (Uc) Phase angle of phase-C voltage °

19 Prot.CB1.Ang (Ia)
Phase angle of phase-A current corresponding to circuit breaker
°
5
No.1

Phase angle of phase-B current corresponding to circuit breaker

20 Prot.CB1.Ang (Ib) °
No.1

Phase angle of phase-C current corresponding to circuit breaker

21 Prot.CB1.Ang (Ic) °
No.1

Phase angle of phase-A current corresponding to circuit breaker

22 Prot.CB2.Ang (Ia) °
No.2

Phase angle of phase-B current corresponding to circuit breaker

23 Prot.CB2.Ang (Ib) °
No.2

Phase angle of phase-C current corresponding to circuit breaker

24 Prot.CB2.Ang (Ic) °
No.2

25 3I0Adj.Ang (I) Phase angle of residual current from parallel line °

26 UB1.Syn.Ang (U) Phase angle of synchronism voltage (UB1) °

27 UL2.Syn.Ang (U) Phase angle of synchronism voltage (UL2) °

28 UB2.Syn.Ang (U) Phase angle of synchronism voltage (UB2) °

5.1.3 Sequence Components Values

No. Item Definition Unit

Single CB application

1 Prot.I1_Pri Positive-sequence current (from protection CT) A

2 Prot.I2_Pri Negative-sequence current (from protection CT) A

3 Prot.3I0_Pri Residual current (from protection CT) A

PCS-902S Line Distance Relay 5-5

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

4 Prot.U1_Pri Positive-sequence voltage kV

5 Prot.U2_Pri Negative-sequence voltage kV

6 Prot.3U0_Pri Residual voltage kV

7 Meas.I1_Pri Positive-sequence current (from measurement CT) A

8 Meas.I2_Pri Negative-sequence current (from measurement CT) A

9 Meas.3I0_Pri Residual current (from measurement CT) A

10 Meas.U1_Pri Positive-sequence voltage kV

11 Meas.U2_Pri Negative-sequence voltage kV

12 Meas.3U0_Pri Residual voltage kV

Double CBs application

1 Prot.CB1.I1_Pri Positive-sequence current corresponding to circuit breaker No.1 A

2 Prot.CB1.I2_Pri Negative-sequence current corresponding to circuit breaker No.1 A

3 Prot.CB1.3I0_Pri Residual current corresponding to circuit breaker No.1 A

4 Prot.CB2.I1_Pri Positive-sequence current corresponding to circuit breaker No.2 A

5 5 Prot.CB2.I2_Pri Negative-sequence current corresponding to circuit breaker No.2 A

6 Prot.CB2.3I0_Pri Residual current corresponding to circuit breaker No.2 A

7 Prot.U1_Pri Positive-sequence voltage kV

8 Prot.U2_Pri Negative-sequence voltage kV

9 Prot.3U0_Pri Residual voltage kV

5.1.4 Power Values

No. Item Definition Unit

Single CB application

1 Prot.Pa_Pri Phase-A active power MW

2 Prot.Pb_Pri Phase-B active power MW

3 Prot.Pc_Pri Phase-C active power MW

4 Prot.Qa_Pri Phase-A reactive power MVAr

5 Prot.Qb_Pri Phase-B reactive power MVAr

6 Prot.Qc_Pri Phase-C reactive power MVAr

7 Prot.Sa_Pri Phase-A apparent power MVA

8 Prot.Sb_Pri Phase-B apparent power MVA

9 Prot.Sc_Pri Phase-C apparent power MVA

10 Prot.P_Pri Active power MW

11 Prot.Q_Pri Reactive power MVAr

12 Prot.S_Pri Apparent power MVA

5-6 PCS-902S Line Distance Relay

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

13 Prot.Cosa Phase-A power factor

14 Prot.Cosb Phase-B power factor

15 Prot.Cosc Phase-C power factor

16 Prot.Cos Power factor

17 Meas.Pa_Pri Phase-A active power MW

18 Meas.Pb_Pri Phase-B active power MW

19 Meas.Pc_Pri Phase-C active power MW

20 Meas.Qa_Pri Phase-A reactive power MVAr

21 Meas.Qb_Pri Phase-B reactive power MVAr

22 Meas.Qc_Pri Phase-C reactive power MVAr

23 Meas.Sa_Pri Phase-A apparent power MVA

24 Meas.Sb_Pri Phase-B apparent power MVA

25 Meas.Sc_Pri Phase-C apparent power MVA

26 Meas.P_Pri Active power MW

27 Meas.Q_Pri Reactive power MVAr 5

28 Meas.S_Pri Apparent power MVA

29 Meas.Cosa Phase-A power factor

30 Meas.Cosb Phase-B power factor

31 Meas.Cosc Phase-C power factor

32 Meas.Cos Power factor

Double CBs application

1 Prot.CB1.Pa_Pri Phase-A active power corresponding to circuit breaker No.1 MW

2 Prot.CB1.Pb_Pri Phase-B active power corresponding to circuit breaker No.1 MW

3 Prot.CB1.Pc_Pri Phase-C active power corresponding to circuit breaker No.1 MW

4 Prot.CB1.Qa_Pri Phase-A reactive power corresponding to circuit breaker No.1 MVAr

5 Prot.CB1.Qb_Pri Phase-B reactive power corresponding to circuit breaker No.1 MVAr

6 Prot.CB1.Qc_Pri Phase-C reactive power corresponding to circuit breaker No.1 MVAr

7 Prot.CB1.Sa_Pri Phase-A apparent power corresponding to circuit breaker No.1 MVA

8 Prot.CB1.Sb_Pri Phase-B apparent power corresponding to circuit breaker No.1 MVA

9 Prot.CB1.Sc_Pri Phase-C apparent power corresponding to circuit breaker No.1 MVA

10 Prot.CB1.P_Pri Active power corresponding to circuit breaker No.1 MW

11 Prot.CB1.Q_Pri Reactive power corresponding to circuit breaker No.1 MVAr

12 Prot.CB1.S_Pri Apparent power corresponding to circuit breaker No.1 MVA

13 Prot.CB1.Cosa Phase-A power factor corresponding to circuit breaker No.1

14 Prot.CB1.Cosb Phase-B power factor corresponding to circuit breaker No.1

PCS-902S Line Distance Relay 5-7

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

15 Prot.CB1.Cosc Phase-C power factor corresponding to circuit breaker No.1

16 Prot.CB1.Cos Power factor corresponding to circuit breaker No.1

17 Prot.CB2.Pa_Pri Phase-A active power corresponding to circuit breaker No.2 MW

18 Prot.CB2.Pb_Pri Phase-B active power corresponding to circuit breaker No.2 MW

19 Prot.CB2.Pc_Pri Phase-C active power corresponding to circuit breaker No.2 MW

20 Prot.CB2.Qa_Pri Phase-A reactive power corresponding to circuit breaker No.2 MVAr

21 Prot.CB2.Qb_Pri Phase-B reactive power corresponding to circuit breaker No.2 MVAr

22 Prot.CB2.Qc_Pri Phase-C reactive power corresponding to circuit breaker No.2 MVAr

23 Prot.CB2.Sa_Pri Phase-A apparent power corresponding to circuit breaker No.2 MVA

24 Prot.CB2.Sb_Pri Phase-B apparent power corresponding to circuit breaker No.2 MVA

25 Prot.CB2.Sc_Pri Phase-C apparent power corresponding to circuit breaker No.2 MVA

26 Prot.CB2.P_Pri Active power corresponding to circuit breaker No.2 MW

27 Prot.CB2.Q_Pri Reactive power corresponding to circuit breaker No.2 MVAr

28 Prot.CB2.S_Pri Apparent power corresponding to circuit breaker No.2 MVA

5 29 Prot.CB2.Cosa Phase-A power factor corresponding to circuit breaker No.2

30 Prot.CB2.Cosb Phase-B power factor corresponding to circuit breaker No.2

31 Prot.CB2.Cosc Phase-C power factor corresponding to circuit breaker No.2

32 Prot.CB2.Cos Power factor corresponding to circuit breaker No.2

5.1.5 Harmonics

No. Item Definition Unit

Single CB application

1 Prot.Ua_Hm01_Pri 1st voltage harmonic (phase A) kV

2 Prot.Ua_Hm02_Pri 2nd voltage harmonic (phase A) kV

3 Prot.Ua_Hm03_Pri 3rd voltage harmonic (phase A) kV

4 Prot.Ua_Hm04_Pri 4th voltage harmonic (phase A) kV

5 Prot.Ua_Hm05_Pri 5th voltage harmonic (phase A) kV

6 Prot.Ua_Hm06_Pri 6th voltage harmonic (phase A) kV

7 Prot.Ua_Hm07_Pri 7th voltage harmonic (phase A) kV

8 Prot.Ua_Hm08_Pri 8th voltage harmonic (phase A) kV

9 Prot.Ua_Hm09_Pri 9th voltage harmonic (phase A) kV

10 Prot.Ua_Hm10_Pri 10th voltage harmonic (phase A) kV

11 Prot.Ua_Hm11_Pri 11th voltage harmonic (phase A) kV

12 Prot.Ua_Hm12_Pri 12th voltage harmonic (phase A) kV

13 Prot.Ua_Hm13_Pri 13th voltage harmonic (phase A) kV

5-8 PCS-902S Line Distance Relay

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

14 Prot.Ua_Hm14_Pri 14th voltage harmonic (phase A) kV

15 Prot.Ua_Hm15_Pri 15th voltage harmonic (phase A) kV

Double CBs application

16 Meas.Ua_Hm01_Pri 1st voltage harmonic (phase A) kV

17 Meas.Ua_Hm02_Pri 2nd voltage harmonic (phase A) kV

18 Meas.Ua_Hm03_Pri 3rd voltage harmonic (phase A) kV

19 Meas.Ua_Hm04_Pri 4th voltage harmonic (phase A) kV

20 Meas.Ua_Hm05_Pri 5th voltage harmonic (phase A) kV

21 Meas.Ua_Hm06_Pri 6th voltage harmonic (phase A) kV

22 Meas.Ua_Hm07_Pri 7th voltage harmonic (phase A) kV

23 Meas.Ua_Hm08_Pri 8th voltage harmonic (phase A) kV

24 Meas.Ua_Hm09_Pri 9th voltage harmonic (phase A) kV

25 Meas.Ua_Hm10_Pri 10th voltage harmonic (phase A) kV

26 Meas.Ua_Hm11_Pri 11th voltage harmonic (phase A) kV

27 Meas.Ua_Hm12_Pri 12th voltage harmonic (phase A) kV

5
28 Meas.Ua_Hm13_Pri 13th voltage harmonic (phase A) kV

29 Meas.Ua_Hm14_Pri 14th voltage harmonic (phase A) kV

30 Meas.Ua_Hm15_Pri 15th voltage harmonic (phase A) kV

5.2 Secondary Values

Access path: MainMenuMeasurementsSecondary Values

5.2.1 General Values

No. Item Definition Unit

Single CB application

1 Prot.Ia_Sec Phase-A current (from protection CT) A

2 Prot.Ib_Sec Phase-B current (from protection CT) A

3 Prot.Ic_Sec Phase-C current (from protection CT) A

4 Prot.Ua_Sec Phase-A voltage V

5 Prot.Ub_Sec Phase-B voltage V

6 Prot.Uc_Sec Phase-C voltage V

7 Prot.Uab_Sec Phases-AB voltage V

8 Prot.Ubc_Sec Phases-BC voltage V

9 Prot.Uca_Sec Phases-CA voltage V

10 Prot.f Frequency of protection voltage Hz

PCS-902S Line Distance Relay 5-9

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

11 3I0Adj.I_Sec The residual current from parallel line V

12 UB1.Syn.U_Sec Synchronism voltage (UB1) Hz

13 UB1.Syn.f Frequency of synchronism voltage (UB1) V

14 UL2.Syn.U_Sec Synchronism voltage (UL2) Hz

15 UL2.Syn.f Frequency of synchronism voltage (UL2) V

16 UB2.Syn.U_Sec Synchronism voltage (UB2) Hz

17 UB2.Syn.f Frequency of synchronism voltage (UB2) V

18 Meas.Ia_Sec Phase-A current (from measurement CT) A

19 Meas.Ib_Sec Phase-B current (from measurement CT) A

20 Meas.Ic_Sec Phase-C current (from measurement CT) A

21 Meas.Ua_Sec Phase-A voltage V

22 Meas.Ub_Sec Phase-B voltage V

23 Meas.Uc_Sec Phase-C voltage V

24 Meas.Uab_Sec Phases-AB voltage V

5 25 Meas.Ubc_Sec Phases-BC voltage V

26 Meas.Uca_Sec Phases-CA voltage V

27 Meas.f Frequency of protection voltage Hz

Double CBs application

1 Prot.CB1.Ia_Sec Phase-A current corresponding to circuit breaker No.1 A

2 Prot.CB1.Ib_Sec Phase-B current corresponding to circuit breaker No.1 A

3 Prot.CB1.Ic_Sec Phase-C current corresponding to circuit breaker No.1 A

4 Prot.CB2.Ia_Sec Phase-A current corresponding to circuit breaker No.2 A

5 Prot.CB2.Ib_Sec Phase-B current corresponding to circuit breaker No.2 A

6 Prot.CB2.Ic_Sec Phase-C current corresponding to circuit breaker No.2 A

7 Prot.Ua_Sec Phase-A voltage V

8 Prot.Ub_Sec Phase-B voltage V

9 Prot.Uc_Sec Phase-C voltage V

10 Prot.Uab_Sec Phases-AB voltage V

11 Prot.Ubc_Sec Phases-BC voltage V

12 Prot.Uca_Sec Phases-CA voltage V

13 Prot.f Frequency of protection voltage Hz

14 3I0Adj.I_Sec The residual current from parallel line V

15 UB1.Syn.U_Sec Synchronism voltage (UB1) Hz

16 UB1.Syn.f Frequency of synchronism voltage (UB1) V

17 UL2.Syn.U_Sec Synchronism voltage (UL2) Hz

5-10 PCS-902S Line Distance Relay

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

18 UL2.Syn.f Frequency of synchronism voltage (UL2) V

19 UB2.Syn.U_Sec Synchronism voltage (UB2) Hz

20 UB2.Syn.f Frequency of synchronism voltage (UB2) V

5.2.2 Angle Values

All angle values are based on the same base phase angle. This base may be the phase angle of
positive-sequence voltage or positive-sequence current and is automatically switched following
with the priority of phase angle. (U1: positive-sequence voltage, I1: positive-sequence current)

⚫ Single circuit breaker application scenario

The priority of base phase angle switching is:

1. Ang(U1)

2. Ang(I1)

⚫ Double circuit breakers application scenario

The priority of base phase angle switching is: 5

1. Bus.Ang(U1)

2. CB1.Ang(I1)

3. CB2.Ang(I1)

⚫ Double busbars application scenario

The priority of base phase angle switching is:

1. Bus1.Ang(U1)

2. Bus2.Ang(U1)

No. Item Definition Unit

Single CB application

Phase angle between phase-A voltage and phase-A current (from

1 Prot.Ang (Ua-Ia) °
measurement CT)

Phase angle between phase-B voltage and phase-B current (from

2 Prot.Ang (Ub-Ib) °
measurement CT)

Phase angle between phase-C voltage and phase-C current (from

3 Prot.Ang (Uc-Ic) °
measurement CT)

4 Prot.Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °

5 Prot.Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °

6 Prot.Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °

7 Prot.Ang (Ia-Ib) Phase angle between phase-A current and phase-B current (from °

PCS-902S Line Distance Relay 5-11

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

measurement CT)

Phase angle between phase-B current and phase-C current (from

8 Prot.Ang (Ib-Ic) °
measurement CT)

Phase angle between phase-C current and phase-A current (from

9 Prot.Ang (Ic-Ia) °
protection CT)

10 Prot.Ang (Ua) Phase angle of phase-A voltage °

11 Prot.Ang (Ub) Phase angle of phase-B voltage °

12 Prot.Ang (Uc) Phase angle of phase-C voltage °

13 Prot.Ang (Ia) Phase angle of phase-A current (from protection CT) °

14 Prot.Ang (Ib) Phase angle of phase-B current (from protection CT) °

15 Prot.Ang (Ic) Phase angle of phase-C current (from protection CT) °

16 3I0Adj.Ang (I) Phase angle of residual current from parallel line °

17 UB1.Syn.Ang (U) Phase angle of synchronism voltage (UB1) °

18 UL2.Syn.Ang (U) Phase angle of synchronism voltage (UL2) °

5 19 UB2.Syn.Ang (U) Phase angle of synchronism voltage (UB2) °

Phase angle between phase-A voltage and phase-A current (from

20 Meas.Ang (Ua-Ia) °
measurement CT)

Phase angle between phase-B voltage and phase-B current (from

21 Meas.Ang (Ub-Ib) °
measurement CT)

Phase angle between phase-C voltage and phase-C current (from

22 Meas.Ang (Uc-Ic) °
measurement CT)

23 Meas.Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °

24 Meas.Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °

25 Meas.Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °

Phase angle between phase-A current and phase-B current (from

26 Meas.Ang (Ia-Ib) °
measurement CT)

Phase angle between phase-B current and phase-C current (from

27 Meas.Ang (Ib-Ic) °
measurement CT)

Phase angle between phase-C current and phase-A current (from

28 Meas.Ang (Ic-Ia) °
measurement CT)

29 Meas.Ang (Ua) Phase angle of phase-A voltage °

30 Meas.Ang (Ub) Phase angle of phase-B voltage °

31 Meas.Ang (Uc) Phase angle of phase-C voltage °

32 Meas.Ang (Ia) Phase angle of phase-A current (from measurement CT) °

33 Meas.Ang (Ib) Phase angle of phase-B current (from measurement CT) °

34 Meas.Ang (Ic) Phase angle of phase-C current (from measurement CT) °

5-12 PCS-902S Line Distance Relay

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

Double CBs application

Phase angle between phase-A voltage and phase-A current

1 Prot.CB1.Ang (Ua-Ia) °
corresponding to circuit breaker No.1

Phase angle between phase-B voltage and phase-B current

2 Prot.CB1.Ang (Ub-Ib) °
corresponding to circuit breaker No.1

Phase angle between phase-C voltage and phase-C current

3 Prot.CB1.Ang (Uc-Ic) °
corresponding to circuit breaker No.1

Phase angle between phase-A voltage and phase-A current

4 Prot.CB2.Ang (Ua-Ia) °
corresponding to circuit breaker No.2

Phase angle between phase-B voltage and phase-B current

5 Prot.CB2.Ang (Ub-Ib) °
corresponding to circuit breaker No.2

Phase angle between phase-C voltage and phase-C current

6 Prot.CB2.Ang (Uc-Ic) °
corresponding to circuit breaker No.2

7 Prot.Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °

8 Prot.Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °

9 Prot.Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage ° 5
Phase angle between phase-A current and phase-B current
10 Prot.CB1.Ang (Ia-Ib) °
corresponding to circuit breaker No.1

Phase angle between phase-B current and phase-C current

11 Prot.CB1.Ang (Ib-Ic) °
corresponding to circuit breaker No.1

Phase angle between phase-C current and phase-A current

12 Prot.CB1.Ang (Ic-Ia) °
corresponding to circuit breaker No.1

Phase angle between phase-A current and phase-B current

13 Prot.CB2.Ang (Ia-Ib) °
corresponding to circuit breaker No.2

Phase angle between phase-B current and phase-C current

14 Prot.CB2.Ang (Ib-Ic) °
corresponding to circuit breaker No.2

Phase angle between phase-C current and phase-A current

15 Prot.CB2.Ang (Ic-Ia) °
corresponding to circuit breaker No.2

16 Prot.Ang (Ua) Phase angle of phase-A voltage °

17 Prot.Ang (Ub) Phase angle of phase-B voltage °

18 Prot.Ang (Uc) Phase angle of phase-C voltage °

19 Prot.CB1.Ang (Ia) Phase angle of phase-A current corresponding to circuit breaker No.1 °

20 Prot.CB1.Ang (Ib) Phase angle of phase-B current corresponding to circuit breaker No.1 °

21 Prot.CB1.Ang (Ic) Phase angle of phase-C current corresponding to circuit breaker No.1 °

22 Prot.CB2.Ang (Ia) Phase angle of phase-A current corresponding to circuit breaker No.2 °

23 Prot.CB2.Ang (Ib) Phase angle of phase-B current corresponding to circuit breaker No.2 °

24 Prot.CB2.Ang (Ic) Phase angle of phase-C current corresponding to circuit breaker No.2 °

PCS-902S Line Distance Relay 5-13

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

25 3I0Adj.Ang (I) Phase angle of residual current from parallel line °

26 UB1.Syn.Ang (U) Phase angle of synchronism voltage (UB1) °

27 UL2.Syn.Ang (U) Phase angle of synchronism voltage (UL2) °

28 UB2.Syn.Ang (U) Phase angle of synchronism voltage (UB2) °

5.2.3 Sequence Components Values

No. Item Definition Unit

Single CB application

1 Prot.I1_Sec Positive-sequence current (from protection CT) A

2 Prot.I2_Sec Negative-sequence current (from protection CT) A

3 Prot.3I0_Sec Residual current (from protection CT) A

4 Prot.U1_Sec Positive-sequence voltage V

5 Prot.U2_Sec Negative-sequence voltage V

6 Prot.3U0_Sec Residual voltage V

5 7 Meas.I1_Sec Positive-sequence current (from measurement CT) A

8 Meas.I2_Sec Negative-sequence current (from measurement CT) A

9 Meas.3I0_Sec Residual current (from measurement CT) A

10 Meas.U1_Sec Positive-sequence voltage V

11 Meas.U2_Sec Negative-sequence voltage V

12 Meas.3U0_Sec Residual voltage V

Double CBs application

1 Prot.CB1.I1_Sec Positive-sequence current corresponding to circuit breaker No.1 A

2 Prot.CB1.I2_Sec Negative-sequence current corresponding to circuit breaker No.1 A

3 Prot.CB1.3I0_Sec Residual current corresponding to circuit breaker No.1 A

4 Prot.CB2.I1_Sec Positive-sequence current corresponding to circuit breaker No.2 A

5 Prot.CB2.I2_Sec Negative-sequence current corresponding to circuit breaker No.2 A

6 Prot.CB2.3I0_Sec Residual current corresponding to circuit breaker No.2 A

5.2.4 Power Values

No. Item Definition Unit

Single CB application

1 Prot.Pa_Sec Phase-A active power W

2 Prot.Pb_Sec Phase-B active power W

3 Prot.Pc_Sec Phase-C active power W

4 Prot.Qa_Sec Phase-A reactive power VAr

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 5 Measurement

No. Item Definition Unit

5 Prot.Qb_Sec Phase-B reactive power VAr

6 Prot.Qc_Sec Phase-C reactive power VAr

7 Prot.Sa_Sec Phase-A apparent power VA

8 Prot.Sb_Sec Phase-B apparent power VA

9 Prot.Sc_Sec Phase-C apparent power VA

10 Prot.P_Sec Active power W

11 Prot.Q_Sec Reactive power VAr

12 Prot.S_Sec Apparent power VA

13 Prot.Cosa Phase-A power factor

14 Prot.Cosb Phase-B power factor

15 Prot.Cosc Phase-C power factor

16 Prot.Cos Power factor

17 Meas.Pa_Sec Phase-A active power W

18 Meas.Pb_Sec Phase-B active power W

19 Meas.Pc_Sec Phase-C active power W 5

20 Meas.Qa_Sec Phase-A reactive power VAr

21 Meas.Qb_Sec Phase-B reactive power VAr

22 Meas.Qc_Sec Phase-C reactive power VAr

23 Meas.Sa_Sec Phase-A apparent power VA

24 Meas.Sb_Sec Phase-B apparent power VA

25 Meas.Sc_Sec Phase-C apparent power VA

26 Meas.P_Sec Active power W

27 Meas.Q_Sec Reactive power VAr

28 Meas.S_Sec Apparent power VA

29 Meas.Cosa Phase-A power factor

30 Meas.Cosb Phase-B power factor

31 Meas.Cosc Phase-C power factor

32 Meas.Cos Power factor

Double CBs application

1 Prot.CB1.Pa_Sec Phase-A active power corresponding to circuit breaker No.1 W

2 Prot.CB1.Pb_Sec Phase-B active power corresponding to circuit breaker No.1 W

3 Prot.CB1.Pc_Sec Phase-C active power corresponding to circuit breaker No.1 W

4 Prot.CB1.Qa_Sec Phase-A reactive power corresponding to circuit breaker No.1 VAr

5 Prot.CB1.Qb_Sec Phase-B reactive power corresponding to circuit breaker No.1 VAr

6 Prot.CB1.Qc_Sec Phase-C reactive power corresponding to circuit breaker No.1 VAr

PCS-902S Line Distance Relay 5-15

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

7 Prot.CB1.Sa_Sec Phase-A apparent power corresponding to circuit breaker No.1 VA

8 Prot.CB1.Sb_Sec Phase-B apparent power corresponding to circuit breaker No.1 VA

9 Prot.CB1.Sc_Sec Phase-C apparent power corresponding to circuit breaker No.1 VA

10 Prot.CB1.P_Sec Active power corresponding to circuit breaker No.1 W

11 Prot.CB1.Q_Sec Reactive power corresponding to circuit breaker No.1 VAr

12 Prot.CB1.S_Sec Apparent power corresponding to circuit breaker No.1 VA

13 Prot.CB1.Cosa Phase-A power factor corresponding to circuit breaker No.1

14 Prot.CB1.Cosb Phase-B power factor corresponding to circuit breaker No.1

15 Prot.CB1.Cosc Phase-C power factor corresponding to circuit breaker No.1

16 Prot.CB1.Cos Power factor corresponding to circuit breaker No.1

17 Prot.CB2.Pa_Sec Phase-A active power corresponding to circuit breaker No.2 W

18 Prot.CB2.Pb_Sec Phase-B active power corresponding to circuit breaker No.2 W

19 Prot.CB2.Pc_Sec Phase-C active power corresponding to circuit breaker No.2 W

20 Prot.CB2.Qa_Sec Phase-A reactive power corresponding to circuit breaker No.2 VAr

5 21 Prot.CB2.Qb_Sec Phase-B reactive power corresponding to circuit breaker No.2 VAr

22 Prot.CB2.Qc_Sec Phase-C reactive power corresponding to circuit breaker No.2 VAr

23 Prot.CB2.Sa_Sec Phase-A apparent power corresponding to circuit breaker No.2 VA

24 Prot.CB2.Sb_Sec Phase-B apparent power corresponding to circuit breaker No.2 VA

25 Prot.CB2.Sc_Sec Phase-C apparent power corresponding to circuit breaker No.2 VA

26 Prot.CB2.P_Sec Active power corresponding to circuit breaker No.2 W

27 Prot.CB2.Q_Sec Reactive power corresponding to circuit breaker No.2 VAr

28 Prot.CB2.S_Sec Apparent power corresponding to circuit breaker No.2 MA

29 Prot.CB2.Cosa Phase-A power factor corresponding to circuit breaker No.2

30 Prot.CB2.Cosb Phase-B power factor corresponding to circuit breaker No.2

31 Prot.CB2.Cosc Phase-C power factor corresponding to circuit breaker No.2

32 Prot.CB2.Cos Power factor corresponding to circuit breaker No.2

5.2.5 Harmonics

No. Item Definition Unit

Single CB application

1 Prot.Ua_Hm01_Sec 1st voltage harmonic (phase A) V

2 Prot.Ua_Hm02_Sec 2nd voltage harmonic (phase A) V

3 Prot.Ua_Hm03_Sec 3rd voltage harmonic (phase A) V

4 Prot.Ua_Hm04_Sec 4th voltage harmonic (phase A) V

5 Prot.Ua_Hm05_Sec 5th voltage harmonic (phase A) V

6 Prot.Ua_Hm06_Sec 6th voltage harmonic (phase A) V

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 5 Measurement

No. Item Definition Unit

7 Prot.Ua_Hm07_Sec 7th voltage harmonic (phase A) V

8 Prot.Ua_Hm08_Sec 8th voltage harmonic (phase A) V

9 Prot.Ua_Hm09_Sec 9th voltage harmonic (phase A) V

10 Prot.Ua_Hm10_Sec 10th voltage harmonic (phase A) V

11 Prot.Ua_Hm11_Sec 11th voltage harmonic (phase A) V

12 Prot.Ua_Hm12_Sec 12th voltage harmonic (phase A) V

13 Prot.Ua_Hm13_Sec 13th voltage harmonic (phase A) V

14 Prot.Ua_Hm14_Sec 14th voltage harmonic (phase A) V

15 Prot.Ua_Hm15_Sec 15th voltage harmonic (phase A) V

Double CBs application

16 Meas.Ua_Hm01_Sec 1st voltage harmonic (phase A) V

17 Meas.Ua_Hm02_Sec 2nd voltage harmonic (phase A) V

18 Meas.Ua_Hm03_Sec 3rd voltage harmonic (phase A) V

19 Meas.Ua_Hm04_Sec 4th voltage harmonic (phase A) V

20 Meas.Ua_Hm05_Sec 5th voltage harmonic (phase A) V

5
21 Meas.Ua_Hm06_Sec 6th voltage harmonic (phase A) V

22 Meas.Ua_Hm07_Sec 7th voltage harmonic (phase A) V

23 Meas.Ua_Hm08_Sec 8th voltage harmonic (phase A) V

24 Meas.Ua_Hm09_Sec 9th voltage harmonic (phase A) V

25 Meas.Ua_Hm10_Sec 10th voltage harmonic (phase A) V

26 Meas.Ua_Hm11_Sec 11th voltage harmonic (phase A) V

27 Meas.Ua_Hm12_Sec 12th voltage harmonic (phase A) V

28 Meas.Ua_Hm13_Sec 13th voltage harmonic (phase A) V

29 Meas.Ua_Hm14_Sec 14th voltage harmonic (phase A) V

30 Meas.Ua_Hm15_Sec 15th voltage harmonic (phase A) V

5.3 Function Values

Access path: MainMenuMeasurementsFunction Values

5.3.1 Sum Values

No. Item Definition Unit

1 Prot.Sum.Ia_Pri Sum of phase-A currents (primary value) A

2 Prot.Sum.Ib_Pri Sum of phase-B currents (primary value) A

3 Prot.Sum.Ic_Pri Sum of phase-C currents (primary value) A

4 Prot.Sum.Ia_Sec Sum of phase-A currents (secondary value) A

PCS-902S Line Distance Relay 5-17

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

5 Prot.Sum.Ib_Sec Sum of phase-B currents (secondary value) A

6 Prot.Sum.Ic_Sec Sum of phase-C currents (secondary value) A

7 Prot.Sum.Pa_Pri Sum of phase-A active power (primary value) MW

8 Prot.Sum.Pb_Pri Sum of phase-B active power (primary value) MW

9 Prot.Sum.Pc_Pri Sum of phase-C active power (primary value) MW

10 Prot.Sum.Qa_Pri Sum of phase-A reactive power (primary value) MVAr

11 Prot.Sum.Qb_Pri Sum of phase-B reactive power (primary value) MVAr

12 Prot.Sum.Qc_Pri Sum of phase-C reactive power (primary value) MVAr

13 Prot.Sum.Sa_Pri Sum of phase-A apparent power (primary value) MVA

14 Prot.Sum.Sb_Pri Sum of phase-B apparent power (primary value) MVA

15 Prot.Sum.Sc_Pri Sum of phase-C apparent power (primary value) MVA

16 Prot.Sum.P_Pri Sum of three-phase active power (primary value) MW

17 Prot.Sum.Q_Pri Sum of three-phase reactive power (primary value) MVAr

18 Prot.Sum.S_Pri Sum of three-phase apparent power (primary value) MVA

5 19 Prot.Sum.Pa_Sec Sum of phase-A active power (secondary value) W

20 Prot.Sum.Pb_Sec Sum of phase-B active power (secondary value) W

21 Prot.Sum.Pc_Sec Sum of phase-C active power (secondary value) W

22 Prot.Sum.Qa_Sec Sum of phase-A reactive power (secondary value) VAr

23 Prot.Sum.Qb_Sec Sum of phase-B reactive power (secondary value) VAr

24 Prot.Sum.Qc_Sec Sum of phase-C reactive power (secondary value) VAr

25 Prot.Sum.Sa_Sec Sum of phase-A apparent power (secondary value) VA

26 Prot.Sum.Sb_Sec Sum of phase-B apparent power (secondary value) VA

27 Prot.Sum.Sc_Sec Sum of phase-C apparent power (secondary value) VA

28 Prot.Sum.P_Sec Sum of three-phase active power (secondary value) W

29 Prot.Sum.Q_Sec Sum of three-phase reactive power (secondary value) VAr

30 Prot.Sum.S_Sec Sum of three-phase apparent power (secondary value) VA

31 Prot.Sum.Cosa Power factor of phase-A sum power

32 Prot.Sum.Cosb Power factor of phase-B sum power

33 Prot.Sum.Cosc Power factor of phase-C sum power

34 Prot.Sum.Cos Power factor of three-phase sum power

5.3.2 ThOvLd Values

No. Item Definition Unit

The thermal accumulation for stage 1 of thermal overload protection

1 49P1.Accu_A %
(Phase A)

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 5 Measurement

No. Item Definition Unit

The thermal accumulation for stage 1 of thermal overload protection

2 49P1.Accu_B %
(Phase B)

The thermal accumulation for stage 1 of thermal overload protection

3 49P1.Accu_C %
(Phase C)

The calculated temperature difference between the protected

4 49P1.T_Diff_A component's temperature and the environmental medium ˚C
temperature for stage 1 of thermal overload protection (Phase A)

The calculated temperature difference between the protected

5 49P1.T_Diff_B component's temperature and the environmental medium ˚C
temperature for stage 1 of thermal overload protection (Phase B)

The calculated temperature difference between the protected

6 49P1.T_Diff_C component's temperature and the environmental medium ˚C
temperature for stage 1 of thermal overload protection (Phase C)

The thermal accumulation for stage 2 of thermal overload protection

7 49P2.Accu_A %
(Phase A)

8 49P2.Accu_B
The thermal accumulation for stage 2 of thermal overload protection
(Phase B)
% 5
The thermal accumulation for stage 2 of thermal overload protection
9 49P2.Accu_C %
(Phase C)

The calculated temperature difference between the protected

10 49P2.T_Diff_A component's temperature and the environmental medium ˚C
temperature for stage 2 of thermal overload protection (Phase A)

The calculated temperature difference between the protected

11 49P2.T_Diff_B component's temperature and the environmental medium ˚C
temperature for stage 2 of thermal overload protection (Phase B)

The calculated temperature difference between the protected

12 49P2.T_Diff_C component's temperature and the environmental medium ˚C
temperature for stage 2 of thermal overload protection (Phase C)

5.3.3 Synchronism Check

No. Item Definition Unit

Primary voltage of reference side corresponding to circuit breaker

1 CB1.25.U_Ref_Pri kV
No.1

Primary voltage of synchronization side corresponding to circuit

2 CB1.25.U_Syn_Pri kV
breaker No.1

Primary voltage difference for synchronism check corresponding to

3 CB1.25.U_Diff_Pri kV
circuit breaker No.1

Secondary voltage of reference side corresponding to circuit

4 CB1.25.U_Ref_Sec V
breaker No.1

PCS-902S Line Distance Relay 5-19

Date: 2023-08-01
 5 Measurement

No. Item Definition Unit

Secondary voltage of synchronization side corresponding to circuit

5 CB1.25.U_Syn_Sec V
breaker No.1

Secondary voltage difference for synchronism check corresponding

6 CB1.25.U_Diff_Sec V
to circuit breaker No.1

Phase angle difference for synchronism check corresponding to

7 CB1.25.phi_Diff °
circuit breaker No.1

8 CB1.25.f_Ref Frequency of reference side corresponding to circuit breaker No.1 Hz

Frequency of synchronization side corresponding to circuit breaker

9 CB1.25.f_Syn Hz
No.1

Frequency difference for synchronism check corresponding to

10 CB1.25.f_Diff Hz
circuit breaker No.1

Frequency variation rate for synchronism check corresponding to

11 CB1.25.df/dt Hz/s
circuit breaker No.1

12 CB1.25.RSYN_OK The synchronism check logic of circuit breaker No.1 is satisfied.

13 CB1.25.SynChk_OK The synchro-check logic of circuit breaker No.1 is satisfied.

5 14 CB1.25.DdChk_OK The dead charge check logic of circuit breaker No.1 is satisfied.

15 CB1.25.U_Diff_OK Voltage difference criteria of circuit breaker No.1 is satisfied.

16 CB1.25.f_Diff_OK Frequency difference criteria of circuit breaker No.1 is satisfied.

17 CB1.25.df/dt_OK Frequency variation criteria of circuit breaker No.1 is satisfied.

18 CB1.25.phi_Diff_OK Phase difference criteria of circuit breaker No.1 is satisfied.

19 CB1.25.RefDd Dead check of circuit breaker No.1 at reference side is passed.

20 CB1.25.RefLv Live check of circuit breaker No.1 at reference side is passed.

Dead check of circuit breaker No.1 at synchronization side is

21 CB1.25.SynDd
passed.

22 CB1.25.SynLv Live check of circuit breaker No.1 at synchronization side is passed.

Primary voltage of reference side corresponding to circuit breaker

23 CB2.25.U_Ref_Pri kV
No.2

Primary voltage of synchronization side corresponding to circuit

24 CB2.25.U_Syn_Pri kV
breaker No.2

Primary voltage difference for synchronism check corresponding to

25 CB2.25.U_Diff_Pri kV
circuit breaker No.2

Secondary voltage of reference side corresponding to circuit

26 CB2.25.U_Ref_Sec V
breaker No.2

Secondary voltage of synchronization side corresponding to circuit

27 CB2.25.U_Syn_Sec V
breaker No.2

Secondary voltage difference for synchronism check corresponding

28 CB2.25.U_Diff_Sec V
to circuit breaker No.2

29 CB2.25.phi_Diff Phase angle difference for synchronism check corresponding to °

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 5 Measurement

No. Item Definition Unit

circuit breaker No.2

30 CB1.25.f_Ref Frequency of reference side corresponding to circuit breaker No.2 Hz

Frequency of synchronization side corresponding to circuit breaker

31 CB2.25.f_Syn Hz
No.2

Frequency difference for synchronism check corresponding to

32 CB2.25.f_Diff Hz
circuit breaker No.2

Frequency variation rate for synchronism check corresponding to

33 CB2.25.df/dt Hz/s
circuit breaker No.2

34 CB2.25.RSYN_OK The synchronism check logic of circuit breaker No.2 is satisfied.

35 CB2.25.SynChk_OK The synchro-check logic of circuit breaker No.2 is satisfied.

36 CB2.25.DdChk_OK The dead charge check logic of circuit breaker No.2 is satisfied.

37 CB2.25.U_Diff_OK Voltage difference criteria of circuit breaker No.2 is satisfied.

38 CB2.25.f_Diff_OK Frequency difference criteria of circuit breaker No.2 is satisfied.

39 CB2.25.df/dt_OK Frequency variation criteria of circuit breaker No.2 is satisfied.

40

41
CB2.25.phi_Diff_OK

CB2.25.RefDd
Phase difference criteria of circuit breaker No.2 is satisfied.

Dead check of circuit breaker No.2 at reference side is passed.

5
42 CB2.25.RefLv Live check of circuit breaker No.2 at reference side is passed.

Dead check of circuit breaker No.2 at synchronization side is

43 CB2.25.SynDd
passed.

44 CB2.25.SynLv Live check of circuit breaker No.2 at synchronization side is passed.

5.3.4 SCBR Values

Please refer to Section 6.6.8.

5.4 Energy Metering

Access path: MainMenuMeasurementsEnergy Metering

No. Item Definition Unit

1 MMTR.EA_Accu_Fwd Positive active energy kWh

2 MMTR.EA_Accu_Rev Negative active energy kWh

3 MMTR.ER_Accu_Fwd Positive reactive energy kVArh

4 MMTR.ER_Accu_Rev Negative reactive energy kVArh

5 MMTR.EA_Accu_Fwd_A Positive active energy for phase A kWh

6 MMTR.EA_Accu_Rev_A Negative active energy for phase A kWh

7 MMTR.ER_Accu_Fwd_A Positive reactive energy for phase A kVArh

8 MMTR.ER_Accu_Rev_A Negative reactive energy for phase A kVArh

PCS-902S Line Distance Relay 5-21

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 5 Measurement

No. Item Definition Unit

9 MMTR.EA_Accu_Fwd_B Positive active energy for phase B kWh

10 MMTR.EA_Accu_Rev_B Negative active energy for phase B kWh

11 MMTR.ER_Accu_Fwd_B Positive reactive energy for phase B kVArh

12 MMTR.ER_Accu_Rev_B Negative reactive energy for phase B kVArh

13 MMTR.EA_Accu_Fwd_C Positive active energy for phase C kWh

14 MMTR.EA_Accu_Rev_C Negative active energy for phase C kWh

15 MMTR.ER_Accu_Fwd_C Positive reactive energy for phase C kVArh

16 MMTR.ER_Accu_Rev_C Negative reactive energy for phase C kVArh

5.5 Power Quality

Access path: MainMenuMeasurementsPower Quality

No. Item Definition Unit

Deviation of phase-A voltage

5 1 Prot.Ua_Devn Ua × √3 − Unn %
=
Unn

Deviation of phase-B voltage

2 Prot.Ub_Devn Ub × √3 − Unn %
=
Unn

Deviation of phase-C voltage

3 Prot.Uc_Devn Uc × √3 − Unn %
=
Unn

Deviation of frequency
4 Prot.f_Devn Hz
=f_meas-fn

Unbalance rate of negative-sequence voltage

5 Prot.UnbalRate_U2 U2 %
=
U1

Unbalance rate of calculated zero-sequence voltage

6 Prot.UnbalRate_3U0 3U0 %
=
U1

Total Harmonic Distortion (THD) of phase-A voltage

7 Prot.THD_Ua √∑15 2 %
i=2 Ua Hm_i
THD =
UHm_1

Total Harmonic Distortion (THD) of phase-B voltage

8 Prot.THD_Ub √∑15 2 %
i=2 Ub Hm_i
THD =
UHm_1

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 5 Measurement

No. Item Definition Unit

Total Harmonic Distortion (THD) of phase-C voltage

9 Prot.THD_Uc √∑15 2 %
i=2 Uc Hm_i
THD =
UHm_1

Unbalance rate of negative-sequence current = I2/I1

10 Prot.UnbalRate_I2 I2 %
=
I1

Unbalance rate of calculated zero-sequence current

11 Prot.UnbalRate_3I0 3I0 %
=
I1

Total Harmonic Distortion (THD) of phase-A current

12 Prot.THD_Ia √∑15 2 %
i=2 Ia Hm_i
THD =
IHm_1

Total Harmonic Distortion (THD) of phase-B current

13 Prot.THD_Ib
THD =
√∑15 2
i=2 Ib Hm_i
%
5
IHm_1

Total Harmonic Distortion (THD) of phase-C current

14 Prot.THD_Ic √∑15 2 %
i=2 Ic Hm_i
THD =
IHm_1

Unbalance rate of negative-sequence current corresponding to

circuit breaker No.1
15 Prot.CB1.UnbalRate_I2 %
I2
=
I1

Unbalance rate of calculated zero-sequence current corresponding

to circuit breaker No.1
16 Prot.CB1.UnbalRate_3I0 %
3I0
=
I1

Unbalance rate of negative-sequence current corresponding to

circuit breaker No.2
17 Prot.CB2.UnbalRate_I2 %
I2
=
I1

Unbalance rate of calculated zero-sequence current corresponding

to circuit breaker No.2
18 Prot.CB2.UnbalRate_3I0 %
3I0
=
I1

PCS-902S Line Distance Relay 5-23

Date: 2023-08-01
 5 Measurement

5.6 Synchrophasor Measurement

The integrated Phasor Measurement Unit (PMU) function of synchrophasor measurement receives
raw data from the common A/D module. It is applied to measure synchrophasor of busbar, line or
transformer in substation and power plant, to calculate frequency and active/reactive power, and to
send real-time data to local Phasor Data Concentrators (PDC) in substation or to super PDC of
upper level.

Figure 5.6-1 Structure of a wide-area monitoring system with PMU

5.6.1 Function Description

The PMU measures the phasor values of current and voltage. These values get a high precision
time stamp and together with the values of power frequency, power frequency change rate and
optional binary data that are also time stamped are transmitted to a central analysis station. The
standardized transmission protocol IEEEC 37.118 is used to do this. The PMU function adopts
phasor measurement model recommended in C37.118.1-2011 to achieve high measurement
accuracy.

The typical processing steps is:

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 5 Measurement

Low-pass filter Low-pass filter

Three-phase cos
Measured A
current
point

Three-phase
D
voltage sin

Synchronized Quadrature Single-phase

UTC signal
Clock Oscillator phasors

Figure 5.6-2 Single-phase section of PMU phasor signal processing model

This model is the same for both P class and M class algorithms. It assumes fixed frequency
sampling synchronized to an absolute time reference, followed by complex multiplication with the
nominal frequency carrier. The low-pass (LP) filtering can be applied individually to the real and
imaginary outputs of the complex demodulator.

The complete PMU signal processing model is as follows, in which all processing shown are at the
A/D sampling rate. The reporting rate is produced by resampling at the system output.

Va(t)
Single-phase
phasor section
5
Measuring point

Single-phase Single-phase phasors

Vb(t) (Ua, Ub, Uc, Ia, Ib, Ic)
phasor section

Single-phase
Vc(t)
phasor section

Phasor calculation
(positive-sequence/ Sequence component phasors
negative-sequence/ (I1, I2, I0)
zero-sequence)

Deviation of phase angle Frequency (f)

Rate-of-change of frequency
Time synchronization Deviation of frequency (df/dt)
Decimator

Figure 5.6-3 Complete PMU signal processing model

The normal positive sequence is calculated using the symmetrical component transformation. The
system frequency is calculated from the rate of change of phase angle, and the rate-of-change of
frequency (ROCOF) is then calculated.

The calculation equations for the total active and reactive power are as follows.

P = real(U̇a ∗ İa + U̇b ∗ İb + U̇c ∗ İc )

Q = imag(U̇a ∗ İa + U̇b ∗ İb + U̇c ∗ İc )

P is three-phase active power.

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 5 Measurement

Q is three-phase reactive power.

U̇a , U̇b , U̇c are three phase voltage phasors.
İa , İb , İc are three phase current phasors.

Multiply symbol * means the voltage phasor multiplies the conjugated current phasor.

5.6.2 Function Block Diagram

PMU

in_ua Ua

in_ub Ub

in_uc Uc

in_ia Ia

in_ib Ib

in_ic Ic

I1
5 I2

I0

df/dt

5.6.3 PMU Values

Access path: MainMenuMeasurementsPMU Values

5.6.3.1 PMU Phasor Values

The description names of the following quantities are their default value. These items are the
combination of two settings, which are determined by the setting [Name_PMUBay] in the submenu
PMUBay Settings and the settings in the submenu PMU Label Settings.

No. Item Definition Unit

1 STN-Bay01-UAV Amplitude of phase A voltage phasor kV

2 STN-Bay01-UBV Amplitude of phase B voltage phasor kV

3 STN-Bay01-UCV Amplitude of phase C voltage phasor kV

4 STN-Bay01-U1V Amplitude of positive sequence voltage phasor kV

5 STN-Bay01-U2V Amplitude of negative sequence voltage phasor kV

6 STN-Bay01-U0V Amplitude of zero sequence voltage phasor kV

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No. Item Definition Unit

7 STN-Bay01-IAV Amplitude of phase A current phasor A

8 STN-Bay01-IBV Amplitude of phase B current phasor A

9 STN-Bay01-ICV Amplitude of phase C current phasor A

10 STN-Bay01-I1V Amplitude of positive sequence current phasor A

11 STN-Bay01-I2V Amplitude of negative sequence current phasor A

12 STN-Bay01-I0V Amplitude of zero sequence current phasor A

13 STN-Bay01-UAP Angle of phase A voltage phasor °

14 STN-Bay01-UBP Angle of phase B voltage phasor °

15 STN-Bay01-UCP Angle of phase C voltage phasor °

16 STN-Bay01-U1P Angle of positive sequence voltage phasor °

17 STN-Bay01-U2P Angle of negative sequence voltage phasor °

18 STN-Bay01-U0P Angle of zero sequence voltage phasor °

19 STN-Bay01-IAP Angle of phase A current phasor °

20 STN-Bay01-IBP Angle of phase B current phasor °

21 STN-Bay01-ICP Angle of phase C current phasor °

5
22 STN-Bay01-I1P Angle of positive sequence current phasor °

23 STN-Bay01-I2P Angle of negative sequence current phasor °

24 STN-Bay01-I0P Angle of zero sequence current phasor °

5.6.3.2 PMU Analog Values

The description names of the following quantities are their default value. These items are the
combination of two settings, which are determined by the setting [Name_PMUBay] in the submenu
PMUBay Settings and the settings in the submenu PMU Label Settings.

No. Item Definition Unit

1 STN-Bay01-FRQ Frequency Hz

2 STN-Bay01-DFT Rate-of-change of frequency Hz/s

3 STN-Bay01-00P Active power MW

4 STN-Bay01-00Q Reactive power MVAr

5.6.3.3 PMU Digital Values

The description names of the following quantities are their default value. These items are
determined by the setting [Name_BI_**] in the submenu PMU BI Settings.

No. Item Definition Unit

1 STN-Digital01 Binary status 1

2 … …

3 STN-Digital32 Binary status 32

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5.6.3.4 PMU Miscellaneous Values

No. Item Definition Unit

1 STAT Bit mapped status, defined in IEEE C37.118 standard

2 f System frequency Hz

3 f_Diff System frequency deviation Hz

4 df/dt Rate-of-change of system frequency Hz/s

5.6.4 PMU Status

Access path: MainMenuStatusPMU Status

5.6.4.1 PMU Clock Synchronization Status

No. Item Definition Unit

1 Sig_TimeSyn_OK Flag of time synchronization

2 TQ_IRIG-B Time quality of IRIG-B signal

3 Sig_TimeKeep Flag of time keeping

5 4 Quality_TimeKeep Quality bit of time keeping

5 Flg_LeapSecond Flag of leap second

5.6.4.2 PDC** Communication Status

No. Item Definition Unit

1 PDC**.Name Name of PDC**

2 PDC**.Connected Connection status with PDC

3 PDC**.DataRate Transmission data rate fps

4 PDC**.N_Phasor Number of transmitted phasors

5 PDC**.N_Analog Number of transmitted analogue quantities

6 PDC**.N_BI Number of transmitted digital status

7 PDC**.DataRate_CFG2 Transmission data rate in CFG2 fps

8 PDC**.N_SendCFG1 Number of sending CFG1 commands

9 PDC**.N_SendCFG2 Number of sending CFG2 commands

10 PDC**.N_TurnOnData Number of turning on real-time data

5.6.4.3 PMU CFG1 Status

No. Item Definition Unit

1 N_Phasor_CFG1 Number of phasors in CFG1

2 N_Analog_CFG1 Number of analogue quantities in CFG1

3 N_BI_CFG1 Number of digital status in CFG1

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5.6.4.4 PMU Supervision Status

xx is determined by the setting [Name_PMUBay] in the submenu PMUBay

Settings.

No. Item Definition Unit

1 Alm_Phasor_Config Error of phasor configuration

2 Alm_Analog_Config Error of analogue input configuration

3 Alm_BI_Config Error of digital status configuration

4 PDC01.Alm_Invalid_IDCODE ID code of PDC01 is invalid

5 PDC02.Alm_Invalid_IDCODE ID code of PDC02 is invalid

6 PDC03.Alm_Invalid_IDCODE ID code of PDC03 is invalid

7 PDC04.Alm_Invalid_IDCODE ID code of PDC04 is invalid

8 Alm_TimeSyn Error of time synchronization 5

9 xx.Alm_VTS Error of VT circuit

10 xx.Alm_CTS Error of CT circuit

5.6.5 PMU Settings

Table 5.6-1 PMU global settings

Name Range Step Unit Default Description

Disabled Enabling/Disabling the synchrophasor
En_PMU Enabled
Enabled measurement function
The option of performance class, which
is used for the calculation of the
P_Class measured values.
Opt_Class_PMU M_Class
M_Class P class: faster response time
M class: higher measurement
precision
Data transmission rate
Data is transmitted continuously from
DataRate 10~120 1 fps 50
the PMU to the PDC at the configured
transmission rate.
Max. 16
Substation_PMU NR_Station1 Name of PMU substation
characters
To inform the update of CFG1 of CFG2
version, this number should be
N_Chgd_CFG 0~65535 1 1
increased if CFG1 or CFG2 has been
modified.

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 5 Measurement

Name Range Step Unit Default Description

PMU port when the communication
between the PMU and the PDC is
passed via TCP protocol. (i.e., the
Port_TCP 0~65535 1 4712 setting [PDC**.Opt_Protocol] is set as
"TCP" or "TCP-UDP")
The port setting must be configured on
the PDC correspondingly.
PMU port when the communication
between the PMU and the PDC is
passed via UDP protocol. (i.e., the
Port_UDP 1024~65535 1 4713 setting [PDC**.Opt_Protocol] is set as
"UDP" or "TCP-UDP")
The port setting must be configured on
the PDC correspondingly.

Table 5.6-2 PMU communication settings

Name Range Step Unit Default Description

5 PDC01.Name WAMS1
PDC01 name that the
device is connected to
Destination IP address
when the communication
between the PMU and
PDC01 is related with
PDC01.IP_TCP 0.0.0.0~255.255.255.255 198.120.0.20 TCP protocol.
When the setting
[PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
when the communication
between the PMU and
PDC01 is related with
UDP protocol.
PDC01.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when
the communication
PDC01.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1
between the PMU and
PDC01 is through UDP

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 5 Measurement

Name Range Step Unit Default Description

protocol and multicast
mode.
When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP",
and the setting
[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
PDC01 communication
protocol
None: communication
protocol is null, the
communication between
PMU and PDC is not
established. 5
TCP: TCP for the
transmission of
configuration frame,
command frame and
data frame.
Spontaneous-UDP:
Spontaneous-mode
None
UDP for the transmission
TCP
of configuration frame,
PDC01.Opt_Protocol Spontaneous-UDP None
and data frame. his
TCP-UDP
device sends data by
Commanded-UDP
UDP to a designated
destination without
stopping, whether a
receiving device is
present or not.
TCP-UDP: TCP for the
transmission of
configuration frame,
command frame, and
UDP for the transmission
of data frame.
Commanded-UDP:
Commanded-mode UDP
for the transmission of

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Name Range Step Unit Default Description

configuration frame,
command frame and
data frame. Commands
can be sent in UDP
frames. This device only
sends data when a client
requests it.
Unicast
Option of UDP broadcast
PDC01.Opt_UDP Broadcast Multicast
mode
Multicast
ID code of PDC01 that
PDC01.IDCODE 1~65534 1 the device is connected
to
PDC02 name that the
PDC02.Name WAMS2
device is connected to
Destination IP address
when the communication
5 between the PMU and
PDC02 is related with
PDC02.IP_TCP 0.0.0.0~255.255.255.255 198.121.0.20 TCP protocol.
When the setting
[PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
when the communication
between the PMU and
PDC02 is related with
UDP protocol.
PDC02.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when
the communication
between the PMU and
PDC02 is through UDP
PDC02.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1
protocol and multicast
mode.
When the setting
[PDC01.Opt_Protocol] is

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 5 Measurement

Name Range Step Unit Default Description

set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP",
and the setting
[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
PDC02 communication
protocol
None: communication
protocol is null, the
communication between
PMU and PDC is not
established.
TCP: TCP for the
transmission of
configuration frame,
command frame and 5
data frame.
Spontaneous-UDP:
Spontaneous-mode
UDP for the transmission
of configuration frame,
None
and data frame. his
TCP
device sends data by
PDC02.Opt_Protocol Spontaneous-UDP None
UDP to a designated
TCP-UDP
destination without
Commanded-UDP
stopping, whether a
receiving device is
present or not.
TCP-UDP: TCP for the
transmission of
configuration frame,
command frame, and
UDP for the transmission
of data frame.
Commanded-UDP:
Commanded-mode UDP
for the transmission of
configuration frame,
command frame and
data frame. Commands
can be sent in UDP

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Name Range Step Unit Default Description

frames. This device only
sends data when a client
requests it.
Unicast
Option of UDP broadcast
PDC02.Opt_UDP Broadcast Multicast
mode
Multicast
ID code of PDC02 that
PDC02.IDCODE 1~65534 2 the device is connected
to
PDC03 name that the
PDC03.Name WAMS3
device is connected to
Destination IP address
when the communication
between the PMU and
PDC03 is related with
PDC03.IP_TCP 0.0.0.0~255.255.255.255 198.122.0.20 TCP protocol.
When the setting
5 [PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
when the communication
between the PMU and
PDC03 is related with
UDP protocol.
PDC03.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when
the communication
between the PMU and
PDC03 is through UDP
protocol and multicast
mode.
PDC03.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1
When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP",
and the setting

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 5 Measurement

Name Range Step Unit Default Description

[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
PDC03 communication
protocol
None: communication
protocol is null, the
communication between
PMU and PDC is not
established.
TCP: TCP for the
transmission of
configuration frame,
command frame and
data frame.
Spontaneous-UDP:
Spontaneous-mode
UDP for the transmission 5
of configuration frame,
and data frame. his
None device sends data by
TCP UDP to a designated
PDC03.Opt_Protocol Spontaneous-UDP None destination without
TCP-UDP stopping, whether a
Commanded-UDP receiving device is
present or not.
TCP-UDP: TCP for the
transmission of
configuration frame,
command frame, and
UDP for the transmission
of data frame.
Commanded-UDP:
Commanded-mode UDP
for the transmission of
configuration frame,
command frame and
data frame. Commands
can be sent in UDP
frames. This device only
sends data when a client
requests it.
PDC03.Opt_UDP Unicast Multicast Option of UDP broadcast

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Name Range Step Unit Default Description

Broadcast mode
Multicast
ID code of PDC03 that
PDC03.IDCODE 1~65534 3 the device is connected
to
PDC04 name that the
PDC04.Name WAMS4
device is connected to
Destination IP address
when the communication
between the PMU and
PDC04 is related with
PDC04.IP_TCP 0.0.0.0~255.255.255.255 198.120.0.100 TCP protocol.
When the setting
[PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
5 when the communication
between the PMU and
PDC01 is related with
UDP protocol.
PDC04.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC04.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when
the communication
between the PMU and
PDC04 is through UDP
protocol and multicast
mode.
When the setting
PDC04.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1 [PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP",
and the setting
[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
PDC04.Opt_Protocol None None PDC04 communication

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Name Range Step Unit Default Description

TCP protocol
Spontaneous-UDP None: communication
TCP-UDP protocol is null, the
Commanded-UDP communication between
PMU and PDC is not
established.
TCP: TCP for the
transmission of
configuration frame,
command frame and
data frame.
Spontaneous-UDP:
Spontaneous-mode
UDP for the transmission
of configuration frame,
and data frame. his
device sends data by
UDP to a designated 5
destination without
stopping, whether a
receiving device is
present or not.
TCP-UDP: TCP for the
transmission of
configuration frame,
command frame, and
UDP for the transmission
of data frame.
Commanded-UDP:
Commanded-mode UDP
for the transmission of
configuration frame,
command frame and
data frame. Commands
can be sent in UDP
frames. This device only
sends data when a client
requests it.
Unicast
Option of UDP broadcast
PDC04.Opt_UDP Broadcast Multicast
mode
Multicast
ID code of PDC04 that
PDC04.IDCODE 1~65534 4
the device is connected

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 5 Measurement

Name Range Step Unit Default Description

to

xx is determined by the setting [Name_PMUBay] in the submenu PMUBay

Settings.

Table 5.6-3 PMU bay settings

Name Range Step Unit Default Description

STN- Configurable the name of PMU
Name_PMUBay Max. 12 characters
Bay01 bay
VT primary rated voltage for
xx.U1n 0.001~1000.000 0.001 kV 220.000
PMU bay
CT primary rated current for
xx.I1n 0.1~20000.0 0.1 A 1000.0
PMU bay
None
Bay
5 xx.Opt_UnitType
Bus(U_3P)
1 Bay Bay application scenario

Bus(U_1P)
U1
Ua Option of base voltage for
xx.Opt_U_MeasFreq 1 U1
Ub frequency measurement
Uc
Enabling/Disabling disturbance
Disabled
xx.En_TrigDFR Enabled fault recording function in case
Enabled
any following over limit situation
xx.Up_UpLmt 0.010~2.000 0.001 Un 1.200 Upper limit of phase voltage
Upper limit of positive
xx.U1_UpLmt 0.010~2.000 0.001 Un 1.200
sequence voltage
Upper limit of negative
xx.U2_UpLmt 0.010~2.000 0.001 Un 0.200
sequence voltage
Upper limit of zero sequence
xx.U0_UpLmt 0.010~2.000 0.001 Un 0.200
voltage
xx.Up_LowLmt 0.010~2.000 0.001 Un 0.900 Lower limit of phase voltage
Lower limit of positive
xx.U1_LowLmt 0.010~2.000 0.001 Un 0.900
sequence voltage
xx.Ip_UpLmt 0.010~2.000 0.001 In 1.200 Upper limit of phase current
Upper limit of positive
xx.I1_UpLmt 0.010~2.000 0.001 In 1.200
sequence current
Upper limit of negative
xx.I2_UpLmt 0.010~2.000 0.001 In 0.200
sequence current
Upper limit of zero sequence
xx.I0_UpLmt 0.010~2.000 0.001 In 0.200
current

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Name Range Step Unit Default Description

xx.f_Diff_Lmt 0.01~10.00 0.01 Hz 0.50 Limit of frequency deviation
Limit of rate-of-change of
xx.df/dt_Lmt 0.01~50.00 0.01 Hz/s 1.00
frequency

Table 5.6-4 PMU BI settings

Name Range Step Unit Default Description

STN- Configurable the name of PMU binary
Name_BI_** Max. 16 characters
Digital** signal
Enabling/Disabling disturbance fault
Disabled
Link_BI_TrigDFR Enabled recording function in case state
Enabled
change of any PMU binary signal
Enabling/Disabling disturbance fault
Disabled recording function in case state
BI_**.En_TrigDFR Enabled
Enabled change of the PMU binary signal
BI_**

Table 5.6-5 PMU label settings

Name Range Step Unit Default Description 5

Max. 4
Name_Amp_Ua -UAV Label for amplitude of phase A voltage phasor
characters
Max. 4
Name_Amp_Ub -UBV Label for amplitude of phase B voltage phasor
characters
Max. 4
Name_Amp_Uc -UCV Label for amplitude of phase C voltage phasor
characters
Max. 4 Label for amplitude of zero sequence voltage
Name_Amp_U0 -U0V
characters phasor
Max. 4 Label for amplitude of positive sequence voltage
Name_Amp_U1 -U1V
characters phasor
Max. 4 Label for amplitude of negative sequence voltage
Name_Amp_U2 -U2V
characters phasor
Max. 4
Name_Amp_Ia -IAV Label for amplitude of phase A current phasor
characters
Max. 4
Name_Amp_Ib -IBV Label for amplitude of phase B current phasor
characters
Max. 4
Name_Amp_Ic -ICV Label for amplitude of phase C current phasor
characters
Max. 4 Label for amplitude of zero sequence current
Name_Amp_I0 -I0V
characters phasor
Max. 4 Label for amplitude of positive sequence current
Name_Amp_I1 -I1V
characters phasor
Max. 4 Label for amplitude of negative sequence current
Name_Amp_I2 -I2V
characters phasor

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Name Range Step Unit Default Description

Max. 4
Name_Ang_Ua -UAP Label for angle of phase A voltage phasor
characters
Max. 4
Name_Ang_Ub -UBP Label for angle of phase B voltage phasor
characters
Max. 4
Name_Ang_Uc -UCP Label for angle of phase C voltage phasor
characters
Max. 4
Name_Ang_U0 -U0P Label for angle of zero sequence voltage phasor
characters
Max. 4 Label for angle of positive sequence voltage
Name_Ang_U1 -U1P
characters phasor
Max. 4 Label for angle of negative sequence voltage
Name_Ang_U2 -U2P
characters phasor
Max. 4
Name_Ang_Ia -IAP Label for angle of phase A current phasor
characters
Max. 4
Name_Ang_Ib -IBP Label for angle of phase B current phasor
characters
Max. 4
5 Name_Ang_Ic
characters
-ICP Label for angle of phase C current phasor

Max. 4
Name_Ang_I0 -I0P Label for angle of zero sequence current phasor
characters
Max. 4 Label for angle of positive sequence current
Name_Ang_I1 -I1P
characters phasor
Max. 4 Label for angle of negative sequence current
Name_Ang_I2 -I2P
characters phasor
Max. 4
Name_f -FRQ Label for bay frequency
characters
Max. 4
Name_df/dt -DFT Label for bay rate-of-change of frequency
characters
Max. 4
Name_P -00P Label for bay active power
characters
Max. 4
Name_Q -00Q Label for bay reactive power
characters

5.7 AC Analog Input Calibration

The calculated power values can get class 0.5 measuring precision by calibrating AC analog inputs
of current and voltage.

5.7.1 Function Description

This function is achieved by injecting the rated voltage and rated current with an angle of 45 degree
(voltage leading current) into the device with the help of a high-precision tester. When input the
rated analog values, use the device menu Main Menu→Debugging→Precision Calibration to

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adjust the corresponding calibration coefficients and make the device displayed quantities precision
to be more accurate. After the manual calibration procedure, the modified coefficients will be
automatically filled in as the following calibration settings values.

Modify the settings values ONLY when it is necessary.

The AC analog inputs have been calibrated at the factory. Besides, this
device supports automatic AC analog inputs calibration when replacing
CPU and ACAI module.

5.7.2 Settings
Table 5.7-1 AC calibration settings

Setting Range Step Unit Default Remark

Phase-A current input calibration coefficients
Prot.CBx.K_Calbr_Ia 9000~11000 1 10000
for circuit breaker No.x
Phase-B current input calibration coefficients
Prot.CBx.K_Calbr_Ib 9000~11000 1 10000
for circuit breaker No.x 5
Phase-C current input calibration coefficients
Prot.CBx.K_Calbr_Ic 9000~11000 1 10000
for circuit breaker No.x
Prot.K_Calbr_Ua 9000~11000 1 10000 Phase-A voltage input calibration coefficients
Prot.K_Calbr_Ub 9000~11000 1 10000 Phase-B voltage input calibration coefficients
Prot.K_Calbr_Uc 9000~11000 1 10000 Phase-C voltage input calibration coefficients
Prot.K_Calbr_Uab 9000~11000 1 10000 Phase-AB voltage input calibration coefficients
Phase-BC voltage input calibration
Prot.K_Calbr_Ubc 9000~11000 1 10000
coefficients
Prot.K_Calbr_Uca 9000~11000 1 10000 Phase-CA voltage input calibration coefficients
Phase-A active power calibration coefficients
Prot.CBx.K_Calbr_Pa -900~11000 1 10000
for circuit breaker No.x
Phase-B active power calibration coefficients
Prot.CBx.K_Calbr_Pb -900~11000 1 10000
for circuit breaker No.x
Phase-C active power calibration coefficients
Prot.CBx.K_Calbr_Pc -900~11000 1 10000
for circuit breaker No.x
Phase-A reactive power calibration
Prot.CBx.K_Calbr_Qa -900~11000 1 0
coefficients for circuit breaker No.x
Phase-B reactive power calibration
Prot.CBx.K_Calbr_Qb -900~11000 1 0
coefficients for circuit breaker No.x
Phase-C reactive power calibration
Prot.CBx.K_Calbr_Qc -900~11000 1 0
coefficients for circuit breaker No.x
Single voltage input calibration coefficient for
UB1.K_Calbr_U 9000~11000 1 10000
synchronization check, double bus, etc.

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 6 Supervision

6 Supervision

Table of Contents

6.1 Overview........................................................................................................... 6-1

6.2 Device Hardware Supervision ........................................................................ 6-1
6.2.1 Hardware Resource Consumption Supervision ................................................................... 6-2

6.2.2 Hardware Status Supervision............................................................................................... 6-2

6.2.3 Hardware Configuration Supervision ................................................................................... 6-3

6.2.4 Device Firmware Supervision .............................................................................................. 6-3

6.2.5 CPU Process and Module Supervision ................................................................................ 6-3

6.3 Analogue Input Supervision ........................................................................... 6-4

6.4 Secondary Circuit Supervision ...................................................................... 6-4
6.4.1 CT Circuit Supervision (CTS) ............................................................................................... 6-4

6.4.2 VT Circuit Supervision (VTS) ............................................................................................... 6-4

6.5 Binary Input Supervision ................................................................................ 6-4

6
6.5.1 Debounce Time .................................................................................................................... 6-4

6.5.2 Jitter Processing ................................................................................................................... 6-7

6.5.3 High-Power Conducting Mode ............................................................................................. 6-8

6.6 Circuit Breaker Supervision (SCBR) .............................................................. 6-9

6.6.1 Function Description........................................................................................................... 6-10

6.6.2 Breaker Contact Travel Time.............................................................................................. 6-10

6.6.3 Interrupted Current ............................................................................................................. 6-11

6.6.4 Breaker Remaining Life ...................................................................................................... 6-11

6.6.5 Trip Counter ........................................................................................................................ 6-13

6.6.6 Accumulated Abrasion Calculation ..................................................................................... 6-13

6.6.7 Function Block Diagram ..................................................................................................... 6-14

6.6.8 I/O Signals .......................................................................................................................... 6-14

6.6.9 Logic ................................................................................................................................... 6-16

6.6.10 Settings............................................................................................................................. 6-17

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6.7 Supervision Alarms and Handling Suggestion ........................................... 6-19

List of Figures

Figure 6.5-1 Sequence chart of debounce technique ............................................................. 6-5

Figure 6.5-2 Debounce time configuration page ..................................................................... 6-5

Figure 6.5-3 Sequence chart of jitter processing .................................................................... 6-8

Figure 6.5-4 High-power conducting mode .............................................................................. 6-9

Figure 6.6-1 Sequence chart of breaker contact travel time ................................................ 6-10

Figure 6.6-2 Relation example between CB interrupted current and operation times ...... 6-12

Figure 6.6-3 Logic diagram of breaker contact travel time overtime alarm ........................ 6-16

Figure 6.6-4 Logic diagram of breaker remaining life alarm ................................................ 6-16

Figure 6.6-5 Logic diagram of breaker trip counting result out-of-limit alarm ................... 6-16

Figure 6.6-6 Logic diagram of breaker accumulated abrasion out-of-limit alarm.............. 6-17

List of Tables

6 Table 6.6-1 Input signals of circuit breaker supervision ....................................................... 6-14

Table 6.6-2 Output signals of circuit breaker supervision .................................................... 6-15

Table 6.6-3 Circuit breaker supervison settings .................................................................... 6-17

Table 6.7-1 Alarm description .................................................................................................... 6-19

Table 6.7-2 Troubleshooting....................................................................................................... 6-27

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6.1 Overview

Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED “HEALTHY” is on, the device needs to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.

The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.

In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.

When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed if required.

6.2 Device Hardware Supervision

All hardware has real-time monitoring functions, such as CPU module monitoring, communication
interface status monitoring, power supply status monitoring. 6
The monitoring function of CPU module also includes processor self-check, memory self-check
and so on. The processor self-check is checked by designing execution instructions and data
operations. Check whether the processor can execute all instructions correctly, and whether it can
correctly calculate complex data operations to determine whether it works normally. For peripherals,
it can monitor the status of the interface module, check the input and output data, send the
communication interface and receive self-loop detection. Memory self-check is used to detect
unexpected memory errors in the running process. It can effectively prevent program logic
abnormality caused by memory errors.

The status monitoring of communication interface also includes Ethernet communication interface
monitoring and differential channel communication interface monitoring. By accessing the status
register of the communication interface, the state of the corresponding interface is obtained, such
as the state of connection, the number of sending frames, the number of frames received, and the
number of wrong frames. According to the statistics of the acquired interface state, it is detected
whether the interface work is abnormal.

The hardware supervision also includes the power supply status monitoring. The voltage monitoring
chip is used by all the power supplies. The reset voltage threshold is pre-set to the reset monitoring
circuit. When the power supply is abnormal, the voltage monitoring chip will output the reset signal
to control CPU to be in the reset state and avoid the wrong operation.

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6.2.1 Hardware Resource Consumption Supervision

1. Logic component total execution time monitoring

In the process of operation, the safety allowance should always be kept and no overload
phenomenon is allowed. When the user configures logic components with PCS-Studio, the PCS-
Studio automatically calculates the time required for the theoretical execution of the configured
components. When the security limit is exceeded, the PCS-Studio will indicate that the
configuration error is not allowed to download the current configuration to the device.

2. Module data exchange monitoring

During the operation of the device, there is a lot of data exchange between modules. The number
of data exchanges is related to the number of logical components configured by the user. When
the configuration is too large to cause the number of data exchange to exceed the upper limit
supported by the device, the PCS-Studio prompts the configuration error.

3. Configuration file size monitoring

The initialization of the device depends on the configuration files of each module. The user
configured logical components will eventually be embodied in the configuration file, limited to the
hardware memory space. When the configuration file size is more than the upper limit, the PCS-
Studio prompts the configuration error.

6.2.2 Hardware Status Supervision

6 1. Memory ECC and parity functions.

The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate
unexpected changes in memory caused by electromagnetic interference. The chip memory has
parity function. When an error occurs, the system can detect anomalies immediately, and eliminate
the logic abnormity caused by memory errors.

2. Memory error monitoring in code area and constant data area

In addition to the above hardware memory reliability measures, the device software is also
constantly checking the memory during operation, including code, constant data, and so on. Once
the error detection, the system will automatically restart the restore operation. If they detect the
error immediately after the restart, it may be the result of a permanent fault locking device hardware,
only at the moment and not restart.

3. Binary output relay drive monitoring

The reliability of the device is largely determined by the reliability of the export drive. By reading
the driving state of the binary output relay, the alarm signal will be generated and the device is
immediately blocked to prevent the relay from maloperation when the device is not given a tripping
order and the binary output relay driver is detected in the effective state.

4. CPU temperature monitoring

The CPU chip needs to be able to ensure long-term stability under the permissible working
temperature of the specification. Therefore, it is necessary to monitor the working temperature

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monitored by CPU.

5. SFP light intensity monitoring

The SFP optical module is used for data communication by optical fiber. The module has the
function of sending and receiving light intensity. When the transmitted or received light exceeds the
normal threshold, the alarm signal is sent to the user to check the optical fiber loop and the SFP
module hardware after the delay is confirmed.

6.2.3 Hardware Configuration Supervision

The device is blocked when the actual hardware configuration is not consistent with the hardware
configuration file. Compared with pre-configured modules, this device will be blocked if more
module is inserted, fewer module is inserted, and wrong modules is inserted.

6.2.4 Device Firmware Supervision

1. Each hardware module configuration check code needs to be consistent with CPU module.

The device CPU module stores the configuration check codes of other modules. In initialization
procedure, it checks whether the configuration check code of each module is consistent with the
stored code in CPU module, and if it is not consistent, this device is blocked.

2. The hardware modules and process interface versions need to be consistent with the CPU
module.

If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this 6
moment, each hardware module and process will be upgraded synchronously, otherwise the
version of the interface will be inconsistent.

3. Configuration text is correct.

The configuration text formed by the device calibration visualization project includes checking
whether the check code is wrong or not.

4. Whether any setting is over the range, whether it needs to confirm the settings.

If the setting exceeds the configuration range, the device is blocked; if some settings are added, it
is necessary to confirm the new values through the LCD.

6.2.5 CPU Process and Module Supervision

1. Monitor the heartbeat of the module.

In the operation procedure, the CPU module sends a time synchronization command to other
module, each module repeats heartbeat message to the CPU module, if it does not respond or the
heartbeat is abnormal, then this device is blocked.

2. Check whether the settings of other modules are consistent with the CPU module.

The actual values of all the settings in the CPU module are initialized to send to the corresponding
slave modules. In the process of operation, the setting values stored in the CPU module and the
setting values of other modules will be checked one by one. If they are not consistent, this device

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will issue the alarm signal "Fail_Settings".

6.3 Analogue Input Supervision

The sampling circuit of this device is designed as dual-design scheme. Each analogue sampling
channel is sampled by two groups of ADC. The sampling data is self checking and inter checking
in real time. If any sampling circuit is abnormal, the device reports the alarm signal "Alm_Sample",
and the protection function related to the sampling channel is disabled at the same time. When the
sampling circuit returns to normal state, the related protection is not blocked after 10s.

6.4 Secondary Circuit Supervision

The secondary circuit supervision function includes current transformer supervision (CTS), voltage
transformer supervision (VTS), power supply supervision of binary inputs and tripping/closing
circuit supervision.

6.4.1 CT Circuit Supervision (CTS)

The purpose of the CTS is to detect whether the current transformer circuit is failed. In some cases,
if the CT is failed (broken-conductor, short-circuit), related protective element should be blocked for
preventing this device from mal-operation.

6 See further details about the CTS, please refer Section 3.40.

6.4.2 VT Circuit Supervision (VTS)

The purpose of the VTS is to detect whether the VT analogue input is normal. Because some
function, such as synchronism check, will be influenced by a voltage input failure.

The VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect the failure, and then
issue an alarm signal and block relevant function.

See further details about the VTS, please refer Section 3.39.

6.5 Binary Input Supervision

6.5.1 Debounce Time

The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.5-1.

All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the binary
input will be validated and wrote into SOE.

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Binary input
state

SOE report SOE report

timestamps timestamps
Validated binary input Validated binary input
state changes state changes
1

Debounce time of Debounce time of

delayed pickup delayed dropout
Time

Figure 6.5-1 Sequence chart of debounce technique

In order to meet flexible configurable requirement for different project field, all binary inputs provided
by the device are configurable. Through the configuration tool, this device provides two parameters
to setup debounce time of delayed pickup and dropout based on specific binary signal.

Figure 6.5-2 Debounce time configuration page

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The configurable binary signals can be classified as follows:

1. Type 1

This type of binary inputs includes enable/disable of protection functions, AR mode selection,
"BI_RstTarg", "BI_Maintenance", disconnector position, settings group switch, open and close
command of circuit breaker and disconnector, enable/disable of auxiliary functions (for
example, manually trigger recording). They are on the premise of reliability, and the debounce
time of delayed pickup and delayed dropout is recommended to set as 100ms at least.

2. Type 2

This type of binary inputs includes initiating breaker failure protection (CBx.50BF.ExTrpA,
CBx.50BF.ExTrpB, CBx.50BF.ExTrpC, CBx.50BF.ExTrp3P, CBx.50BF.ExTrp_WOI), line
disconnector position (87STB.89b_DS, 87STB.89b_DS_Rmt), initiating dead zone protection
(CBx.50DZ.Init), initiating transfer trip (TT.Init_3P, TT.Init_A, TT.Init_B, TT.Init_C), and so on.

Debounce time

BI Input Signal t1 t2 &

Time delay Output
SIG Operation condition

⚫ Time delay is equal to 0

6 The debounce time of delayed pickup and delayed dropout is recommended to set as
15ms, in order to prevent binary signals from maloperation due to mixed connection of AC
system and DC system.

⚫ Time delay is not equal to 0

The debounce time of delayed pickup and delayed dropout is recommended to set as (-
t1+ t2+Time delay)≥15ms, in order to prevent binary signals from maloperation due to
mixed connection of AC system and DC system. Where, "t1" is the debounce time of
delayed pickup, and “t2” is the debounce time of delayed dropout.

3. Type 3

This type of binary inputs is usually used as auxiliary input condition, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 5ms.

When users have their own reasonable setting principles, they can set the
debounce time related settings according to their own setting principles.

When the setting [En_BICheckInstP] is set as "Enabled", and the

debouncing time should be larger than the during time (10ms) of the
instantaneous active power.

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6.5.2 Jitter Processing

This device can handle repetitive signal or so-called jitter via binary input module with the following
settings:

Symbol Related Setttings Description

T [Mon_Window_Jitter] monitoring window of binary input jitter processing
N [Num_Blk_Jitter] times threshold to block binary input status change due to jitter
T' [Blk_Window_Jitter] blocking window of binary input status change due to jitter
times threshold to initiate immediately another blocking window of binary
N' [Num_Reblk_Jitter]
input status change due to continuous jitter

For a binary input voltage variation, if the jitter processing function is enabled, its handling principle
is:

1. During the T,

⚫ If the actual jitter times < N, the block will not be initiated and the status change of this
binary input will be considered.

⚫ If the actual jitter times ≥ N, the T' is initiated, and the status change of binary input will be
ignored during the T'.

2. During the T',

⚫ If the actual jitter times < N', the block window will expire. The final status of this binary
input will be compared to the original one before T', so as to determine whether there is a 6
change or not.

⚫ If the actual jitter times ≥ N', the T' will be initiated again immediately (i.e. restart the timer),
and the status change of binary input will be ignored during the next T'.

An example of jitter processing is shown in Figure 6.5-3:

Signal1 (red) Voltage variation of binary input

Signal2 (green) Blocking signal of binary input status change due to jitter
Signal3 (blue) Binary input status after debounce and jitter processing
n Actual jitter times

Taking N = 7 and N' = 5 in this example.

1. T = t2 - t1

⚫ n=6<N

⚫ No blocking, Signal2 stays at 0 and Signal3 is tracing the voltage variation to create SOE.

2. T = t4 - t3, at t5'

⚫ n=7=N

⚫ The processing initiates the blocking immediately due to jitter

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⚫ Jitter blocking, no more SOE, Signal2 changes its status to 1 and Signal3 stops the
tracing.

3. T' = t6' - t5'

⚫ At t7', n = 5 =N', the processing prolongs the blocking immediately due to jitter

⚫ Jitter blocking continues, no SOE, Signal2 stays at 1 and Signal3 keeps its status.

4. T'= t8' - t7'

⚫ At t9', n = 5 =N', the processing prolongs the blocking immediately due to jitter.

⚫ Jitter blocking continues, no SOE, Signal2 stays at 1 and Signal3 keeps its status.

5. T'= t10' - t9'

⚫ n = 2 < N'

⚫ At t10', jitter unblocking, Signal2 changes its status to 0, the blocking window expires and
Signal3 restart to trace the voltage varation immediately. At this point, no debounce time
takes effect and SOE can be created since then.

Signal1

debounce time
(falling edge)

6
initiate jitter block (n = N) Signal2
debounce time
(rising edge)
1 2 3 4 5 6
Signal3

n=6<N=7
prolong blocking window (n = N' ) T'

T'

T'

t'
t5' t7' t6' t9' t8' t10'

Signal1:input voltage level

T T
Signal2: jitter blocking flag
t Signal3: signal after debounce & jitter processing
t1 t2 t3 t4

Figure 6.5-3 Sequence chart of jitter processing

6.5.3 High-Power Conducting Mode

In order to realize protection functions of primary equipment body or thermal overlaod protection,
signals may be transmitted to the binary input terminal of the device through a long cable, which
directly triggers the protection operating without any auxiliuary criterion.

Because of the long cable and the large coupling capacitance, it is easy to be interfered by external

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signals, to cause undesired operation. The device provides two kinds of BI modules, NR6604 and
NR6611, which support the high-power conducting mode of binary inputs through the setting
[En_BICheckInstP] to fulfill mechanical binary input.

⚫ When voltage is greater than 95% of the settable ON value of binary input, the high-power
conducting mode is triggered. Under the compensation of a relatively large current, the
instantaneous active power immediately rises to the threshold.

⚫ This pulsed current will remain constant for the next 10ms. During which time, as the voltage
rises, the power will also rise.

⚫ If the voltage drops below 95% of the settable ON value of binary input, the device turns off
the high-power conducting mode.

⚫ However, if the voltage rises and exceeds the 95% threshold again, the high-power conducting
mode will restart.

Therefore, it is possible to avoid interference signal in small voltage fluctuations so as to ensure

correct state change of binary input. The logical process is shown in Figure 6.5-4.

20ms 20ms

UPickup
0.95UPickup
Interference Signal Valid Signal UDropout
U (In)

6
Pulsed constant current Pulsed constant current
I (Load)

BI (Out)
BI debounce time BI debounce time
(rising edge, >10ms) (falling edge, >10ms)

Time

Figure 6.5-4 High-power conducting mode

Only the binary inputs whose rated voltage is 110Vdc, 125Vdc, 220Vdc or
250Vdc (@50Hz), is capable to apply the high-power conducting mode.

6.6 Circuit Breaker Supervision (SCBR)

This function is used to monitor circuit breaker states and parameters, and to calculate the breaker

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abrasion and estimate its remaining life. The breaker requires maintenance or even replacement
when the monitored parameters reach their limit threshold.

6.6.1 Function Description

To ensure a propre operation of the circuit breaker, it is essential to monitor the circuit breaker key
parameters, including contact travel time, interrupted current, trip counter, remaining life,
accumulated abrasion, etc. This monitoring function is disabled by default and could be enabled
via the path: Device Setup→Global Config→Function Group through the PCS-Studio
configuration tool. It is independent for up to 3 breakers in certain applications scenarios, such as
transformer sides, and is suitable for both phase-segregated and three-phase circuit breakers.

6.6.2 Breaker Contact Travel Time

As the wear on the circuit breaker mainly depends on the current amplitude and duration of the
actual switching action, determination of the start and end criteria is important. The following
describes the timing method to a switching operation.

The breaker contact travel time is the period between the state change of auxiliary contacts. The
time difference between auxiliary contact operation and the actual physical opening of the breaker
mechanism contact should be considered. The following figure shows the time difference of
auxiliary contacts in opening and closing procedures.

Auxiliary Contact 1

6
(NO)

Auxiliary Contact
0
(NC)

IED BI_52a 1

IED BI_52b 0

t1 topen t2 t3 tclose t4

t1 + t 2 = t_Opn_Comp t3 + t 4 = t_Cls_Comp
t_Opn_Comp + t open = t OpenTravelTime t_Cls_Comp + t close = t CloseTravelTime

Figure 6.6-1 Sequence chart of breaker contact travel time

The settings [CBx.SCBR.t_Opn_Comp] and [CBx.SCBR.t_Cls_Comp] are provided to compensate

the state change time of the normally closed contact (NC) and normally open contact (NO) for the
circuit breaker position indication by double points. Thus, the breaker contact travel time can be
derived by adding the measured DPS state change time and the compensation factor.

The calculated contact travel time is stored in non-volatile memory. Even if the device is powered

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off after a CB switching operation, the contact travel time is memorized. User may configure the
two input terminals "in_t_Opn_rst" and "in_t_Cls_rst" to reset the contact travel time to zero.
Besides, 2 stages of overtime alarm are provided for both CB opening and closing operations
contact travel time. When the contact travel time is longer than the alarm or the warning setting,
the corresponding alarm signal shall be issued.

6.6.3 Interrupted Current

The remaining life estimation and accumulated abrasion calculation of a circuit breaker are based
on the sampled value of phase current during the breaking time, which is called as interrupted
current.

From the moment that CB opening command is received to the moment that DPS has changed
into DPS_OFF, the device continuously samples the phase-segregated current flowing through the
CB to calculate the tripping current during the opening procedure. The maximum value of the three-
phase tripping current is taken as the interrupted current and will be further used for CB remaining
life estimation and accumulated abrasion calculation.

The sampled interrupted current is stored in non-volatile memory. Even if the device is powered off
after a CB opening operation, the current value is memorized. User may configure the input terminal
"in_I_Interrupted_rst" to reset the current value to zero.

6.6.4 Breaker Remaining Life

The remaining life indicates the circuit breaker wear and tear condition. Each time the breaker
operates, its service life reduces due to abrasion.
6
The CB remaining life estimation depends on the maintenance curve, which is illustrated on the
double-logarithmic diagram provided by the apparatus manufacturer. The remaining life decreases
once the circuit breaker is opened. As shown in the following example, for different interrupted
current values which are higher or lower than the rated tripping current, the CB remaining life
decreases correspondingly along the curve.

The following example figure shows that there are 10000 possible operations at 2.5kA (rated
tripping current), 800 operations at 10kA or 60 operations at 50kA (rated fault current). Therefore,
if the interrupted current is 10kA, one operation is equivalent to 10000/800=12 operations at the
rated current. It is assumed that prior to tripping, the initial remaining life of a breaker is 10000
operations.

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100000

P1

10000
Number of CB operations

1000

100

P2
6
10
0.1 1 10 100
Interrupted Current (kA)

Figure 6.6-2 Relation example between CB interrupted current and operation times

The remaining life estimation for three different interrupted current conditions are:

⚫ The interrupted current (2kA) is not higher than the rated tripping current (2.5kA, P1)

The CB remaining life decreases by 1 operation to be 9999 operations at the rated tripping
current.

⚫ The interrupted current (10kA) is larger than the rated tripping current (2.5kA, P1) but smaller
than the rated fault current (50kA, P2)

One operation at 10kA is equivalent to 10000/800=12 operations at the rated tripping current.
The CB remaining life would be (10000-12)=9988 operations after one operation at 10kA.

⚫ The interrupted current (50kA) is not smaller than the rated fault current (50kA)

One operation at 50kA is equivalent to 10000/60=166 operations at the rated tripping current.
The CB remaining life would be (10000-166)=9834 operations after one operation at 50kA.

Users can set the rated current and fault current with the corresponding operations times of the

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circuit breaker, and by using the multi-segment polyline approximation method, set the interrupted
current and operation times relation in this interval according to the CB maintenance curve. Up to
16 groups of interrupted current-operation times can be set.

The breaker remaining life is stored in non-volatile memory. Even if the device is powered off after
a CB opening operation, the left operation time is memorized. User may configure the input terminal
"in_RemainLife_rst" to reset the remaining life to its initial value which is defined by the setting
[CBx.SCBR.RemainLife_Init]. Besides, when the CB remaining life drops below the limit setting
[CBx.SCBR.Th_Alm_RemainLife], the alarm signal "CBx.SCBR.Alm_RemainLife" shall be issued.

6.6.5 Trip Counter

This counter counts the number of open operations based on DPS of the circuit breaker auxiliary
contacts.

When the circuit breaker is in the closed position and the opening command is received, the trip
counter is initiated. Once the DPS changes from DPS_ON to DPS_OFF, the trip counting result
increases. For a phase-segregated circuit breaker, if the position of any phase changes from close
to open, the trip counting result shall increase.

The trip counting result is stored in non-volatile memory. Even if the device is powered off after a
CB opening operation, the trip times is memorized. User may configure the input terminal
"in_N_Opn_rst" to reset the trip counter to its initial value which is defined by the setting
[CBx.SCBR.N_Opn_Init]. Besides, 2 stages of operation times alarm are provided. When the trip
counting result exceeds the limit alarm or warning setting, the corresponding alarm signal shall be 6
issued.

6.6.6 Accumulated Abrasion Calculation

The accumulated energy is calculated by exponent value of the interrupted current during breaker
contact opening travel time, which has been detailed in Section 6.6.2 Breaker Contact Travel Time.
The exponent factor could be set by the setting [CBx.SCBR.CurrExponent] and the initial abrasion
may be above zero by the setting [CBx.SCBR.Abr_Init].

The accumulated abrasion is stored in non-volatile memory. Even if the device is powered off after
a CB opening operation, the accumulated abrasion is memorized. User may configure the input
terminal "in_Abr_rst" to reset the abrasion to its initial value which is defined by the setting
[CBx.SCBR.Abr_Init]. Besides, 2 stages of accumulated abrasion alarm are provided. The abrasion
will stop to accumulate if the device is in maintenance state. When the accumulated abrasion
exceeds the limit alarm or warning setting, the corresponding alarm signal shall be issued.

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6.6.7 Function Block Diagram

SCBR

in_Ia

in_Ib

in_Ic

in_I_Interrupted_rst

in_N_Opn_rst

in_t_Opn_rst

in_t_Cls_rst

in_RemainLife_rst

in_AccuAbrasion_rst

in_open

in_close

in_opn_pos

in_cls_pos

6 in_opn_pos_a

in_opn_pos_b

in_opn_pos_c

in_cls_pos_a

in_cls_pos_b

in_cls_pos_c

6.6.8 I/O Signals

Table 6.6-1 Input signals of circuit breaker supervision

No. Input Signal Description

1 CBx.SCBR.in_Ia Input of phase-A current channel
2 CBx.SCBR.in_Ib Input of phase-B current channel
3 CBx.SCBR.in_Ic Input of phase-C current channel
4 CBx.SCBR.in_I_Interrupted_rst Input signal to reset interrupted current
5 CBx.SCBR.in_N_Opn_rst Input signal to reset trip counter
6 CBx.SCBR.in_t_Opn_rst Input signal to reset contact travel time during CB opening operation
7 CBx.SCBR.in_t_Cls_rst Input signal to reset contact travel time during CB closing operation
8 CBx.SCBR.in_RemainLife_rst Input signal to reset CB's remaining life
9 CBx.SCBR.in_AccuAbrasion_rst Input signal to reset CB's accumulated abrasion

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 6 Supervision

10 CBx.SCBR.in_open Input signal of CB's open command

11 CBx.SCBR.in_close Input signal of CB's close command
12 CBx.SCBR.in_opn_pos Input signal of CB's normally open auxiliary contact (three-phase)
13 CBx.SCBR.in_cls_pos Input signal of CB's normally closed auxiliary contact (three-phase)
14 CBx.SCBR.in_opn_pos_a Input signal of CB's normally open auxiliary contact (phase-A)
15 CBx.SCBR.in_opn_pos_b Input signal of CB's normally open auxiliary contact (phase-B)
16 CBx.SCBR.in_opn_pos_c Input signal of CB's normally open auxiliary contact (phase-C)
17 CBx.SCBR.in_cls_pos_a Input signal of CB's normally closed auxiliary contact (phase-A)
18 CBx.SCBR.in_cls_pos_b Input signal of CB's normally closed auxiliary contact (phase-B)
19 CBx.SCBR.in_cls_pos_c Input signal of CB's normally closed auxiliary contact (phase-C)

Table 6.6-2 Output signals of circuit breaker supervision

No. Input Signal Description

1 CBx.SCBR.I_Interrupted Sampled interrupted current during opening CB
2 CBx.SCBR.Ia_Interrupted Sampled phase-A interrupted current during opening CB
3 CBx.SCBR.Ib_Interrupted Sampled phase-B interrupted current during opening CB
4 CBx.SCBR.Ic_Interrupted Sampled phase-C interrupted current when opening CB
5 CBx.SCBR.N_Opn Total counting result of CB's trip counter
6 CBx.SCBR.N_Opn_A Phase-A counting result of CB's trip counter
7 CBx.SCBR.N_Opn_B Phase-B counting result of CB's trip counter
8 CBx.SCBR.N_Opn_C Phase-C counting result of CB's trip counter

10
9 CBx.SCBR.t_Opn
CBx.SCBR.t_Opn_A
Calculated contact travel time during CB opening operation
Calculated contact travel time during CB opening operation (phase-A)
6
11 CBx.SCBR.t_Opn_B Calculated contact travel time during CB opening operation (phase-B)
12 CBx.SCBR.t_Opn_C Calculated contact travel time during CB opening operation (phase-C)
13 CBx.SCBR.t_Cls Calculated contact travel time during CB closing operation
14 CBx.SCBR.t_Cls_A Calculated contact travel time during CB closing operation (phase-A)
15 CBx.SCBR.t_Cls_B Calculated contact travel time during CB closing operation (phase-B)
16 CBx.SCBR.t_Cls_C Calculated contact travel time during CB closing operation (phase-C)
17 CBx.SCBR.RemainLife Estimated remaining life of CB
18 CBx.SCBR.RemainLife_A Estimated remaining life of CB (phase-A)
19 CBx.SCBR.RemainLife_B Estimated remaining life of CB (phase-B)
20 CBx.SCBR.RemainLife_C Estimated remaining life of CB (phase-C)
21 CBx.SCBR.Abr Calculated accumulated abrasion of CB
22 CBx.SCBR.Abr_A Calculated accumulated abrasion of CB (phase-A)
23 CBx.SCBR.Abr_B Calculated accumulated abrasion of CB (phase-B)
24 CBx.SCBR.Abr_C Calculated accumulated abrasion of CB (phase-C)
Alarm signal indicates that the counting result of CB's tripp counter is out
25 CBx.SCBR.Alm_N_Opn
of limit
Warning signal indicates that the counting result of CB's tripp counter is
26 CBx.SCBR.Wrn_N_Opn
out of limit
Alarm signal indicates that the travel time of CB's opening contact is
27 CBx.SCBR.Alm_t_Opn
overtime

PCS-902S Line Distance Relay 6-15

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 6 Supervision

Warning signal indicates that the travel time of CB's opening contact is
28 CBx.SCBR.Wrn_t_Opn
overtime
Alarm signal indicates that the travel time of CB's closing contact is
29 CBx.SCBR.Alm_t_Cls
overtime
Warning signal indicates that the travel time of CB's closing contact is
30 CBx.SCBR.Wrn_t_Cls
overtime
31 CBx.SCBR.Alm_RemainLife Alarm signal indicates that the remaining life of CB is out of limit
32 CBx.SCBR.Alm_Abr Alarm signal indicates that the accumulated abrasion of CB is out of limit
Warning signal indicates that the accumulated abrasion of CB is out of
33 CBx.SCBR.Wrn_Abr
limit

6.6.9 Logic

EN [CBx.SCBR.En_Wrn_t_Opn] &
CBx.SCBR.Wrn_t_Opn
SET CBx.SCBR.t_Opn>[CBx.SCBR.Th_Wrn_t_Opn]

EN [CBx.SCBR.En_Alm_t_Opn] &
CBx.SCBR.Alm_t_Opn
SET CBx.SCBR.t_Opn>[CBx.SCBR.Th_Alm_t_Opn]

EN [CBx.SCBR.En_Wrn_t_Cls] &
CBx.SCBR.Wrn_t_Cls
SET CBx.SCBR.t_Cls>[CBx.SCBR.Th_Wrn_t_Cls]

6 EN [CBx.SCBR.En_Alm_t_Cls] &
CBx.SCBR.Alm_t_Cls
SET CBx.SCBR.t_Cls>[CBx.SCBR.Th_Alm_t_Cls]

Figure 6.6-3 Logic diagram of breaker contact travel time overtime alarm

EN [CBx.SCBR.En_Alm_RemainLife] &
CBx.SCBR.Alm_RemainLife
SET CBx.SCBR.RemainLife>[CBx.SCBR.Th_Alm_RemainLife]

Figure 6.6-4 Logic diagram of breaker remaining life alarm

EN [CBx.SCBR.En_Wrn_N_Opn] &
CBx.SCBR.Wrn_N_Opn
SET CBx.SCBR.N_Opn>[CBx.SCBR.Th_Wrn_N_Opn]

EN [CBx.SCBR.En_Alm_N_Opn] &
CBx.SCBR.Alm_N_Opn_Alm
SET CBx.SCBR.N_Opn>[CBx.SCBR.Th_Alm_N_Opn]

Figure 6.6-5 Logic diagram of breaker trip counting result out-of-limit alarm

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 6 Supervision

EN [CBx.SCBR.En_Wrn_Abr] &
CBx.SCBR.Wrn_Abr
SET CBx.SCBR.Abr>[CBx.SCBR.Th_Wrn_Abr]

EN [CBx.SCBR.En_ALm_Abr] &
CBx.SCBR.Alm_Abr
SET CBx.SCBR.Abr>[CBx.SCBR.Th_Alm_Abr]

Figure 6.6-6 Logic diagram of breaker accumulated abrasion out-of-limit alarm

6.6.10 Settings

Table 6.6-3 Circuit breaker supervison settings

Name Range Step Unit Default Description

The primary rated current for the
CBx.SCBR.I1n 1~60000 1 A 1000
circuit breaker supervision
The secondary rated current for
CBx.SCBR.I2n 1~5 1 A 5
the circuit breaker supervision
Initial counting number of CB's
CBx.SCBR.N_Opn_Init 0~1000000 1 0
trip counter
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Alm_N_Opn Disabled alarm for the counting result of
Enabled
CB's trip counter

CBx.SCBR.Th_Alm_N_Opn 0~1000000 1 1000

The threshold of out-of-limit
alarm for the counting result of
6
CB's trip counter
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Wrn_N_Opn Disabled warning for the counting result of
Enabled
CB's trip counter
The threshold of the out-of-limit
CBx.SCBR.Th_Wrn_N_Opn 0~1000000 1 5000 warning for the counting result of
CB's trip counter
The compensation factor for the
CBx.SCBR.t_Opn_Comp 0~500 1 ms 0 travel time of CB's opening
contact
The compensation factor for the
CBx.SCBR.t_Cls_Comp 0~500 1 ms 0
travel time of CB's closing contact
Enabling/disabling the overtime
Disabled
CBx.SCBR.En_Alm_t_Opn Disabled alarm for the travel time of CB's
Enabled
opening contact
The threshold of overtime alarm
CBx.SCBR.Th_Alm_t_Opn 0~10000 1 ms 50 for the travel time of CB's opening
contact
Disabled Enabling/disabling the overtime
CBx.SCBR.En_Wrn_t_Opn Disabled
Enabled warning for the travel time of CB's

PCS-902S Line Distance Relay 6-17

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 6 Supervision

Name Range Step Unit Default Description

opening contact
The threshold of overtime
CBx.SCBR.Th_Wrn_t_Opn 0~10000 1 ms 100 warning for the travel time of CB's
opening contact
Enabling/disabling the overtime
Disabled
CBx.SCBR.En_Alm_t_Cls Disabled alarm for the travel time of CB's
Enabled
closing contact
The threshold of overtime alarm
CBx.SCBR.Th_Alm_t_Cls 0~10000 1 ms 50 for the travel time of CB's closing
contact
Enabling/disabling the overtime
Disabled
CBx.SCBR.En_Wrn_t_Cls Disabled warning for the travel time of CB's
Enabled
closing contact
The threshold of overtime
CBx.SCBR.Th_Wrn_t_Cls 0~10000 1 ms 100 warning for the travel time of CB's
closing contact
CBx.SCBR.RemainLife_Init 0~100000 1 10000 Initial value of CB remaining life
Disabled Enabling/disabling the alarm of
CBx.SCBR.En_Alm_RemainLife Disabled
Enabled CB remaining life
The alarm threshold of CB
CBx.SCBR.Th_Alm_RemainLife 0~10000 1 ms 5000
remaining life
6 The rated current of the initial
CBx.SCBR.I_Rated_Life 0~1000 0.1 kA 1.0
point on CB maintenance curve
The characteristic current of the
CBx.SCBR.I_**_Life 0~1000 0.1 kA 2.0 point No.** on CB maintenance
curve (** is 02~15)
The fault current of the terminal
CBx.SCBR.I_Fault_Life 0~1000 0.1 kA 10.0
point on CB maintenance curve
The operating times
corresponding to the rated
CBx.SCBR.Num_Rated_Life 0-100000 1 10000
current of the initial point on CB
maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_**_Life 0-100000 1 8000 characteristic current of the point
No.** on CB maintenance curve
(** is 02~15)
The operating times
corresponding to the fault current
CBx.SCBR.Num_Fault_Life 0-100000 1 100
of the terminal point on CB
maintenance curve
The current exponent factor to
CBx.SCBR.CurrExponent 0.5~3.0 0.1 2.0
calculate CB's accumulated

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 6 Supervision

Name Range Step Unit Default Description

abrasion
The initial value of CB's
CBx.SCBR.Abr_Init 0~10000000 0.01 0
accumulated abrasion
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Alm_Abr Disabled alarm of CB's accumulated
Enabled
abrasion
The threshold of out-of-limit
CBx.SCBR.Th_Alm_Abr 0~10000000 0.01 2000 alarm of CB's accumulated
abrasion
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Wrn_Abr Disabled warning of CB's accumulated
Enabled
abrasion
The threshold of out-of-limit
CBx.SCBR.Th_Alm_Abr 0~10000000 0.01 5000 warning of CB's accumulated
abrasion

6.7 Supervision Alarms and Handling Suggestion

Hardware circuit and operation status of this device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued. 6
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure, DC
converter failure and so on, are detected, all protection functions will be blocked and the LED
"HEALTHY" will be extinguished and blocking output contacts "BO_Fail" will be given. The
protective device then cannot work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.

If the device is blocked or alarm signal is sent during operation, please do find out its reason with
the help of self-diagnostic record. If the reason cannot be found at site, please notify the
manufacturer, NR. Please do not simply press button "TARGET RESET" on the protection panel
or re-energize on the device.

Table 6.7-1 Alarm description

LED
No. Item Configurable Description
"ALARM"
Fail signals (Device will be blocked, LED "HEALTHY" will be OFF.)
This signal will be issued if any fail signal
1 Fail_Device OFF × picks up and it will drop off when all fail
signals drop off.
This signal will be issued if any hardware
2 Fail_DeviceInit OFF ×
or software failure is detected in the device

PCS-902S Line Distance Relay 6-19

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 6 Supervision

LED
No. Item Configurable Description
"ALARM"
initialization process.
This signal will be issued due to mismatch
between the configuration of plug-in
3 Fail_BoardConfig OFF ×
modules and the designing drawing of an
applied-specific project.
This signal will be issued if the CCD
process level configure file is parsed
4 Fail_ProcLevelConfig OFF ×
wrongly or the type in the file is inconsistent
with the actual device.
After configuration file is updated, settings
of the file and settings saved on the device
are not matched. This signal will be issued
5 Fail_SettingItem_Chgd OFF ×
instantaneously and will be latched unless
the recommended handling suggestion is
adopted.
The value of any setting is out of scope.
This signal will be issued instantaneously
6 Fail_Setting_OvRange OFF × and will be latched unless the
recommended handling suggestion is
adopted.
6 The alarm signal will be issued
instantaneously when an error is found
7 Fail_Memory OFF ×
during checking memory data, and usually,
it will automatically drop out.
The configuration process does not run
8 Fail_ProcessConfig OFF ×
properly.
The board fails to register the variable,
9 Fail_BoardRegister OFF × because of abnormal board, insufficient
memory space, or incorrect configuration.
The board fails to be initialized, because of
10 Fail_BoardInit OFF × abnormal board, insufficient memory
space, or incorrect configuration.
Error is found during checking settings.
11 Fail_Settings OFF × The inappropriate or incorrect value is set
in a certain application scenario.
A/D sampling data push error, the possible
12 Fail_Sample OFF × cause is that the data verification fails or no
data is sampled by A/D converter.
13 P1.Fail_Board OFF × The PWR module is abnormal.
An abnormality is detected during the
14 Bxx.Fail_Board OFF × module self-check located in slot xx of the
device.

6-20 PCS-902S Line Distance Relay

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 6 Supervision

LED
No. Item Configurable Description
"ALARM"
15 Fail_Output OFF × The BO module or IO module is abnormal.
Alarm signals (Device will not be blocked)
The device is abnormal. This signal will be
issued if any alarm signal picks up and it
16 Alm_Device ON ×
will drop off when all alarm signals drop
out.
This signal will be issued if any hardware
17 Alm_DeviceInit OFF × or software configuration wrong is detected
in the device initialization process.
The error is found during checking the
version of software downloaded to the
18 Alm_Version ON × device. This signal will be issued
instantaneously and will drop off
instantaneously.
The device is in the communication test
mode. This signal will be issued
19 Alm_CommTest ON ×
instantaneously and will drop off
instantaneously.
The device is in the GOOSE test mode.
20 Alm_GOOSETest OFF × This signal will be issued instantaneously
and will drop off instantaneously. 6
The active group set by settings in device
and that set by binary input are not
21 Alm_BI_SettingGrp OFF × matched. This signal will be issued
instantaneously and will drop off
instantaneously.
The time synchronization abnormality
22 Alm_TimeSyn ON √
alarm.
The memory of CPU plug-in module is
23 Alm_Insuf_Memory ON ×
insufficient.
The configuration file of IEC103 is detected
24 Alm_CfgFile_IEC103 ON × to not be correct when this file is parsed in
the device initialization process.
CPU module detects that some module is
25 Alm_Board OFF × reset due to the abnormality during the
device operating.
No sufficient NOR flash space used to
26 Alm_Insuf_NORflash OFF ×
store the program in CPU module
The network mode is inconsistent, such as
27 Alm_NetMode_Unmatched OFF × the setting is set as HSR mode, but the
actual operation mode is PRP mode.
28 Alm_Settings_DFR OFF × The set value of the setting

PCS-902S Line Distance Relay 6-21

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 6 Supervision

LED
No. Item Configurable Description
"ALARM"
[RecDur_PostFault] is greater than the set
value of the setting
[MaxRecDur_PostTrigDFR].
The settings which are stored in CPU
29 Alm_Settings ON × module are different with the settings
which are used by other modules.
The device's master process is abnormal
30 Alm_master ON ×
and it is blocked for more than 1 minute.
Error is detected in the FPGA configuration
31 Alm_CfgFile_FPGA OFF ×
file.
Error is detected in internal
32 Alm_DSP_HTM_Comm ON ×
communication.
Error is detected in the configuration file of
33 Alm_CRC_ProcLevel OFF ×
process level by CRC.
The configuration file of DNP client 1 is
34 Alm_CfgFile_TCP1_DNP OFF ×
incorrect.
The configuration file of DNP client 2 is
35 Alm_CfgFile_TCP2_DNP OFF ×
incorrect.
The configuration file of DNP client 3 is
36 Alm_CfgFile_TCP3_DNP OFF ×
incorrect.
6 The configuration file of DNP client 4 is
37 Alm_CfgFile_TCP4_DNP OFF ×
incorrect.
38 Alm_ARP_Bind_Failure × × ARP binding fails.
Pilot channel alarm signals (Device will not be blocked)
Received ID from the remote end is not as
same as the setting [FOx.RmtID] of the
device in local end
39 FOx.Alm_ID ON ×
This signal will pick up with a time delay of
100ms and will drop off with a time delay of
1s.
Channel x is abnormal
This signal will pick up with a time delay of
40 FOx.Alm ON ×
100ms and will drop off with a time delay of
1s.
No valid frame of channel x is received.
This signal will pick up with a time delay of
41 FOx.Alm_NoValFram ON ×
100ms and will drop off with a time delay of
1s.
Rate of error code of channel x is larger
than 40 error codes per second.
42 FOx.Alm_CRC ON ×
This signal will pick up instantaneously and
will drop off with a time delay of 10s.

6-22 PCS-902S Line Distance Relay

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 6 Supervision

LED
No. Item Configurable Description
"ALARM"
Channel x is out of service due to receive
error codes after device picking up.
43 FOx.Alm_Off ON ×
This signal will pick up instantaneously and
will drop off instantaneously.
Optical fibre of channel x is connected
wrongly.
44 FOx.Alm_Connect ON × This signal will pick up with a time delay of
100ms and will drop off with a time delay of
1s.
Function alarm signals (Device will not be blocked)
45 Alm_Maintenance ON √ The device is in maintenance state.
46 Alm_BOTest OFF × The device is in output test mode.
The sampled values from the dual A/D
converters are inconsistent or the sampled
47 Alm_Sample ON × value contains a large DC component
during the self or mutual check of sampling
channels.
48 Alm_Quality ON × The quality of sampled data is abnormal.
Fault detector element operates for more
than 50s.
49 Alm_Pkp_FD OFF √ This signal will pick up with a time delay of 6
50s and will drop off with a time delay of
10s.
The initiating signal of breaker failure
50 CBx.50BF.Alm_Init ON √
protection is abnormal.
Differential current is abnormal.
This signal will pick up with a time delay of
51 87STB.Alm_Diff OFF √
10s and will drop off with a time delay of
10s.
Disconnector position is abnormal.
This signal will pick up with a time delay of
52 87STB.Alm_89b_DS OFF √
10s and will drop off with a time delay of
10s.
The initiating signal of dead zone
53 CBx.50DZ.Alm_Init ON √
protection is abnormal.
The initiating signal of pole discrepancy
54 CBx.62PD.Alm_Init ON √
protection is abnormal.
Input signal of receiving transfer trip is
energized for longer than the setting
55 TT.Alm ON √
[TT.t_Op]+5s and it will drop off with a time
delay of 10s.
56 CBx.Alm_52b OFF √ The auxiliary normally closed contact (52b)

PCS-902S Line Distance Relay 6-23

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-06-15
 6 Supervision

LED
No. Item Configurable Description
"ALARM"
of circuit breaker No.x is abnormal.
This signal will pick up with a time delay of
10s and will drop off with a time delay of
10s.
CT circuit fails of circuit breaker No.x.
This signal will pick up with a time delay
57 CBx.CTS.Alm ON ×
[CTS.t_DPU] and will drop off with a time
delay [CTS.t_DDO].
The synchronism check mode for AR is
58 CBx.79.Alm_RSYN_Mode ON √
abnormal.
VT circuit fails. (delay alarm signal)
This signal will pick up with a time delay
59 VTS.Alm ON ×
[VTS.t_DPU] and will drop off with a time
delay [VTS.t_DDO].
VT circuit fails. (instantaneous alarm
signal)
60 VTS.InstAlm OFF √
This signal will pick up with a time delay of
25ms and will drop off without time delay.
For synchronism check voltage input
channel configuration, the voltage source
6 61 CBx.25.Alm_Cfg_Ch ON √
to connect to the inputs "in_ref" and
"in_syn" should be the same with that
used in measurement function. Otherwise,
this alarm will be issued.
Voltage selection corresponding to circuit
62 CBx.VoltSel.Alm_Invalid_Sel ON √
breaker No.x is invalid.
Control circuit of circuit breaker No.x is
63 CBx.TCCS.Alm OFF √
abnormal
The residual voltage "3U0_Pri" is greater
than the overvoltage alarm threshold
multiplying the measurement VT rated
64 Prot.Alm_ROV OFF √ voltage (i.e.,
[3U0_Alm_ROV]×[U1n_VT_Measmt]).
This signal will pick up with a time delay of
10s and drop off with a time delay of 1s
The residual current "3I0_Pri" of circuit
breaker No.x is greater than the
overcurrent alarm threshold multiplying the
65 CBx.Prot.Alm_ROC OFF √ measurement CT rated current (i.e.,
[3I0_Alm_ROC]×[I1n_CT_Measmt]).
This signal will pick up with a time delay of
10s and drop off with a time delay of 1s

6-24 PCS-902S Line Distance Relay

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 6 Supervision

LED
No. Item Configurable Description
"ALARM"
A phase voltage is less than the
undervoltage alarm threshold multiplying
the measurement VT rated voltage (i.e.,
66 Prot.Alm_UV OFF √
[U_Alm_UV]×[XXXX.U1n_VT_Measmt]).
This signal will pick up with a time delay of
10s and drop off with a time delay of 1s.
If a DPS signal indicating CB/DS/ES
position is intermediate or bad, this alarm
will be issued.
67 xx.DPS.Alm OFF √
This signal will pick up and drop off with a
time delay defined by [xx.DPS.t_Alm]. (xx
can CB** or DS**)
68 Alm_Phasor_Config OFF √ Error of phasor configuration
69 Alm_Analog_Config OFF √ Error of analogue input configuration
70 Alm_BI_Config OFF √ Error of digital status configuration
71 PDC01.Alm_Invalid_IDCODE OFF √ ID code of PDC01 is invalid
72 PDC02.Alm_Invalid_IDCODE OFF √ ID code of PDC02 is invalid
73 PDC03.Alm_Invalid_IDCODE OFF √ ID code of PDC03 is invalid
74 PDC04.Alm_Invalid_IDCODE OFF √ ID code of PDC04 is invalid
Error of VT circuit (xx is determined by the
75 xx.Alm_VTS ON √ setting [Name_PMUBay] in the submenu 6
PMUBay Settings)
Error of CT circuit (xx is determined by the
76 xx.Alm_CTS ON √ setting [Name_PMUBay] in the submenu
PMUBay Settings)
GOOSE alarm signals (Device will not be blocked)
The GOOSE communication is abnormal.
It is an overall alarm signal and will be
77 GAlm_Overall ON × issued if any GOOSE alarm signal picks up
and it will drop-off when all these alarm
signals drop-off.
Error is detected in the GOOSE
78 GAlm_CfgFile ON ×
configuration file.
For GOOSE communication link, the
incoming data with test=true &
79 B01.GAlm_Maint_Unmatched ON × validity=good & operatorBlocked=false,
but the quality status (q) of the device
equals to "on".
For GOOSE communication link XX, the
connection of GOOSE network A is
80 XX.GAlm_ADisc ON ×
disconnected. (No GOOSE message is
received within two times TAL from

PCS-902S Line Distance Relay 6-25

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 6 Supervision

LED
No. Item Configurable Description
"ALARM"
GOOSE communication link XX)
XX is determined by description setting
[Bxx.Name_**_GCommLink]
For GOOSE communication link XX, the
connection of GOOSE network A is
disconnected. (No GOOSE message is
81 XX.GAlm_BDisc ON × received within two times TAL from
GOOSE communication link XX)
XX is determined by description setting
[Bxx.Name_**_GCommLink]
Between GOOSE control blocks received
on network and GOOSE control blocks
defined in GOOSE configuration file are
82 XX.GAlm_CfgUnmatched ON × unmatched. (Including config version,
number of data sets and data type)
XX is determined by description setting
[Bxx.Name_**_GCommLink]
SV alarm signals (Device will not be blocked)
The SV communication is abnormal.
It is an overall alarm signal and will be
6 83 SVAlm_Overall ON × issued if any SV alarm signal picks up and
it will drop-off when all these alarm signals
drop-off.
Error is detected in the SV configuration
84 SVAlm_CfgFile ON ×
file.
For SV communication link, the incoming
data with test=true & validity=good &
85 SVAlm_Maint_Unmatched ON ×
operatorBlocked=false, but the quality
status (q) of the device equals to "on".
For SV communication link XX, the
connection of SV network A is
disconnected. (Including data timeout,
86 XX.SVAlm_ADisc ON ×
decoding error, or sampling counter error)
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
For SV communication link XX, the
connection of SV network B is
disconnected. (Including data timeout,
87 XX.SVAlm_BDisc ON ×
decoding error, or sampling counter error)
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
88 XX.SVAlm_Data ON × Interpolation error of sampling data in SV

6-26 PCS-902S Line Distance Relay

Date: 2023-08-01
 6 Supervision

LED
No. Item Configurable Description
"ALARM"
communication link XX
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
Loss of synchronization of sampling data in
SV communication link XX
89 XX.SVAlm_SmplSynLoss ON ×
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
Invalid sampling data in SV communication
link XX
90 XX.SVAlm_InvalidSample ON ×
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
Jittering error of sampling data in SV
communication link XX
91 XX.SVAlm_Jitter_Ch ON ×
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
The delay of SV communication link XX
changes.
92 XX.SVAlm_tdrChgd_Ch ON ×
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
The delay of SV communication link XX

93 XX.SVAlm_tdrOvRange_Ch ON ×
exceeds the limit. 6
XX is determined by description setting
[Bxx.Name_**_SVCommLink]
SV communication link XX is in
maintenance state
94 XX.SVAlm_Maintenance ON ×
XX is determined by description setting
[Bxx.Name_**_SVCommLink]

Table 6.7-2 Troubleshooting

No. Item Handling suggestion

Fail signals
The signal is issued with other specific fail signals, and please refer to
1 Fail_Device
the handling suggestion other specific alarm signals.
2 Fail_DeviceInit Please inform the manufacturer or the agent for repair.
1. Go to the menu "Information→Borad Info", check the abnormality
information.
3 Fail_BoardConfig 2. For the abnormality board, if the board is not used, then remove, and
if the board is used, then check whether the board is installed properly
and work normally.
Please check whether the CCD process level configuration file of this
4 Fail_ProcLevelConfig device is existing and whether the file content is correct. May need to
download and update the correct CCD process level configuration file.

PCS-902S Line Distance Relay 6-27

Date: 2023-08-01
-06-15
 6 Supervision

No. Item Handling suggestion

Please check the settings mentioned in the prompt message on the
LCD, and go to the menu “Settings” and select “Confirm Settings”
5 Fail_SettingItem_Chgd
item to confirm settings. Then, the device will restore to normal
operation stage.
Please reset setting values according to the range described in the
6 Fail_Setting_OvRange technical manual, then re-power or reboot the device and the device
will restore to normal operation state.
7 Fail_Memory Please inform the manufacturer or the agent for repair.
Please view the menu "Initialization Error" to check the detailed
8 Fail_ProcessConfig
reason, and send the reason to the manufacturer or the agent.
9 Fail_BoardRegister Please inform the manufacturer or the agent for repair.
Please view the menu "Initialization Error" to check the detailed
10 Fail_BoardInit
reason, and send the reason to the manufacturer or the agent.
11 Fail_Settings Please check the settings and set them correctly
Please check the connection of CPU module, or inform the
12 Fail_Sample
manufacturer or the agent to deal with it.
Please check the connection of PWR module, or inform the
13 P1.Fail_Board
manufacturer or the agent to deal with it.
14 Bxx.Fail_Board Please inform the manufacturer or the agent to deal with it.
Please put the device out of service at once, and inform the
15 Fail_Output

6
manufacturer or the agent to maintain it.
Alarm signals
The signal is issued with other specific alarm signals, and please refer
16 Alm_Device
to the handling suggestion other specific alarm signals.
17 Alm_DeviceInit Please inform the manufacturer or the agent to deal with it.
Users may pay no attention to the alarm signal in the project
commissioning stage, but it is needed to download the latest package
file (including correct version checksum file) provided by R&D engineer
18 Alm_Version to make the alarm signal disappear. Then users get the correct
software version. It is not allowed that the alarm signal is issued on the
device already has been put into service. The devices have been put
into service so that the alarm signal disappears.
No special treatment is needed, and disable the communication test
19 Alm_CommTest
function after completing the test.
No special treatment is needed, and disable the GOOSE test function
20 Alm_GOOSETest
after completing the test.
Please check the value of the setting [Active_Grp] and binary inputs of
indicating active group, and make them matched. Then the “ALARM”
21 Alm_BI_SettingGrp
LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.

6-28 PCS-902S Line Distance Relay

Date: 2023-08-01
 6 Supervision

No. Item Handling suggestion

1. Check whether the selected clock synchronization mode matches
the clock synchronization source;
2. Check whether the wiring connection between the device and the
clock synchronization source is correct
3. Check whether the setting for selecting clock synchronization (i.e.
22 Alm_TimeSyn
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization,
please set the setting [Opt_TimeSyn] as "No TimeSyn".
After the abnormality is removed, the “ALARM” LED will be
extinguished and the corresponding alarm message will disappear and
the device will restore to normal operation state.
23 Alm_Insuf_Memory Please inform the manufacturer or the agent to deal with it.
Please inform the configuration engineer to check and confirm the
24 Alm_CfgFile_IEC103
contents of IEC 60870-5-103 configuration file.
25 Alm_Board Please inform the manufacturer or the agent to deal with it.
26 Alm_Insuf_NORflash Please inform the manufacturer or the agent to deal with it.
Please check the setting of network mode, or upload the device log and
27 Alm_NetMode_Unmatched confirm with the manufacturer or agent whether the network mode is
supported.
Please check the settings [RecDur_PostFault] and
28 Alm_Settings_DFR
[MaxRecDur_PostTrigDFR], and set them reasonably.
29 Alm_Settings Please inform the manufacturer or the agent for repair.
30 Alm_master Please check the load of the device. 6
31 Alm_CfgFile_FPGA Please inform the manufacturer or the agent for repair.
32 Alm_DSP_HTM_Comm Please inform the manufacturer or the agent for repair.
33 Alm_CRC_ProcLevel Please inform the manufacturer or the agent for repair.
34 Alm_CfgFile_TCP1_DNP
35 Alm_CfgFile_TCP2_DNP Please contact the configuration engineer to check and confirm the
36 Alm_CfgFile_TCP3_DNP contents of DNP configuration file.
37 Alm_CfgFile_TCP4_DNP
If ARP binding function is necessary, please generate ARP binding
38 Alm_ARP_Bind_Failure information again. If ARP binding function is not required, please set
the setting [En_ARP_Bind] as "0".
Pilot channel alarm signals
39 FOx.Alm_ID Please check the connection of optical fibre channel.
40 FOx.Alm Please check the connection of optical fibre channel.
41 FOx.Alm_NoValFram Please check the connection of optical fibre channel.
42 FOx.Alm_CRC Please check the connection of optical fibre channel.
43 FOx.Alm_Off Please check the connection of optical fibre channel.
Please check the connection of optical fibre channel. (For example,
44 FOx.Alm_Connect receiving and sending are inconsistent, or channel 1 and channel 2 are
inconsistent)
Function alarm signals

PCS-902S Line Distance Relay 6-29

Date: 2023-08-01
-06-15
 6 Supervision

No. Item Handling suggestion

It is normal prompt information of the device and does not need to be
45 Alm_Maintenance
handled.
It is normal prompt information of the device and does not need to be
46 Alm_BOTest
handled.
47 Alm_Sample Please check the connection of AI module and CPU module.
48 Alm_Quality Please check SV qualify if adopting IEC 61850-9-2.
Please check secondary values and protection settings. If settings are
not set reasonable to make fault detectors pick up, please reset
49 Alm_Pkp_FD
settings, and then the alarm message will disappear and the device will
restore to normal operation state.
Please check the contacts of binary inputs "CBx.50BF.ExTrpA",
50 CBx.50BF.Alm_Init "CBx.50BF.ExTrpB", "CBx.50BF.ExTrpC", "CBx.50BF.ExTrp3P",
"CBx.50BF.ExTrp_WOI"
Please check the corresponding current circuit. After the abnormality is
51 87STB.Alm_Diff eliminated, the device returns to normal operation state with a time
delay of 10s.
Please check the corresponding binary input secondary circuit. After
52 87STB.Alm_89b_DS the abnormality is eliminated, the device returns to normal operation
state with a time delay of 10s.
53 CBx.50DZ.Alm_Init Please check the contact of binary input "CBx.50DZ.Init"
54 CBx.62PD.Alm_Init Please check the contact of binary input "CBx.62PD.Init"
6 Please check the corresponding binary input secondary circuit. After
55 TT.Alm the abnormality is eliminated, “ALARM” LED will go off automatically
and device returns to normal operation state with a time delay of 10s.
Please check the auxiliary contact of circuit breaker No.x. After the
56 CBx.Alm_52b
abnormality is eliminated, the device returns to normal operation state.
Please check CT secondary circuit corresponding to circuit breaker
57 CBx.CTS.Alm No.x. After the abnormality is eliminated, the device returns to normal
operation state.
58 CBx.79.Alm_RSYN_Mode Please check the related settings.
Please check the corresponding VT secondary circuit. After the
59 VTS.Alm
abnormality is eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit. After the
60 VTS.InstAlm
abnormality is eliminated, the device returns to normal operation state.
61 CBx.25.Alm_Cfg_Ch Please check the channel configuration for synchronism check.
Please check voltage selection logic corresponding to circuit breaker
62 CBx.VoltSel.Alm_Invalid_Sel
No.x.
63 CBx.TCCS.Alm Please check whether the position of breaker circuit No.x is correct.
64 Prot.Alm_ROV Please check the residual voltage with the corresponding settings.
Please check the residual current with the corresponding settings
65 CBx.Prot.Alm_ROC
corresponding to circuit breaker No.x.
66 Prot.Alm_UV Please check the phase voltages with the corresponding settings.

6-30 PCS-902S Line Distance Relay

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 6 Supervision

No. Item Handling suggestion

67 xx.DPS.Alm Please check the corresponding DPS signal. (xx can be CB** or DS**)
68 Alm_Phasor_Config Please check the label setting of bay to make sure it is within 12
69 Alm_Analog_Config characters.
Please check the name of binary signal to make sure it is within 16
70 Alm_BI_Config
characters.
71 PDC01.Alm_Invalid_IDCODE Please check the ID code of PDC01
72 PDC02.Alm_Invalid_IDCODE Please check the ID code of PDC02
73 PDC03.Alm_Invalid_IDCODE Please check the ID code of PDC03
74 PDC04.Alm_Invalid_IDCODE Please check the ID code of PDC04
Check the VT circuit of the bay. (xx is determined by the setting
75 xx.Alm_VTS
[Name_PMUBay] in the submenu PMUBay Settings)
Check the CT circuit of the bay. (xx is determined by the setting
76 xx.Alm_CTS
[Name_PMUBay] in the submenu PMUBay Settings)
GOOSE alarm signals
The signal is issued with other specific GOOSE alarm signals, and
77 GAlm_Overall
please refer to the handling suggestion of them.
78 GAlm_CfgFile Please check GOOSE configuration file.
79 B01.GAlm_Maint_Unmatched Please check the quality status (q) of incoming data and the device.
80 XX.GAlm_ADisc Please check GOOSE network and GOOSE configuration file.
81 XX.GAlm_BDisc Please check GOOSE network and GOOSE configuration file.
82 XX.GAlm_CfgUnmatched Please check GOOSE network and GOOSE configuration file.
SV alarm signals
6
The signal is issued with other specific SV alarm signals, and please
83 SVAlm_Overall
refer to the handling suggestion of them.
84 SVAlm_CfgFile Please check SV configuration file.
85 SVAlm_Maint_Unmatched Please check the quality status (q) of incoming data and the device.
86 XX.SVAlm_ADisc Please check SV network and SV configuration file.
87 XX.SVAlm_BDisc Please check SV network and SV configuration file.
88 XX.SVAlm_Data Please check SV network and SV configuration file.
89 XX.SVAlm_SmplSynLoss Please check synchronization clock of SV communication link XX.
Please check the validity of quality type definition in SV communication
90 XX.SVAlm_InvalidSample
link XX.
91 XX.SVAlm_Jitter_Ch Please check send interval of SV communication link XX.
92 XX.SVAlm_tdrChgd_Ch Please check channel delay of SV communication link XX
93 XX.SVAlm_tdrOvRange_Ch Please check channel delay of SV communication link XX
Please check the quality status (q) of SV communication link XX via
94 XX.SVAlm_Maintenance
MU

PCS-902S Line Distance Relay 6-31

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-06-15
 6 Supervision

6-32 PCS-902S Line Distance Relay

Date: 2023-08-01
 7 System Functions

7 System Functions

Table of Contents

7.1 Clock Synchronization .................................................................................... 7-1

7.1.1 Clock Synchronization Mode................................................................................................ 7-1

7.1.2 Clock Synchronization Abnormality ...................................................................................... 7-1

7.1.3 Clock Synchronization Priority ............................................................................................. 7-1

7.1.4 SNTP Setup.......................................................................................................................... 7-2

7.2 State Information ............................................................................................. 7-2

7.2.1 Overview............................................................................................................................... 7-2

7.2.2 Access Method ..................................................................................................................... 7-3

7.3 Event Recording .............................................................................................. 7-4

7.3.1 Overview............................................................................................................................... 7-4

7.3.2 Disturbance Records ............................................................................................................ 7-4

7.3.3 Supervision Events............................................................................................................... 7-4

7.3.4 Binary Events ....................................................................................................................... 7-4

7.3.5 Device Logs .......................................................................................................................... 7-4 7

7.3.6 Control Logs ......................................................................................................................... 7-4

7.3.7 Access Method ..................................................................................................................... 7-4

7.4 High-frequency Recording.............................................................................. 7-5

7.5 Fault Recording ............................................................................................... 7-6
7.5.1 Overview............................................................................................................................... 7-6

7.5.2 Fault Report .......................................................................................................................... 7-6

7.5.3 Fault Waveform .................................................................................................................... 7-6

7.5.4 Access Method ..................................................................................................................... 7-7

7.6 Mode and Behaviour ....................................................................................... 7-8

7.7 Maintenance State ......................................................................................... 7-10
7.8 Communication Test ..................................................................................... 7-10
7.9 Output Test ..................................................................................................... 7-11

PCS-902S Line Distance Relay 7-a

Date: 2023-08-01
 7 System Functions

7.10 Target Reset ................................................................................................. 7-11

7.11 Switch Setting Groups ................................................................................ 7-12

7-b PCS-902S Line Distance Relay

Date: 2023-08-01
 7 System Functions

7.1 Clock Synchronization

7.1.1 Clock Synchronization Mode

The device supports both hardware-based and software-based clock synchronization modes.

1. Hardware clock synchronization ([Opt_TimeSyn]=Conventional)

⚫ IRIG-B: IRIG-B via serial port (RS-485 or TTL level) or BNC port (TTL level)

⚫ PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), BNC port (TTL level)
or binary input

⚫ IEEE 1588: Clock message based on IEEE 1588 via Ethernet network

2. Software clock synchronization ([Opt_TimeSyn]=SAS)

⚫ SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network

⚫ Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol

7.1.2 Clock Synchronization Abnormality

The device provides an alarm signal "Alm_TimeSyn", which indicates the signal of clock
synchronization is abnormal or is lost. The setting [Opt_TimeSyn] should be set reasonably
according to actual clock synchronization source. If the setting [Opt_TimeSyn] is set as
"NoTimeSyn" and no clock synchronization signal is connected, the device will not issue the alarm
signal.

7.1.3 Clock Synchronization Priority

The device provides a priority-based adaptive clock synchronization scheme, which means that the
7
device can automatically identify multiple clock synchronization sources in the same clock
synchronization mode and choose the highest priority of lock synchronization sources.

The setting [Opt_TimeSyn] is set as "SAS".

Clock synchronization mode Clock synchronization signal Priority selection

Software-based SNTP + Clock message SNTP

The setting [Opt_TimeSyn] is set as "Conventional" and the setting [En_ConvModeSNTP] is set
as "Disabled"

Clock synchronization mode Clock synchronization signal Priority selection

IRIG-B + PPS + IEEE 1588 IRIG-B

Hardware-based
PPS + IEEE 1588 PPS

The setting [Opt_TimeSyn] is set as "Conventional" and the setting [En_ConvModeSNTP] is set
as "Enabled"

PCS-902S Line Distance Relay 7-1

Date: 2023-08-01
 7 System Functions

Clock synchronization mode Clock synchronization signal Priority selection

IRIG-B + PPS + IEEE 1588 + SNTP IRIG-B

Hardware-based + SNTP PPS + IEEE 1588 + SNTP PPS

IEEE 1588 + SNTP IEEE 1588

7.1.4 SNTP Setup

When the device adopts SNTP to realize clock synchronization, [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] shall be set correctly.

[IP_Server_SNTP] is the address of SNTP clock synchronization server which sends SNTP timing
messages to the relay or BCU. [IP_StandbyServer_SNTP] is the address of standby SNTP clock
synchronization server.

Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock

synchronization is valid.

When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000", the

device receives broadcast SNTP synchronization message.

When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting whose value is not equal to "000.000.000.000" as SNTP server address
and receives unicast SNTP synchronization message.

If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "000.000.000.000", the device

adopts the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive any server response after 30s, it adopts
7 the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP
synchronization message.

The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it

does not receive any server response in 30s.

7.2 State Information

7.2.1 Overview

The device can provide real-time state information, including analogue quantities (such primary
measurement value, secondary measurement value, metering value and so on) and status
quantities (supervision status, input status, output status and so on). By check these state
informations, operators can know operation state of the protected equipment and whether the
device is healthy.

7-2 PCS-902S Line Distance Relay

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-02-27
 7 System Functions

7.2.2 Access Method

7.2.2.1 Access by Local HMI (Human Machine Interface)

These state informations can be gained via local HMI. The menu path is:

1. Analogue quantities

⚫ MainMenuMeasurementsPrimary Values

⚫ MainMenuMeasurementsSecondary Values

⚫ MainMenuMeasurementsFunction ValuesSynchronism Check

⚫ MainMenuMeasurementsGOOSE Analog

⚫ MainMenuMeasurementsEnergy Metering

⚫ MainMenuMeasurementsPower Quality

⚫ MainMenuMeasurementsPMU Values

⚫ MainMenuMeasurementsUserDef Values

2. Status quantities

⚫ MainMenuStatusInputs

⚫ MainMenuStatusOutputs

⚫ MainMenuStatusPMU Status

⚫ MainMenuStatusSuperv Status

⚫ MainMenuStatusLogic Links Status

7
⚫ MainMenuStatusRunning Status

⚫ MainMenuStatusUserDef Status

7.2.2.2 Access by Virtual HMI

Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.

7.2.2.3 Access by Communication Client

Device's state information can be uploaded into clients through message communication. For
different protocols, the state information can be gained through corresponding communication
service.

7.2.2.4 Access by Printer

The device can print the current state information, so that the operator can observe and save the
current operation condition. The access path is:

MainMenuPrintDevice Status

PCS-902S Line Distance Relay 7-3

Date: 2023-08-01
 7 System Functions

7.3 Event Recording

7.3.1 Overview

The device can store the latest 1024 time-stamped disturbance records, 1024 time-stamped binary
events, 1024 time-stamped supervision events, 256 time-stamped control logs and 1024 time-
stamped device logs. All the records are stored in non-volatile memory, and when the available
space is exhausted, the oldest record is automatically overwritten by the latest one.

7.3.2 Disturbance Records

When any protection element operates or drops out, such as fault detector, distance protection etc.,
they will be logged in event records. Disturbance records include signal name, its value before and
after changing, and the time precision is up to 1ms.

7.3.3 Supervision Events

The device is under automatic supervision all the time. If there are any failure or abnormal condition
detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event records.
Supervision events include signal name, its value before and after changing, and the time precision
is up to 1ms.

7.3.4 Binary Events

When there is a binary input is energized or de-energized, i.e., its state has changed from "0" to
"1" or from "1" to "0", it will be logged in event records. Binary events include signal name, its value
before and after changing, and the time precision is up to 1ms.

7 7.3.5 Device Logs

If an operator executes some operations on the device, such as reboot protective device, modify
setting, etc., they will be logged in event records. Device logs include signal name, its value before
and after changing, and the time precision is up to 1ms.

7.3.6 Control Logs

When an operator executes a control command via local LCD, PCS-Studio or communication client,
it will be logged in control logs. Control logs include time stamp, controlled object, control origination,
control position, operation condition, interlocking condition, control command and operation result.

7.3.7 Access Method

7.3.7.1 Access by Local HMI

The device provides corresponding menus to view event recorders. The menu path is:

MainMenuTestDisturb Item

MainMenuRecordsSuperv Events

MainMenuRecordsIO Events

7-4 PCS-902S Line Distance Relay

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-02-27
 7 System Functions

MainMenuRecordsDevice Logs

MainMenuRecordsControl Logs

7.3.7.2 Access by Virtual HMI

Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.

7.3.7.3 Access by Communication Client

Event recorders can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).

7.3.7.4 Access by Printer

The device can print event recorders, so that the operator can observe and save the current
operation condition. The access path is:

MainMenuPrintSuperv Events

MainMenuPrintIO Events

7.4 High-frequency Recording

The high-frequency recording is available by PCS-Studio. By switching the option "Disabled" or

"Enabled" to enable or disable the function in the following path through the PCS-Studio
configuration tool: Project Node→Device Node→Device Setup→Global Config→System
Config.

When high-frequency recording is enabled, a high-frequency waveforms record (9.6KHz sampling)

can also be gained besides the normal disturbance waveforms record (1.2KHz sampling). The
difference between high-frequency waveforms records and normal disturbance waveforms records
is only the sampling rate. This kind of high-resolution records is convenient to perform post-fault
system and device operation analysis.

PCS-902S Line Distance Relay 7-5

Date: 2023-08-01
 7 System Functions

7.5 Fault Recording

7.5.1 Overview

Fault recorder can be used to have a better understanding of the behavior of the power network
and related primary and secondary equipment during and after a disturbance. Analysis of the
recorded data provides valuable information that can be used to improve existing equipment. This
information can also be used when planning for and designing new installations.

The fault recorder is comprised of the report and the waveform, which can be triggered by pickup
signals, trip signals and configurable binary signal "BI_TrigDFR".

The fault memory of the device is automatically updated with every recording. When the fault
memory is filled completely, the oldest records are overwritten automatically. Thus, the most recent
recordings are always stored safely. The maximum number of recordings is up to 64.

7.5.2 Fault Report

For each fault report, the following items are included:

1. Sequence number

Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.

2. Date and time of fault occurrence

The date and time are recorded when a system fault is detected. The time resolution is 1ms.

3. Relative operating time

7 An operating time (not including the operating time of output relays) is recorded in the record. The
time resolution is 1ms.

4. Fault information

Including faulty phase, fault location and protection elements

7.5.3 Fault Waveform

A fault waveform contains all analogue and digital quantities related to protection such as currents,
voltages, alarm elements, and binary inputs and etc..

The overall duration of a single fault recording comprises the total duration of the configurable
recording criterion, the pre-trigger time and the post-trigger time. With the fault recording parameter,
these components can be individually set. The pre-trigger waveform recorded duration is
configured via the setting [RecDur_PreTrigDFR]. The waveform recorded duration after the fault
disappears is configured via the setting [RecDur_PostFault]. The maximum post-trigger waveform
recorded duration is configured via the setting [MaxRecDur_PostTrigDFR].

7-6 PCS-902S Line Distance Relay

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-02-27
 7 System Functions

4. [MaxRecDur_PostTrigDFR]

1. [RecDur_PreTrigDFR] 2.Pickup 3. [RecDur_PostFault]

Trigger point

Total recording time

1. Pre-trigger recording time

Use the setting [RecDur_PreTrigDFR] to set this time.

2. Pickup recording time

The pickup recording time cannot be set. It continues as long as any valid trigger condition, binary
or analogue, persists (unless limited by the limit time, which is determined by the setting
[MaxRecDur_PostTrigDFR]).

3. Post-fault recording time

The recording time begins after all activated triggers are reset. Use the setting [RecDur_PostFault]
to set this time.

4. Maximal post-trigger recording time

Use the setting [MaxRecDur_PostTrigDFR] to set this time. If the summation of pickup recording
time and post-fault recording time is larger than maximal post-trigger recording time, the post-
trigger recording time shall be equal to the setting [MaxRecDur_PostTrigDFR].

7.5.4 Access Method

The device provides several access methods to fault recording.

7
7.5.4.1 Access by Local HMI

The device provides corresponding menus to check fault recording. The menu path is:

MainMenuRecordsDisturb Records

7.5.4.2 Access by Virtual HMI

Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.

7.5.4.3 Access by Communication Client

Fault recording can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).

7.5.4.4 Access by Printer

The device can print fault recording, so that the operator can observe and save the current
operation condition. The access path is:

PCS-902S Line Distance Relay 7-7

Date: 2023-08-01
 7 System Functions

MainMenuPrintDisturb Records

7.6 Mode and Behaviour

The device supports five kinds of LD-level mode/behaviour defined in IEC 61850-7-4, including
"On", "Blocked", "Test", "Test/Blocked" and "Off". By the function, the device can realize the test,
blocking and other operations of all or several functions. The function block diagram is shown as
below.

xxx.Beh

Mod Out

In the above diagram, the prefix "xxx" represents the name of the module,
such as "LD0", "Prot", "Mea", etc.

The input signal "Mod" is the input command, and its values are "On", "Blocked", "Test",
"Test/Blocked" and "Off". The output signal "Out" is the output status signal to Beh components
of protection functions, control functions, process layer and station layer. Its values are "On",
"Blocked", "Test", "Test/Blocked" and "Off". According to IEC 61850 Ed2, the operation principle
of LD-level Mode/Behaviour are as follows.

LD0.Beh Prot.Beh

7
Mod Mod
On

MATRIX MATRIX
Blocked

Beh Out Beh Out Test

B&T

.. Off

.
Mea.Beh

Mod
On

MATRIX
Blocked

Beh Out Test

B&T

Off

Figure 7.6-1 Functional diagram of LD-level Mode/Behaviour

For different functions, the process modes of "Beh" signal are different.

1. Protection logic

7-8 PCS-902S Line Distance Relay

Date: 2023-08-01
-02-27
 7 System Functions

ON Blocked Test Blocked/Test OFF

Normal Normal Normal Normal Exit operation

2. Trip output

ON Blocked Test Blocked/Test OFF

Normal Blocking output Normal Blocking output Blocking output

3. GOOSE output

ON Blocked Test Blocked/Test OFF

The data quality is Set maintenance The data is normal, the quality flag is set No
Normal
normal quality flag as "maintenance" output

4. Station–layer signals

ON Blocked Test Blocked/Test OFF

MMS: processing Set maintenance quality MMS: processing MMS: processing
Normal
quality flag quality quality

5. Control functions

ON Blocked Test Blocked/Test OFF

Blocking output, return Handle according to Blocking output, return No
Normal
error quality error response

6. GOOSE input

ON Blocked Test Blocked/Test OFF

Normal Normal Normal Normal Normal

7. Binary input 7
ON Blocked Test Blocked/Test OFF
Normal Normal Normal Normal Normal

8. SV input

ON Blocked Test Blocked/Test OFF

Normal Normal Normal Normal Zero clearing

9. GOOSE analog input

ON Blocked Test Blocked/Test OFF

Normal Normal Normal Normal Zero clearing

10. Conventional sampling

ON Blocked Test Blocked/Test OFF

Normal Normal Normal Normal Zero clearing

PCS-902S Line Distance Relay 7-9

Date: 2023-08-01
 7 System Functions

7.7 Maintenance State

The device provides maintenance state, i.e., the binary input [BI_Maintenance] is energized, which
is convenient for maintenance work. For adopting conventional CT/VT, binary inputs and binary
outputs, maintenance state has no influence on protection logics. For binary inputs and binary
outputs by GOOSE connections. During device maintenance, the object will send GOOSE
message with Test quality attribute. The Test quality attribute indicates to the receiver device that
the object received via a GOOSE message was created under test conditions and not operating
conditions. If the Test quality attribute received is different with the object's Test quality attribute,
binary inputs and binary outputs by GOOSE connections will be affected based on different types
of binary inputs and binary outputs. For SV (Sampling Value) message, if the Test quality attribute
received is different with the object's Test quality attribute, the relevant protection functions will be
blocked.

For IEC60870-5-103 protocol, only the messages in link layer maintained, service messages in the
application layer which is uploaded automatically are blocked, and service messages in the
application layer which is issued by the client are rejected. For IEC61850 protocol, all Test quality
attribute set as "1". For DNP3.0 and ModBus protocol, they are not affected.

7.8 Communication Test

The device provides Test Mode to allow all protection elements, supervision events and binary
events to fulfill communication test, but to avoid the output contacts to close. During communication
test, protection functions are not affected, the signals generated by communication test are
recorded in relevant reports, and event recording and fault recording will not stop recording
7 disturbance information. The alarm signal "Alm_CommTest" will be issued to indicate the operator
when activating Test Mode and exiting Test Mode.

Communication test can be gained via local HMI and the virtual HMI, the corresponding content
can be viewed through the following menu paths:

⚫ Events Simulation

Main MenuTestDevice TestDisturb Events

Main MenuTestDevice TestSuperv Events

Main MenuTestDevice TestIO Events

⚫ Forced Measurements

Main MenuTestDevice TestMeasurements

7-10 PCS-902S Line Distance Relay

Date: 2023-08-01
-02-27
 7 System Functions

Forced measurement ONLY affects the values modified and transmitted to

station control or control center. Primary circuit, secondary circuit and device
local logic will not be influenced. Forced value will remain during the test
until the exit of this menu.

If no input operation is carried out within 60s, this test will exit and return to
the previous menu automatically.

7.9 Output Test

The device provides Output Test Mode to test all outputs. Through this mode, there will be real
operations, such as contact closing and GOOSE output value change, triggered by the device to
test output circuits and links. So, protection functions outputs and the connecting primary
equipment are affected. The output signals generated by output test are not recorded, while the
entering and exiting of output test mode will be recorded in Superv Events. During the output test,
the protection functions will not stop, nor will the all recording functions.

Output test can be gained via the local LCD or virtual HMI of a debugging PC, the corresponding
content can be viewed through the following menu paths:

⚫ Contacts Outputs

Main MenuTestDevice TestContact Outputs

⚫ GOOSE Outputs

Main MenuTestDevice TestGOOSE Outputs

Dismantle the wiring connection if any influence on relevant primary

7
equipment is undesired. The output test will cause operation of relay
contacts through secondary circuit and GOOSE link.

7.10 Target Reset

The device provides target reset which can be used to reset local signals (including magnetic
latching output relays), latched LEDs, and confirm pop-up windows of reports. The function does
not affect the protection logic and communication function. There are several ways to reset.

1. Reset via local HMI

⚫ Access menu path: MainMenuLocal CmdReset Target

⚫ Press the command push-button "ESC"+"ENT" on operation panel of the device under
main interface

⚫ Press the command push-button "TARGET RESET" on operation panel of the device

2. Reset via virtual HMI

PCS-902S Line Distance Relay 7-11

Date: 2023-08-01
 7 System Functions

Access menu path: MainMenuLocal CmdReset Target

3. Reset via binary input

Energize the binary input "BI_RstTarg"

4. Reset via IEC60870-5-103

Use ASDU20, INF19 of IEC60870-5-103 protocol

5. Reset via remote control

Use standard remote service of corresponding protocol

7.11 Switch Setting Groups

For different applications users can save the respective function settings in so-called settings
groups, and enable them quickly if necessary. Up to 20 different settings groups can be saved in
the device. In the process, only one settings group is active at any given time. During operation,
the operator can switch between setting groups.

The device will be temporarily blocked during switching setting groups. During temporary device
blocking, the device will loss protection functions and communication functions. Alarm signals
"Fail_Device" and "Alm_Device" will be issued. There are several ways to switch setting groups.

1. Switch via local HMI

⚫ Access menu path: MainMenuSettingGlobal SettingsSystem Settings, change

the value of the setting [Active_Grp]

7 ⚫ Press the command push-button "MENU" under main interface (password is required)

2. Switch via virtual HMI

Access menu path: MainMenuSettingGlobal SettingsSystem Settings, modify the

setting [Active_Grp]

3. Switch via communication client

The communication protocols IEC60870-5-103 or IEC 61850 can be used for switching the
setting groups via a communication connection.

⚫ Use "General Service" of IEC60870-5-103 protocol to modify the setting [Active_Grp]

⚫ Use "SelectActiveSG" of IEC61850 protocol to switch setting groups.

4. Switch via binary signals

The device also provides an available function by configuring associated binary signals via
PCS-Studio to switch setting group, which can be external binary inputs or internal logic signals.
By default, no binary signals are configured, so the function is invalid. (The specified
configuration method can refer to "PCS-902S Line Distance Relay Application Manual")

7-12 PCS-902S Line Distance Relay

Date: 2023-08-01
-02-27
 7 System Functions

Each input signal is coded with a sequence number that corresponds to a setting group. When
the associated input signal changes, the device scans all input signals and selects the input
with the smallest sequence number as the valid input. The device switches to the setting range
corresponding to the input signal. The device can switch up to 20 setting groups.

PCS-902S Line Distance Relay 7-13

Date: 2023-08-01
 7 System Functions

7-14 PCS-902S Line Distance Relay

Date: 2023-08-01
-02-27
 8 Hardware

8 Hardware

Table of Contents

8.1 Overview........................................................................................................... 8-1

8.2 Typical Wiring .................................................................................................. 8-4
8.3 CT Requirement ............................................................................................... 8-9
8.3.1 Current Transformer Classification ...................................................................................... 8-9

8.3.2 Phase Overcurrent Protection and Earth Fault Protection ................................................ 8-11

8.3.3 Line Distance Protection .................................................................................................... 8-12

8.4 Plug-in Module Description .......................................................................... 8-14

8.4.1 Human-machine Interface Module (NR6855/NR6856)...................................................... 8-14

8.4.2 Power Supply Module (NR6305/NR6310/NR6311) ........................................................... 8-14

8.4.3 CPU Module (NR6106) ...................................................................................................... 8-20

8.4.4 NET-DSP Module (NR6113)............................................................................................... 8-31

8.4.5 Analogue Input Module (NR6641) ...................................................................................... 8-33

8.4.6 Binary Input Module (NR6601/NR6604/NR6610/NR6611)................................................ 8-40

8.4.7 Binary Output Module (NR6651/NR6652/NR6660/NR6663) ............................................ 8-49

8.4.8 Binary Input and Output Module (NR6661) ....................................................................... 8-58

List of Figures 8
Figure 8.1-1 Hardware diagram.................................................................................................. 8-1

Figure 8.1-2 Front view of PCS-902S......................................................................................... 8-3

Figure 8.1-3 Typical rear view of PCS-902S with pin ferrule ................................................... 8-3

Figure 8.1-4 Typical rear view of PCS-902S with ring ferrule ................................................. 8-3

Figure 8.2-1 Typical hardware configuration with pin ferrule (6U, 1/1) ..................................... 8-4

Figure 8.2-2 Typical hardware configuration with pin ferrule (6U, 1/2) ..................................... 8-5

Figure 8.2-3 Typical wiring with pin ferrule................................................................................. 8-6

Figure 8.2-4 Typical hardware configuration with ring ferrule (6U, 1/1).................................... 8-7

Figure 8.2-5Typical hardware configuration with ring ferrule (6U, 1/2)..................................... 8-8

PCS-902S Line Distance Relay 8-a

Date: 2023-08-01
 8 Hardware

Figure 8.2-6 Typical wiring with ring ferrule ............................................................................... 8-9

Figure 8.4-1 View of power supply module ............................................................................... 8-15

Figure 8.4-2 View of CPU module .............................................................................................. 8-22

Figure 8.4-3 Connection of communication terminal ............................................................ 8-31

Figure 8.4-4 Jumpers of printer/RS-485 port .......................................................................... 8-31

Figure 8.4-5 View of NET-DSP module ...................................................................................... 8-32

Figure 8.4-6 Schematic diagram of CT circuit automatically closed ................................... 8-33

Figure 8.4-7 View of analogue input module ............................................................................. 8-34

Figure 8.4-8 Terminal definition of analogue input module .................................................. 8-35

Figure 8.4-9 Current connection examples ............................................................................ 8-37

Figure 8.4-10 Voltage connection examples .......................................................................... 8-39

Figure 8.4-11 Voltage dependence for binary inputs (default set) ....................................... 8-40

Figure 8.4-12 View of binary input module (NR6601A) ......................................................... 8-41

Figure 8.4-13 View of binary input module (NR6604A) ......................................................... 8-43

Figure 8.4-14 View of binary input module (NR6610A/NR6610B) ........................................ 8-45

Figure 8.4-15 View of binary input module (NR6611A).......................................................... 8-47

Figure 8.4-16 View of binary output module (NR6651A) ....................................................... 8-49

Figure 8.4-17 View of binary output module (NR6651B) ....................................................... 8-51

Figure 8.4-18 View of binary output module (NR6652A) ....................................................... 8-53

Figure 8.4-19 View of binary output module (NR6660A) ....................................................... 8-55

8 Figure 8.4-20 View of binary output module (NR6663A) ....................................................... 8-57

Figure 8.4-21 View of binary input and output module (NR6661A)...................................... 8-59

List of Tables

Table 8.3-1 The transformation of e.m.f ................................................................................... 8-10

Table 8.4-1 Terminal definition and description of power supply module ............................... 8-15

Table 8.4-2 Terminal definition and description of power supply module ............................... 8-17

Table 8.4-2 Terminal definition and description of power supply module ............................... 8-18

Table 8.4-3 Terminal definition and description of power supply module ............................... 8-19

Table 8.4-4 Interface and terminal definition of CPU module ................................................... 8-22

8-b PCS-902S Line Distance Relay

Date: 2023-08-01
 8 Hardware

Table 8.4-5 Pilot channel interface ............................................................................................. 8-30

Table 8.4-6 Configuration and terminal definition of NET-DSP module ................................... 8-32

Table 8.4-7 Terminal definition and description of binary input module ................................. 8-41

Table 8.4-8 Terminal definition and description of binary input module ................................. 8-43

Table 8.4-9 Terminal definition and description of binary input module ................................. 8-45

Table 8.4-10 Terminal definition and description of binary input module ............................... 8-47

Table 8.4-11 Terminal definition and description of binary output module ............................. 8-50

Table 8.4-12 Terminal definition and description of binary output module ............................. 8-51

Table 8.4-13 Terminal definition and description of binary output module ............................. 8-53

Table 8.4-14 Terminal definition and description of binary output module ............................. 8-55

Table 8.4-15 Terminal definition and description of binary output module ............................. 8-57

Table 8.4-16 Terminal definition and description of binary input and output module ............ 8-59

PCS-902S Line Distance Relay 8-c

Date: 2023-08-01
 8 Hardware

8-d PCS-902S Line Distance Relay

Date: 2023-08-01
 8 Hardware

8.1 Overview

The modular design of this device allows this device to be easily upgraded or repaired by a qualified
service person. The faceplate is hinged to allow easy access to the configurable modules, and
back-plugging structure design makes it easy to repair or replace any module.

This device adopts one 32-bit ARM core in the CPU chip as control core for management and
monitoring function, and adopts another 32-bit ARM core in the CPU chip for all the protection
calculation. The parallel processing of sampled data can be realized in each sampling interval to
ensure ultrahigh reliability and safety of the device.

This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in anti-
interference. See Figure 8.1-1 for the hardware diagram.

External
Binary Input

Conventional CT/VT A/D

Output
ARM1
Relay
A/D

Pickup
ECVT Relay

ETHERNET
+E
LCD
Clock SYN
Power
Uaux LED ARM2
Supply
RJ45

Keypad
PRINT

Figure 8.1-1 Hardware diagram

8
The working process of the device is as shown in above figure: the currents and voltages from
conventional CT/VT are converted into small voltage signal and sent to ARM1 core after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signals are sent
to the device without small signal and A/D conversion). The ARM1 core carries out fault detector,
protection logic calculation, tripping output, and the ARM2 core performs SOE (sequence of event)
record, waveform recording, printing, communication between the device and SAS and
communication between HMI and CPU. When the fault detector detects a fault and picks up, the
positive power supply for output relay is provided.

The items can be flexibly configured depending on the situations like sampling method of the device
(conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary output or
GOOSE binary output). The configurations for PCS S series based on microcomputer are classified
into standard and optional modules.

PCS-902S Line Distance Relay 8-1

Date: 2023-08-01
 8 Hardware

Table 8.1-1 Module configuration of this device

Module ID Module description Remark

NR6855/NR6856 Human machine interface module (HMI module) Mandatory
NR6305/NR6310/NR6311 Power supply module (PWR module) Mandatory
NR6106 Main CPU module (CPU module) Mandatory
GOOSE & SV communication, and PRP/HSR network
NR6113 Optional
module (NET-DSP module)
NR6641 Analogue input module (AI module) Mandatory
NR6601/NR6604/NR6610/NR6611 Binary input module (BI module) Optional
NR6651/NR6652/NR6660/NR6663 Binary output module (BO module) Optional
NR6661 Binary input and output module (IO module) Optional

⚫ HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.

⚫ PWR module converts AC100V/110V/115V/120V/127V/220V/230V/240V/250V or

DC24V/30V/48V/60V/110V/125V/220V/250V into various DC voltage levels for modules of the
device.

⚫ CPU module provides functions like communication with SAS, event record, setting
management etc., and performs filtering, sampling, protection calculation, fault detector
calculation, and performs information exchange with the remote device through a dedicated
optical fibre channel or multiplex optical fibre channel.

⚫ NET-DSP module provides 100Mbit/s & 1000Mbit/s optical fibre interface (LC-connector) for
GOOSE & SV communication, and 1000Mbit/s optical fibre interface (LC-connector) for
PRP/HSR network communication.

⚫ AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.

8 ⚫ BI module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V~250V (configurable).

⚫ BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.

⚫ IO module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V~250V (configurable), and provides tripping & signal output contacts.

PCS-902S is made of a 6U height 19” chassis. Components mounted on its front include a 320×240
dot matrix LCD, a 9-button keypad, four programmable buttons, 20 LED indicators and a multiplex
RJ45 port. A monolithic micro controller is installed in the device for these functions. Following
figures show front and rear views of this device respectively.

8-2 PCS-902S Line Distance Relay

Date: 2023-08-01
 8 Hardware

Figure 8.1-2 Front view of PCS-902S

Figure 8.1-3 Typical rear view of PCS-902S with pin ferrule

Figure 8.1-4 Typical rear view of PCS-902S with ring ferrule

PCS-902S Line Distance Relay 8-3

Date: 2023-08-01
 PCS-902S Line Distance Relay
B01 B02 & B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 P1
NR6106AA NR6641-6I6U Option NR6610A NR6660A Option Option Option Option Option Option Option Option NR6310A
01 Ia1 Ia1n 02 BI_01 01 01 BI_01+ 01
BO1
BI_02 02 02 BI_01- 02
03 Ib1 Ib1n 04 BI_03 03 03 BI_02+ 03
BO2
05 Ic1 Ic1n 06 BI_04 04 04 BI_02- 04
NET BI_05 05 05 BI_COM 05
BO3

Figure 8.2-1 Typical hardware configuration with pin ferrule (6U, 1/1)
07 Ia2 Ia2n 08 BI_06 06 06 BI_03 06
LC
09 Ib2 Ib2n 10 BI_07 07 07 BI_04 07
BO4
LC BI_08 08 08 BI_05 08
11 Ic2 Ic2n 12 BI_09 09 09 BI_06 09
BO5
13 UB2 UB2n 14 BI_10 10 10 BI_07 10
BI_11 11 11 BI_08 11
15 UL1 UL1n 16 BO6
BI_12 12 12 BI_09 12
17 UB1 UB1n 18 BI_13 13 13 13
BO7 BO_01
BI_14 14 14 14
19 Ua Uan 20 BI_15 15 15 15

Date: 2023-08-01
BO8 BO_02
21 Ub Ubn 22 BI_16 16 16 16
17 17 17
23 Uc Ucn 24 BI_COM BO9 BO_03
18 18 18
19
BI_17 19 19 BO_04
B10 20
BI_18 20 20
21
BI_19 21 21 BO_05
B11 22
BI_20 22 22
BI_21 23 23 23
B12 BO_Fail
01 1A BI_22 24 24 24
02 1B
BI_23 25 25 PWR+ 25
03 SGND B13
04 2A
BI_24 26 26 PWR- 26
BI_25 27 27
8.2 Typical Wiring

05 2B
B14
06 SGND BI_26 28 28
07 SYN+
BI_27 29 29
08 SYN- B15
09 SGND
BI_28 30 30
10 SYN-TTL BI_29 31 BO16-COM 31
BI_30 32 BO16-NO 32
BI_31 33 BO16-NC 33
8 Hardware

CONSOLE
BI_32 34 BO17-COM 34
35 BO17-NO 35
BI_COM
36 BO17-NC 36 Ground

8-4
8
 8
8 Hardware

8-5
B01 B02 & B03 B04 B05 B06 P1
NR6106AA NR6641-6I6U Option NR6610A NR6660A NR6310A
01 Ia1 Ia1n 02 BI_01 01 01 BI_01+ 01
BO1
BI_02 02 02 BI_01- 02
03 Ib1 Ib1n 04 BI_03 03 03 BI_02+ 03
BO2
05 Ic1 Ic1n 06 BI_04 04 04 BI_02- 04
NET BI_05 05 05 BI_COM 05
07 Ia2 Ia2n 08 BO3

Figure 8.2-2 Typical hardware configuration with pin ferrule (6U, 1/2)
LC BI_06 06 06 BI_03 06
09 Ib2 Ib2n 10 BI_07 07 07 BI_04 07
BO4
LC BI_08 08 08 BI_05 08
11 Ic2 Ic2n 12 BI_09 09 09 BI_06 09
BO5
13 UB2 UB2n 14 BI_10 10 10 BI_07 10
BI_11 11 11 BI_08 11
15 UL1 UL1n 16 BO6
BI_12 12 12 BI_09 12
17 UB1 UB1n 18 BI_13 13 13 13
BO7 BO_01

The wiring is given based on above hardware configuration

BI_14 14 14 14
19 Ua Uan 20 BI_15 15 15 15

Date: 2023-08-01
BO8 BO_02
21 Ub Ubn 22 BI_16 16 16 16
17 17 17
23 Uc Ucn 24 BI_COM BO9 BO_03
18 18 18
19
BI_17 19 19 BO_04
BO10 20
BI_18 20 20
21
BI_19 21 21 BO_05
BO11 22
BI_20 22 22
BI_21 23 23 23
BO12 BO_Fail
01 1A BI_22 24 24 24
02 1B
BI_23 25 25 PWR+ 25
03 SGND BO13
04 2A
BI_24 26 26 PWR- 26
05 2B BI_25 27 27
BO14

PCS-902S Line Distance Relay

06 SGND BI_26 28 28
07 SYN+
BI_27 29 29
08 SYN- BO15
09 SGND
BI_28 30 30
10 SYN-TTL BI_29 31 BO16-COM 31
BI_30 32 BO16-NO 32
BI_31 33 BO16-NC 33
CONSOLE
BI_32 34 BO17-COM 34
35 BO17-NO 35
BI_COM
36 BO17-NC 36 Ground
 8 Hardware

0201
0202

0204
0205

0207
0208

0210

0216

0219

0222
0203

0206

0209

0211
0212

0215

0217
0218

0220
0221

0223
0224
0213
0214
Ia1 Ib1 Ic1 Ia2 Ib2 Ic2 UB2 UL1 UB1 Ua Ub Uc

BI_01 + 0501

Ethernet (RJ 45 and LC-

Connector) BI_02 + 0502

To SCADA

…
BI_16 + 0516

0517 -
0518 -

BI_17 + 0519

BI_18 + 0520

…
BI_32 + 0534
1A 0101
COM

1B 0102 0535 -
SGND 0103 0536 -
cable with single point earthing

BI_01 + P101
To the screen of other coaxial

2A 0104
COM

2B 0105 P102 -
SGND 0106
BI_02 + P103
SYN+ 0107
Clock SYN

SYN- 0108 P104 -

SGND 0109 P105 -
TTL 0110 BI_03 + P106

Console
BI_04 + P107
0601
0602 BO_01
…

0603
BO_02 BI_09 + P112
0604

8 P113
…

0617 BO_01
BO_09 P114
0618
P115
0619 BO_02 P116
0620 BO_10
…

P121
0621 BO_05
BO_11 P122
0622
P123
…

0631 BO_Fail P124

0632 BO_16 P125 PWR+
BO_16 Power External DC power
0633
Supply P126 supply
0634 PWR-

0635 BO_17

0636 BO_17
Grounding Bus

Figure 8.2-3 Typical wiring with pin ferrule

8-6 PCS-902S Line Distance Relay

Date: 2023-08-01
 8
8 Hardware

8-7
B01 B02 & B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 P1

Figure 8.2-4 Typical hardware configuration with ring ferrule (6U, 1/1)
NR6106AA NR6641-6I6U Option NR6601A NR6651A Option Option Option Option Option Option Option Option NR6305A
01 Ia1 Ia1n 02 01 BI_01 BI_02 02 01 BO_01 02 01 BI_01+ BI_01- 02
03 Ib1 Ib1n 04 03 BI_03 BI_04 04 03 BO_02 04 03 BI_02+ BI_02- 04
NET 05 Ic1 Ic1n 06 05 BI_05 BI_06 06 05 BO_03 06 05 BI_COM BI_03 06
LC 07 Ia2 Ia2n 08 07 BI_07 BI_08 08 07 BO_04 08 07 BI_04 BI_05 08
LC
09 Ib2 Ib2n 10 09 BI_09 BI_10 10 09 BO_05 10 09 BI_06 BI_07 10
11 Ic2 Ic1n 12 11 BI_11 BI_02 12 11 BO_06 12 11 BI_08 BI_09 12

Date: 2023-08-01
13 UB2 UB2n 14 13 BI_13 BI_02 14 13 BO_07 14 13 BO_01 14
15 UL1 UL1n 16 15 BI_15 BI_02 16 15 BO_08 16 15 BO_02 16
17 UB1 UB1n 18 17 BI_17 BI_02 18 17 BO_09 18 17 BO_03 18
01 1A 19 Ua Uan 20 19 BI_19 BI_02 20 19 BO_10 20 19 BO_04 20
02 1B
03 SG ND 21 Ub Ubn 22 21 BI_21 BI_02 22 21 BO_11 22 21 BO_05 22
04 2A
23 Uc Ucn 24 23 BI_23 BI_24 24 23 BO_12 24 23 BO_Fail 24
05 2B
06 SG ND
25 BI_25 BI_COM 26 25 BO_13 26 25 PWR+ PWR- 26
07 SYN+
08 SYN-
09 SGND
10 SYN-TTL

PCS-902S Line Distance Relay

CONSOLE
Ground
 PCS-902S Line Distance Relay
B01 B02 & B03 B04 B05 B06 P1
NR6106AA NR6641-6I6U Option NR6601A NR6651A NR6305A
01 Ia1 Ia1n 02 01 BI_01 BI_02 02 01 BO_01 02 01 BI_01+ BI_01- 02

Figure 8.2-5Typical hardware configuration with ring ferrule (6U, 1/2)

03 Ib1 Ib1n 04 03 BI_03 BI_04 04 03 BO_02 04 03 BI_02+ BI_02- 04
NET 05 Ic1 Ic1n 06 05 BI_05 BI_06 06 05 BO_03 06 05 BI_COM BI_03 06
LC 07 Ia2 Ia2n 08 07 BI_07 BI_08 08 07 BO_04 08 07 BI_04 BI_05 08
LC
09 Ib2 Ib2n 10 09 BI_09 BI_10 10 09 BO_05 10 09 BI_06 BI_07 10
11 Ic2 Ic1n 12 11 BI_11 BI_02 12 11 BO_06 12 11 BI_08 BI_09 12

Date: 2023-08-01
13 UB2 UB2n 14 13 BI_13 BI_02 14 13 BO_07 14 13 BO_01 14
15 UL1 UL1n 16 15 BI_15 BI_02 16 15 BO_08 16 15 BO_02 16
17 UB1 UB1n 18 17 BI_17 BI_02 18 17 BO_09 18 17 BO_03 18
01 1A 19 Ua Uan 20 19 BI_19 BI_02 20 19 BO_10 20 19 BO_04 20
02 1B
03 SGND 21 Ub Ubn 22 21 BI_21 BI_02 22 21 BO_11 22 21 BO_05 22
04 2A
23 Uc Ucn 24 23 BI_23 BI_24 24 23 BO_12 24 23 BO_Fail 24
05 2B
06 SGND
25 BI_25 BI_COM 26 25 BO_13 26 25 PWR+ PWR- 26
07 SYN+
08 SYN-
09 SG ND
10 SYN-TTL
CONSOLE
Ground
8 Hardware

8-8
8
 8 Hardware

The wiring is given based on above hardware configuration

0201
0202

0204
0205

0207
0208

0210

0216

0219

0222
0203

0206

0209

0211
0212

0215

0217
0218

0220
0221

0223
0224
0213
0214
Ia1 Ib1 Ic1 Ia2 Ib2 Ic2 UB2 UL1 UB1 Ua Ub Uc

BI_01 + 0501
Ethernet (RJ 45 and LC-
Connector)

BI_02 + 0502

To SCADA

…
BI_25 + 0525

0526 -

BI_01 + P101

P102 -

BI_02 + P103

P104 -
P105 -

1A 0101 BI_03 + P106

COM

1B 0102
SGND 0103 BI_04 + P107
cable with single point earthing
To the screen of other coaxial

2A 0104
COM

2B 0105
SGND 0106 BI_09 + P112

SYN+ 0107 P113

Clock SYN

SYN- 0108 BO_01 P114

SGND 0109 P115
TTL 0110 BO_02 P116
…

Console P121
BO_05 P122
0601 P123
0602 BO_01 BO_Fail P124
0603
0604 BO_02 P125 PWR+
8
Power External DC power
…

0625 Supply P126 supply

PWR-
0626 BO_13

Grounding Bus

Figure 8.2-6 Typical wiring with ring ferrule

8.3 CT Requirement

8.3.1 Current Transformer Classification

There are several different ways to specify CTs. Conventional magnetic core CTs are usually
specified and manufactured according to some international or national standards, which specify
different protection classes as well. There are many different standards and a lot of classes but

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 8 Hardware

fundamentally there are three different types of CTs:

1. High remanence type CT

The high remanence type CT has no given limit for the remanent flux. Typical examples of high
remanence type CT are class P, PX, TPX according to IEC 60044.

2. Low remanence type CT

The low remanence type CT has a specified limit for the remanent flux, which does not exceed 10%
of the saturation flux. Typical examples of low remanence type CT are class PR according to IEC
60044-6 and class TPY according to IEC 60044-1.

3. Non remanence type CT

The non remanence type CT has practically negligible level of remanent flux. An example is class
TPZ according to IEC 60044-6.

The high remanence type CT may have large remanence, and the degree of CT saturation d will
be more serious when faulty aperiodic component and remanence are in the same direction. The
following check calculation of CT selection takes into account the maximum remanence of CT and
the maximum aperiodic component that may appear in the field.

Different types of current transformers adopt different methods to calculate equivalent

electromotive force (e.m.f). Although the definitions of the three methods are quite different, they
all define the secondary equivalent e.m.f under the limit conditions related to rated frequency.

⚫ Class P, PR

𝐸𝐴𝐿𝐹 = 𝐴𝐿𝐹 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑍𝑏 )

⚫ Class PX, PXR

𝐸𝑘 = 𝐾𝑋 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑅𝑏 )

⚫ Class TPX, TPY, TPZ

8 𝐸al = 𝐾𝑆𝑆𝐶 × 𝐾𝑡𝑑 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑅𝑏 )

The comparison of e.m.f among different types of CT is shown in Table 8.3-1.

Table 8.3-1 The transformation of e.m.f

Class P, PR Class PX, PXR Class TPX, TPY, TPZ

Class P, PR 𝐸ALF ≈ 𝐹 × 𝐸𝑘 𝐸ALF ≈ 𝐸al

𝐸𝐴𝐿𝐹 𝐸al
Class PX, PXR 𝐸𝑘 ≈ 𝐸𝑘 ≈
𝐹 𝐹

Class TPX, TPY, TPZ 𝐸al ≈ 𝐸𝐴𝐿𝐹 𝐸al ≈ 𝐹 × 𝐸𝑘

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 8 Hardware

The coefficient "F" depends on the characteristics of the core material, and
the actual value range is:

For the magnetic core without air gap, the coefficient "F" is between 1.2 and
1.3.

For the magnetic core with air gap, the coefficient "F" about 1.1.

The explanation of used abbreviations and symbols are:

𝐸al Secondary rated equivalent limiting e.m.f (V)

𝐸𝐴𝐿𝐹 Class P, PR CT secondary limiting e.m.f (V)

𝐸𝑘 Rated knee-point e.m.f (V)

ALF Accuracy limit factor

𝐼𝑠𝑟 Rated secondary CT current (A)

𝐾𝑆𝑆𝐶 Rated coefficient of symmetric short-circuit current

𝐾td Transient area coefficient

𝐾𝑋 Dimensioning factor

𝑅𝑏 Rated resitive load (Ω)

𝑆𝑟
𝑍𝑏 Rated load, including resitive load and inductive load (Ω), 𝑍𝑏 =
𝐼2𝑠𝑟

𝑆𝑟 Rated apparent power of secondary load (VA)

𝑅𝑐𝑡 Secondary resistance of the CT (Ω)

The CT requirements for the different protection functions below are specified. 8
8.3.2 Phase Overcurrent Protection and Earth Fault Protection

8.3.2.1 CT Requirement

CT saturation will cause a certain delay to the protective oprating, which is obvious for invser-time
overcurrent protection. When the maximum fault current is much larger than the setting, the delay
can be ignored. If the maximum fault current is slightly larger than the setting, the delay generated
at this time is equivalent to the primary time constant of the system. If there is a coordination
relationship between the upstream and the downstream, the influence of this delay should be
considered. Generally, the CT requirement is as follows:

𝐸sl ′ < 𝐸𝐴𝐿𝐹

𝐸sl ′ is required secondary e.m.f for the maximum expected fault current

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 8 Hardware

According to the operating characteristics, phase overcurrent protection and earth fault protection
are divided into the following two cases:

1. Instantaneous or definite-time phase overcurrent protection and earth fault protection

(𝑅𝑐𝑡 + 𝑅𝑏 ′)
𝐸sl ′ = 𝐼pc𝑓 × 𝐼𝑠𝑟 × Equation 8.3-1
𝐼𝑝𝑟

2. Inverse-time phase overcurrent protection and earth fault protection

𝐸sl ′ = 20𝐼set × (𝑅𝑐𝑡 + 𝑅𝑏 ′) Equation 8.3-2

For directional phase overcurrent protection and earth fault protection, low or non remanence type
CT should be selected as far as possible.

𝐼pc𝑓 Maximum fault current (A)

𝐼pr Rated primary CT current (A)

Actual secondary resistance burden (Ω)

𝑅𝑏 ′ = 𝑅𝑟 + 2𝑅𝐿
𝑅𝑏 ′
𝑅𝑟 : input impedance of phase current, taking 0.01Ω

𝑅𝐿 : resistance from the device to CT's single lead

𝐼set Iinverse-time reference current setting or 1.1 times maximum load current (A)

8.3.2.2 Calulation Example

CT type is 5P30 ("5P" indicates Accuracy Class, "30" indicates Overcurrent Accuracy Limit Factor),
and related parameters are as follows.

𝐼pr = 2000A, 𝐼𝑠𝑟 = 5A, 𝑅𝑐𝑡 = 1.0Ω, 𝑆𝑟 = 60VA, 𝐼pc𝑓 = 40000A, 𝑅𝐿 = 0.5Ω, 𝑅𝑟 = 0.01Ω
8
The system's primary time constant is 80ms.

60
𝐸𝐴𝐿𝐹 = 𝐴𝐿𝐹 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑍𝑏 ) = 30 × 5 × (1.0 + ) = 510𝑉
5×5

𝑅𝑐𝑡 + 𝑅𝑏 ′ 1.0 + (0.01 + 2 × 0.5)

𝐸sl′ = 𝐼pc𝑓 × 𝐼𝑠𝑟 × = 40000 × 5 × = 201𝑉
𝐼𝑝𝑟 2000

𝐸sl ′ < 𝐸𝐴𝐿𝐹

Hence, the CT can meet the requirement of definite-time phase overcurrent protection and earth
fault protection.

8.3.3 Line Distance Protection

For line distance protection, the CT requirement is as follows:

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 8 Hardware

𝐸sl ′ < 𝐸𝐴𝐿𝐹

𝐸sl ′ is required secondary e.m.f for the maximum expected fault current

According to the operating characteristics, line distance protection is divided into the following
cases:

(𝑅𝑐𝑡 + 𝑅𝑏 ′)
𝐸sl ′ = 𝛼 × 𝐼𝑘𝑚𝑎𝑥 × 𝐼𝑠𝑟 × Equation 8.3-3
𝐼𝑝𝑟

(𝑅𝑐𝑡 + 𝑅𝑏 ′)
𝐸sl ′ = 𝐾 × 𝐼𝑘𝑧𝑜𝑛𝑒1 × 𝐼𝑠𝑟 × Equation 8.3-4
𝐼𝑝𝑟

𝐼𝑘𝑧𝑜𝑛𝑒1 Maximum primary current for faults at the end of zone 1 reach (A).

This factor is a function of the primary time constant for the DC component in the fault current.

а=1.5, the primary time constant is less than 100ms

𝛼
а=2, the primary time constant is less than 150ms

a=3, the primary time constant is more than 150ms

A factor of the primary time constant for the DC component in the fault current for a fault at the
set reach of zone 1.
𝐾
k=4, the primary time constant is less than 50ms

k=5, the primary time constant is more than 50ms

8.3.3.1 Calulation Example

CT type is 5P30, and related parameters are as follows.

8
𝐼pr = 2000A, 𝐼𝑠𝑟 = 5A, 𝑅𝑐𝑡 = 1.0Ω, 𝑆𝑟 = 60VA, 𝐼𝑘𝑚𝑎𝑥 = 40000A, 𝐼𝑘𝑧𝑜𝑛𝑒1 = 10000A, 𝑅𝐿 = 0.5Ω,

𝑅𝑟 = 0.01Ω

Assumption: the setting of zone 1 of distance protection is 80% of the whole line, the time constant
Tc=80ms for the internal close-in faults, and the time constant Tc'=60ms for the faults at the end of
zone 1 reach.

60
𝐸𝐴𝐿𝐹 = 𝐴𝐿𝐹 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑍𝑏 ) = 30 × 5 × (1.0 + ) = 510V
5×5

Because the time constant Tc=80ms for the internal close-in faults, а=1.5.

(𝑅𝑐𝑡 + 𝑅𝑏 ′) 1.0 + (0.01 + 2 × 0.5)

𝐸sl ′ = 𝛼 × 𝐼𝑘𝑚𝑎𝑥 × 𝐼𝑠𝑟 × = 1.5 × 40000 × 5 × = 301.5V
𝐼𝑝𝑟 2000

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Date: 2023-08-01
 8 Hardware

Because the time constant Tc'=60ms for the faults at the end of zone 1 reach, k=5.

(𝑅𝑐𝑡 + 𝑅𝑏 ′) 1.0 + (0.01 + 2 × 0.5)

𝐸sl ′ = 𝐾 × 𝐼𝑘𝑧𝑜𝑛𝑒1 × 𝐼𝑠𝑟 × = 5 × 10000 × 5 × = 251.25V
𝐼𝑝𝑟 2000

max(𝐸sl′ ) = 301.5𝑉 < 𝐸𝐴𝐿𝐹 = 510𝑉

Hence, the CT can meet the requirement of line distance protection.

8.4 Plug-in Module Description

The device consists of power supply module (PWR), main CPU module (CPU), AI module, BI
module, BO plug-in module and NET-DSP plug-in module. Terminal definitions and application of
each plug-in module are introduced as follows.

8.4.1 Human-machine Interface Module (NR6855/NR6856)

The human machine interface (HMI) module is installed on the front panel of this device. It is used
to observe the running status and event information on the LCD, and configure the protection
settings and device operation mode. It can help the user to know the status of this device and
detailed event information easily, and provide convenient and friendly access interface for the user.

8.4.2 Power Supply Module (NR6305/NR6310/NR6311)

The power supply module is a DC/DC converter with electrical insulation between input and output.
It has an input voltage range as described in Chapter 2 Technical Data. The standardized output
voltages are +5Vdc and +12Vdc. The tolerances of the output voltages are continuously monitored.

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 8 Hardware

Figure 8.4-1 View of power supply module

The +5Vdc output provides power supply for all the electrical elements that need +5Vdc power
supply in this device. It is recommended to use an external miniature circuit breaker to control the
power on/off of the device.

Three types of power supply modules are provided: NR6305A, NR6305E, NR6310A and NR6311A.

⚫ NR6305A
8
The power supply module supports external power source whose voltage level is
AC100V/110V/115V/120V/127V/220V/230V/240V/250V or DC110V/125V/220V/250V, also
provides 9 binary inputs, 5 binary outputs and a device failure binary output. A 26-pin connector is
fixed on the power supply module. The terminal definition of the connector is described as below.

Table 8.4-1 Terminal definition and description of power supply module

Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-

03 BI_02+
The No.2 programmable binary input
04 BI_02-

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 8 Hardware

05 BI_COM The common negative connection of the BI_03 to BI_09

06 BI_03 The No.3 programmable binary input

07 BI_04 The No.4 programmable binary input

08 BI_05 The No.5 programmable binary input

09 BI_06 The No.6 programmable binary input

10 BI_07 The No.7 programmable binary input

11 BI_08 The No.8 programmable binary input

12 BI_09 The No.9 programmable binary input

13
BO_01 The No.1 programmable binary output
14

15
BO_02 The No.2 programmable binary output
16

17
BO_03 The No.3 programmable binary output
18

19
BO_04 The No.4 programmable binary output
20

21
BO_05 The No.5 programmable binary output
22

23
BO_Fail The device failure signal output

8 24

25 PWR+ DC power supply positive input

26 PWR- DC power supply negative input

Grounded connection of the power supply

⚫ NR6305E

The power supply module supports external power source whose voltage level is
DC48V/110V/220V, also provides 9 binary inputs, 4 binary outputs and a device failure binary
output. A 26-pin connector is fixed on the power supply module. The terminal definition of the
connector is described as below.

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 8 Hardware

Table 8.4-2 Terminal definition and description of power supply module

Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-

03 BI_02+
The No.2 programmable binary input
04 BI_02-

05 BI_COM The common negative connection of the BI_03 to BI_09

06 BI_03 The No.3 programmable binary input

07 BI_04 The No.4 programmable binary input

08 BI_05 The No.5 programmable binary input

09 BI_06 The No.6 programmable binary input

10 BI_07 The No.7 programmable binary input

11 BI_08 The No.8 programmable binary input

12 BI_09 The No.9 programmable binary input

13
BO_01 The No.1 programmable binary output
14

15
BO_02 The No.2 programmable binary output
16

17
BO_03 The No.3 programmable binary output
18
8
19
BO_04 The No.4 programmable binary output
20

21 Blank

22 Blank

23
BO_Fail The device failure signal output
24

25 PWR+ DC power supply positive input

26 PWR- DC power supply negative input

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 8 Hardware

Grounded connection of the power supply

⚫ NR6310A

The power supply module supports external power source whose voltage level is
AC100V/110V/115V/120V/127V/220V/230V/240V/250V or DC110V/125V/220V/250V, also
provides 9 binary inputs, 5 binary outputs and a device failure binary output. A 22-pin connector
and a 4-pin connector are fixed on the power supply module. The terminal definition of the
connector is described as below.

Table 8.4-3 Terminal definition and description of power supply module

Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-

03 BI_02+
The No.2 programmable binary input
04 BI_02-

05 BI_COM The common negative connection of the BI_03 to BI_09

06 BI_03 The No.3 programmable binary input

07 BI_04 The No.4 programmable binary input

08 BI_05 The No.5 programmable binary input

09 BI_06 The No.6 programmable binary input

10 BI_07 The No.7 programmable binary input

22-pin
11 BI_08 The No.8 programmable binary input

8 12 BI_09 The No.9 programmable binary input

13
BO_01 The No.1 programmable binary output
14

15
BO_02 The No.2 programmable binary output
16

17
BO_03 The No.3 programmable binary output
18

19
BO_04 The No.4 programmable binary output
20

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 8 Hardware

21
BO_05 The No.5 programmable binary output
22

23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input

26 PWR- DC power supply negative input

Grounded connection of the power supply

⚫ NR6311A

The power supply module supports external power source whose voltage level is
DC24V/30V/48V/60V, also provides 9 binary inputs, 5 binary outputs and a device failure binary
output. A 22-pin connector and a 4-pin connector are fixed on the power supply module. The
terminal definition of the connector is described as below.

Table 8.4-4 Terminal definition and description of power supply module

Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-

03 BI_02+
The No.2 programmable binary input
04 BI_02-

05 BI_COM The common negative connection of the BI_03 to BI_09

06 BI_03 The No.3 programmable binary input

07 BI_04 The No.4 programmable binary input

8
22-pin 08 BI_05 The No.5 programmable binary input

09 BI_06 The No.6 programmable binary input

10 BI_07 The No.7 programmable binary input

11 BI_08 The No.8 programmable binary input

12 BI_09 The No.9 programmable binary input

13
BO_01 The No.1 programmable binary output
14

15 BO_02 The No.2 programmable binary output

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 8 Hardware

16

17
BO_03 The No.3 programmable binary output
18

19
BO_04 The No.4 programmable binary output
20

21
BO_05 The No.5 programmable binary output
22

23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input

26 PWR- DC power supply negative input

Grounded connection of the power supply

The standard rated voltage of the PWR module is self-adaptive to

88~300Vdc or 80~275Vac. For a non-standard rated voltage power supply
module please specify when place order, and check if the rated voltage of
power supply module is the same as the voltage of power source before the
device being put into service.

The PWR module a grounding screw for device grounding. The grounding
screw shall be connected to grounding screw and then connected to the

8 earth copper bar of panel via dedicated grounding wire.

Effective grounding is the most important measure for a device to prevent

EMI, so effective grounding must be ensured before the device is put into
service.

8.4.3 CPU Module (NR6106)

The CPU module is the central part of this device, and contains a multi-core 32-bit powerful
processor and some necessary electronic elements. This powerful processor performs all of the
functions for this device: protection function, communication function, human-machine interface
function and so on. There are several A/D conversion circuits on this module, which are used to
convert the AC analogue signals to corresponding DC signals for fulfilling the demand of the
electrical level standard. A high-accuracy clock chip is contained in this module, it provides accurate
current time for this device.

The CPU module uses the internal bus to receive the data from other modules of the device. It

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 8 Hardware

comprises 100BaseT Ethernet interfaces, RS-485 communication interfaces, PPS/IRIG-B

differential time synchronization interface and RS-232 printing interface, and supports independent
networking mode and mixed networking mode based on MMS/GOOSE/SV. By the settings
[B01.Grp01.Opt_NetMode] and [B01.Grp02.Opt_NetMode], the network mode of the first group
ports (port 1 & port 2) can be set as "Normal", "PRP", "HSR" or "Bond" and the network mode of
the second group of ports (port 3 & port 4) can be set as "Normal", "PRP", "HSR", "RSTP" or
"Bond" in station level. Four Ethernet interfaces in CPU module support ARP binding function
through the setting [En_ARP_Bind].

The device provides three menus, "Create ARP Bind", "Clear ARP Bind" and "ARP Bind Info",
to creat, clear and display ARP binding mapping information.

The main functional details of the CPU module are listed as below:

⚫ Protection calculation and logical judgment function

The CPU module can calculate protective elements (such as overcurrent element) on the basis
of the analogue sampled values (voltages and currents) and binary inputs, then it does logical
judgment function and decides whether the device needs to trip or close.

⚫ Communication function

The CPU module can effectively manage all communication procedures, and reliably send out
some useful information through its various communication interfaces. These interfaces are
used to communicate with a SAS or a RTU. It also can communicate with the human machine
interface module. If an event occurs (such as SOE, protective tripping event etc.), this module
will send out the relevant event information through these interfaces, and make it be easily
observed by the user.

⚫ Auxiliary calculation

Based on the voltage and current inputs, the CPU module also can calculate out the metering
values, such as active power, reactive power and power factor etc. All these values can be
sent to a SAS or a RTU through the communication interfaces.

⚫ Human-machine interface function

8
This module can respond the commands from the keypad of this device and show the results
on the LCD and LED indicators of this device. It also can show the operation situation and
event information for the users through the LCD and LED indicators.

⚫ Time synchronization

This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B signal.
Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on the IRIG-
B signal, this module can synchronize local clock with the standard clock.

⚫ Optical fiber channel

This module can exchange information between the device at local end and the device at the

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 8 Hardware

opposite end through a dedicated optical fibre channel or multiplex channel. It transmits and
receives optical signal using FC/PC or ST optical connector.

The routine of both directions shall be same to each other, so the time delays of both directions
are the same. The maximum one-way channel propagation delay shall be less than 15ms.

There are several types of CPU modules for different applications, and these modules with various
combinations of memory and interface are available as shown in the table below.

8 Figure 8.4-2 View of CPU module

Do NOT look into the end of an optical fiber connected to an optical port.

Do NOT look into an optical port/connector.

A direct sight to laser light may cause temporary or permanent blindness.

The configuration and terminal definition of the CPU modules are listed in following table

Table 8.4-5 Interface and terminal definition of CPU module

Module ID Memory Interface Terminal No. Usage Physical Layer

NR6106AA 1G DDR 2 RJ45 Ethernet communication Twisted pair wire or

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Ethernet optic fibre

2 SFP Ethernet

(LC connector)

01 A

RS-485 02 B To SCADA

03 SGND

04 A

RS-485 05 B To SCADA or printer

06 SGND
Twisted pair wire
07 SYN+

RS-485 08 SYN- To clock

09 SGND synchronization

TTL 10 TTL

1 RJ45
For debugging
Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

(LC connector)

8
Optical channel for pilot Optical fiber (single-
2 FC connector
protection mode)

01 A
NR6106AB 1G DDR
RS-485 02 B To SCADA

03 SGND

04 A
Twisted pair wire
RS-485 05 B To SCADA or printer

06 SGND

07 SYN+ To clock
RS-485
08 SYN- synchronization

PCS-902S Line Distance Relay 8-23

Date: 2023-08-01
 8 Hardware

09 SGND

TTL 10 TTL

1 RJ45
For debugging
Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

(LC connector)

Optical channel for pilot Optical fiber (single-

2 FC connector
protection mode)

01 A

RS-485 02 B To SCADA

03 SGND
NR6106AC 1G DDR
04 A

RS-485 05 B To SCADA or printer

06 SGND
Twisted pair wire
07 SYN+

RS-485 08 SYN- To clock

09 SGND synchronization

8 TTL 10 TTL

1 RJ45
For debugging
Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

NR6106AD 1G DDR (LC connector)

Optical channel for pilot Optical fiber (multi-

2 ST connector
protection mode)

RS-485 01 A To SCADA Twisted pair wire

8-24 PCS-902S Line Distance Relay

Date: 2023-08-01
 8 Hardware

02 B

03 SGND

04 A

RS-485 05 B To SCADA or printer

06 SGND

07 SYN+

RS-485 08 SYN- To clock

09 SGND synchronization

TTL 10 TTL

1 RJ45
For debugging
Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

(LC connector)

Optical channel for pilot Optical fiber (single-

2 FC connector
protection mode)

01 A

NR6106AF 1G DDR RS-485 02 B To SCADA

03 SGND
Twisted pair wire 8
04 A

RS-485 05 B To SCADA or printer

06 SGND

1 BNC To clock synchronization Coaxial cable

1 RJ45
For debugging Twisted pair wire
Ethernet

2 RJ45
Twisted pair wire or
NR6106AG 1G DDR Ethernet Ethernet communication
optic fibre
2 SFP Ethernet

PCS-902S Line Distance Relay 8-25

Date: 2023-08-01
 8 Hardware

(LC connector)

Optical channel for pilot Optical fiber (single-

2 FC connector
protection mode)

01 A

RS-485 02 B To SCADA

03 SGND
Twisted pair wire
04 A

RS-485 05 B To SCADA or printer

06 SGND

1 BNC To clock synchronization Coaxial cable

1 RJ45
For debugging Twisted pair wire
Ethernet

4 SFP Ethernet Twisted pair wire or

Ethernet communication
(LC connector) optic fibre

Optical channel for pilot Optical fiber (single-

2 FC connector
protection mode)

01 A

RS-485 02 B To SCADA

03 SGND

8 NR6106AK 1G DDR
04 A

RS-485 05 B To SCADA or printer

06 SGND
Twisted pair wire
07 SYN+

RS-485 08 SYN- To clock

09 SGND synchronization

TTL 10 TTL

1 RJ45
For debugging
Ethernet

NR6106AL 1G DDR 4 SFP Ethernet Ethernet communication Twisted pair wire or

8-26 PCS-902S Line Distance Relay

Date: 2023-08-01
 8 Hardware

(LC connector) optic fibre

Optical channel for pilot Optical fiber (single-

2 FC connector
protection mode)

01 A

RS-485 02 B To SCADA

03 SGND
Twisted pair wire
04 A

RS-485 05 B To SCADA or printer

06 SGND

1 BNC To clock synchronization Coaxial cable

1 RJ45
For debugging Twisted pair wire
Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

(LC connector)

Optical channel for pilot Optical fiber (single-

1 FC connector
protection mode)

Optical channel for pilot Optical fiber (multi-

1 ST connector
protection mode)
8
NR6106AM 1G DDR 01 A

RS-485 02 B To SCADA

03 SGND
Twisted pair wire
04 A

RS-485 05 B To SCADA or printer

06 SGND

1 BNC To clock synchronization Coaxial cable

1 RJ45
For debugging Twisted pair wire
Ethernet

PCS-902S Line Distance Relay 8-27

Date: 2023-08-01
 8 Hardware

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

(LC connector)

Optical channel for pilot Optical fiber (single-

1 FC connector
protection mode)

Optical channel for pilot Optical fiber (multi-

1 ST connector
protection mode)

NR6106AN 1G DDR 01 A

RS-485 02 B To SCADA

03 SGND
Twisted pair wire
04 A

RS-485 05 B To SCADA or printer

06 SGND

1 BNC To clock synchronization Coaxial cable

1 RJ45
For debugging Twisted pair wire
Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre
8
(LC connector)

01 A

RS-485 02 B To SCADA
NR6106AP 1G DDR
03 SGND
Twisted pair wire
04 A

RS-485 05 B To SCADA or printer

06 SGND

1 BNC To clock synchronization Coaxial cable

1 RJ45 For debugging Twisted pair wire

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Date: 2023-08-01
 8 Hardware

Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

(LC connector)

Optical channel for pilot Optical fiber (single-

1 FC connector
protection mode)

Optical channel for pilot Optical fiber (multi-

1 ST connector
protection mode)

01 A

RS-485 02 B To SCADA
NR6106AQ 1G DDR
03 SGND

04 A

RS-485 05 B To SCADA or printer

06 SGND
Twisted pair wire
07 SYN+

RS-485 08 SYN- To clock

09 SGND synchronization

TTL 10 TTL

1 RJ45
For debugging 8
Ethernet

2 RJ45

Ethernet Twisted pair wire or

Ethernet communication
2 SFP Ethernet optic fibre

(LC connector)
NR6106AR 1G DDR
Optical channel for pilot Optical fiber (single-
1 FC connector
protection mode)

Optical channel for pilot Optical fiber (multi-

1 ST connector
protection mode)

PCS-902S Line Distance Relay 8-29

Date: 2023-08-01
 8 Hardware

01 A

RS-485 02 B To SCADA

03 SGND

04 A

RS-485 05 B To SCADA or printer

06 SGND
Twisted pair wire
07 SYN+

RS-485 08 SYN- To clock

09 SGND synchronization

TTL 10 TTL

1 RJ45
For debugging
Ethernet

Table 8.4-6 Pilot channel interface

Type Wavelength Application

NR6106AB 1310nm Single-mode, dual channels, transmission distance <60 km

NR6106AC 1550nm Single-mode, dual channels, transmission distance <120 km

NR6106AD 850nm Multi-mode, dual channels transmission distance <2 km

NR6106AF 1310nm Single-mode, dual channels, transmission distance <60 km

NR6106AG 1550nm Single-mode, dual channels, transmission distance <120 km

8 NR6106AK 1310nm Single-mode, dual channels, transmission distance <60 km

NR6106AL 1310nm Single-mode, dual channels, transmission distance <60 km

1310nm Single-mode, single channel, transmission distance <60 km

NR6106AM
850nm Multi-mode, single channel transmission distance <2 km

1550nm Single-mode, single channel, transmission distance <120 km

NR6106AN
850nm Multi-mode, single channel transmission distance <2 km

1310nm Single-mode, single channel, transmission distance <60 km

NR6106AQ
850nm Multi-mode, single channel transmission distance <2 km

NR6106AR 1550nm Single-mode, single channel, transmission distance <120 km

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 8 Hardware

850nm Multi-mode, single channel transmission distance <2 km

The correct connection is shown in Figure 8.4-3. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The external shield of the cable shall be
grounded at one of the ends only.

Twisted pair wire

A 01

COM
B 02

SGND 03
cable with single point earthing
To the screen of other coaxial

Twisted pair wire

SYN+ 01

Clock SYN
SYN- 02

SGND 03

Cable
RTS 05

PRINT
TXD 06

SGND 07

Figure 8.4-3 Connection of communication terminal

Pin2

Figure 8.4-4 Jumpers of printer/RS-485 port

The 2nd RS-485 port also can be configured as a printer port through the jumpers "J10" and "J11".

Jumper RS-485 Printer

J10 Pin1 and Pin2 are connected Pin2 and Pin3 are connected

J11 Pin1 and Pin2 are connected Pin2 and Pin3 are connected

8.4.4 NET-DSP Module (NR6113)

This module consists of high-performance DSP (digital signal processor), Ethernet controller and other
peripherals. It supports GOOSE and SV (IEC 61850-9-2) communication in digital substation and

PCS-902S Line Distance Relay 8-31

Date: 2023-08-01
 8 Hardware

PRP/HSR network communication.

Table 8.4-7 Configuration and terminal definition of NET-DSP module

Module ID Interface Usage Physical Layer

NR6113A 12 SFP Ethernet GOOSE & SV communication 100Mbit/s optical fiber (LC type)

The first four ports: 1000Mbit/s optical

GOOSE & SV communication,
fiber (LC type)
NR6113B 12 SFP Ethernet and PRP/HSR network
The rest of ports: 100Mbit/s optical fiber
communication
(LC type)

Do NOT look into the end of an optical fiber connected to an optical port.

Do NOT look into an optical port/connector.

A direct sight to laser light may cause temporary or permanent blindness.

Figure 8.4-5 View of NET-DSP module

NR6113A consists of 12 × 100Mbit/s optical Ethernet interface (LC type). The module supports GOOSE
and SV per IEC 61850-9-2 protocol, and it can receive and send GOOSE messages to intelligent control

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 8 Hardware

device, and receive SV from MU (merging unit). Each port can be used not only for GOOSE signal or
SV signal individually but also GOOSE signal and SV signal simultaneously by peer-to-peer (P2P) mode
and networking mode.

NR6113B consists of 4 × 1000Mbit/s optical Ethernet interface (LC type) and 8 × 100Mbit/s optical
Ethernet interface (LC type). The 4 × 1000Mbit/s optical Ethernet interface support both GOOSE &
SV communication and PRP/HSR network communication, which can be 2 groups of PRP or HSR
ports, or 1 group of PRP ports + 1 group of HSR ports. The 8 × 100Mbit/s optical Ethernet interface
are as similar as that of NR6113A.

8.4.5 Analogue Input Module (NR6641)

The analogue input module is applicable for power plant or substation with conventional VT and
CT, and it can transform high AC input values to relevant low AC output value, which are suited to
the analogue inputs of the CPU module. The transformers are used both to step-down the currents
and voltages to levels appropriate to the device’s electronic circuitry and to provide effective
isolation between this device and the power system. A low pass filter circuit is connected to each
transformer (CT or VT) secondary circuit for reducing the noise of each analogue AC input signal.

For the analogue input module, if the plug is not put in the socket, external CT circuit is closed itself.
Just shown as below.

Plug
Socket

In

Out

plug is not put in the socket

8
In

Out

Put the plug in the socket

Figure 8.4-6 Schematic diagram of CT circuit automatically closed

PCS-902S Line Distance Relay 8-33

Date: 2023-08-01
 8 Hardware

Figure 8.4-7 View of analogue input module

There are several types of analogue input modules. The rated current is adaptive (1A/5A). Please
declare which kind of AI module is needed before ordering. Maximum linear range of the current
converter is 40In.

⚫ 4CT+4VT

⚫ 4CT+7VT
8 ⚫ 6CT+6VT

⚫ 7CT+5VT

The terminal definition of the analogue input module is shown as below.

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 8 Hardware

NR6641-4I4U NR6641-4I7U NR6641-6I6U NR6641-7I5U

01 I1 I1n 02 01 I1 I1n 02 01 I1 I1n 02 01 I1 I1n 02
03 I2 I2n 04 03 I2 I2n 04 03 I2 I2n 04 03 I2 I2n 04
05 I3 I3n 06 05 I3 I3n 06 05 I3 I3n 06 05 I3 I3n 06
07 I4 I4n 08 07 I4 I4n 08 07 I4 I4n 08 07 I4 I4n 08
09 10 09 10 09 I5 I5n 10 09 I5 I5n 10
11 12 11 U1 U1n 12 11 I6 I6n 12 11 I6 I6n 12
13 14 13 U2 U2n 14 13 U1 U1n 14 13 I7 I7n 14
15 16 15 U3 U3n 16 15 U2 U2n 16 15 U1 U1n 16
17 U1 U1n 18 17 U4 U5n
U4n 18 17 U3 U3n 18 17 U2 U2n 18
19 U2 U2n 20 19 U5 U5n 20 19 U4 U4n 20 19 U3 U3n 20
21 U3 U3n 22 21 U6 U6n 22 21 U5 U5n 22 21 U4 U4n 22
23 U4 U4n 24 23 U7 U7n 24 23 U6 U6n 24 23 U5 U5n 24

Figure 8.4-8 Terminal definition of analogue input module

NEVER allow the current transformer (CT) secondary circuit connected to

this device to be opened while the primary system is energized. The opened
CT secondary circuit will produce a dangerously high voltage. If this safety
precaution is disregarded, personal death, severe personal injury or
considerable equipment damage will occur.

Each analogue input channel can be configured according to practical

application through PCS Studio.

Some connection examples of the current transformers and voltage transformers which are
supported by this relay are shown in this section. If one of the analogue inputs has no input in a
practical engineering, the relevant input terminals should be disconnected.
8
1. Current connections examples

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Date: 2023-08-01
 8 Hardware

P2 S2

P1 S1

02 01

04 03

06 05

A B C C B A

P2 P1 P1 P2

S2 S1 S1 S2

8 02 01

04 03

06 05

08 07

10 09

12 11

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 8 Hardware

P2 S2 P2 S2

P1 S1 P1 S1

02 01 02 01

04 03 04 03

06 05 06 05

08 07 08 07

Figure 8.4-9 Current connection examples

2. Voltage connections examples

17 18

8
19 20

21 22

23 24

PCS-902S Line Distance Relay 8-37

Date: 2023-08-01
 8 Hardware

17 18

19 20

21 22

23 24

11 12

13 14

15 16

17 18

19 20

21 22

23 24

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 8 Hardware

11 12

13 14

19 20

21 22

23 24

A B C C B A

20 19

22 21

24 23

18 17

16 15

14 13

Figure 8.4-10 Voltage connection examples

PCS-902S Line Distance Relay 8-39

Date: 2023-08-01
 8 Hardware

8.4.6 Binary Input Module (NR6601/NR6604/NR6610/NR6611)

There are several kinds of BI modules available, common negative supply: NR6601A, NR6610A
and NR6610B, which can respectively provide 25 or 32 binary inputs, and independent negative
supply: NR6604A and NR6611A, which can provide 13 or 14 binary inputs. All binary inputs that
are provided by the binary input module are configurable through PCS-Studio according to practical
application.

The rated voltage of binary input is optional: 24Vdc~250Vdc, 110Vac or

220Vac. It is necessary to check whether the rated voltage of binary input
module complies with site DC power supply rating before put this device in
service.

Voltage

300

157.5

138.6

125

110

8 78.75

69.3

62.5
55 Operation

30.24
24 Operation uncertain
15.12
12
No operation
0 24V 48V 110V 125V 220V 250V

Figure 8.4-11 Voltage dependence for binary inputs (default set)

⚫ NR6601A

Each BI module is with a 26-pin connector for 25 binary inputs which share one common negative
power input and can be configurable. The pickup voltages and dropout voltages of the binary inputs

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 8 Hardware

are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from 50%Un to
80%Un.

01 BI_01 BI_02 02

03 BI_03 BI_04 04

05 BI_05 BI_06 06

07 BI_07 BI_08 08

09 BI_09 BI_10 10

11 BI_11 BI_12 12

13 BI_13 BI_14 14

15 BI_15 BI_16 16

17 BI_17 BI_18 18

19 BI_19 BI_20 20

21 BI_21 BI_22 22

23 BI_23 BI_24 24

25 BI_25 BI_COM 26

Figure 8.4-12 View of binary input module (NR6601A)

The terminal definition of the connector is described as below.

Table 8.4-8 Terminal definition and description of binary input module

Pin No. Symbol Description 8

01 BI_01 The No.1 programmable binary input

02 BI_02 The No.2 programmable binary input

03 BI_03 The No.3 programmable binary input

04 BI_04 The No.4 programmable binary input

05 BI_05 The No.5 programmable binary input

06 BI_06 The No.6 programmable binary input

07 BI_07 The No.7 programmable binary input

08 BI_08 The No.8 programmable binary input

PCS-902S Line Distance Relay 8-41

Date: 2023-08-01
 8 Hardware

09 BI_09 The No.9 programmable binary input

10 BI_10 The No.10 programmable binary input

11 BI_11 The No.11 programmable binary input

12 BI_12 The No.12 programmable binary input

13 BI_13 The No.13 programmable binary input

14 BI_14 The No.14 programmable binary input

15 BI_15 The No.15 programmable binary input

16 BI_16 The No.16 programmable binary input

17 BI_17 The No.17 programmable binary input

18 BI_18 The No.18 programmable binary input

19 BI_19 The No.19 programmable binary input

20 BI_20 The No.20 programmable binary input

21 BI_21 The No.21 programmable binary input

22 BI_22 The No.22 programmable binary input

23 BI_23 The No.23 programmable binary input

24 BI_24 The No.24 programmable binary input

25 BI_25 The No.25 programmable binary input

26 BI_COM The common negative connection of the BI_01 to BI_25

⚫ NR6604A

8 Each BI module is with a 26-pin connector for 13 binary inputs which have independent negative
power input and can be configurable. The pickup voltages and dropout voltages of the binary inputs
are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from 50%Un to
80%Un.

When the rated voltage of binary input is 110Vdc or above and the setting [En_BICheckInstP] is
set as "Enabled", NR6604A can be applied to acquire the mechanical signal, for example, the
binary signal from winding temperature relay, oil temperature relay or Buchholz relay. The
conducting mode of each binary input is switched into the high-power mode to improve the anti-
interference ability. The binary input will not be considered as being energized unless the
instantaneous active power rises to a certain value and during time is larger than 20ms, so as to
avoid mistaken signal.

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 8 Hardware

01 BI_01
02 Opto01-
03 BI_02
04 Opto02-
05 BI_03
06 Opto03-
07 BI_04
08 Opto04-
09 BI_05
10 Opto05-
11 BI_06
12 Opto06-
13 BI_07
14 Opto07-
15 BI_08
16 Opto08-
17 BI_09
18 Opto09-
19 BI_10
20 Opto10-
21 BI_11
22 Opto11-
23 BI_12
24 Opto12-
25 BI_13
26 Opto13-

Figure 8.4-13 View of binary input module (NR6604A)

The terminal definition of the connector is described as below.

Table 8.4-9 Terminal definition and description of binary input module

Pin No. Symbol Description

01 BI_01 The No.1 programmable binary input

02 Opto 01- The negative connection of the BI_01

8
03 BI_02 The No.2 programmable binary input

04 Opto 02- The negative connection of the BI_02

05 BI_03 The No.3 programmable binary input

06 Opto 03- The negative connection of the BI_03

07 BI_04 The No.4 programmable binary input

08 Opto 04- The negative connection of the BI_04

09 BI_05 The No.5 programmable binary input

10 Opto 05- The negative connection of the BI_05

PCS-902S Line Distance Relay 8-43

Date: 2023-08-01
 8 Hardware

11 BI_06 The No.6 programmable binary input

12 Opto 06- The negative connection of the BI_06

13 BI_07 The No.7 programmable binary input

14 Opto 07- The negative connection of the BI_07

15 BI_08 The No.8 programmable binary input

16 Opto 08- The negative connection of the BI_08

17 BI_09 The No.9 programmable binary input

18 Opto 09- The negative connection of the BI_09

19 BI_10 The No.10 programmable binary input

20 Opto 10- The negative connection of the BI_10

21 BI_11 The No.11 programmable binary input

22 Opto 11- The negative connection of the BI_11

23 BI_12 The No.12 programmable binary input

24 Opto 12- The negative connection of the BI_12

25 BI_13 The No.13 programmable binary input

26 Opto 13- The negative connection of the BI_13

⚫ NR6610A & NR6610B

Each BI module is with two 18-pin connectors for 32 binary inputs. The first 16 binary inputs share
one common negative power input and the last 16 binary inputs share another common negative
power input. All binary inputs are configurable. The pickup voltages and dropout voltages of the
8 binary inputs are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from
50%Un to 80%Un. The difference between NR6610A and NR6610B is that NR6610A equips single
AD sampling and NR6610B equips dual AD sampling.

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 8 Hardware

01 BI_01 19 BI_01

02 BI_02 20 BI_02

03 BI_03 21 BI_03

04 BI_04 22 BI_04

05 BI _05 23 BI_05

06 BI_06 24 BI_06

07 BI_07 25 BI_07

08 BI_08 26 BI_08

09 BI_09 27 BI_09

10 BI _10 28 BI_10

11 BI_11 29 BI_11

12 BI_12 30 BI_12

13 BI _13 31 BI_13

14 BI_14 32 BI_14

15 BI _15 33 BI_15

16 BI_16 34 BI_16

17 BI_COM 35 BI_COM

18 BI_COM 36 BI _COM

Figure 8.4-14 View of binary input module (NR6610A/NR6610B)

The terminal definition of the connector is described as below.

Table 8.4-10 Terminal definition and description of binary input module

Pin No. Symbol Description

01 BI_01 The No.1 programmable binary input

02 BI_02 The No.2 programmable binary input

8
03 BI_03 The No.3 programmable binary input

04 BI_04 The No.4 programmable binary input

05 BI_05 The No.5 programmable binary input

18-pin
06 BI_06 The No.6 programmable binary input

07 BI_07 The No.7 programmable binary input

08 BI_08 The No.8 programmable binary input

09 BI_09 The No.9 programmable binary input

10 BI_10 The No.10 programmable binary input

PCS-902S Line Distance Relay 8-45

Date: 2023-08-01
 8 Hardware

11 BI_11 The No.11 programmable binary input

12 BI_12 The No.12 programmable binary input

13 BI_13 The No.13 programmable binary input

14 BI_14 The No.14 programmable binary input

15 BI_15 The No.15 programmable binary input

16 BI_16 The No.16 programmable binary input

17
BI_COM The common negative connection of the BI_01 to BI_16
18

19 BI_17 The No.17 programmable binary input

20 BI_18 The No.18 programmable binary input

21 BI_19 The No.19 programmable binary input

22 BI_20 The No.20 programmable binary input

23 BI_21 The No.21 programmable binary input

24 BI_22 The No.22 programmable binary input

25 BI_23 The No.23 programmable binary input

26 BI_24 The No.24 programmable binary input

27 BI_25 The No.25 programmable binary input

18-pin
28 BI_26 The No.26 programmable binary input

29 BI_27 The No.27 programmable binary input

8 30 BI_28 The No.28 programmable binary input

31 BI_29 The No.29 programmable binary input

32 BI_30 The No.30 programmable binary input

33 BI_31 The No.31 programmable binary input

34 BI_32 The No.32 programmable binary input

35
BI_COM The common negative connection of the BI_17 to BI_32
36

⚫ NR6611A

Each BI module is with two 18-pin connectors for 14 binary inputs which have independent negative
power input and can be configurable. The pickup voltages and dropout voltages of the binary inputs

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 8 Hardware

are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from 50%Un to
80%Un.

When the rated voltage of binary input is 110Vdc or above and the setting [En_BICheckInstP] is
set as "Enabled", NR6604A can be applied to acquire the mechanical signal, for example, the
binary signal from winding temperature relay, oil temperature relay or Buchholz relay. The
conducting mode of each binary input is switched into the high-power mode to improve the anti-
interference ability. The binary input will not be considered as being energized unless the
instantaneous active power rises to a certain value during time is larger than 20ms, so as to avoid
mistaken signal.

01 19

02 20

03 BI_01 21 BI _08

04 Opto01- 22 Opto08-

05 BI_02 23 BI _09

06 Opto02- 24 Opto09-

07 BI_03 25 BI _10

08 Opto03- 26 Opto10-

09 BI_04 27 BI _11

10 Opto04- 28 Opto11-

11 BI_05 29 BI _12

12 Opto05- 30 Opto12-

13 BI_06 31 BI _13

14 Opto06- 32 Opto13-

15 BI_07 33 BI _14

16 Opto07- 34 Opto14-

17

18
35

36
8
Figure 8.4-15 View of binary input module (NR6611A)

The terminal definition of the connector is described as below.

Table 8.4-11 Terminal definition and description of binary input module

Pin No. Symbol Description

01 Blank

02 Blank
18-pin
03 BI_01 The No.1 programmable binary input

04 Opto 01- The negative connection of the BI_01

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 8 Hardware

05 BI_02 The No.2 programmable binary input

06 Opto 02- The negative connection of the BI_02

07 BI_03 The No.3 programmable binary input

08 Opto 03- The negative connection of the BI_03

09 BI_04 The No.4 programmable binary input

10 Opto 04- The negative connection of the BI_04

11 BI_05 The No.5 programmable binary input

12 Opto 05- The negative connection of the BI_05

13 BI_06 The No.6 programmable binary input

14 Opto 06- The negative connection of the BI_06

15 BI_07 The No.7 programmable binary input

16 Opto 07- The negative connection of the BI_07

17 Blank

18 Blank

19 Blank

20 Blank

21 BI_08 The No.8 programmable binary input

22 Opto 08- The negative connection of the BI_08

23 BI_09 The No.9 programmable binary input

8 24 Opto 09- The negative connection of the BI_09

25 BI_10 The No.10 programmable binary input

18-pin 26 Opto 10- The negative connection of the BI_10

27 BI_11 The No.11 programmable binary input

28 Opto 11- The negative connection of the BI_11

29 BI_12 The No.12 programmable binary input

30 Opto 12- The negative connection of the BI_12

31 BI_13 The No.13 programmable binary input

32 Opto 13- The negative connection of the BI_13

33 BI_14 The No.14 programmable binary input

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34 Opto 14- The negative connection of the BI_14

35 Blank

36 Blank

8.4.7 Binary Output Module (NR6651/NR6652/NR6660/NR6663)

The binary output module consists of some necessary contact outputs, and the binary outputs are
used as tripping and closing (protection, auto-reclosing or remote control) outputs or signal outputs.
It can receive tripping commands or closing commands from the CPU module, and then executes
these commands. It also can output some alarm signals from the CPU module.

The device can provide several types of binary output modules: NR6651A, NR6651B, NR6652A
NR6660A and NR6663A.

⚫ NR6651A

A 26-pin connector is fixed on the binary output module. The NR6651A provides 13 normally open
contacts (NOC). The terminal definition of the connector is shown in Figure 8.4-16.

BO _01 01 02

BO_02 03 04

BO _03 05 06

BO_04 07 08

BO_05 09 10

BO _06 11 12

BO_07 13 14

BO_08 15 16 8
BO _09 17 18

BO_10 19 20

BO_11 21 22

BO _12 23 24

BO_13 25 26

Figure 8.4-16 View of binary output module (NR6651A)

The terminal definition of the connector is described as below.

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Table 8.4-12 Terminal definition and description of binary output module

Pin No. Symbol Description

01
BO_01 The No.01 binary output contact (normally open contact, NOC)
02

03
BO_02 The No.02 binary output contact (normally open contact, NOC)
04

05
BO_03 The No.03 binary output contact (normally open contact, NOC)
06

07
BO_04 The No.04 binary output contact (normally open contact, NOC)
08

09
BO_05 The No.05 binary output contact (normally open contact, NOC)
10

11
BO_06 The No.06 binary output contact (normally open contact, NOC)
12

13
BO_07 The No.07 binary output contact (normally open contact, NOC)
14

15
BO_08 The No.08 binary output contact (normally open contact, NOC)
16

17
BO_09 The No.09 binary output contact (normally open contact, NOC)

8 18

19
BO_10 The No.10 binary output contact (normally open contact, NOC)
20

21
BO_11 The No.11 binary output contact (normally open contact, NOC)
22

23
BO_12 The No.12 binary output contact (normally open contact, NOC)
24

25
BO_13 The No.13 binary output contact (normally open contact, NOC)
26

⚫ NR6651B

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A 26-pin connector is fixed on the binary output module. The NR6651B provides 11 normally open
contacts (NOC, the first 11 contacts) and 2 normally close contacts (NCC, the last 2 contacts). The
terminal definition of the connector is shown in Figure 8.4-17.

BO _01 01 02

BO_02 03 04

BO_03 05 06

BO _04 07 08

BO_05 09 10

BO_06 11 12

BO _07 13 14

BO_08 15 16

BO_09 17 18

BO _10 19 20

BO_11 21 22

BO_12 23 24

BO _13 25 26

Figure 8.4-17 View of binary output module (NR6651B)

The terminal definition of the connector is described as below.

Table 8.4-13 Terminal definition and description of binary output module

8
Pin No. Symbol Description

01
BO_01 The No.01 binary output contact (normally open contact, NOC)
02

03
BO_02 The No.02 binary output contact (normally open contact, NOC)
04

05
BO_03 The No.03 binary output contact (normally open contact, NOC)
06

07
BO_04 The No.04 binary output contact (normally open contact, NOC)
08

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09
BO_05 The No.05 binary output contact (normally open contact, NOC)
10

11
BO_06 The No.06 binary output contact (normally open contact, NOC)
12

13
BO_07 The No.07 binary output contact (normally open contact, NOC)
14

15
BO_08 The No.08 binary output contact (normally open contact, NOC)
16

17
BO_09 The No.09 binary output contact (normally open contact, NOC)
18

19
BO_10 The No.10 binary output contact (normally open contact, NOC)
20

21
BO_11 The No.11 binary output contact (normally open contact, NOC)
22

23
BO_12 The No.12 binary output contact (normally closed contact, NCC)
24

25
BO_13 The No.13 binary output contact (normally closed contact, NCC)
26

⚫ NR6652A

8 A 26-pin connector is fixed on the binary output module. The NR6652A provides 4 normally open
contacts (NOC, the first 4 contacts) with heavy capacity for controlling the circuit breaker directly,
and provides 4 general normal open contacts (NOC, the last 4 contacts). The terminal definition of
the connector is shown in Figure 8.4-18.

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BO _01 01 02

03 04

BO_02 05 06

07 08

BO_03 09 10

11 12

BO _04 13 14

15 16

17 18

BO _05 19 20

BO_06 21 22

BO _07 23 24

BO_08 25 26

Figure 8.4-18 View of binary output module (NR6652A)

The terminal definition of the connector is described as below.

Table 8.4-14 Terminal definition and description of binary output module

Pin No. Symbol Description

01 The No.01 binary output contact with heavy capacity for controlling

02
BO_01
the circuit breaker directly (normally open contact, NOC) 8
03 Blank

04 Blank

05 The No.02 binary output contact with heavy capacity for controlling
BO_02
the circuit breaker directly (normally open contact, NOC)
06

07 Blank

08 Blank

09 The No.03 binary output contact with heavy capacity for controlling
BO_03
the circuit breaker directly (normally open contact, NOC)
10

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11 Blank

12 Blank

13 The No.04 binary output contact with heavy capacity for controlling
BO_04
the circuit breaker directly (normally open contact, NOC)
14

15 Blank

16 Blank

17 Blank

18 Blank

19
BO_05 The No.05 binary output contact (normally open contact, NOC)
20

21
BO_06 The No.06 binary output contact (normally open contact, NOC)
22

23
BO_07 The No.07 binary output contact (normally open contact, NOC)
24

25
BO_08 The No.08 binary output contact (normally open contact, NOC)
26

⚫ NR6660A

Two 18-pin connectors are fixed on the binary output module. The NR6660A provides 15 normally
open contacts (NOC) and 2 normally open contacts & normally close contacts (NOC/NCC). The
terminal definition of the connector is shown in Figure 8.4-19.
8

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BO_01 01 02

BO _02 03 04

BO_03 05 06

BO _04 07 08

18-pin
BO_05 09 10

BO _06 11 12

BO_07 13 14

BO _08 15 16

BO_09 17 18

BO _10 19 20

BO_11 21 22

BO _12 23 24

BO_13 25 26

BO _14 27 28
18-pin

BO_15 29 30

BO _16 32
31
BO_16 33

BO _17 35
34
BO_17 36

Figure 8.4-19 View of binary output module (NR6660A)

The terminal definition of the connector is described as below.

Table 8.4-15 Terminal definition and description of binary output module

Pin No. Symbol Description

01

02
BO_01 The No.01 binary output contact (normally open contact, NOC)
8
03
BO_02 The No.02 binary output contact (normally open contact, NOC)
04

05
18-pin BO_03 The No.03 binary output contact (normally open contact, NOC)
06

07
BO_04 The No.04 binary output contact (normally open contact, NOC)
08

09
BO_05 The No.05 binary output contact (normally open contact, NOC)
10

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11
BO_06 The No.06 binary output contact (normally open contact, NOC)
12

13
BO_07 The No.07 binary output contact (normally open contact, NOC)
14

15
BO_08 The No.08 binary output contact (normally open contact, NOC)
16

17
BO_09 The No.09 binary output contact (normally open contact, NOC)
18

19
BO_10 The No.10 binary output contact (normally open contact, NOC)
20

21
BO_11 The No.11 binary output contact (normally open contact, NOC)
22

23
BO_12 The No.12 binary output contact (normally open contact, NOC)
24

25
BO_13 The No.13 binary output contact (normally open contact, NOC)
26

27
18-pin BO_14 The No.14 binary output contact (normally open contact, NOC)
28

29
BO_15 The No.15 binary output contact (normally open contact, NOC)

8 30

31
The No.16 binary output contact (normally open contact, NOC
32 BO_16
and normally closed contact in parallel)

33

34
The No.17 binary output contact (normally open contact, NOC
35 BO_17
and normally closed contact in parallel)

36

⚫ NR6663A

Two 18-pin connectors are fixed on the binary output module. The NR6663A provides 4 normally
open contacts (NOC, the first 4 contacts) with heavy capacity for controlling the circuit breaker

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directly, and provides 4 general normal open contacts (NOC, the last 4 contacts). The terminal
definition of the connector is shown in Figure 8.4-20.

01 19

02 20

03 21

BO_01-1 04 BO_05-1 22

05 23

BO_01-2 06 BO_05-2 24

07 25

BO_02-1 08 BO_06-1 26

09 27
18-pin

18-pin
BO _02-2 10 BO_06-2 28

11 29

BO _03-1 12 BO_07-1 30

13 31

BO_03-2 14 BO_07-2 32

15 33

BO_04-1 16 BO_08-1 34

17 35

BO_04-2 18 BO_08-2 36

Figure 8.4-20 View of binary output module (NR6663A)

The terminal definition of the connector is described as below.

Table 8.4-16 Terminal definition and description of binary output module

Pin No. Symbol Description 8

01 Blank

02 Blank

03 Blank

The No.01 binary output contact with heavy capacity for

18-pin
04~06 BO_01 controlling the circuit breaker directly (normally open contact,

NOC)

05 Blank

07 Blank

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 8 Hardware

The No.02 binary output contact with heavy capacity for

08~10 BO_02 controlling the circuit breaker directly (normally open contact,

NOC)

09 Blank

11 Blank
The No.03 binary output contact with heavy capacity for

12~14 BO_03 controlling the circuit breaker directly (normally open contact,
NOC)

13 Blank

15 Blank

The No.04 binary output contact with heavy capacity for

16~18 BO_04 controlling the circuit breaker directly (normally open contact,
NOC)

17 Blank

19 Blank

20 Blank

21 Blank

22~24 BO_05 The No.05 binary output contact (normally open contact, NOC)

23 Blank

25 Blank

26~28 BO_06 The No.06 binary output contact (normally open contact, NOC)
18-pin

8 27 Blank

Blank
29

30~32 BO_07 The No.07 binary output contact (normally open contact, NOC)

31 Blank

33 Blank

34~36 BO_08 The No.08 binary output contact (normally open contact, NOC)

35 Blank

8.4.8 Binary Input and Output Module (NR6661)

The binary input and output module, NR6661A as shown in Figure 8.4-21, contains both binary
inputs and contact outputs.

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The rated voltage of binary input is optional: 24Vdc~250Vdc, 110Vac or

220Vac. It is necessary to check whether the rated voltage of binary input
module complies with site DC power supply rating before put this device in
service.

Each IO module is with two 18-pin connectors for 16 binary inputs, 6 normally open contacts (NOC)
and 2 normally open contacts & normally close contacts (NOC/NCC). The 16 binary inputs share
one common negative power input. All binary inputs are configurable. The pickup voltages and
dropout voltages of the binary inputs are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI],
and the range is from 50%Un to 80%Un.

01 BI _01
BO_10 19 20
02 BI_02

03 BI_03 BO _11 21 22
04 BI _04

05 BI_05 BO_12 23 24

06 BI _06

07 BI_07 BO _13 25 26

08 BI_08
BO_14 27 28
09 BI _09

10 BI_10
BO _15 29 30
11 BI _11

12 BI_12 BO_16 32
13 BI_13 31

14 BI _14 BO _16 33

8
15 BI_15

16 BI _16 BO_17 35

34
17 BI_COM
BO _17 36
18 BI_COM

Figure 8.4-21 View of binary input and output module (NR6661A)

The terminal definition of the connector is described as below.

Table 8.4-17 Terminal definition and description of binary input and output module

Pin No. Symbol Description

01 BI_01 The No.1 programmable binary input

18-pin
02 BI_02 The No.2 programmable binary input

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 8 Hardware

03 BI_03 The No.3 programmable binary input

04 BI_04 The No.4 programmable binary input

05 BI_05 The No.5 programmable binary input

06 BI_06 The No.6 programmable binary input

07 BI_07 The No.7 programmable binary input

08 BI_08 The No.8 programmable binary input

09 BI_09 The No.9 programmable binary input

10 BI_10 The No.10 programmable binary input

11 BI_11 The No.11 programmable binary input

12 BI_12 The No.12 programmable binary input

13 BI_13 The No.13 programmable binary input

14 BI_14 The No.14 programmable binary input

15 BI_15 The No.15 programmable binary input

16 BI_16 The No.16 programmable binary input

17
BI_COM The common negative connection of the BI_01 to BI_16
18

19
BO_01 The No.01 binary output contact (normally open contact, NOC)
20

21
BO_02 The No.02 binary output contact (normally open contact, NOC)

8 22

23
BO_03 The No.03 binary output contact (normally open contact, NOC)
24

18-pin 25
BO_04 The No.04 binary output contact (normally open contact, NOC)
26

27
BO_05 The No.05 binary output contact (normally open contact, NOC)
28

29
BO_06 The No.06 binary output contact (normally open contact, NOC)
30

31 BO_07 The No.07 binary output contact (normally open contact, NOC and

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normally closed contact, NCC in parallel)

32

33

34
The No.08 binary output contact (normally open contact, NOC and
35 BO_08
normally closed contact, NCC in parallel)

36

Each binary output can be set as a specified tripping output contact or a

signal output contact through PCS Studio according to practical application.

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 9 Settings

9 Settings

Table of Contents

9.1 Global Settings ................................................................................................ 9-1

9.1.1 System Settings ................................................................................................................... 9-1

9.1.2 Device Settings .................................................................................................................... 9-4

9.1.3 Communication Settings ...................................................................................................... 9-5

9.1.4 Disturbance Fault Recording Settings ............................................................................... 9-28

9.1.5 Label Settings..................................................................................................................... 9-28

9.1.6 Clock Synchronization Settings.......................................................................................... 9-28

9.1.7 Supervision Settings........................................................................................................... 9-31

9.2 Protection Settings ........................................................................................ 9-32

9.2.1 Fault Detector (FD)............................................................................................................. 9-32

9.2.2 Optical Pilot Channel (FO) ................................................................................................. 9-32

9.2.3 Pilot Distance Protection (85)............................................................................................. 9-32

9.2.4 Pilot Directional Earth-fault Protection (85) ........................................................................ 9-34

9.2.5 DPFC Distance Protection (21D) ....................................................................................... 9-35

9.2.6 Distance Protection (21L)................................................................................................... 9-35

9.2.7 Out-of-step Protection (78)................................................................................................. 9-53

9.2.8 Distance SOTF Protection (21SOTF) ................................................................................ 9-54

9.2.9 Phase Overcurrent Protection (50/51P) ............................................................................. 9-55

9.2.10 Phase Current SOTF Protection (50PSOTF) .................................................................. 9-72

9
9.2.11 Earth Fault Protection (50/51G) ....................................................................................... 9-73

9.2.12 Residual Current SOTF Protection (50GSOTF) .............................................................. 9-86

9.2.13 Negative-sequence Overcurrent Protection (50/51Q) ..................................................... 9-86

9.2.14 Phase Overvoltage Protection (59P) ............................................................................... 9-91

9.2.15 Residual Overvoltage Protection (59G) ........................................................................... 9-94

9.2.16 Negative-sequence Overvoltage Protection (59Q) .......................................................... 9-95

9.2.17 Phase Undervoltage Protection (27P) ............................................................................. 9-96

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 9 Settings

9.2.18 Overfrequency Protection (81O) .................................................................................... 9-100

9.2.19 Underfrequency Protection (81U) .................................................................................. 9-101

9.2.20 Frequency Rate-of-change Protection (81R) ................................................................. 9-102

9.2.21 Reverse Power Protection (32R) ................................................................................... 9-104

9.2.22 Thermal Overload Protection (49P) ............................................................................... 9-105

9.2.23 Undercurrent Protection (37).......................................................................................... 9-106

9.2.24 Breaker Failure Protection (50BF) ................................................................................. 9-107

9.2.25 Stub Differential Protection (87STB) .............................................................................. 9-108

9.2.26 Dead Zone Protection (50DZ) ........................................................................................ 9-109

9.2.27 Broken Conductor Protection (46BC) ............................................................................ 9-109

9.2.28 Pole Discrepancy Protection (62PD) ............................................................................. 9-109

9.2.29 Flashover Protection (50F)............................................................................................. 9-110

9.2.30 Transfer Trip (TT) ........................................................................................................... 9-110

9.2.31 Trip Logic (TRP) ..............................................................................................................9-111

9.2.32 Automatic Reclosure (79) ................................................................................................ 9-111

9.2.33 Impedance-Based Fault Location (FL)........................................................................... 9-114

9.3 Measurement and Control Settings ............................................................9-114

9.3.1 Function ............................................................................................................................ 9-114

9.3.2 Synchronism Check (25) .................................................................................................. 9-117

9.3.3 Double Point Status.......................................................................................................... 9-121

9.3.4 Control .............................................................................................................................. 9-121

9.3.5 Interlocking Logic ............................................................................................................. 9-121

9.3.6 AC Analog Input Calibration ............................................................................................. 9-122

9
9.3.7 Energy Metering ............................................................................................................... 9-123

9.3.8 Circuit Breaker Supervision (SCBR) ................................................................................ 9-123

9.4 PMU Settings ............................................................................................... 9-127

9.4.1 PMU Global Settings ........................................................................................................ 9-127

9.4.1 PMU Comm Settings ........................................................................................................ 9-128

9.4.2 PMU Bay Settings ............................................................................................................ 9-135

9.4.3 PMU BI Settings ............................................................................................................... 9-137

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9.4.4 PMU Label Settings.......................................................................................................... 9-137

9.5 Logic Links................................................................................................... 9-138

9.5.1 Function Links .................................................................................................................. 9-138

9.5.2 GOOSE Send Links ......................................................................................................... 9-139

9.5.3 GOOSE Receive Links ..................................................................................................... 9-139

9.5.4 SV Receive Links ............................................................................................................. 9-140

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 9 Settings

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 9 Settings

9.1 Global Settings

9.1.1 System Settings

Access path: MainMenuSettingsGlobal SettingsSystem Settings

Name Range Step Unit Default Description

The number of active setting
group, several setting groups
Active_Grp 1~20 1 1 can be configured for
protection settings, and only
one is active at a time.
Name of the protected primary
Max 20
PrimaryEquip_Name DeviceName equipment, such as busbar,
characters
transformer, etc.
Opt_SysFreq 50, 60 Hz 50Hz The system frequency.
This setting informs the device
of the actual system phase
sequence, either ABC or ACB.
ABC CT and VT inputs on the
Opt_PhSeq ABC
ACB device, labeled as A, B and C,
must be connected to system
phase A, B and C for correct
operation.
Primary rated voltage of VT
Prot.U1n 0.00~1100.00 0.01 kV 220.00 (protection voltage, phase-to-
phase value)
Secondary rated voltage of VT
Prot.U2n 1.00~500.00 0.01 V 100.00 (protection voltage, phase-to-
phase value)
Primary rated value of CT
Prot.CB1.I1n 0~60000 1 A 1000 corresponding to circuit
breaker 1 (protection current)
Secondary rated value of CT
Prot.CB1.I2n 1 or 5 A 1 corresponding to circuit
breaker 1 (protection current)
9
Primary rated value of CT
Prot.CB2.I1n 0~60000 1 A 1000 corresponding to circuit
breaker 2 (protection current)
Secondary rated value of CT
Prot.CB2.I2n 1 or 5 A 1 corresponding to circuit
breaker 2 (protection current)
Primary rated voltage of
UB1.Syn.U1n 0.00~1100.00 0.01 kV 220.00 busbar No.1 VT (synchronism
voltage, phase-to-phase

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 9 Settings

Name Range Step Unit Default Description

value)
Secondary rated voltage of
busbar No.1 VT (synchronism
UB1.Syn.U2n 1.00~500.00 0.01 V 100.00
voltage, phase-to-phase
value)
Primary rated voltage of line
No.2 VT (synchronism
UL2.Syn.U1n 0.00~1100.00 0.01 kV 220.00
voltage, phase-to-phase
value)
Secondary rated voltage of
line No.2 VT (synchronism
UL2.Syn.U2n 1.00~500.00 0.01 V 100.00
voltage, phase-to-phase
value)
Primary rated voltage of
busbar No.2 VT (synchronism
UB2.Syn.U1n 0.00~1100.00 0.01 kV 220.00
voltage, phase-to-phase
value)
Secondary rated voltage of
busbar No.2 VT (synchronism
UB2.Syn.U2n 1.00~500.00 0.01 V 100.00
voltage, phase-to-phase
value)
Primary rated value of CT
3I0Adj.I1n 0~60000 1 A 1000 (residual current for mutual
coupling compensation)
Secondary rated value of CT
3I0Adj.I2n 1 or 5 A 1 (residual current for mutual
coupling compensation)
It is used to adjust the current
polarity of CT corresponding
to circuit breaker 1.
Disabled
Prot.CB1.En_RevCT Disabled Disabled: keep connected
Enabled
current polarity unchanged

9 Enabled: make connected

current polarity reversed
It is used to adjust the current
polarity of CT corresponding
to circuit breaker 2.
Disabled
Prot.CB2.En_RevCT Disabled Disabled: keep connected
Enabled
current polarity unchanged
Enabled: make connected
current polarity reversed
Disabled It is used to adjust residual
3I0Adj.En_RevCT Disabled
Enabled current polarity from parallel

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 9 Settings

Name Range Step Unit Default Description

line.
Disabled: keep connected
current polarity unchanged
Enabled: make connected
current polarity reversed
Enabling/disabling VT connect
Disabled
Prot.En_VT Enabled to the device, which is used for
Enabled
protection calculation
Option of circuit breaker 1
configuration, and it should be
set as "NoVoltSel" if no
voltage selection is adopted.
NoVoltSel: no voltage
selection
NoVoltSel DblBusOneCB: one circuit
DblBusOneCB breaker for double busbar
CB1.VoltSel.Opt_CBConfig 3/2BusCB1 NoVoltSel 3/2BusCB1: bus 1 side circuit
3/2TieCB breaker for one and a half
3/2BusCB2 breakers
3/2TieCB: line side circuit
breaker for one and a half
breakers
3/2BusCB2: bus 2 side circuit
breaker for one and a half
breakers
Option of circuit breaker 2
configuration, and it should be
set as "NoVoltSel" if no
voltage selection is adopted.
NoVoltSel: no voltage
selection
NoVoltSel DblBusOneCB: one circuit

CB2.VoltSel.Opt_CBConfig
DblBusOneCB
3/2BusCB1 NoVoltSel
breaker for double busbar
3/2BusCB1: bus 1 side circuit
9
3/2TieCB breaker for one and a half
3/2BusCB2 breakers
3/2TieCB: line side circuit
breaker for one and a half
breakers
3/2BusCB2: bus 2 side circuit
breaker for one and a half
breakers

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 9 Settings

9.1.2 Device Settings

Access path: MainMenuSettingsGlobal SettingsDevice Settings

Name Range Step Unit Default Description

Enabling/disabling the debugging
Disabled port. Used for debugging tool
En_DebugPort Enabled
Enabled connection, program download,
variable debugging, etc.
Disabled
En_TelnetPort Disabled Enabling/disabling the Telnet port.
Enabled
Disabled Enabling/disabling connect to the
En_VirtualLCDPort Enabled
Enabled device via the software Teldevice
Ctrl_Password 000~999 1 111 The control password via local LCD
Disabled Override control password via local
En_NoCtrlPwd Disabled
Enabled LCD
It is used to enable/disable the
Disabled
En_PopupRecord_Blkd Disabled blocking function to automatic pop
Enabled
up of event records
It is used to enable/disable the
single line diagram (abbreviated as
SLD) to auto-scroll horizontally, so
as to display the whole diagram on
Disabled
En_AutoScroll_SLD Enabled the local HMI of this device. It's
Enabled
unnecessary to configure this
setting if there is no SLD, or the
whole SLD can be displayed
without scrolling.
This setting is used to set voltage
Un_BinaryInput 24~250 1 V 220
level of binary input module.
DC
Power supply mode of binary input
Opt_Pwr_BI AC50Hz DC
module
AC60Hz
This setting is used to set pickup

9
U_Pickup_BI 50.0%Un~80.0%Un 0.1 % 63.0
voltage of binary input module.
This setting is used to set dropoff
U_Dropoff_BI 50.0%Un~80.0%Un 0.1 % 55.0
voltage of binary input module.
Monitoring window of binary input
Mon_Window_Jitter 0.000~500.000 0.001 s 1
jitter processing
Times threshold to block binary
Num_Blk_Jitter 2~500000 1 10
input status change due to jitter
Blocking window of binary input
Blk_Window_Jitter 0.000~500.000 0.001 s 1
status change due to jitter
Num_Reblk_Jitter 1~500000 1 10 Times threshold to initiate

9-4 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

immediately another blocking
window of binary input status
change due to continuous jitter
It is used to enable/disable the jitter
Disabled
En_Jitter_Blk Disabled processing function in case of
Enabled
binary input voltage variation
It is used to enable/disable high-
power conducting mode.
Disabled
En_BICheckInstP Disabled The setting is invisible unless
Enabled
NR6604A or NR6611A is chosen.
Please refer to Section 6.5.3.

9.1.3 Communication Settings

9.1.3.1 General Communication Settings

Access path: MainMenuSettingsGlobal SettingsComm SettingsGeneral Comm

Settings

Name Range Step Unit Default Description

IP address of Ethernet
IP_LAN1 0.0.0.0~255.255.255.255 172.16.0.100
port A
Subnet mask of
Mask_LAN1 0.0.0.0~255.255.255.255 255.255.0.0
Ethernet port A
Disabled Put Ethernet port A into
En_LAN1 Enabled
Enabled service
IP address of Ethernet
IP_LAN2 0.0.0.0~255.255.255.255 172.17.0.100
port B
Subnet mask of
Mask_LAN2 0.0.0.0~255.255.255.255 255.255.0.0
Ethernet port B
Disabled Put Ethernet port B into
En_LAN2 Enabled
Enabled service
IP address of Ethernet
IP_LAN3 0.0.0.0~255.255.255.255 172.18.0.100
port C

Mask_LAN3 0.0.0.0~255.255.255.255 255.255.0.0

Subnet mask of 9
Ethernet port C
Disabled Put Ethernet port C into
En_LAN3 Disabled
Enabled service
IP address of Ethernet
IP_LAN4 0.0.0.0~255.255.255.255 172.19.0.100
port D
Subnet mask of
Mask_LAN4 0.0.0.0~255.255.255.255 255.255.0.0
Ethernet port D
Disabled Put Ethernet port D into
En_LAN4 Disabled
Enabled service

PCS-902S Line Distance Relay 9-5

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

IP address of the
Gateway 0.0.0.0~255.255.255.255 0.0.0.0
gateway (router)
4800
9600
19200
Baud_Printer bps 19200 Baud rate of printer port
38400
57600
115200
Enable/disable
Disabled
En_AutoPrint Disabled automatic printing
Enabled
function
Communication
protocol of rear RS-485
serial port 1.
IEC103
Protocol_RS485-1 IEC103 IEC103: IEC60870-5-
Modbus
103 protocol
Modbus: Modbus
protocol
Communication
protocol of rear RS-485
serial port 2.
IEC103
Protocol_RS485-2 IEC103 IEC103: IEC60870-5-
Modbus
103 protocol
Modbus: Modbus
protocol
4800
9600
19200 Baud rate of rear RS-
Baud_RS485-1 bps 19200
38400 485 serial port 1.
57600
115200
4800

9 9600
19200 Baud rate of rear RS-
Baud_RS485-2 bps 19200
38400 485 serial port 2.
57600
115200
Communication
address between the
Addr_RS485-1 1~254 1 100 device and the SCADA
or RTU via RS-485
serial port 1.
Addr_RS485-2 1~254 1 100 Communication

9-6 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

address between the
device and the SCADA
or RTU via RS-485
serial port 2.
The network mode of
Normal
the first group of ports
PRP
B01.Grp01.Opt_NetMode Normal (port 1 & port 2) of the
HSR
CPU module located in
Bond
slot No.1
Normal The network mode of
PRP the second group of
B01.Grp02.Opt_NetMode HSR Normal ports (port 3 & port 4) of
RSTP the CPU module
Bond located in slot No.1
The setting is used to
set IP address of syslog
server 01, and the
device can upload audit
log to syslog server.
The setting is invalid
unless cyber security is
IP_SyslogServer01 0.0.0.0~255.255.255.255 0.0.0.0 configured in the
device.
Syslog is a
communication
protocol for message
logging, it is used for
security auditing in this
device.
The setting is used to
set IP address of syslog
server 02, and the
device can upload audit
log to syslog server.
9
The setting is invalid
unless cyber security is
IP_SyslogServer02 0.0.0.0~255.255.255.255 0.0.0.0
configured in the
device.
Syslog is a
communication
protocol for message
logging, it is used for
security auditing in this

PCS-902S Line Distance Relay 9-7

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

device.
The setting is used to
set IP address of syslog
server 03, and the
device can upload audit
log to syslog server.
The setting is invalid
unless cyber security is
IP_SyslogServer03 0.0.0.0~255.255.255.255 0.0.0.0 configured in the
device.
Syslog is a
communication
protocol for message
logging, it is used for
security auditing in this
device.
The setting is used to
set IP address of syslog
server 04, and the
device can upload audit
log to syslog server.
The setting is invalid
unless cyber security is
IP_SyslogServer04 0.0.0.0~255.255.255.255 0.0.0.0 configured in the
device.
Syslog is a
communication
protocol for message
logging, it is used for
security auditing in this
device.
The setting is used to

9 configure the period to

send the heartbeat
messages to the syslog
server. If this setting is
configured as “0”, this
t_Send_Heartbeat_Syslog 0~14400 1 min 0
device will not send
heartbeat messages to
the syslog server.
If the interval between
two data messages is
more than the setting,

9-8 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

the heartbeat message
will be sent with the
time delay of this
setting.
This setting is used to
enable/disable the
whitelist function of this
device.
A whitelist is a list of IP
addresses that are
Disabled
En_IP_Whitelist Disabled granted access to a
Enabled
certain system or
protocol. When a
whitelist is used, all IP
addresses are denied
access, except those
included in the whitelist.
No.** IP address of the
whitelist. (**=01...16)
This setting is effective
IP**_Whitelist 0.0.0.0~255.255.255.255 0.0.0.0
only when the setting
[En_IP_Whitelist] is
enabled.
This setting is used to
enable/disable the ARP
(Address Resolution
Protocol) binding
Disabled
En_ARP_Bind Disabled function.
Enabled
ARP binding indicates
that the IP address is
bound with the MAC
address of this device.

9.1.3.2 IEC61850 Communication Settings 9

Access path: MainMenuSettingsGlobal SettingsComm SettingsIEC61850 Settings

Name Range Step Unit Default Description

The identification of the IED in IEC
61850 protocol.
It cannot be an empty string and
IEDNAME TEMPLATE
shall be unique within an SCL file.
IEDNAME should be less than 20
characters comprising letters or

PCS-902S Line Distance Relay 9-9

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

digits or underline ( _ ), and it is case
sensitive.
If this setting is modified, the IED
name in ".cid" file will be changed
simultaneously and vice versa.
If users need to support the quality
Disabled change upload function, this
En_Send_MMS_Qual_Chg Disabled
Enabled parameter should be set as
"Enabled"
It is used to select the MMS network
communication mode with SCADA
via network A and B of the device.
IEC61850: Network mode with IEC
61850 protocol. In this mode, the
instances of Report Control Block
(RCB) cannot be shared, so
different clients should use different
report instances to send reports.
The "IEC61850" mode is preferred
overseas.
GB32890: Network mode with
GB32890 standard. In this mode, for
IEC61850
Opt_DualNetMode_MMS IEC61850 different clients meeting the
GB32890
redundancy conditions of A and B
networks, if one client enables an
RCB instance, the device will only
send a report to the enabled client.
When the enabled client is
interrupted, another redundant
client will cancel and re-enable the
RCB instance, and the device will
send a report to the re-enabled

9 redundant client. The “GB32890”

mode is a special mode widely used
in China, which needs to be used
with clients supporting.
It is used to set the change detection
threshold for suddenly sending
Pcnt_Deadband 0~100.00 0.01 % 1 measurement value to the SCADA
via the device's Ethernet port using
IEC 61850
Measurement values zero drift
Threshold_ZeroDrift 0.001~0.500 0.001 0.02
suppression threshold

9-10 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Disabled It is used to enable/disable TCP port
En_IEC62351_TCP_Port Disabled
Enabled when using IEC62351 protocol
Disabled It is used to enable/disable TCP port
En_IEC61850_TCP_Port Enabled
Enabled when using IEC61850 protocol
Processing rules for establishing
connections to multiple clients with
the same IP address:
OnlyNew: It does not allow multiple
clients to use the same IP. The old
connection will be disconnected
when a new connection is
OnlyNew
successfully established.
Opt_Client_SameIP RefuseNew OnlyNew
RefuseNew: It does not allow
Multiple
multiple clients to use the same IP.
If an old connection already exists,
the new connection will be rejected.
Multiple: It allows multiple clients to
use the same IP and supports
establishing multiple connection
simultaneously.

9.1.3.3 IEC103 Communication Settings

Access path: MainMenuSettingsGlobal SettingsComm SettingsIEC103 Settings

Name Range Step Unit Default Description

The language of group
caption of IEC103
Current_Language protocol
Opt_Caption_103 Fixed_Chinese Current_Language It is recommended to be
Fixed_English set as "Fixed_Chinese" if
the device communicate
with SCADA in Chinese.
It is used to
enable/disable that the 9
device sends UDP
Disabled
En_Broadcast_LAN1 Disabled messages through
Enabled
Ethernet port A when
using NR network 103
protocol.
It is used to
Disabled enable/disable that the
En_Broadcast_LAN2 Disabled
Enabled device sends UDP
messages through

PCS-902S Line Distance Relay 9-11

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Ethernet port B when
using NR network 103
protocol.
It is used to
enable/disable that the
device sends UDP
Disabled
En_Broadcast_LAN3 Disabled messages through
Enabled
Ethernet port C when
using NR network 103
protocol.
It is used to
enable/disable that the
device sends UDP
Disabled
En_Broadcast_LAN4 Disabled messages through
Enabled
Ethernet port D when
using NR network 103
protocol.
This setting is used to set
the data format for
sending waveform list
using IEC 60870-5-103.
DisturbData
Format_Wave_Sent File DisturbData: Send the
File
waveform list in ASDU23
mode
File: Send the waveform
list in ASDU222 mode
It is used to set the
change detection
threshold for suddenly
sending measurement
Pcnt_Deadband_Net 0~100.00 0.01 % 1.00
value to the SCADA via
the device's Ethernet port

9 when using NR network

103 protocol.
It is used to set the time
period for sending the
measurement value to
Period_Measmt_Net 0~65535 1 s 30
SCADA via the device's
Ethernet port when using
NR network 103 protocol.
It is used to
Disabled
En_103_TCP&UDP_Port Enabled enable/disable the TCP
Enabled
port and the UDP port

9-12 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

when using NR network
103 protocol

9.1.3.4 DNP Communication Settings

Access path: MainMenuSettingsGlobal SettingsComm SettingsDNP Settings

Name Range Step Unit Default Description

The logic setting
to
Disabled enable/disable
En_TCP1_DNP Disabled
Enabled the No.1
network DNP
client
The local
address of the
Addr_Slave_TCP1_DNP 0~65519 1 2
No.1 network
DNP client
The master
address of the
Addr_Master_TCP1_DNP 0~65519 1 1
No.1 network
DNP client
The IP address
of the master of
IP_Master_TCP1_DNP 0.0.0.0~255.255.255.255 0.0.0.0 the No.1
network DNP
client
The
communication
Opt_Map_TCP1_DNP 0~4 1 0 map of the No.1
network DNP
client
The timeout of
the application
t_AppLayer_TCP1_DNP 1~5 1 s 3 layer of the No.1 9
network DNP
client
The heartbeat
time interval of
t_KeepAlive_TCP1_DNP 0~7200 1 s 120 the No.1
network DNP
client
Disabled The logic setting
En_UR_TCP1_DNP Disabled
Enabled to

PCS-902S Line Distance Relay 9-13

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

enable/disable
the UR
(Unsolicited
Response)
message
function of the
No.1 network
DNP client.
The setting is
used to
determine the
mode of sending
Class 1, 2, 3
events to the
master station
spontaneously.
Enabled: the
device's No.1
network DNP
client cannot
send Class 1, 2,
3 events to the
master station
spontaneously
unless the
Disabled
En_MsgCtrlUR_TCP1_DNP Enabled master station
Enabled
activate UR
reporting by
enabling
unsolicited
application
function

9 (Function code:
20).
Disabled: the
device's No.1
network DNP
client can
directly send
Class 1, 2, 3
events to the
master station
spontaneously.

9-14 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The online
retransmission
number for
sending the
Num_URRetry_TCP1_DNP 2~10 1 3
unsolicited
message of the
No.1 network
DNP client
The offline
retransmission
interval for
sending the
t_UROfflRetry_TCP1_DNP 1~5000 1 s 60
unsolicited
message of the
No.1 network
DNP client
The default
class level of the
"Binary Input" of
Class_BI_TCP1_DNP 0~3 1 1
the No.1
network DNP
client
The default
class level of the
"Analogue
Class_AI_TCP1_DNP 0~3 1 2
Input" of the
No.1 network
DNP client
The selection
timeout of the
remote control
t_Select_TCP1_DNP 0~240 1 s 30 and remote
adjustment
No.1 network
of
9
DNP client
The time interval
of the time
synchronization
t_TimeSynIntvl_TCP1_DNP 0~3600 1 s 180
function of the
No.1 network
DNP client
1-BISingleBit The "OBJ1"
Obj01DefltVar_TCP1_DNP 1-BISingleBit
2-BIWithStatus default variation

PCS-902S Line Distance Relay 9-15

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

of the No.1
network DNP
client
The "OBJ2"
1-BIChWoutT default variation
2-
Obj02DefltVar_TCP1_DNP 2-BIChWithAbsTime of the No.1
BIChWithAbsTime
3-BIChWithRelTime network DNP
client
1-AI32Int The "OBJ30"
2-AI16Int default variation
Obj30DefltVar_TCP1_DNP 3-AI32IntWoutF 3-AI32IntWoutF of the No.1
4-AI16IntWoutF network DNP
5-AI32Flt client
The "OBJ32"
1-AI32IntEvWoutT default variation
1-
Obj32DefltVar_TCP1_DNP 2-AI16IntEvWoutT of the No.1
AI32IntEvWoutT
5-AI32FltEvWoutT network DNP
client
The "OBJ40"
1-AO32Int default variation
Obj40DefltVar_TCP1_DNP 2-AO16Int 1-AO32Int of the No.1
3-AO32Flt network DNP
client
The logic setting
to
Disabled enable/disable
En_TCP2_DNP Disabled
Enabled the No.2
network DNP
client
The local
address of the
Addr_Slave_TCP2_DNP 0~65519 1 2
No.2 network

9 DNP client
The master
address of the
Addr_Master_TCP2_DNP 0~65519 1 1
No.2 network
DNP client
The IP address
of the master of
IP_Master_TCP2_DNP 0.0.0.0~255.255.255.255 0.0.0.0 the No.2
network DNP
client
Opt_Map_TCP2_DNP 0~4 1 0 The

9-16 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

communication
map of the No.2
network DNP
client
The timeout of
the application
t_AppLayer_TCP2_DNP 1~5 1 s 3 layer of the No.2
network DNP
client
The heartbeat
time interval of
t_KeepAlive_TCP2_DNP 0~7200 1 s 120 the No.2
network DNP
client
The logic setting
to
enable/disable
the UR
Disabled (Unsolicited
En_UR_TCP2_DNP Disabled
Enabled Response)
message
function of the
No.2 network
DNP client.
The setting is
used to
determine the
mode of sending
Class 1, 2, 3
events to the
master station
spontaneously.

En_MsgCtrlUR_TCP2_DNP
Disabled
Enabled
Enabled:
device's
the
No.2
9
Enabled
network DNP
client cannot
send Class 1, 2,
3 events to the
master station
spontaneously
unless the
master station
activate UR

PCS-902S Line Distance Relay 9-17

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

reporting by
enabling
unsolicited
application
function
(Function code:
20).
Disabled: the
device's No.2
network DNP
client can
directly send
Class 1, 2, 3
events to the
master station
spontaneously.
The online
retransmission
number for
sending the
Num_URRetry_TCP2_DNP 2~10 1 3
unsolicited
message of the
No.2 network
DNP client
The offline
retransmission
interval for
sending the
t_UROfflRetry_TCP2_DNP 1~5000 1 s 60
unsolicited
message of the
No.2 network
DNP client

9 The default
class level of the
"Binary Input" of
Class_BI_TCP2_DNP 0~3 1 1
the No.2
network DNP
client
The default
class level of the
Class_AI_TCP2_DNP 0~3 1 2 "Analogue
Input" of the
No.2 network

9-18 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

DNP client
The selection
timeout of the
remote control
t_Select_TCP2_DNP 0~240 1 s 30 and remote
adjustment of
No.2 network
DNP client
The time interval
of the time
synchronization
t_TimeSynIntvl_TCP2_DNP 0~3600 1 s 180
function of the
No.2 network
DNP client
The "OBJ1"
default variation
1-BISingleBit
Obj01DefltVar_TCP2_DNP 1-BISingleBit of the No.2
2-BIWithStatus
network DNP
client
The "OBJ2"
1-BIChWoutT default variation
2-
Obj02DefltVar_TCP2_DNP 2-BIChWithAbsTime of the No.2
BIChWithAbsTime
3-BIChWithRelTime network DNP
client
1-AI32Int The "OBJ30"
2-AI16Int default variation
Obj30DefltVar_TCP2_DNP 3-AI32IntWoutF 3-AI32IntWoutF of the No.2
4-AI16IntWoutF network DNP
5-AI32Flt client
The "OBJ32"
1-AI32IntEvWoutT default variation
1-
Obj32DefltVar_TCP2_DNP 2-AI16IntEvWoutT of the No.2
AI32IntEvWoutT
5-AI32FltEvWoutT network
client
DNP
9
The "OBJ40"
1-AO32Int default variation
Obj40DefltVar_TCP2_DNP 2-AO16Int 1-AO32Int of the No.2
3-AO32Flt network DNP
client
The logic setting
Disabled to
En_TCP3_DNP Disabled
Enabled enable/disable
the No.3

PCS-902S Line Distance Relay 9-19

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

network DNP
client
The local
address of the
Addr_Slave_TCP3_DNP 0~65519 1 2
No.3 network
DNP client
The master
address of the
Addr_Master_TCP3_DNP 0~65519 1 1
No.3 network
DNP client
The IP address
of the master of
IP_Master_TCP3_DNP 0.0.0.0~255.255.255.255 0.0.0.0 the No.3
network DNP
client
The
communication
Opt_Map_TCP3_DNP 0~4 1 0 map of the No.3
network DNP
client
The timeout of
the application
t_AppLayer_TCP3_DNP 1~5 1 s 3 layer of the No.3
network DNP
client
The heartbeat
time interval of
t_KeepAlive_TCP3_DNP 0~7200 1 s 120 the No.3
network DNP
client
The logic setting
to

9 enable/disable
the UR
Disabled (Unsolicited
En_UR_TCP3_DNP Disabled
Enabled Response)
message
function of the
No.3 network
DNP client.
The setting is
Disabled
En_MsgCtrlUR_TCP3_DNP Enabled used to
Enabled
determine the

9-20 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

mode of sending
Class 1, 2, 3
events to the
master station
spontaneously.
Enabled: the
device's No.3
network DNP
client cannot
send Class 1, 2,
3 events to the
master station
spontaneously
unless the
master station
activate UR
reporting by
enabling
unsolicited
application
function
(Function code:
20).
Disabled: the
device's No.3
network DNP
client can
directly send
Class 1, 2, 3
events to the
master station
spontaneously.
The online
retransmission
9
number for
sending the
Num_URRetry_TCP3_DNP 2~10 1 3
unsolicited
message of the
No.3 network
DNP client
The offline
t_UROfflRetry_TCP3_DNP 1~5000 1 s 60 retransmission
interval for

PCS-902S Line Distance Relay 9-21

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

sending the
unsolicited
message of the
No.3 network
DNP client
The default
class level of the
"Binary Input" of
Class_BI_TCP3_DNP 0~3 1 1
the No.3
network DNP
client
The default
class level of the
"Analogue
Class_AI_TCP3_DNP 0~3 1 2
Input" of the
No.3 network
DNP client
The selection
timeout of the
remote control
t_Select_TCP3_DNP 0~240 1 s 30 and remote
adjustment of
No.3 network
DNP client
The time interval
of the time
synchronization
t_TimeSynIntvl_TCP3_DNP 0~3600 1 s 180
function of the
No.3 network
DNP client
The "OBJ1"
default variation
1-BISingleBit
9 Obj01DefltVar_TCP3_DNP
2-BIWithStatus
1-BISingleBit of
network
the No.3
DNP
client
The "OBJ2"
1-BIChWoutT default variation
2-
Obj02DefltVar_TCP3_DNP 2-BIChWithAbsTime of the No.3
BIChWithAbsTime
3-BIChWithRelTime network DNP
client
1-AI32Int The "OBJ30"
Obj30DefltVar_TCP3_DNP 2-AI16Int 3-AI32IntWoutF default variation
3-AI32IntWoutF of the No.3

9-22 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

4-AI16IntWoutF network DNP
5-AI32Flt client
The "OBJ32"
1-AI32IntEvWoutT default variation
1-
Obj32DefltVar_TCP3_DNP 2-AI16IntEvWoutT of the No.3
AI32IntEvWoutT
5-AI32FltEvWoutT network DNP
client
The "OBJ40"
1-AO32Int default variation
Obj40DefltVar_TCP3_DNP 2-AO16Int 1-AO32Int of the No.3
3-AO32Flt network DNP
client
The logic setting
to
Disabled enable/disable
En_TCP4_DNP Disabled
Enabled the No.4
network DNP
client
The local
address of the
Addr_Slave_TCP4_DNP 0~65519 1 2
No.4 network
DNP client
The master
address of the
Addr_Master_TCP4_DNP 0~65519 1 1
No.4 network
DNP client
The IP address
of the master of
IP_Master_TCP4_DNP 0.0.0.0~255.255.255.255 0.0.0.0 the No.4
network DNP
client
The

Opt_Map_TCP4_DNP 0~4 1 0
communication
map of the No.4
9
network DNP
client
The timeout of
the application
t_AppLayer_TCP4_DNP 1~5 1 s 3 layer of the No.4
network DNP
client
The heartbeat
t_KeepAlive_TCP4_DNP 0~7200 1 s 120
time interval of

PCS-902S Line Distance Relay 9-23

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

the No.4
network DNP
client
The logic setting
to
enable/disable
the UR
Disabled (Unsolicited
En_UR_TCP4_DNP Disabled
Enabled Response)
message
function of the
No.4 network
DNP client.
The setting is
used to
determine the
mode of sending
Class 1, 2, 3
events to the
master station
spontaneously.
Enabled: the
device's No.4
network DNP
client cannot
send Class 1, 2,
3 events to the
Disabled master station
En_MsgCtrlUR_TCP4_DNP Enabled
Enabled spontaneously
unless the
master station
activate UR

9 reporting
enabling
by

unsolicited
application
function
(Function code:
20).
Disabled: the
device's No.4
network DNP
client can

9-24 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

directly send
Class 1, 2, 3
events to the
master station
spontaneously.
The online
retransmission
number for
sending the
Num_URRetry_TCP4_DNP 2~10 1 3
unsolicited
message of the
No.4 network
DNP client
The offline
retransmission
interval for
sending the
t_UROfflRetry_TCP4_DNP 1~5000 1 s 60
unsolicited
message of the
No.4 network
DNP client
The default
class level of the
"Binary Input" of
Class_BI_TCP4_DNP 0~3 1 1
the No.4
network DNP
client
The default
class level of the
"Analogue
Class_AI_TCP4_DNP 0~3 1 2
Input" of the
No.4 network
DNP client
The selection
9
timeout of the
remote control
t_Select_TCP4_DNP 0~240 1 s 30 and remote
adjustment of
No.4 network
DNP client
The time interval
t_TimeSynIntvl_TCP4_DNP 0~3600 1 s 180 of the time
synchronization

PCS-902S Line Distance Relay 9-25

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

function of the
No.4 network
DNP client
The "OBJ1"
default variation
1-BISingleBit
Obj01DefltVar_TCP4_DNP 1-BISingleBit of the No.4
2-BIWithStatus
network DNP
client
The "OBJ2"
1-BIChWoutT default variation
2-
Obj02DefltVar_TCP4_DNP 2-BIChWithAbsTime of the No.4
BIChWithAbsTime
3-BIChWithRelTime network DNP
client
1-AI32Int The "OBJ30"
2-AI16Int default variation
Obj30DefltVar_TCP4_DNP 3-AI32IntWoutF 3-AI32IntWoutF of the No.4
4-AI16IntWoutF network DNP
5-AI32Flt client
The "OBJ32"
1-AI32IntEvWoutT default variation
1-
Obj32DefltVar_TCP4_DNP 2-AI16IntEvWoutT of the No.4
AI32IntEvWoutT
5-AI32FltEvWoutT network DNP
client
The "OBJ40"
1-AO32Int default variation
Obj40DefltVar_TCP4_DNP 2-AO16Int 1-AO32Int of the No.4
3-AO32Flt network DNP
client

9.1.3.5 Modbus Communication Settings

Access path: MainMenuSettingsGlobal SettingsComm SettingsModbus Settings

Name Range Step Unit Default Description

9 En_Modbus_TCP_Port
Disabled
Enabled
It is used to enable/disable the TCP port when
Enabled using Modbus protocol

9.1.3.6 SV Communication Settings

Access path: MainMenuSettingsGlobal SettingsComm SettingsSV Settings

These settings will be invisible unless "Sampling Mode" is chosen as "B:

Non-conventional instrument transformer" by PCS-Studio. Please refer to

9-26 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

"MOT Selection in Application Manual".

Name Range Step Unit Default Description

SampleRate_SV 0~65535 1 4000 It is used to set sampling rate of SV.
It is backward time delay of SV
t_Dly_Interp_Net_SV 1500~15000 1 μs 2000
interpolation for networking mode.
It is backward time delay of SV
t_Dly_Interp_P2P_SV 600~1500 1 μs 850 interpolation for peer-to-peer (P2P)
mode.
The option of SV receiving mode.
NetMode
NetMode: networking mode
Opt_RecvMode_SV P2P P2P
P2P: peer-to-peer (P2P) mode
Resv
Resv: reserved
The option of sampling rate in mixed
sampling mode.
None: mixed sampling is disabled.
4k_50Hz: 4kHz SV sampling rate in
50Hz power system (i.e.: 80 samples
in fundamental power system).
None 4.8k_50Hz: 4.8kHz SV sampling rate
4k_50Hz in 50Hz power system (i.e.: 96
Opt_MixedSmpl None
4.8k_50Hz samples in fundamental power
4.8k_60Hz system).
4.8k_60Hz: 4.8kHz SV sampling rate
in 60Hz power system (i.e.: 80
samples in fundamental power
system).
This setting is available only in mixed
sampling mode.
It is backward interrupt point number
for mixed sampling mode (24
Num_Point_Interp_MixedSmpl 3~7 1 3 samples per cycle).
This setting is available only in mixed
sampling mode.
It is used to set the backward 9
compensation time for the mixed
sampling mode, so as to realize the
synchronization via tiny adjustment
t_Comp_Interp_MixedSmpl -100~100 1 μs 0 between SV sampling data and
conventional sampling data in the
mixed sampling mode.
This setting is available only in mixed
sampling mode.

PCS-902S Line Distance Relay 9-27

Date: 2023-08-01
 9 Settings

9.1.4 Disturbance Fault Recording Settings

Access path: MainMenuSettingsGlobal SettingsDFR Settings

Name Range Step Unit Default Description

Waveform recorded duration before the
RecDur_PreTrigDFR 0.000~1.000 0.001 s 0.100
trigger element operating
Waveform recorded duration after the
RecDur_PostFault 0.000~10.000 0.001 s 1.000
fault happens
The maximum waveform recorded
MaxRecDur_PostTrigDFR 0.000~10.000 0.001 s 10.000 duration after the trigger element
operating

9.1.5 Label Settings

Access path: MainMenuSettingsGlobal SettingsLabel Settings

Name Range Step Unit Default Description

The description setting of
Max. 30 GOOSE communication
Bxx.Name_**_GCommLink GOOSE_Link**
characters link** in the module
located in slot No.xx
The description setting of
Max. 30 SV communication link**
Bxx.Name_**_SVCommLink SV_Link**
characters in the module located in
slot No.xx

9.1.6 Clock Synchronization Settings

Access path: MainMenuSettingsGlobal SettingsClockSyn Settings

Name Range Step Unit Default Description

Conventional Select the time
Opt_TimeSyn SAS 1 NoTimeSyn synchronization mode of
NoTimeSyn the device.
The local time zone also
OffsetHour_UTC -12~12 8 refered to as the hour
9 offset hour from UTC
The offset minute of local
OffsetMinute_UTC 0~60 0
time from UTC
The IP address of the
server when SNTP time
IP_Server_SNTP 0.0.0.0~255.255.255.255 0.0.0.0
synchronization mode is
selected
The IP address of the
IP_StandbyServer_SNTP 0.0.0.0~255.255.255.255 0.0.0.0 standby server when
SNTP time

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 9 Settings

Name Range Step Unit Default Description

synchronization mode is
selected
Enabling/disabling
receive the SNTP
message as the backup
clock synchronization
source while hardware-
based clock (IRIG-B,
IEEE 1588 or PPS) is lost
when the setting
Enabled
En_ConvModeSNTP Disabled [OptTimeSyn] is
Disabled
configured as
"Conventional".
However, the alarm
"Alm_TimeSyn" will still
be issued, so as to
indicate the failure of the
conventional clock
synchronization.
The logic setting is used
Enabled to enable or disable
DST.En Disabled
Disabled Daylight Saving Time
(DST)
It is used to set the minute
offset of DST, i.e. the
DST.OffsetMinute 0~255 1 60
difference between DST
time and local time
Jan
Feb
Mar
Apr
May

DST.MonthInYear_Start
Jun
Jul
1 Mar
It is used to set the start
month of DST.
9
Aug
Sep
Oct
Nov
Dec
1st
2nd It is used to set the start
DST.WeekInMonth_Start 1 1st
3rd week of DST.
4th

PCS-902S Line Distance Relay 9-29

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Last
Sunday
Monday
Tuesday
It is used to set the start
DST.DayInWeek_Start Wednesday 1 Sunday
day of DST.
Thursday
Friday
Saturday
It is used to set the start
DST.HourInDay_Start 0~23 1 3
hour of DST.
Jan
Feb
Mar
Apr
May
Jun It is used to set the end
DST.MonthInYear_End 1 Oct
Jul month of DST.
Aug
Sep
Oct
Nov
Dec
1st
2nd
It is used to set the end
DST.WeekInMonth_End 3rd 1 1st
week of DST.
4th
Last
Sunday
Monday
Tuesday
It is used to set the end
DST.DayInWeek_End Wednesday 1 Sunday
day of DST.
Thursday

9 Friday
Saturday
It is used to set the end
DST.HourInDay_End 0~23 1 9
hour of DST.

1. [Opt_TimeSyn]

There are three selections for clock synchronization of the device, each selection includes different
time clock synchronization signals shown in the following table.

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 9 Settings

Option Description

IRIG-B: IRIG-B via serial port (RS-485 or TTL level) or BNC port (TTL level)

PPS: Pulse per second (PPS) via serial port (RS-485 or TTL level), BNC port (TTL
Conventional
level) or binary input

IEEE 1588: Clock message based on IEEE 1588 via Ethernet network

SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network
SAS
Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol

If the time synchronization function is not required, please select "NoTimeSyn". No

NoTimeSyn
clock synchronization alarm will be issued in this mode.

9.1.7 Supervision Settings

9.1.7.1 VT Circuit Supervision (VTS)

Access path: MainMenuSettingsGlobal SettingsSuperv Settings

Name Range Step Unit Default Description

Disabled
VTS.En Enabled Enabling/disabling VT circuit supervision
Enabled
Voltage selection for protection calculation from
Bus busbar VT or line VT
VTS.Opt_VT Bus
Bay Bus: busbar VT
Bay: bay VT
VTS.t_DPU 0.200~30.000 0.001 s 1.250 Pickup time delay of VT circuit supervision
VTS.t_DDO 0.200~30.000 0.001 s 10.000 Dropoff time delay of VT circuit supervision
Positive-sequence voltage setting of VT circuit
VTS.U1_Set 0.00~100.00 0.01 V 30.00
supervision
Zero-sequence voltage setting of VT circuit
VTS.3U0_Set 0.00~100.00 0.01 V 8.00
supervision
Negative-sequence voltage setting of VT circuit
VTS.U2_Set 0.00~100.00 0.01 V 8.00
supervision

9.1.7.2 CT Circuit Supervision (CTS)

9
Access path: MainMenuSettingsGlobal SettingsSuperv Settings

Name Range Step Unit Default Description

Zero-sequence current setting of CT circuit
CBx.CTS.3I0_Set 0.00~200.00 0.01 A 0.10
supervision
Zero-sequence voltage setting of CT circuit
CBx.CTS.3U0_Set 0.00~200.00 0.01 V 30.00
supervision
CBx.CTS.t_DPU 0.000~100.000 0.001 s 10.000 Pickup time delay of CT circuit supervision
CBx.CTS.t_DDO 0.000~100.000 0.001 s 10.000 Dropoff time delay of CT circuit supervision

PCS-902S Line Distance Relay 9-31

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Disabled
CBx.CTS.En Enabled Enabling/disabling CT circuit supervision
Enabled

9.2 Protection Settings

9.2.1 Fault Detector (FD)
Access path: MainMenuSettingsProtection SettingsFD Settings

Name Range Step Unit Default Description

Current setting of DPFC current fault
FD.DPFC.I_Set (0.050~40.000)×In 0.001 A 0.100
detector element
Current setting of residual current
FD.ROC.3I0_Set (0.050~40.000)×In 0.001 A 0.100
fault detector element
Current setting of negative-sequence
FD.NOC.I2_Set (0.050~40.000)×In 0.001 A 0.100
current fault detector element
Enabling/disabling negative-
Disabled
FD.NOC.En Enabled sequence current fault detector
Enabled
element

9.2.2 Optical Pilot Channel (FO)

Access path: MainMenuSettingsProtection SettingsRmt CommCh Settings

Name Range Step Unit Default Description

FO.LocID 0~65535 1 1 Identity code of the device at local end

FO.RmtID 0~65535 1 2 Identity code of the device at remote end

64
FO.BaudRate kbps 2048 Baud rate of optical pilot channel
2048

G.703
FO.Protocol C37.94 It is used to select protocol type, G.703 or C37.94
C37.94

The setting for the times of 64kbits/s, which is an

FOx.Nx64k_C37.94 1~12 1 12 N×64kbits/s standard defined by IEEE C37.94
standard
9 Ext
Option of internal clock or external clock
FOx.Opt_ClkSrc Int Ext: external clock
Int
Int: internal clock
Disabled
FOx.En Enabled Enabling/disabling channel x
Enabled

9.2.3 Pilot Distance Protection (85)

Access path: MainMenuSettingsProtection SettingsPilot Scheme Settings

Name Range Step Unit Default Description

85.Opt_Mode POTT POTT Option of pilot scheme

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 9 Settings

Name Range Step Unit Default Description

PUTT
Blocking
Disabled Enabling/disabling phase-
85.En_Ch_PhSeg Disabled
Enabled segregated signal scheme
Disabled Enabling/disabling weak infeed
85.En_WI Disabled
Enabled scheme
Undervoltage setting of weak
85.U_UV_WI 0.000~200.000 0.001 V 50.000
infeed logic
Enabling/disabling the device
pick up at weak infeed end.
Disabled For weak infeed end, If the
85.En_WI_Pkp Disabled
Enabled device does not pick up for
internal fault, it is used to enable
the device pick up.
Enabling/disabling sending
Disabled
85.En_Trp_Send Enabled permissive signal controlled by
Enabled
the device operating
Enabling/disabling sending
Disabled
85.En_PilotTrp_Send Enabled permissive signal controlled by
Enabled
pilot protection operating
Enabling/disabling sending
Disabled
85.En_52b_Send Enabled permissive signal controlled by
Enabled
CB open position
Enabling/disabling sending
Disabled permissive signal of CB echo
85.En_52b_Echo Enabled
Enabled logic controlled by CB open
position
Disabled Enabling/disabling pilot distance
85.Z.En Enabled
Enabled protection
Disabled Enabling/disabling unblocking
85.En_Unblocking1 Disabled
Enabled scheme
Phase-to-phase
Phase-to- Option of PLC channel for pilot
85.Opt_Ch1 Phase-to-
ground
ground channel 1 9
Pickup time delay of unblocking
85.t_Unblocking1 0.000~10.000 0.001 s 0.100
scheme for pilot channel 1
Time delay for blocking scheme
85.t_DPU_Blocking1 0.000~1.000 0.001 s 0.100 of pilot distance protection
operation
Pickup time delay of current
85.t_DPU_CR1 0.000~1.000 0.001 s 0.025
reversal logic
Dropout time delay of current
85.t_DDO_CR1 0.000~1.000 0.001 s 0.025
reversal logic

PCS-902S Line Distance Relay 9-33

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling zone
Disabled
85.ZX.En Enabled extension of pilot distance
Enabled
protection
Pickup time delay for zone
85.t_DPU_ZX 0.000~10.000 0.001 s 0.000 extension of pilot distance
protection

9.2.4 Pilot Directional Earth-fault Protection (85)

Access path: MainMenuSettingsProtection SettingsPilot Scheme Settings

Name Range Step Unit Default Description

Disabled Enabling/disabling pilot directional
85.DEF.En Enabled
Enabled earth-fault protection
Enabling/disabling pilot directional
earth-fault protection operate to block
AR
Disabled
85.DEF.En_BlkAR Enabled Disabled: selective phase tripping and
Enabled
not blocking AR
Enabled: three-phase tripping and
blocking AR
Enabling/disabling independent
channel for pilot directional earth-fault
protection
Disabled Disabled: pilot directional earth-fault
85.DEF.En_IndepCh Enabled
Enabled protection sharing same channel with
pilot distance protection
Enabled: pilot directional earth-fault
adopting independent pilot channel
Disabled Enabling/disabling unblocking scheme
85.En_Unblocking2 Disabled
Enabled for pilot DEF via pilot channel 2
Pickup time delay of unblocking
85.t_Unblocking2 0.000~10.000 0.001 s 0.200
scheme for pilot channel 2
Zero-sequence current setting of pilot
9 85.DEF.3I0_Set (0.050~40.000)×In 0.001 A 0.200
directional earth-fault protection
Time delay of pilot directional earth-fault
85.DEF.t_DPU 0.000~10.000 0.001 s 0.150
protection
Time delay pickup for current reversal
logic when pilot directional earth-fault
85.t_DPU_CR2 0.000~1.000 0.001 s 0.025
protection adopts independent pilot
channel 2
Time delay dropoff for current reversal
85.t_DDO_CR2 0.000~1.000 0.001 s 0.025 logic when pilot directional earth-fault
protection adopts independent pilot

9-34 PCS-902S Line Distance Relay

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 9 Settings

Name Range Step Unit Default Description

channel 2

9.2.5 DPFC Distance Protection (21D)

Access path: MainMenuSettingsProtection SettingsDPFC Dist Settings

Name Range Step Unit Default Description

Impedance setting of DPFC distance
21D.Z_Set (0.000~4Unn)/In 0.001 Ω 5.000
protection
Impedance setting of DPFC distance
21D.Z_Overreach (0.000~4Unn)/In 0.001 Ω 10.000
protection with overreaching characteristic
Disabled
21D.En Enabled Enabling/disabling DPFC distance protection
Enabled

9.2.6 Distance Protection (21L)

Access path: MainMenuSettingsProtection SettingsDistProt Settings

Name Range Step Unit Default Description

The angle of directional line in the
second quadrant for quadrilateral
21L.Ang_Alpha 5~30 1 ° 15
phase-to-ground distance
element
The angle of directional line in the
fourth quadrant for quadrilateral
21L.Ang_Beta 5~30 1 ° 15
phase-to-ground distance
element
Phase-to-ground angle setting of
load trapezoid characteristics, it
should be set according to the
21L.LoadEnch.ZG.phi 5~50 1 ° 12
maximum load area angle
(φLoad_Max), φLoad_Max+5° is
recommended.
Phase-to-ground resistance
setting of load trapezoid

21L.LoadEnch.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 40.000

characteristics, it should be set 9
according to the minimum load
resistance, 70%~90% minimum
load resistance is recommended.
Phase-to-phase angle setting of
load trapezoid characteristics, it
should be set according to the
21L.LoadEnch.ZP.phi 5~50 1 ° 12
maximum load area angle
(φLoad_Max), φLoad_Max+5° is
recommended.

PCS-902S Line Distance Relay 9-35

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Phase-to-phase resistance
setting of load trapezoid
characteristics, it should be set
21L.LoadEnch.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 40.000
according to the minimum load
resistance, 70%~90% minimum
load resistance is recommended.
Current setting for power swing
21L.I_PSBR (0.050~40.000)×In 0.001 A 1.000
blocking releasing
Mho Characteristics option of phase-
21L.ZG.Opt_Characteristic Mho
Quad to-ground distance element
Mho Characteristics option of phase-
21L.ZP.Opt_Characteristic Mho
Quad to-phase distance element
Real component of zero-
sequence compensation
21L1.Real_K0 -4.000~4.000 0.001 0.660
coefficient for zone 1 of distance
protection
Imaginary component of zero-
sequence compensation
21L1.Imag_K0 -4.000~4.000 0.001 0.000
coefficient for zone 1 of distance
protection
Phase angle of positive-
21L1.phi1_Reach 30~89 1 ° 78 sequence impedance for zone 1
of distance protection
Downward offset angle of the
reactance line for zone 1 of
21L1.ZG.RCA 0~45 1 ° 12
phase-to-ground distance
element
Impedance setting of zone 1 of
21L1.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 phase-to-ground distance
element
Resistance setting of zone 1 of
21L1.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-ground

9 distance element
Shift resistance setting of zone 1
21L1.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Phase shift of zone 1 of phase-to-
21L1.ZG.phi_Shift 0~30 1 ° 0
ground distance element
Time delay of zone 1 of phase-to-
21L1.ZG.t_Op 0.000~10.000 0.001 s 0.200
ground distance element
Enabling/disabling zone 1 of
Disabled
21L1.ZG.En Enabled phase-to-ground distance
Enabled
element

9-36 PCS-902S Line Distance Relay

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 9 Settings

Name Range Step Unit Default Description

Enabling/disabling zone 1 of
Disabled
21L1.ZG.En_BlkAR Disabled phase-to-ground distance
Enabled
element operating to block AR
Enabling/disabling zone 1 of
Disabled phase-to-ground distance
21L1.ZG.En_3I0 Enabled
Enabled element controlled by residual
current fault detector element
Enabling/disabling zone 1 of
phase-to-ground distance
Disabled
21L1.ZG.En_NeuDir_Blk Enabled element blocked by direction
Enabled
control element of earth fault
protection
Enabling/disabling zone 1 of
phase-to-ground distance
Disabled
21L1.ZG.En_NegDir_Blk Enabled element blocked by direction
Enabled
control element of negative-
sequence overcurrent protection
Enabling/disabling phase-to-
Disabled ground load trapezoid
21L1.LoadEnch.ZG.En Enabled
Enabled characteristics for zone 1 of
distance protection
Downward offset angle of the
21L1.ZP.RCA 0~45 1 ° 12 reactance line for zone 1 of
phase-to-phase distance element
Impedance setting of zone 1 of
21L1.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000
phase-to-phase distance element
Resistance setting of zone 1 of
21L1.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-phase
distance element
Shift resistance setting of zone 1
21L1.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element

21L1.ZP.phi_Shift 0~30 1 ° 0
Phase shift of zone 1 of phase-to-
phase distance element
9
Time delay of zone 1 of phase-to-
21L1.ZP.t_Op 0.000~10.000 0.001 s 0.200
phase distance element
Disabled Enabling/disabling zone 1 of
21L1.ZP.En Enabled
Enabled phase-to-phase distance element
Enabling/disabling zone 1 of
Disabled
21L1.ZP.En_BlkAR Disabled phase-to-phase distance element
Enabled
operating to block AR
Disabled Enabling/disabling zone 1 of
21L1.ZP.En_NegDir_Blk Enabled
Enabled phase-to-phase distance element

PCS-902S Line Distance Relay 9-37

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

blocked by direction control
element of negative-sequence
overcurrent protection
Enabling/disabling phase-to-
Disabled phase load trapezoid
21L1.LoadEnch.ZP.En Enabled
Enabled characteristics for zone 1 of
distance protection
Enabling/disabling zone 1 of
Disabled
21L1.En_PSBR Enabled distance protection controlled by
Enabled
PSBR
Enabling/disabling zone 1 of
Disabled
21L1.En_ReacLine Disabled distance protection controlled by
Enabled
the reactance line
Forward
Direction option for zone 2 of
21L2.DirMode Reverse Forward
distance protection
Non_Directional
Real component of zero-
sequence compensation
21L2.Real_K0 -4.000~4.000 0.001 0.660
coefficient for zone 2 of distance
protection
Imaginary component of zero-
sequence compensation
21L2.Imag_K0 -4.000~4.000 0.001 0.000
coefficient for zone 2 of distance
protection
Phase angle of positive-
21L2.phi1_Reach 30~89 1 ° 78 sequence impedance for zone 2
of distance protection
Downward offset angle of the
reactance line for zone 2 of
21L2.ZG.RCA 0~45 1 ° 12
phase-to-ground distance
element
Impedance setting of zone 2 of

9 21L2.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 phase-to-ground

element
distance

Shift impedance setting of zone 2

21L2.ZG.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Resistance setting of zone 2 of
21L2.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-ground
distance element
Shift resistance setting of zone 2
21L2.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element

9-38 PCS-902S Line Distance Relay

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 9 Settings

Name Range Step Unit Default Description

Phase shift of zone 2 of phase-to-
21L2.ZG.phi_Shift 0~30 1 ° 0
ground distance element
Time delay of zone 2 of phase-to-
21L2.ZG.t_Op 0.000~10.000 0.001 s 0.200
ground distance element
Short time delay of zone 2 of
21L2.ZG.t_ShortDly 0.000~10.000 0.001 s 0.100 phase-to-ground distance
element
Enabling/disabling zone 2 of
Disabled
21L2.ZG.En Enabled phase-to-ground distance
Enabled
element
Enabling/disabling zone 2 of
Disabled
21L2.ZG.En_BlkAR Disabled phase-to-ground distance
Enabled
element operating to block AR
Enabling/disabling zone 2 of
Disabled phase-to-ground distance
21L2.ZG.En_3I0 Enabled
Enabled element controlled by residual
current fault detector element
Enabling/disabling zone 2 of
phase-to-ground distance
Disabled
21L2.ZG.En_NeuDir_Blk Enabled element blocked by direction
Enabled
control element of earth fault
protection
Enabling/disabling zone 2 of
phase-to-ground distance
Disabled
21L2.ZG.En_NegDir_Blk Enabled element blocked by direction
Enabled
control element of negative-
sequence overcurrent protection
Enabling/disabling phase-to-
Disabled ground load trapezoid
21L2.LoadEnch.ZG.En Enabled
Enabled characteristics for zone 2 of
distance protection
Downward offset angle of the
21L2.ZP.RCA 0~45 1 ° 12 reactance line for zone 2 of
phase-to-phase distance element
9
Impedance setting of zone 2 of
21L2.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000
phase-to-phase distance element
Shift impedance setting of zone 2
21L2.ZP.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Resistance setting of zone 2 of
21L2.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-phase
distance element
21L2.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 Shift resistance setting of zone 2

PCS-902S Line Distance Relay 9-39

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

of phase-to-phase distance
element
Phase shift of zone 2 of phase-to-
21L2.ZP.phi_Shift 0~30 1 ° 0
phase distance element
Time delay of zone 2 of phase-to-
21L2.ZP.t_Op 0.000~10.000 0.001 s 0.200
phase distance element
Short time delay of zone 2 of
21L2.ZP.t_ShortDly 0.000~10.000 0.001 s 0.100
phase-to-phase distance element
Disabled Enabling/disabling zone 2 of
21L2.ZP.En Enabled
Enabled phase-to-phase distance element
Enabling/disabling zone 2 of
Disabled
21L2.ZP.En_BlkAR Disabled phase-to-phase distance element
Enabled
operating to block AR
Enabling/disabling zone 2 of
phase-to-phase distance element
Disabled
21L2.ZP.En_NegDir_Blk Enabled blocked by direction control
Enabled
element of negative-sequence
overcurrent protection
Enabling/disabling phase-to-
Disabled phase load trapezoid
21L2.LoadEnch.ZP.En Enabled
Enabled characteristics for zone 2 of
distance protection
Enabling/disabling fixed
Disabled
21L2.En_ShortDly Disabled accelerate zone 2 of distance
Enabled
protection
Enabling/disabling zone 2 of
Disabled
21L2.En_PSBR Enabled distance protection controlled by
Enabled
PSBR
Enabling/disabling zone 2 of
Disabled
21L2.En_ReacLine Disabled distance protection controlled by
Enabled
the reactance line
Forward
Direction option for zone 3 of
9 21L3.DirMode Reverse
Non_Directional
Forward
distance protection

Real component of zero-

sequence compensation
21L3.Real_K0 -4.000~4.000 0.001 0.660
coefficient for zone 3 of distance
protection
Imaginary component of zero-
sequence compensation
21L3.Imag_K0 -4.000~4.000 0.001 0.000
coefficient for zone 3 of distance
protection
21L3.phi1_Reach 30~89 1 ° 78 Phase angle of positive-

9-40 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

sequence impedance for zone 3
of distance protection
Downward offset angle of the
reactance line for zone 3 of
21L3.ZG.RCA 0~45 1 ° 12
phase-to-ground distance
element
Impedance setting of zone 3 of
21L3.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 phase-to-ground distance
element
Shift impedance setting of zone 3
21L3.ZG.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Resistance setting of zone 2 of
21L3.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-ground
distance element
Shift resistance setting of zone 3
21L3.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Phase shift of zone 3 of phase-to-
21L3.ZG.phi_Shift 0~30 1 ° 0
ground distance element
Time delay of zone 2 of phase-to-
21L3.ZG.t_Op 0.000~10.000 0.001 s 0.200
ground distance element
Short time delay of zone 3 of
21L3.ZG.t_ShortDly 0.000~10.000 0.001 s 0.100 phase-to-ground distance
element
Enabling/disabling zone 3 of
Disabled
21L3.ZG.En Enabled phase-to-ground distance
Enabled
element
Enabling/disabling zone 3 of
Disabled
21L3.ZG.En_BlkAR Disabled phase-to-ground distance
Enabled
element operating to block AR
Enabling/disabling zone 3 of

21L3.ZG.En_3I0
Disabled
Enabled
Enabled
phase-to-ground distance
element controlled by residual
9
current fault detector element
Enabling/disabling zone 3 of
phase-to-ground distance
Disabled
21L3.ZG.En_NeuDir_Blk Enabled element blocked by direction
Enabled
control element of earth fault
protection
Enabling/disabling zone 3 of
Disabled
21L3.ZG.En_NegDir_Blk Enabled phase-to-ground distance
Enabled
element blocked by direction

PCS-902S Line Distance Relay 9-41

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

control element of negative-
sequence overcurrent protection
Enabling/disabling phase-to-
Disabled ground load trapezoid
21L3.LoadEnch.ZG.En Enabled
Enabled characteristics for zone 3 of
distance protection
Downward offset angle of the
21L3.ZP.RCA 0~45 1 ° 12 reactance line for zone 3 of
phase-to-phase distance element
Impedance setting of zone 3 of
21L3.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000
phase-to-phase distance element
Shift impedance setting of zone 3
21L3.ZP.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Resistance setting of zone 3 of
21L3.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-phase
distance element
Shift resistance setting of zone 3
21L3.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Phase shift of zone 3 of phase-to-
21L3.ZP.phi_Shift 0~30 1 ° 0
phase distance element
Time delay of zone 3 of phase-to-
21L3.ZP.t_Op 0.000~10.000 0.001 s 0.200
phase distance element
Short time delay of zone 3 of
21L3.ZP.t_ShortDly 0.000~10.000 0.001 s 0.100
phase-to-phase distance element
Disabled Enabling/disabling zone 3 of
21L3.ZP.En Enabled
Enabled phase-to-phase distance element
Enabling/disabling zone 3 of
Disabled
21L3.ZP.En_BlkAR Disabled phase-to-phase distance element
Enabled
operating to block AR
Enabling/disabling zone 3 of

9 21L3.ZP.En_NegDir_Blk
Disabled
Enabled
phase-to-phase distance element
blocked by direction control
Enabled
element of negative-sequence
overcurrent protection
Enabling/disabling phase-to-
Disabled phase load trapezoid
21L3.LoadEnch.ZP.En Enabled
Enabled characteristics for zone 3 of
distance protection
Enabling/disabling fixed
Disabled
21L3.En_ShortDly Disabled accelerate zone 3 of distance
Enabled
protection

9-42 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling zone 3 of
Disabled
21L3.En_PSBR Enabled distance protection controlled by
Enabled
PSBR
Enabling/disabling zone 3 of
Disabled
21L3.En_ReacLine Disabled distance protection controlled by
Enabled
the reactance line
Forward
Direction option for zone 4 of
21L4.DirMode Reverse Forward
distance protection
Non_Directional
Real component of zero-
sequence compensation
21L4.Real_K0 -4.000~4.000 0.001 0.660
coefficient for zone 4 of distance
protection
Imaginary component of zero-
sequence compensation
21L4.Imag_K0 -4.000~4.000 0.001 0.000
coefficient for zone 4 of distance
protection
Phase angle of positive-
21L4.phi1_Reach 30~89 1 ° 78 sequence impedance for zone 4
of distance protection
Downward offset angle of the
reactance line for zone 4 of
21L4.ZG.RCA 0~45 1 ° 12
phase-to-ground distance
element
Impedance setting of zone 4 of
21L4.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 phase-to-ground distance
element
Shift impedance setting of zone 4
21L4.ZG.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Resistance setting of zone 4 of
21L4.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-ground
distance element
Shift resistance setting of zone 4
9
21L4.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Phase shift of zone 4 of phase-to-
21L4.ZG.phi_Shift 0~30 1 ° 0
ground distance element
Time delay of zone 4 of phase-to-
21L4.ZG.t_Op 0.000~10.000 0.001 s 0.200
ground distance element
Short time delay of zone 4 of
21L4.ZG.t_ShortDly 0.000~10.000 0.001 s 0.100 phase-to-ground distance
element

PCS-902S Line Distance Relay 9-43

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling zone 4 of
Disabled
21L4.ZG.En Enabled phase-to-ground distance
Enabled
element
Enabling/disabling zone 4 of
Disabled
21L4.ZG.En_BlkAR Disabled phase-to-ground distance
Enabled
element operating to block AR
Enabling/disabling zone 4 of
Disabled phase-to-ground distance
21L4.ZG.En_3I0 Enabled
Enabled element controlled by residual
current fault detector element
Enabling/disabling zone 4 of
phase-to-ground distance
Disabled
21L4.ZG.En_NeuDir_Blk Enabled element blocked by direction
Enabled
control element of earth fault
protection
Enabling/disabling zone 4 of
phase-to-ground distance
Disabled
21L4.ZG.En_NegDir_Blk Enabled element blocked by direction
Enabled
control element of negative-
sequence overcurrent protection
Enabling/disabling phase-to-
Disabled ground load trapezoid
21L4.LoadEnch.ZG.En Enabled
Enabled characteristics for zone 4 of
distance protection
Downward offset angle of the
21L4.ZP.RCA 0~45 1 ° 12 reactance line for zone 4 of
phase-to-phase distance element
Impedance setting of zone 4 of
21L4.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000
phase-to-phase distance element
Shift impedance setting of zone 4
21L4.ZP.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element

9 21L4.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000

Resistance setting of zone 4 of
quadrilateral phase-to-phase
distance element
Shift resistance setting of zone 4
21L4.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Phase shift of zone 4 of phase-to-
21L4.ZP.phi_Shift 0~30 1 ° 0
phase distance element
Time delay of zone 4 of phase-to-
21L4.ZP.t_Op 0.000~10.000 0.001 s 0.200
phase distance element
21L4.ZP.t_ShortDly 0.000~10.000 0.001 s 0.100 Short time delay of zone 4 of

9-44 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

phase-to-phase distance element
Disabled Enabling/disabling zone 4 of
21L4.ZP.En Enabled
Enabled phase-to-phase distance element
Enabling/disabling zone 4 of
Disabled
21L4.ZP.En_BlkAR Disabled phase-to-phase distance element
Enabled
operating to block AR
Enabling/disabling zone 4 of
phase-to-phase distance element
Disabled
21L4.ZP.En_NegDir_Blk Enabled blocked by direction control
Enabled
element of negative-sequence
overcurrent protection
Enabling/disabling phase-to-
Disabled phase load trapezoid
21L4.LoadEnch.ZP.En Enabled
Enabled characteristics for zone 4 of
distance protection
Enabling/disabling fixed
Disabled
21L4.En_ShortDly Disabled accelerate zone 4 of distance
Enabled
protection
Enabling/disabling zone 4 of
Disabled
21L4.En_PSBR Enabled distance protection controlled by
Enabled
PSBR
Enabling/disabling zone 4 of
Disabled
21L4.En_ReacLine Disabled distance protection controlled by
Enabled
the reactance line
Forward
Direction option for zone 5 of
21L5.DirMode Reverse Forward
distance protection
Non_Directional
Real component of zero-
sequence compensation
21L5.Real_K0 -4.000~4.000 0.001 0.660
coefficient for zone 5 of distance
protection
Imaginary component of zero-

21L5.Imag_K0 -4.000~4.000 0.001 0.000

sequence compensation
coefficient for zone 5 of distance
9
protection
Phase angle of positive-
21L5.phi1_Reach 30~89 1 ° 78 sequence impedance for zone 5
of distance protection
Downward offset angle of the
reactance line for zone 5 of
21L5.ZG.RCA 0~45 1 ° 12
phase-to-ground distance
element
21L5.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 Impedance setting of zone 5 of

PCS-902S Line Distance Relay 9-45

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

phase-to-ground distance
element
Shift impedance setting of zone 5
21L5.ZG.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Resistance setting of zone 5 of
21L5.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-ground
distance element
Shift resistance setting of zone 5
21L5.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Phase shift of zone 5 of phase-to-
21L5.ZG.phi_Shift 0~30 1 ° 0
ground distance element
Time delay of zone 5 of phase-to-
21L5.ZG.t_Op 0.000~10.000 0.001 s 0.200
ground distance element
Short time delay of zone 5 of
21L5.ZG.t_ShortDly 0.000~10.000 0.001 s 0.100 phase-to-ground distance
element
Enabling/disabling zone 5 of
Disabled
21L5.ZG.En Enabled phase-to-ground distance
Enabled
element
Enabling/disabling zone 5 of
Disabled
21L5.ZG.En_BlkAR Disabled phase-to-ground distance
Enabled
element operating to block AR
Enabling/disabling zone 5 of
Disabled phase-to-ground distance
21L5.ZG.En_3I0 Enabled
Enabled element controlled by residual
current fault detector element
Enabling/disabling zone 5 of
phase-to-ground distance
Disabled
21L5.ZG.En_NeuDir_Blk Enabled element blocked by direction
Enabled
control element of earth fault

9 protection
Enabling/disabling zone 5 of
phase-to-ground distance
Disabled
21L5.ZG.En_NegDir_Blk Enabled element blocked by direction
Enabled
control element of negative-
sequence overcurrent protection
Enabling/disabling phase-to-
Disabled ground load trapezoid
21L5.LoadEnch.ZG.En Enabled
Enabled characteristics for zone 5 of
distance protection
21L5.ZP.RCA 0~45 1 ° 12 Downward offset angle of the

9-46 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

reactance line for zone 5 of
phase-to-phase distance element
Impedance setting of zone 5 of
21L5.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000
phase-to-phase distance element
Shift impedance setting of zone 5
21L5.ZP.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Resistance setting of zone 5 of
21L5.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-phase
distance element
Shift resistance setting of zone 5
21L5.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Phase shift of zone 5 of phase-to-
21L5.ZP.phi_Shift 0~30 1 ° 0
phase distance element
Time delay of zone 5 of phase-to-
21L5.ZP.t_Op 0.000~10.000 0.001 s 0.200
phase distance element
Short time delay of zone 5 of
21L5.ZP.t_ShortDly 0.000~10.000 0.001 s 0.100
phase-to-phase distance element
Disabled Enabling/disabling zone 5 of
21L5.ZP.En Enabled
Enabled phase-to-phase distance element
Enabling/disabling zone 5 of
Disabled
21L5.ZP.En_BlkAR Disabled phase-to-phase distance element
Enabled
operating to block AR
Enabling/disabling zone 5 of
phase-to-phase distance element
Disabled
21L5.ZP.En_NegDir_Blk Enabled blocked by direction control
Enabled
element of negative-sequence
overcurrent protection
Enabling/disabling phase-to-
Disabled phase load trapezoid
21L5.LoadEnch.ZP.En Enabled
Enabled characteristics for zone 5 of
distance protection
Enabling/disabling fixed
9
Disabled
21L5.En_ShortDly Disabled accelerate zone 2 of distance
Enabled
protection
Enabling/disabling zone 5 of
Disabled
21L5.En_PSBR Enabled distance protection controlled by
Enabled
PSBR
Enabling/disabling zone 5 of
Disabled
21L5.En_ReacLine Disabled distance protection controlled by
Enabled
the reactance line
21L6.DirMode Forward Forward Direction option for zone 6 of

PCS-902S Line Distance Relay 9-47

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Reverse distance protection
Non_Directional
Real component of zero-
sequence compensation
21L6.Real_K0 -4.000~4.000 0.001 0.660
coefficient for zone 6 of distance
protection
Imaginary component of zero-
sequence compensation
21L6.Imag_K0 -4.000~4.000 0.001 0.000
coefficient for zone 6 of distance
protection
Phase angle of positive-
21L6.phi1_Reach 30~89 1 ° 78 sequence impedance for zone 6
of distance protection
Downward offset angle of the
reactance line for zone 6 of
21L6.ZG.RCA 0~45 1 ° 12
phase-to-ground distance
element
Impedance setting of zone 6 of
21L6.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 phase-to-ground distance
element
Shift impedance setting of zone 6
21L6.ZG.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Resistance setting of zone 6 of
21L6.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-ground
distance element
Shift resistance setting of zone 6
21L6.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-ground distance
element
Phase shift of zone 6 of phase-to-
21L6.ZG.phi_Shift 0~30 1 ° 0
ground distance element
Time delay of zone 6 of phase-to-
21L6.ZG.t_Op 0.000~10.000 0.001 s 0.200
9 ground distance element
Short time delay of zone 6 of
21L6.ZG.t_ShortDly 0.000~10.000 0.001 s 0.100 phase-to-ground distance
element
Enabling/disabling zone 6 of
Disabled
21L6.ZG.En Enabled phase-to-ground distance
Enabled
element
Enabling/disabling zone 6 of
Disabled
21L6.ZG.En_BlkAR Disabled phase-to-ground distance
Enabled
element operating to block AR
21L6.ZG.En_3I0 Disabled Enabled Enabling/disabling zone 6 of

9-48 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabled phase-to-ground distance
element controlled by residual
current fault detector element
Enabling/disabling zone 6 of
phase-to-ground distance
Disabled
21L6.ZG.En_NeuDir_Blk Enabled element blocked by direction
Enabled
control element of earth fault
protection
Enabling/disabling zone 6 of
phase-to-ground distance
Disabled
21L6.ZG.En_NegDir_Blk Enabled element blocked by direction
Enabled
control element of negative-
sequence overcurrent protection
Enabling/disabling phase-to-
Disabled ground load trapezoid
21L6.LoadEnch.ZG.En Enabled
Enabled characteristics for zone 6 of
distance protection
Downward offset angle of the
21L6.ZP.RCA 0~45 1 ° 12 reactance line for zone 6 of
phase-to-phase distance element
Impedance setting of zone 6 of
21L6.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000
phase-to-phase distance element
Shift impedance setting of zone 6
21L6.ZP.Z_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Resistance setting of zone 6 of
21L6.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000 quadrilateral phase-to-phase
distance element
Shift resistance setting of zone 6
21L6.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000 of phase-to-phase distance
element
Phase shift of zone 6 of phase-to-
21L6.ZP.phi_Shift 0~30 1 ° 0
phase distance element
Time delay of zone 6 of phase-to-
9
21L6.ZP.t_Op 0.000~10.000 0.001 s 0.200
phase distance element
Short time delay of zone 6 of
21L6.ZP.t_ShortDly 0.000~10.000 0.001 s 0.100
phase-to-phase distance element
Disabled Enabling/disabling zone 6 of
21L6.ZP.En Enabled
Enabled phase-to-phase distance element
Enabling/disabling zone 6 of
Disabled
21L6.ZP.En_BlkAR Disabled phase-to-phase distance element
Enabled
operating to block AR
21L6.ZP.En_NegDir_Blk Disabled Enabled Enabling/disabling zone 6 of

PCS-902S Line Distance Relay 9-49

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabled phase-to-phase distance element
blocked by direction control
element of negative-sequence
overcurrent protection
Enabling/disabling phase-to-
Disabled phase load trapezoid
21L6.LoadEnch.ZP.En Enabled
Enabled characteristics for zone 6 of
distance protection
Enabling/disabling fixed
Disabled
21L6.En_ShortDly Disabled accelerate zone 6 of distance
Enabled
protection
Enabling/disabling zone 6 of
Disabled
21L6.En_PSBR Enabled distance protection controlled by
Enabled
PSBR
Enabling/disabling zone 6 of
Disabled
21L6.En_ReacLine Disabled distance protection controlled by
Enabled
the reactance line

Name Range Step Unit Default Description

Real component of zero-
sequence compensation
21L.PilotFwd.Real_K0 -4.000~4.000 0.001 0.660
coefficient for forward pilot
distance zone
Imaginary component of
zero-sequence
21L.PilotFwd.Imag_K0 -4.000~4.000 0.001 0.000
compensation coefficient for
forward pilot distance zone
Phase angle of positive-
21L.PilotFwd.phi1_Reach 30~89 1 ° 78 sequence impedance for
forward pilot distance zone
Downward offset angle of the
reactance line for forward
21L.PilotFwd.ZG.RCA 0~45 1 ° 12
9 pilot distance zone (phase-to-
ground)
Impedance setting of forward
21L.PilotFwd.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
ground)
Resistance setting of
quadrilateral forward pilot
21L.PilotFwd.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
ground)
Shift resistance setting of
21L.PilotFwd.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
quadrilateral forward pilot

9-50 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

distance zone (phase-to-
ground)
Enabling/disabling forward
pilot distance zone controlled
Disabled
21L.PilotFwd.ZG.En_3I0 Enabled by residual current fault
Enabled
detector element (phase-to-
ground)
Enabling/disabling forward
pilot distance zone blocked
Disabled
21L.PilotFwd.ZG.En_NeuDir_Blk Enabled by direction control element
Enabled
of earth fault protection
(phase-to-ground)
Enabling/disabling forward
pilot distance zone blocked
Disabled by direction control element
21L.PilotFwd.ZG.En_NegDir_Blk Enabled
Enabled of negative-sequence
overcurrent protection
(phase-to-ground)
Enabling/disabling load
Disabled trapezoid characteristics for
21L.PilotFwd.LoadEnch.ZG.En Enabled
Enabled forward pilot distance zone
(phase-to-ground)
Downward offset angle of the
reactance line for forward
21L.PilotFwd.ZP.RCA 0~45 1 ° 12
pilot distance zone (phase-to-
phase)
Impedance setting of forward
21L.PilotFwd.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
phase)
Resistance setting of
quadrilateral forward pilot
21L.PilotFwd.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
phase)
Shift resistance setting of
9
quadrilateral forward pilot
21L.PilotFwd.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
phase)
Enabling/disabling forward
pilot distance zone blocked
Disabled by direction control element
21L.PilotFwd.ZP.En_NegDir_Blk Enabled
Enabled of negative-sequence
overcurrent protection
(phase-to-phase)

PCS-902S Line Distance Relay 9-51

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling load
Disabled trapezoid characteristics for
21L.PilotFwd.LoadEnch.ZP.En Enabled
Enabled forward pilot distance zone
(phase-to-phase)
Enabling/disabling forward
Disabled
21L.PilotFwd.En_PSBR Enabled pilot distance zone controlled
Enabled
by PSBR
Enabling/disabling forward
Disabled
21L.PilotFwd.En_ReacLine Disabled pilot distance zone controlled
Enabled
by the reactance line
Real component of zero-
sequence compensation
21L.PilotRev.Real_K0 -4.000~4.000 0.001 0.660
coefficient for reverse pilot
distance zone
Imaginary component of
zero-sequence
21L.PilotRev.Imag_K0 -4.000~4.000 0.001 0.000
compensation coefficient for
reverse pilot distance zone
Phase angle of positive-
21L.PilotRev.phi1_Reach 30~89 1 ° 78 sequence impedance for
reverse pilot distance zone
Downward offset angle of the
reactance line for reverse
21L.PilotRev.ZG.RCA 0~45 1 ° 12
pilot distance zone (phase-to-
ground)
Impedance setting of reverse
21L.PilotRev.ZG.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
ground)
Resistance setting of
quadrilateral reverse pilot
21L.PilotRev.ZG.R_Set (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
ground)

9 Shift resistance setting of

quadrilateral reverse pilot
21L.PilotRev.ZG.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
ground)
Enabling/disabling reverse
pilot distance zone controlled
Disabled
21L.PilotRev.ZG.En_3I0 Enabled by residual current fault
Enabled
detector element (phase-to-
ground)
Disabled Enabling/disabling load
21L.PilotRev.LoadEnch.ZG.En Enabled
Enabled trapezoid characteristics for

9-52 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

reverse pilot distance zone
(phase-to-ground)
Downward offset angle of the
reactance line for reverse
21L.PilotRev.ZP.RCA 0~45 1 ° 12
pilot distance zone (phase-to-
phase)
Impedance setting of reverse
21L.PilotRev.ZP.Z_Set (0.000~4Unn)/In 0.001 Ω 10.000 pilot distance zone (phase-to-
phase)
Resistance setting of
quadrilateral reverse pilot
21L.PilotRev.ZP.R_Set (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
phase)
Shift resistance setting of
quadrilateral reverse pilot
21L.PilotRev.ZP.R_Offset (0.000~4Unn)/In 0.001 Ω 10.000
distance zone (phase-to-
phase)
Enabling/disabling load
Disabled trapezoid characteristics for
21L.PilotRev.LoadEnch.ZP.En Enabled
Enabled reverse pilot distance zone
(phase-to-phase)
Enabling/disabling reverse
Disabled
21L.PilotRev.En_PSBR Enabled pilot distance zone controlled
Enabled
by PSBR
Enabling/disabling reverse
Disabled
21L.PilotRev.En_ReacLine Disabled pilot distance zone controlled
Enabled
by the reactance line

9.2.7 Out-of-step Protection (78)

Access path: MainMenuSettingsProtection SettingsOOS Settings

Name Range Step Unit Default Description

Disabled
78.En
Enabled
Enabled Enabling/disabling out-of-step protection
9
Disabled Enabling/disabling out-of-step protection
78.En_Trp Disabled
Enabled operate to trip
The forward impedance setting of zone detector
78.Z_Fwd (0.000~4Unn)/In 0.001 Ω 10.000
element
The reversal impedance setting of zone
78.Z_Rev (0.000~4Unn)/In 0.001 Ω 5.000
detector element
78.phi1_Reach 30~89 1 ° 78 The positive-sequence impedance angle
The minimum start angle, which generally
78.phi_Start 0~180 1 ° 60
should be greater than maximum load angle.

PCS-902S Line Distance Relay 9-53

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

It is the maximum tripping angle after out-of-
step protection operating, which is used to
prevent the circuit breaker from incorrect
78.phi_Trp 0~180 1 ° 90
operation due to too large current during
tripping. It is generally set based on the
breaking capacity of circuit breaker.
The number setting of out-of-step cycle, and it
78.N_Limit 1~20 1 1
is set as 2~3 generally

9.2.8 Distance SOTF Protection (21SOTF)

Access path: MainMenuSettingsProtection SettingsSOTF Settings

Name Range Step Unit Default Description

Time delay of enabling SOTF
protection (shared by distance
SOTF.t_En 0.200~100.000 0.001 s 0.400 SOTF protection, phase current
SOTF protection and residual
current SOTF protection)
Time delay of distance protection
21SOTF.t_ManCls 0.000~100.000 0.001 s 0.025 accelerating to trip when manual
closing
Time delay of distance protection
21SOTF.t_3PAR 0.000~100.000 0.001 s 0.025 accelerating to trip when 3-pole
reclosing
Time delay of distance protection
21SOTF.t_1PAR 0.000~100.000 0.001 s 0.025 accelerating to trip when 1-pole
reclosing
Disabled Enabling/disabling distance SOTF
21SOTF.En Enabled
Enabled protection
Enabling/disabling zone 2 of
Disabled
21SOTF.Z2.En_ManCls Enabled distance SOTF protection for
Enabled
manual closing
Enabling/disabling zone 3 of
9 21SOTF.Z3.En_ManCls
Disabled
Disabled distance SOTF protection for
Enabled
manual closing
Enabling/disabling zone 4 of
Disabled
21SOTF.Z4.En_ManCls Disabled distance SOTF protection for
Enabled
manual closing
Enabling/disabling zone 2 of
Disabled
21SOTF.Z2.En_3PAR Enabled distance SOTF protection for 3-pole
Enabled
reclosing
Disabled Enabling/disabling zone 3 of
21SOTF.Z3.En_3PAR Disabled
Enabled distance SOTF protection for 3-pole

9-54 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

reclosing
Enabling/disabling zone 4 of
Disabled
21SOTF.Z4.En_3PAR Disabled distance SOTF protection for 3-pole
Enabled
reclosing
Enabling/disabling zone 2
Disabled controlled by PSB of distance
21SOTF.Z2.En_PSBR Enabled
Enabled SOTF protection for 3-pole
reclosing
Enabling/disabling zone 3
Disabled controlled by PSB of distance
21SOTF.Z3.En_PSBR Enabled
Enabled SOTF protection for 3-pole
reclosing
Enabling/disabling zone 4
Disabled controlled by PSB of distance
21SOTF.Z4.En_PSBR Enabled
Enabled SOTF protection for 3-pole
reclosing
Enabling/disabling zone 2 of
Disabled
21SOTF.Z2.En_1PAR Enabled distance SOTF protection for 1-pole
Enabled
reclosing
Time delay of distance protection
21SOTF.t_PDF 0.000~100.000 0.001 s 0.025 operating under pole discrepancy
conditions
Enabling/disabling distance SOTF
Disabled
21SOTF.En_PDF Disabled protection under pole discrepancy
Enabled
conditions
Undervoltage setting of deadline
SOTF.U_Ddl 0.200~100.000 0.001 V 30.000
detection
SOTF.t_Ddl 0.000~100.000 0.001 s 15.000 Time delay of deadline detection
Option of manual SOTF mode
ManClsBI: initiated by input signal
of manual closing
ManClsBI CBPos: initiated by CB position

SOTF.Opt_Mode_ManCls
CBPos
ManClsBI/CBPos CBPos
ManClsBI/CBPos: initiated
either input signal of manual closing
by
9
AutoInit or CB position
All AutoInit: initiated by no voltage
detection
All: initiated by both binary input
and no voltage detection

9.2.9 Phase Overcurrent Protection (50/51P)

Access path: MainMenuSettingsProtection SettingsOC Settings

PCS-902S Line Distance Relay 9-55

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Low voltage setting
50/51P.VCE.Upp 10.000~100.000 0.001 V 70.000 of voltage control
element
Negative-sequence
voltage setting of
50/51P.VCE.U2 2.000~57.000 0.001 V 8.000
voltage control
element
Zero-sequence
voltage setting of
50/51P.VCE.3U0 2.000~57.000 0.001 V 8.000
voltage control
element
The characteristic
50/51P.DIR.RCA -180~179 1 ° 45 angle of direction
control element
The negative-
sequence
50/51P.DIR.RCA_NegOC -180~179 1 ° 45 characteristic angle
of direction control
element
The minimum
boundary in forward
50/51P.DIR.phi_Min_Fwd 10~90 1 ° 90 direction of phase
overcurrent
protection
The maximum
boundary in forward
50/51P.DIR.phi_Max_Fwd 10~90 1 ° 90 direction of phase
overcurrent
protection
The minimum
boundary in reverse
50/51P.DIR.phi_Min_Rev 10~90 1 ° 90 direction of phase

9 overcurrent
protection
The maximum
boundary in reverse
50/51P.DIR.phi_Max_Rev 10~90 1 ° 90 direction of phase
overcurrent
protection
U2 The voltage
Upp polarization mode of
50/51P.DIR.Opt_PolarizedVolt Upp
Up direction control
U1 element

9-56 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

U2: negative-
sequence voltage is
used as polarized
voltage
Upp: phase-to-
phase voltage is
used as polarized
voltage
Up: phase-to-ground
voltage is used as
polarized voltage
U1: positive-
sequence voltage is
used as polarized
The minimum
operating current
50/51P.DIR.I_Min (0.010~1.000)×In 0.001 A 0.050
setting of direction
control element
The minimum
operating voltage
50/51P.DIR.U_Min 1.000~10.000 0.001 V 4.000
setting of direction
control element
Enabling/disabling
phase overcurrent
protection is blocked
Disabled by VT circuit failure
50/51P.En_VTS_Blk Disabled
Enabled when VT circuit
supervision is
enabled and VT
circuit fails
The coefficient of
second harmonics of
50/51P.HMB.K_Hm2 0.100~1.000 0.001 0.200
harmonic
element
control
9
The current setting of
50/51P.HMB.I_Rls (2.000~30.000)×In 0.001 A 20.000 releasing harmonic
control element
The option of
harmonic blocking
PhaseBlk
mode
50/51P.HMB.Opt_Blk CrossBlk PhaseBlk
PhaseBlk: phase
MaxPhaseBlk
blocking
CrossBlk: cross

PCS-902S Line Distance Relay 9-57

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

blocking
MaxPhaseBlk:
maximum phase
blocking
The current setting
for stage 1 of phase
50/51P1.I_Set (0.050~40.000)×In 0.001 A 15.000
overcurrent
protection
The operating time
delay for stage 1 of
50/51P1.t_Op 0.000~100.000 0.001 s 0.100
phase overcurrent
protection
The dropout time
delay for stage 1 of
50/51P1.t_DropOut 0.000~100.000 0.001 s 0.000
phase overcurrent
protection
Enabling/disabling
stage 1 of phase
Disabled overcurrent
50/51P1.En_Volt_Blk Disabled
Enabled protection controlled
by voltage control
element
The option direction
Non_Directional characteristic for
50/51P1.Opt_Dir Forward Non_Directional stage 1 of phase
Reverse overcurrent
protection
Enabling/disabling
stage 1 of phase
Disabled overcurrent
50/51P1.En_Hm_Blk Disabled
Enabled protection controlled
by harmonic control

9 element
Enabling/disabling
Disabled stage 1 of phase
50/51P1.En Enabled
Enabled overcurrent
protection
Enabling/disabling
stage 1 of phase
Trp overcurrent
50/51P1.Opt_Trp/Alm Trp
Alm protection operate to
trip or alarm
Trp: for tripping

9-58 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE The option of
ANSILTV operating
ANSILT characteristics curve
50/51P1.Opt_Curve IECDefTime
IECN for stage 1 of phase
IECV overcurrent
IECI protection
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 1 of phase
overcurrent
protection
Inst Inst: instantaneous
50/51P1.Opt_Curve_DropOut DefTime Inst dropout
IDMT characteristics
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
9
Time multiplier
setting for stage 1 of
50/51P1.TMS 0.040~20.000 0.001 1.000 inverse-time phase
overcurrent
protection
The minimum
operating time for
50/51P1.tmin 0.000~10.000 0.001 s 0.020
stage 1 of inverse-
time phase

PCS-902S Line Distance Relay 9-59

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

overcurrent
protection
The constant “K” for
stage 1 of
customized inverse-
50/51P1.K 0.0010~120.0000 0.0001 0.1400
time phase
overcurrent
protection
The constant “α” for
stage 1 of
customized inverse-
50/51P1.Alpha 0.0100~3.0000 0.0001 0.0200
time phase
overcurrent
protection
The constant “C” for
stage 1 of
customized inverse-
50/51P1.C 0.0000~1.2000 0.0001 0.0000
time phase
overcurrent
protection
The current setting
for stage 2 of phase
50/51P2.I_Set (0.050~40.000)×In 0.001 A 15.000
overcurrent
protection
The operating time
delay for stage 2 of
50/51P2.t_Op 0.000~100.000 0.001 s 0.100
phase overcurrent
protection
The dropout time
delay for stage 2 of
50/51P2.t_DropOut 0.000~100.000 0.001 s 0.000
phase overcurrent
protection

9 Enabling/disabling
stage 2 of phase
Disabled overcurrent
50/51P2.En_Volt_Blk Disabled
Enabled protection controlled
by voltage control
element
The option direction
Non_Directional characteristic for
50/51P2.Opt_Dir Forward Non_Directional stage 2 of phase
Reverse overcurrent
protection

9-60 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling
stage 2 of phase
Disabled overcurrent
50/51P2.En_Hm_Blk Disabled
Enabled protection controlled
by harmonic control
element
Enabling/disabling
Disabled stage 2 of phase
50/51P2.En Enabled
Enabled overcurrent
protection
Enabling/disabling
stage 2 of phase
overcurrent
protection operate to
Trp
50/51P2.Opt_Trp/Alm Trp trip or alarm
Alm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE The option of
ANSILTV operating
ANSILT characteristics curve
50/51P2.Opt_Curve IECDefTime
IECN for stage 2 of phase
IECV overcurrent
IECI protection
IECE
IECST
IECLT
IECDefTime
9
UserDefine
The option of
dropout
characteristics curve
Inst
for stage 2 of phase
50/51P2.Opt_Curve_DropOut DefTime Inst
overcurrent
IDMT
protection
Inst: instantaneous
dropout

PCS-902S Line Distance Relay 9-61

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

characteristics
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage 2 of
50/51P2.TMS 0.040~20.000 0.001 1.000 inverse-time phase
overcurrent
protection
The minimum
operating time for
stage 2 of inverse-
50/51P2.tmin 0.000~10.000 0.001 s 0.020
time phase
overcurrent
protection
The constant “K” for
stage 2 of
customized inverse-
50/51P2.K 0.0010~120.0000 0.0001 0.1400
time phase
overcurrent
protection
The constant “α” for
stage 2 of
customized inverse-
50/51P2.Alpha 0.0100~3.0000 0.0001 0.0200
time phase
overcurrent
protection
The constant “C” for
stage 2 of

9 50/51P2.C 0.0000~1.2000 0.0001 0.0000

customized inverse-
time phase
overcurrent
protection
The current setting
for stage 3 of phase
50/51P3.I_Set (0.050~40.000)×In 0.001 A 15.000
overcurrent
protection
The operating time
50/51P3.t_Op 0.000~100.000 0.001 s 0.100 delay for stage 3 of
phase overcurrent

9-62 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

protection
The dropout time
delay for stage 3 of
50/51P3.t_DropOut 0.000~100.000 0.001 s 0.000
phase overcurrent
protection
Enabling/disabling
stage 3 of phase
Disabled overcurrent
50/51P3.En_Volt_Blk Disabled
Enabled protection controlled
by voltage control
element
The option direction
Non_Directional characteristic for
50/51P3.Opt_Dir Forward Non_Directional stage 3 of phase
Reverse overcurrent
protection
Enabling/disabling
stage 3 of phase
Disabled overcurrent
50/51P3.En_Hm_Blk Disabled
Enabled protection controlled
by harmonic control
element
Enabling/disabling
Disabled stage 3 of phase
50/51P3.En Enabled
Enabled overcurrent
protection
Enabling/disabling
stage 3 of phase
overcurrent
protection operate to
Trp
50/51P3.Opt_Trp/Alm Trp trip or alarm
Alm
Trp: for tripping
purpose
Alm: for alarm
9
purpose
ANSIE
ANSIV The option of
ANSIN operating
ANSIM characteristics curve
50/51P3.Opt_Curve IECDefTime
ANSIDefTime for stage 3 of phase
ANSILTE overcurrent
ANSILTV protection
ANSILT

PCS-902S Line Distance Relay 9-63

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

IECN
IECV
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 3 of phase
overcurrent
protection
Inst Inst: instantaneous
50/51P3.Opt_Curve_DropOut DefTime Inst dropout
IDMT characteristics
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage 3 of
50/51P3.TMS 0.040~20.000 0.001 1.000 inverse-time phase
overcurrent
protection
The minimum
operating time for
stage 3 of inverse-
50/51P3.tmin 0.000~10.000 0.001 s 0.020
time phase

9 overcurrent
protection
The constant “K” for
stage 3 of
customized inverse-
50/51P3.K 0.0010~120.0000 0.0001 0.1400
time phase
overcurrent
protection
The constant “α” for
50/51P3.Alpha 0.0100~3.0000 0.0001 0.0200 stage 3 of
customized inverse-

9-64 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

time phase
overcurrent
protection
The constant “C” for
stage 3 of
customized inverse-
50/51P3.C 0.0000~1.2000 0.0001 0.0000
time phase
overcurrent
protection
The current setting
for stage 4 of phase
50/51P4.I_Set (0.050~40.000)×In 0.001 A 15.000
overcurrent
protection
The operating time
delay for stage 4 of
50/51P4.t_Op 0.000~100.000 0.001 s 0.100
phase overcurrent
protection
The dropout time
delay for stage 4 of
50/51P4.t_DropOut 0.000~100.000 0.001 s 0.000
phase overcurrent
protection
Enabling/disabling
stage 4 of phase
Disabled overcurrent
50/51P4.En_Volt_Blk Disabled
Enabled protection controlled
by voltage control
element
The option direction
Non_Directional characteristic for
50/51P4.Opt_Dir Forward Non_Directional stage 4 of phase
Reverse overcurrent
protection
Enabling/disabling
stage 4 of phase
9
Disabled overcurrent
50/51P4.En_Hm_Blk Disabled
Enabled protection controlled
by harmonic control
element
Enabling/disabling
Disabled stage 4 of phase
50/51P4.En Enabled
Enabled overcurrent
protection
50/51P4.Opt_Trp/Alm Trp Trp Enabling/disabling

PCS-902S Line Distance Relay 9-65

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Alm stage 4 of phase
overcurrent
protection operate to
trip or alarm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE The option of
ANSILTV operating
ANSILT characteristics curve
50/51P4.Opt_Curve IECDefTime
IECN for stage 4 of phase
IECV overcurrent
IECI protection
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 4 of phase
overcurrent
protection
Inst Inst: instantaneous
50/51P4.Opt_Curve_DropOut DefTime Inst dropout

9 IDMT characteristics
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage 4 of
50/51P4.TMS 0.040~20.000 0.001 1.000
inverse-time phase
overcurrent

9-66 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

protection
The minimum
operating time for
stage 4 of inverse-
50/51P4.tmin 0.000~10.000 0.001 s 0.020
time phase
overcurrent
protection
The constant “K” for
stage 4 of
customized inverse-
50/51P4.K 0.0010~120.0000 0.0001 0.1400
time phase
overcurrent
protection
The constant “α” for
stage 4 of
customized inverse-
50/51P4.Alpha 0.0100~3.0000 0.0001 0.0200
time phase
overcurrent
protection
The constant “C” for
stage 4 of
customized inverse-
50/51P4.C 0.0000~1.2000 0.0001 0.0000
time phase
overcurrent
protection
The current setting
for stage 5 of phase
50/51P5.I_Set (0.050~40.000)×In 0.001 A 15.000
overcurrent
protection
The operating time
delay for stage 5 of
50/51P5.t_Op 0.000~100.000 0.001 s 0.100
phase overcurrent
protection
The dropout time
9
delay for stage 5 of
50/51P5.t_DropOut 0.000~100.000 0.001 s 0.000
phase overcurrent
protection
Enabling/disabling
stage 5 of phase
Disabled overcurrent
50/51P5.En_Volt_Blk Disabled
Enabled protection controlled
by voltage control
element

PCS-902S Line Distance Relay 9-67

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The option direction
Non_Directional characteristic for
50/51P5.Opt_Dir Forward Non_Directional stage 5 of phase
Reverse overcurrent
protection
Enabling/disabling
stage 5 of phase
Disabled overcurrent
50/51P5.En_Hm_Blk Disabled
Enabled protection controlled
by harmonic control
element
Enabling/disabling
Disabled stage 5 of phase
50/51P5.En Enabled
Enabled overcurrent
protection
Enabling/disabling
stage 5 of phase
overcurrent
protection operate to
Trp
50/51P5.Opt_Trp/Alm Trp trip or alarm
Alm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE The option of
ANSILTV operating
ANSILT characteristics curve
50/51P5.Opt_Curve IECDefTime
9 IECN
IECV
for stage 5 of phase
overcurrent
IECI protection
IECE
IECST
IECLT
IECDefTime
UserDefine
Inst The option of
50/51P5.Opt_Curve_DropOut DefTime Inst dropout
IDMT characteristics curve

9-68 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

for stage 5 of phase
overcurrent
protection
Inst: instantaneous
dropout
characteristics
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage 5 of
50/51P5.TMS 0.040~20.000 0.001 1.000 inverse-time phase
overcurrent
protection
The minimum
operating time for
stage 5 of inverse-
50/51P5.tmin 0.000~10.000 0.001 s 0.020
time phase
overcurrent
protection
The constant “K” for
stage 5 of
customized inverse-
50/51P5.K 0.0010~120.0000 0.0001 0.1400
time phase
overcurrent
protection
The constant “α” for
stage 5 of
customized inverse-
50/51P5.Alpha 0.0100~3.0000 0.0001 0.0200
time
overcurrent
phase
9
protection
The constant “C” for
stage 5 of
customized inverse-
50/51P5.C 0.0000~1.2000 0.0001 0.0000
time phase
overcurrent
protection
The current setting
50/51P6.I_Set (0.050~40.000)×In 0.001 A 15.000
for stage 6 of phase

PCS-902S Line Distance Relay 9-69

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

overcurrent
protection
The operating time
delay for stage 6 of
50/51P6.t_Op 0.000~100.000 0.001 s 0.100
phase overcurrent
protection
The dropout time
delay for stage 6 of
50/51P6.t_DropOut 0.000~100.000 0.001 s 0.000
phase overcurrent
protection
Enabling/disabling
stage 6 of phase
Disabled overcurrent
50/51P6.En_Volt_Blk Disabled
Enabled protection controlled
by voltage control
element
The option direction
Non_Directional characteristic for
50/51P6.Opt_Dir Forward Non_Directional stage 6 of phase
Reverse overcurrent
protection
Enabling/disabling
stage 6 of phase
Disabled overcurrent
50/51P6.En_Hm_Blk Disabled
Enabled protection controlled
by harmonic control
element
Enabling/disabling
Disabled stage 6 of phase
50/51P6.En Enabled
Enabled overcurrent
protection
Enabling/disabling

9 stage 6 of phase
overcurrent
protection operate to
Trp
50/51P6.Opt_Trp/Alm Trp trip or alarm
Alm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE The option of
50/51P6.Opt_Curve ANSIV IECDefTime operating
ANSIN characteristics curve

9-70 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

ANSIM for stage 6 of phase
ANSIDefTime overcurrent
ANSILTE protection
ANSILTV
ANSILT
IECN
IECV
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 6 of phase
overcurrent
protection
Inst Inst: instantaneous
50/51P6.Opt_Curve_DropOut DefTime Inst dropout
IDMT characteristics
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage 6 of
50/51P6.TMS 0.040~20.000 0.001 1.000 inverse-time phase
overcurrent
protection
The minimum
9
operating time for
stage 6 of inverse-
50/51P6.tmin 0.000~10.000 0.001 s 0.020
time phase
overcurrent
protection
The constant “K” for
stage 6 of
50/51P6.K 0.0010~120.0000 0.0001 0.1400
customized inverse-
time phase

PCS-902S Line Distance Relay 9-71

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

overcurrent
protection
The constant “α” for
stage 6 of
customized inverse-
50/51P6.Alpha 0.0100~3.0000 0.0001 0.0200
time phase
overcurrent
protection
The constant “C” for
stage 6 of
customized inverse-
50/51P6.C 0.0000~1.2000 0.0001 0.0000
time phase
overcurrent
protection

9.2.10 Phase Current SOTF Protection (50PSOTF)

Access path: MainMenuSettingsProtection SettingsSOTF Settings

Name Range Step Unit Default Description

Current setting of phase current
50PSOTF.I_Set (0.050~40.000)×In 0.001 A 1.000
SOTF protection
Time delay for phase current SOTF
50PSOTF.t_Op 0.000~100.000 0.001 s 0.100
protection
Voltage setting for phase
50PSOTF.Up_Set 0.000~200.000 0.001 V 1.000
undervoltage supervision logic
Voltage setting for phase-phase
50PSOTF.Upp_Set 0.000~200.000 0.001 V 1.000
undervoltage supervision logic
Voltage setting for negative-
50PSOTF.U2_Set 0.000~200.000 0.001 V 1.000 sequence overvoltage supervision
logic
Voltage setting for zero-sequence
50PSOTF.3U0_Set 0.000~200.000 0.001 V 1.000
overvoltage supervision logic
Enabling/disabling phase
9 50PSOTF.En_Up_UV
Disabled
Enabled undervoltage supervision logic for
Enabled
phase current SOTF protection
Enabling/disabling phase-phase
Disabled
50PSOTF.En_Upp_UV Enabled undervoltage supervision logic for
Enabled
phase current SOTF protection
Enabling/disabling negative-
Disabled sequence overvoltage supervision
50PSOTF.En_U2_OV Enabled
Enabled logic for phase current SOTF
protection
50PSOTF.En_3U0_OV Disabled Enabled Enabling/disabling zero-sequence

9-72 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabled overvoltage supervision logic for
phase current SOTF protection
Disabled Enabling/disabling phase current
50PSOTF.En Enabled
Enabled SOTF protection
Enabling/disabling second harmonic
Disabled
50PSOTF.En_Hm2_Blk Enabled blocking for phase overcurrent SOTF
Enabled
protection

9.2.11 Earth Fault Protection (50/51G)

Access path: MainMenuSettingsProtection SettingsROC Settings

Name Range Step Unit Default Description

The characteristic
50/51G.DIR.RCA -180~179 1 ° 45 angle of direction
control element
The minimum
boundary in forward
50/51G.DIR.phi_Min_Fwd 10~90 1 ° 90
direction of earth
fault protection
The maximum
boundary in forward
50/51G.DIR.phi_Max_Fwd 10~90 1 ° 90
direction of earth
fault protection
The minimum
boundary in reverse
50/51G.DIR.phi_Min_Rev 10~90 1 ° 90
direction of earth
fault protection
The maximum
boundary in reverse
50/51G.DIR.phi_Max_Rev 10~90 1 ° 90
direction of earth
fault protection
The voltage
polarization mode of
direction control 9
element
3U0: zero-sequence
3U0
50/51G.DIR.Opt_PolarizedVolt 3U0 voltage is used as
U2
polarized
U2: negative-
sequence voltage is
used as polarized
voltage
50/51G.DIR.3I0_Min (0.050~1.000)×In 0.001 A 0.050 The minimum

PCS-902S Line Distance Relay 9-73

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

operating current
setting of direction
control element
The minimum
operating voltage
50/51G.DIR.3U0_Min 1.000~10.000 0.001 V 4.000
setting of direction
control element
The compensation
setting of zero-
sequence
50/51G.DIR.Z0_Comp (0.000~4Unn)/In 0.001 Ω 0.000
impedance of
direction control
element
Enabling/disabling
earth fault protection
is blocked by VT
Disabled circuit failure when
50/51G.En_VTS_Blk Disabled
Enabled VT circuit
supervision is
enabled and VT
circuit fails
The coefficient of
second harmonics of
50/51G.HMB.K_Hm2 0.100~1.000 0.001 0.200
harmonic control
element
The current setting of
50/51G.HMB.I_Rls (2.000~30.000)×In 0.001 A 20.000 releasing harmonic
control element
The zero-sequence
current setting for
50/51G1.3I0_Set (0.050~40.000)×In 0.001 A 15.000
stage 1 of earth fault
protection

9 50/51G1.t_Op 0.000~100.000 0.001 s 0.100

The operating time
delay for stage 1 of
earth fault protection
The dropout time
50/51G1.t_DropOut 0.000~100.000 0.001 s 0.000 delay for stage 1 of
earth fault protection
The option direction
Non_Directional
characteristic for
50/51G1.Opt_Dir Forward Non_Directional
stage 1 of earth fault
Reverse
protection
50/51G1.En_Hm_Blk Disabled Disabled Enabling/disabling

9-74 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabled stage 1 of earth fault
protection controlled
by harmonic control
element
Enabling/disabling
Disabled
50/51G1.En Enabled stage 1 of earth fault
Enabled
protection
Enabling/disabling
stage 1 of earth fault
protection operate to
Trp trip or alarm
50/51G1.Opt_Trp/Alm Trp
Alm Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of
ANSILTV
operating
ANSILT
50/51G1.Opt_Curve IECDefTime characteristics curve
IECN
for stage 1 of earth
IECV
fault protection
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
9
for stage 1 of earth
fault protection
Inst
Inst: instantaneous
50/51G1.Opt_Curve_DropOut DefTime Inst
dropout
IDMT
characteristics
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time

PCS-902S Line Distance Relay 9-75

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

dropout
characteristics
Time multiplier
setting for stage 1 of
50/51G1.TMS 0.040~20.000 0.001 1.000
inverse-time earth
fault protection
The minimum
operating time for
50/51G1.tmin 0.000~10.000 0.001 s 0.020 stage 1 of inverse-
time earth fault
protection
The constant “K” for
stage 1 of
50/51G1.K 0.0010~120.0000 0.0001 0.1400 customized inverse-
time earth fault
protection
The constant “α” for
stage 1 of
50/51G1.Alpha 0.0100~3.0000 0.0001 0.0200 customized inverse-
time earth fault
protection
The constant “C” for
stage 1 of
50/51G1.C 0.0000~1.2000 0.0001 0.0000 customized inverse-
time earth fault
protection
The zero-sequence
current setting for
50/51G2.3I0_Set (0.050~40.000)×In 0.001 A 15.000
stage 2 of earth fault
protection
The operating time
50/51G2.t_Op 0.000~100.000 0.001 s 0.100 delay for stage 2 of

9 earth fault protection

The dropout time
50/51G2.t_DropOut 0.000~100.000 0.001 s 0.000 delay for stage 2 of
earth fault protection
The option direction
Non_Directional
characteristic for
50/51G2.Opt_Dir Forward Non_Directional
stage 2 of earth fault
Reverse
protection
Enabling/disabling
Disabled
50/51G2.En_Hm_Blk Disabled stage 2 of earth fault
Enabled
protection controlled

9-76 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

by harmonic control
element
Enabling/disabling
Disabled
50/51G2.En Enabled stage 2 of earth fault
Enabled
protection
Enabling/disabling
stage 2 of earth fault
protection operate to
Trp trip or alarm
50/51G2.Opt_Trp/Alm Trp
Alm Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of
ANSILTV
operating
ANSILT
50/51G2.Opt_Curve IECDefTime characteristics curve
IECN
for stage 2 of earth
IECV
fault protection
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 2 of earth
fault protection
9
Inst: instantaneous
Inst
dropout
50/51G2.Opt_Curve_DropOut DefTime Inst
characteristics
IDMT
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics

PCS-902S Line Distance Relay 9-77

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Time multiplier
setting for stage 2 of
50/51G2.TMS 0.040~20.000 0.001 1.000
inverse-time earth
fault protection
The minimum
operating time for
50/51G2.tmin 0.000~10.000 0.001 s 0.020 stage 2 of inverse-
time earth fault
protection
The constant “K” for
stage 2 of
50/51G2.K 0.0010~120.0000 0.0001 0.1400 customized inverse-
time earth fault
protection
The constant “α” for
stage 2 of
50/51G2.Alpha 0.0100~3.0000 0.0001 0.0200 customized inverse-
time earth fault
protection
The constant “C” for
stage 2 of
50/51G2.C 0.0000~1.2000 0.0001 0.0000 customized inverse-
time earth fault
protection
The zero-sequence
current setting for
50/51G3.3I0_Set (0.050~40.000)×In 0.001 A 15.000
stage 3 of earth fault
protection
The operating time
50/51G3.t_Op 0.000~100.000 0.001 s 0.100 delay for stage 3 of
earth fault protection
The dropout time

9 50/51G3.t_DropOut 0.000~100.000 0.001 s 0.000 delay for stage 3 of

earth fault protection
The option direction
Non_Directional
characteristic for
50/51G3.Opt_Dir Forward Non_Directional
stage 3 of earth fault
Reverse
protection
Enabling/disabling
stage 3 of earth fault
Disabled
50/51G3.En_Hm_Blk Disabled protection controlled
Enabled
by harmonic control
element

9-78 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling
Disabled
50/51G3.En Enabled stage 3 of earth fault
Enabled
protection
Enabling/disabling
stage 3 of earth fault
protection operate to
Trp trip or alarm
50/51G3.Opt_Trp/Alm Trp
Alm Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of
ANSILTV
operating
ANSILT
50/51G3.Opt_Curve IECDefTime characteristics curve
IECN
for stage 3 of earth
IECV
fault protection
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 3 of earth
fault protection

Inst
Inst:
dropout
instantaneous
9
50/51G3.Opt_Curve_DropOut DefTime Inst
characteristics
IDMT
DefTime: definite-
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
50/51G3.TMS 0.040~20.000 0.001 1.000
setting for stage 3 of

PCS-902S Line Distance Relay 9-79

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

inverse-time earth
fault protection
The minimum
operating time for
50/51G3.tmin 0.000~10.000 0.001 s 0.020 stage 3 of inverse-
time earth fault
protection
The constant “K” for
stage 3 of
50/51G3.K 0.0010~120.0000 0.0001 0.1400 customized inverse-
time earth fault
protection
The constant “α” for
stage 3 of
50/51G3.Alpha 0.0100~3.0000 0.0001 0.0200 customized inverse-
time earth fault
protection
The constant “C” for
stage 3 of
50/51G3.C 0.0000~1.2000 0.0001 0.0000 customized inverse-
time earth fault
protection
The zero-sequence
current setting for
50/51G4.3I0_Set (0.050~40.000)×In 0.001 A 15.000
stage 4 of earth fault
protection
The operating time
50/51G4.t_Op 0.000~100.000 0.001 s 0.100 delay for stage 4 of
earth fault protection
The dropout time
50/51G4.t_DropOut 0.000~100.000 0.001 s 0.000 delay for stage 4 of
earth fault protection

9 Non_Directional
The option direction
characteristic for
50/51G4.Opt_Dir Forward Non_Directional
stage 4 of earth fault
Reverse
protection
Enabling/disabling
stage 4 of earth fault
Disabled
50/51G4.En_Hm_Blk Disabled protection controlled
Enabled
by harmonic control
element
Disabled Enabling/disabling
50/51G4.En Enabled
Enabled stage 4 of earth fault

9-80 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

protection
Enabling/disabling
stage 4 of earth fault
protection operate to
Trp trip or alarm
50/51G4.Opt_Trp/Alm Trp
Alm Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of
ANSILTV
operating
ANSILT
50/51G4.Opt_Curve IECDefTime characteristics curve
IECN
for stage 4 of earth
IECV
fault protection
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 4 of earth
fault protection
Inst: instantaneous
Inst
dropout
50/51G4.Opt_Curve_DropOut DefTime Inst
IDMT
characteristics
DefTime: definite-
9
time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage 4 of
50/51G4.TMS 0.040~20.000 0.001 1.000
inverse-time earth
fault protection

PCS-902S Line Distance Relay 9-81

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The minimum
operating time for
50/51G4.tmin 0.000~10.000 0.001 s 0.020 stage 4 of inverse-
time earth fault
protection
The constant “K” for
stage 4 of
50/51G4.K 0.0010~120.0000 0.0001 0.1400 customized inverse-
time earth fault
protection
The constant “α” for
stage 4 of
50/51G4.Alpha 0.0100~3.0000 0.0001 0.0200 customized inverse-
time earth fault
protection
The constant “C” for
stage 4 of
50/51G4.C 0.0000~1.2000 0.0001 0.0000 customized inverse-
time earth fault
protection
The zero-sequence
current setting for
50/51G5.3I0_Set (0.050~40.000)×In 0.001 A 15.000
stage 1 of earth fault
protection
The operating time
50/51G5.t_Op 0.000~100.0000 0.001 s 0.100 delay for stage 5 of
earth fault protection
The dropout time
50/51G5.t_DropOut 0.000~100.000 0.001 s 0.000 delay for stage 5 of
earth fault protection
The option direction
Non_Directional
characteristic for
50/51G5.Opt_Dir Forward Non_Directional
9 Reverse
stage 5 of earth fault
protection
Enabling/disabling
stage 5 of earth fault
Disabled
50/51G5.En_Hm_Blk Disabled protection controlled
Enabled
by harmonic control
element
Enabling/disabling
Disabled
50/51G5.En Enabled stage 5 of earth fault
Enabled
protection
50/51G5.Opt_Trp/Alm Trp Trp Enabling/disabling

9-82 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Alm stage 5 of earth fault
protection operate to
trip or alarm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of
ANSILTV
operating
ANSILT
50/51G5.Opt_Curve IECDefTime characteristics curve
IECN
for stage 5 of earth
IECV
fault protection
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 5 of earth
fault protection
Inst: instantaneous
Inst
dropout
50/51G5.Opt_Curve_DropOut DefTime Inst
characteristics
IDMT
DefTime: definite-
time
characteristics
dropout
9
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage 5 of
50/51G5.TMS 0.040~20.000 0.001 1.000
inverse-time earth
fault protection
The minimum
50/51G5.tmin 0.000~10.000 0.001 s 0.020
operating time for

PCS-902S Line Distance Relay 9-83

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

stage 5 of inverse-
time earth fault
protection
The constant “K” for
stage 5 of
50/51G5.K 0.0010~120.0000 0.0001 0.1400 customized inverse-
time earth fault
protection
The constant “α” for
stage 5 of
50/51G5.Alpha 0.0100~3.0000 0.0001 0.0200 customized inverse-
time earth fault
protection
The constant “C” for
stage 5 of
50/51G5.C 0.0000~1.2000 0.0001 0.0000 customized inverse-
time earth fault
protection
The zero-sequence
current setting for
50/51G6.3I0_Set (0.050~40.000)×In 0.001 A 15.000
stage 6 of earth fault
protection
The operating time
50/51G6.t_Op 0.000~100.000 0.001 s 0.100 delay for stage 6 of
earth fault protection
The dropout time
50/51G6.t_DropOut 0.000~100.000 0.001 s 0.000 delay for stage 6 of
earth fault protection
The option direction
Non_Directional
characteristic for
50/51G6.Opt_Dir Forward Non_Directional
stage 6 of earth fault
Reverse
protection

9 Enabling/disabling
stage 6 of earth fault
Disabled
50/51G6.En_Hm_Blk Disabled protection controlled
Enabled
by harmonic control
element
Enabling/disabling
Disabled
50/51G6.En Enabled stage 6 of earth fault
Enabled
protection
Enabling/disabling
Trp
50/51G6.Opt_Trp/Alm Trp stage 6 of earth fault
Alm
protection operate to

9-84 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

trip or alarm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
The option of
ANSILTV
operating
ANSILT
50/51G6.Opt_Curve IECDefTime characteristics curve
IECN
for stage 6 of earth
IECV
fault protection
IECI
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
characteristics curve
for stage 6 of earth
fault protection
Inst: instantaneous
Inst
dropout
50/51G6.Opt_Curve_DropOut DefTime Inst
characteristics
IDMT
DefTime: definite-
time dropout
characteristics
IDMT:
dropout
inverse-time
9
characteristics
Time multiplier
setting for stage 6 of
50/51G6.TMS 0.040~20.000 0.001 1.000
inverse-time earth
fault protection
The minimum
operating time for
50/51G6.tmin 0.000~10.000 0.001 s 0.020
stage 6 of inverse-
time earth fault

PCS-902S Line Distance Relay 9-85

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

protection
The constant “K” for
stage 6 of
50/51G6.K 0.0010~120.0000 0.0001 0.1400 customized inverse-
time earth fault
protection
The constant “α” for
stage 6 of
50/51G6.Alpha 0.0100~3.0000 0.0001 0.0200 customized inverse-
time earth fault
protection
The constant “C” for
stage 6 of
50/51G6.C 0.0000~1.2000 0.0001 0.0000 customized inverse-
time earth fault
protection

9.2.12 Residual Current SOTF Protection (50GSOTF)

Access path: MainMenuSettingsProtection SettingsSOTF Settings

Name Range Step Unit Default Description

Current setting of residual current
50GSOTF.3I0_Set (0.050~40.000)×In 0.001 A 1.000
SOTF protection
Time delay for residual current
50GSOTF.t_Op_1P 0.000~100.000 0.001 s 0.060
SOTF protection when 1 pole closed
Time delay for residual current
50GSOTF.t_Op_3P 0.000~100.000 0.001 s 0.100
SOTF protection when 3 pole closed
Disabled Enabling/disabling residual current
50GSOTF.En Enabled
Enabled SOTF protection
Enabling/disabling residual current
Disabled
50GSOTF.En_Hm2_Blk Disabled SOTF protection blocked by
Enabled
harmonic

9 9.2.13 Negative-sequence Overcurrent Protection (50/51Q)

Access path: MainMenuSettingsProtection SettingsNegOC Settings

Name Range Step Unit Default Description

The characteristic
50/51Q.DIR.RCA -180~179 1 ° 45 angle of direction
control element
The minimum
50/51Q.DIR.phi_Min_Fwd 10~90 1 ° 90 boundary in forward
direction of negative-

9-86 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

sequence overcurrent
protection
The maximum
boundary in forward
50/51Q.DIR.phi_Max_Fwd 10~90 1 ° 90 direction of negative-
sequence overcurrent
protection
The minimum
boundary in reverse
50/51Q.DIR.phi_Min_Rev 10~90 1 ° 90 direction of negative-
sequence overcurrent
protection
The maximum
boundary in reverse
50/51Q.DIR.phi_Max_Rev 10~90 1 ° 90 direction of negative-
sequence overcurrent
protection
The minimum
operating current
50/51Q.DIR.I2_Min (0.050~1.000)×In 0.001 A 0.050
setting of direction
control element
The minimum
operating voltage
50/51Q.DIR.U2_Min 1.000~10.000 0.001 V 4.000
setting of direction
control element
The compensation
setting of negative-
50/51Q.DIR.Z2_Comp (0.000~4Unn)/In 0.001 Ω 0.000 sequence impedance
of direction control
element
Enabling/disabling
negative-sequence

Disabled
overcurrent protection
is blocked by VT
9
50/51Q.En_VTS_Blk Disabled
Enabled circuit failure when VT
circuit supervision is
enabled and VT
circuit fails
The negative-
sequence current
50/51Q1.I2_Set (0.050~40.000)×In 0.001 A 15.000 setting for stage 1 of
negative-sequence
overcurrent protection

PCS-902S Line Distance Relay 9-87

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The operating time
delay for stage 1 of
50/51Q1.t_Op 0.030~100.000 0.001 s 0.100
negative-sequence
overcurrent protection
The dropout time
delay for stage 1 of
50/51Q1.t_DropOut 0.000~100.000 0.001 s 0.000
negative-sequence
overcurrent protection
The option direction
Non_Directional characteristic for
50/51Q1.Opt_Dir Forward Non_Directional stage 1 of negative-
Reverse sequence overcurrent
protection
Enabling/disabling
Disabled stage 1 of negative-
50/51Q1.En Enabled
Enabled sequence overcurrent
protection
Enabling/disabling
stage 1 of negative-
sequence overcurrent
protection operate to
Trp
50/51Q1.Opt_Trp/Alm Trp trip or alarm
Alm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE The option of

9 ANSILTV
ANSILT
operating
characteristics curve
50/51Q1.Opt_Curve IECDefTime
IECN for stage 1 of
IECV negative-sequence
IECI overcurrent protection
IECE
IECST
IECLT
IECDefTime
UserDefine
50/51Q1.Opt_Curve_DropOut Inst Inst The option of dropout

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 9 Settings

Name Range Step Unit Default Description

DefTime characteristics curve
IDMT for stage 1 of
negative-sequence
overcurrent protection
Inst: instantaneous
dropout
characteristics
DefTime: definite-time
dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier setting
for stage 1 of inverse-
50/51Q1.TMS 0.040~20.000 0.001 1.000 time negative-
sequence overcurrent
protection
The minimum
operating time for
stage 1 of inverse-
50/51Q1.tmin 0.000~10.000 0.001 s 0.020
time negative-
sequence overcurrent
protection
The constant “K” for
stage 1 of customized
50/51Q1.K 0.0010~120.0000 0.0001 0.1400 inverse-time
negative-sequence
overcurrent protection
The constant “α” for
stage 1 of customized
50/51Q1.Alpha 0.0100~3.0000 0.0001 0.0200 inverse-time
negative-sequence
overcurrent protection
9
The constant “C” for
stage 1 of customized
50/51Q1.C 0.0000~1.2000 0.0001 0.0000 inverse-time
negative-sequence
overcurrent protection
The negative-
sequence current
50/51Q2.I2_Set (0.050~40.000)×In 0.001 A 15.000
setting for stage 2 of
negative-sequence

PCS-902S Line Distance Relay 9-89

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

overcurrent protection
The operating time
delay for stage 2 of
50/51Q2.t_Op 0.030~100.000 0.001 s 0.100
negative-sequence
overcurrent protection
The dropout time
delay for stage 2 of
50/51Q2.t_DropOut 0.000~100.000 0.001 s 0.000
negative-sequence
overcurrent protection
The option direction
Non_Directional characteristic for
50/51Q2.Opt_Dir Forward Non_Directional stage 2 of negative-
Reverse sequence overcurrent
protection
Enabling/disabling
Disabled stage 2 of negative-
50/51Q2.En Enabled
Enabled sequence overcurrent
protection
Enabling/disabling
stage 2 of negative-
sequence overcurrent
protection operate to
Trp
50/51Q2.Opt_Trp/Alm Trp trip or alarm
Alm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime

9 ANSILTE
ANSILTV
The
operating
option of

ANSILT characteristics curve

50/51Q2.Opt_Curve IECDefTime
IECN for stage 2 of
IECV negative-sequence
IECI overcurrent protection
IECE
IECST
IECLT
IECDefTime
UserDefine

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 9 Settings

Name Range Step Unit Default Description

The option of dropout
characteristics curve
for stage 2 of
negative-sequence
overcurrent protection
Inst: instantaneous
Inst
dropout
50/51Q2.Opt_Curve_DropOut DefTime Inst
characteristics
IDMT
DefTime: definite-time
dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier setting
for stage 2 of inverse-
50/51Q2.TMS 0.040~20.000 0.001 1.000 time negative-
sequence overcurrent
protection
The minimum
operating time for
stage 2 of inverse-
50/51Q2.tmin 0.000~10.000 0.001 s 0.020
time negative-
sequence overcurrent
protection
The constant “K” for
stage 2 of customized
50/51Q2.K 0.0010~120.0000 0.0001 0.1400 inverse-time
negative-sequence
overcurrent protection
The constant “α” for
stage 2 of customized
50/51Q2.Alpha 0.0100~3.0000 0.0001 0.0200 inverse-time
negative-sequence
9
overcurrent protection
The constant “C” for
stage 2 of customized
50/51Q2.C 0.0000~1.2000 0.0001 0.0000 inverse-time
negative-sequence
overcurrent protection

9.2.14 Phase Overvoltage Protection (59P)

Access path: MainMenuSettingsProtection SettingsOV Settings

PCS-902S Line Distance Relay 9-91

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The option of the calculation
voltage used by stage 1 of
Up
59P1.Opt_Up/Upp Upp phase overvoltage protection
Upp
Up: phase voltage
Upp: phase-to-phase voltage
The option of the voltage
criterion used by stage 1 of
3P
59P1.Opt_1P/3P 3P phase overvoltage protection
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The voltage setting for stage
59P1.U_Set 57.700~200.000 0.001 V 115.000 1 of phase overvoltage
protection
The dropout coefficient for
59P1.K_DropOut 0.930~1.000 0.001 0.980 stage 1 of phase overvoltage
protection
The operating time delay for
59P1.t_Op 0.100~100.000 0.001 s 1.000 stage 1 of phase overvoltage
protection
The dropout time delay for
59P1.t_DropOut 0.000~100.000 0.001 s 0.000 stage 1 of phase overvoltage
protection
Disabled Enabling/disabling stage 1 of
59P1.En Enabled
Enabled phase overvoltage protection
Enabling/disabling stage 1 of
phase overvoltage protection
Trp
59P1.Opt_Trp/Alm Trp operate to trip or alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose
ANSIDefTime The option of operating
IECDefTime characteristics curve for stage
59P1.Opt_Curve IECDefTime
UserDefine 1 of phase overvoltage

9 InvTime_U protection
The option of dropout
characteristics curve for stage
1 of phase overvoltage
Inst protection
59P1.Opt_Curve_DropOut Inst
DefTime Inst: instantaneous dropout
characteristics
DefTime: definite-time
dropout characteristics
Time multiplier setting for
59P1.TMS 0.040~20.000 0.001 1.000
stage 1 of inverse-time phase

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 9 Settings

Name Range Step Unit Default Description

overvoltage protection
The minimum operating time
59P1.tmin 0.000~10.000 0.001 s 0.020 for stage 1 of inverse-time
phase overvoltage protection
The constant “K” for stage 1 of
59P1.K 0.0010~120.0000 0.0001 1.0000 customized inverse-time
phase overvoltage protection
The constant “α” for stage 1 of
59P1.Alpha 0.0100~3.0000 0.0001 1.0000 customized inverse-time
phase overvoltage protection
The constant “C” for stage 1
59P1.C 0.0000~1.0000 0.0001 0.0000 of customized inverse-time
phase overvoltage protection
The option of the calculation
voltage used by stage 2 of
Up
59P2.Opt_Up/Upp Upp phase overvoltage protection
Upp
Up: phase voltage
Upp: phase-to-phase voltage
The option of the voltage
criterion used by stage 2 of
3P
59P2.Opt_1P/3P 3P phase overvoltage protection
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The voltage setting for stage
59P2.U_Set 57.700~200.000 0.001 V 115.000 2 of phase overvoltage
protection
The dropout coefficient for
59P2.K_DropOut 0.930~1.000 0.001 0.980 stage 2 of phase overvoltage
protection
The operating time delay for
59P2.t_Op 0.100~100.000 0.001 s 1.000 stage 2 of phase overvoltage
protection

59P2.t_DropOut 0.000~100.000 0.001 s 0.000

The dropout time delay for
stage 2 of phase overvoltage
9
protection
Disabled Enabling/disabling stage 2 of
59P2.En Enabled
Enabled phase overvoltage protection
Enabling/disabling stage 2 of
phase overvoltage protection
Trp
59P2.Opt_Trp/Alm Trp operate to trip or alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose
59P2.Opt_Curve ANSIDefTime IECDefTime The option of operating

PCS-902S Line Distance Relay 9-93

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

IECDefTime characteristics curve for stage
UserDefine 2 of phase overvoltage
InvTime_U protection
The option of dropout
characteristics curve for stage
2 of phase overvoltage
Inst protection
59P2.Opt_Curve_DropOut Inst
DefTime Inst: instantaneous dropout
characteristics
DefTime: definite-time
dropout characteristics
Time multiplier setting for
59P2.TMS 0.040~20.000 0.001 1.000 stage 2 of inverse-time phase
overvoltage protection
The minimum operating time
59P2.tmin 0.000~10.000 0.001 s 0.020 for stage 2 of inverse-time
phase overvoltage protection
The constant “K” for stage 2 of
59P2.K 0.0010~120.0000 0.0001 1.0000 customized inverse-time
phase overvoltage protection
The constant “α” for stage 2 of
59P2.Alpha 0.0100~3.0000 0.0001 1.0000 customized inverse-time
phase overvoltage protection
The constant “C” for stage 2
59P2.C 0.0000~1.0000 0.0001 0.0000 of customized inverse-time
phase overvoltage protection

9.2.15 Residual Overvoltage Protection (59G)

Access path: MainMenuSettingsProtection SettingsROV Settings

Name Range Step Unit Default Description

The voltage setting for stage 1 of residual
59G1.3U0_Set 1.000~200.000 0.001 V 50.000
overvoltage protection
9 The dropout coefficient for stage 1 of residual
59G1.K_DropOut 0.930~1.000 0.001 0.980
overvoltage protection
The operating time delay for stage 1 of
59G1.t_Op 0.100~100.000 0.001 s 1.000
residual overvoltage protection
The dropout time delay for stage 1 of residual
59G1.t_DropOut 0.000~100.000 0.001 s 0.000
overvoltage protection
Disabled Enabling/disabling stage 1 of residual
59G1.En Enabled
Enabled overvoltage protection
Trp Enabling/disabling stage 1 of residual
59G1.Opt_Trp/Alm Trp
Alm overvoltage protection operate to trip or alarm

9-94 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Trp: for tripping purpose
Alm: for alarm purpose
The voltage setting for stage 2 of residual
59G2.3U0_Set 1.000~200.000 0.001 V 50.000
overvoltage protection
The dropout coefficient for stage 2 of residual
59G2.K_DropOut 0.930~1.000 0.001 0.980
overvoltage protection
The operating time delay for stage 2 of
59G2.t_Op 0.100~100.000 0.001 s 1.000
residual overvoltage protection
The dropout time delay for stage 2 of residual
59G2.t_DropOut 0.000~100.000 0.001 s 0.000
overvoltage protection
Disabled Enabling/disabling stage 2 of residual
59G2.En Enabled
Enabled overvoltage protection
Enabling/disabling stage 2 of residual
Trp overvoltage protection operate to trip or alarm
59G2.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

9.2.16 Negative-sequence Overvoltage Protection (59Q)

Access path: MainMenuSettingsProtection SettingsNegOV Settings

Name Range Step Unit Default Description

The voltage setting for stage 1 of negative-
59Q1.U2_Set 2.000~100.000 0.001 V 15.000
sequence overvoltage protection
The dropout coefficient for stage 1 of
59Q1.K_DropOut 0.930~1.000 0.001 0.980
negative-sequence overvoltage protection
The operating time delay for stage 1 of
59Q1.t_Op 0.100~100.000 0.001 s 1.000
negative-sequence overvoltage protection
The dropout time delay for stage 1 of
59Q1.t_DropOut 0.000~100.000 0.001 s 0.000
negative-sequence overvoltage protection
Disabled Enabling/disabling stage 1 of negative-
59Q1.En Enabled
Enabled sequence overvoltage protection
Enabling/disabling stage 1 of negative-

59Q1.Opt_Trp/Alm
Trp
Trp
sequence overvoltage protection operate to
trip or alarm
9
Alm
Trp: for tripping purpose
Alm: for alarm purpose
The voltage setting for stage 2 of negative-
59Q2.U2_Set 2.000~100.000 0.001 V 15.000
sequence overvoltage protection
The dropout coefficient for stage 2 of
59Q2.K_DropOut 0.930~1.000 0.001 0.980
negative-sequence overvoltage protection
The operating time delay for stage 2 of
59Q2.t_Op 0.100~100.000 0.001 s 1.000
negative-sequence overvoltage protection

PCS-902S Line Distance Relay 9-95

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The dropout time delay for stage 2 of
59Q2.t_DropOut 0.000~100.000 0.001 s 0.000
negative-sequence overvoltage protection
Disabled Enabling/disabling stage 2 of negative-
59Q2.En Enabled
Enabled sequence overvoltage protection
Enabling/disabling stage 2 of negative-
sequence overvoltage protection operate to
Trp
59Q2.Opt_Trp/Alm Trp trip or alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose

9.2.17 Phase Undervoltage Protection (27P)

Access path: MainMenuSettingsProtection SettingsUV Settings

Name Range Step Unit Default Description

The option of the calculation
voltage used by stage 1 of
Up phase undervoltage
27P1.Opt_Up/Upp Upp
Upp protection
Up: phase voltage
Upp: phase-to-phase voltage
The option of the voltage
criterion used by stage 1 of
3P phase undervoltage
27P1.Opt_1P/3P 3P
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of auxiliary
criterion mode for stage 1 of
phase undervoltage
protection
None: no check
None Curr: check current condition
Curr CBPos: check normally open
9 27P1.Opt_LogicMode CBPos Curr auxiliary contact
CurrOrCBPos CurrOrCBPos: check current
CurrAndCBPos condition or normally open
auxiliary contact
CurrAndCBPos: check
current condition and
normally open auxiliary
contact
The voltage setting for stage
27P1.U_Set 5.000~120.000 0.001 V 80.000
1 of phase undervoltage

9-96 PCS-902S Line Distance Relay

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 9 Settings

Name Range Step Unit Default Description

protection
The dropout coefficient for
27P1.K_DropOut 1.000~1.200 0.001 1.030 stage 1 of phase
undervoltage protection
The operating time delay for
27P1.t_Op 0.100~100.000 0.001 s 1.000 stage 1 of phase
undervoltage protection
The dropout time delay for
27P1.t_DropOut 0.000~100.000 0.001 s 0.000 stage 1 of phase
undervoltage protection
Enabling/disabling stage 1 of
phase undervoltage
Disabled protection is blocked by VT
27P1.En_VTS_Blk Disabled
Enabled circuit failure when VT circuit
supervision is enabled and VT
circuit fails
Enabling/disabling stage 1 of
Disabled
27P1.En Enabled phase undervoltage
Enabled
protection
Enabling/disabling stage 1 of
phase undervoltage
Trp protection operate to trip or
27P1.Opt_Trp/Alm Trp
Alm alarm
Trp: for tripping purpose
Alm: for alarm purpose
ANSIDefTime The option of operating
IECDefTime characteristics curve for stage
27P1.Opt_Curve IECDefTime
UserDefine 1 of phase undervoltage
InvTime_U protection
The option of dropout
characteristics curve for stage
1 of phase undervoltage

27P1.Opt_Curve_DropOut
Inst
DefTime
Inst
protection
Inst: instantaneous dropout
9
characteristics
DefTime: definite-time
dropout characteristics
Time multiplier setting for
27P1.TMS 0.040~20.000 0.001 1.000 stage 1 of inverse-time phase
undervoltage protection
The minimum operating time
27P1.tmin 0.030~10.000 0.001 s 0.030 for stage 1 of inverse-time
phase undervoltage

PCS-902S Line Distance Relay 9-97

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

protection
The constant “K” for stage 1 of
customized inverse-time
27P1.K 0.0010~120.0000 0.0001 0.1400
phase undervoltage
protection
The constant “α” for stage 1 of
customized inverse-time
27P1.Alpha 0.0100~3.0000 0.0001 0.0200
phase undervoltage
protection
The constant “C” for stage 1
of customized inverse-time
27P1.C 0.0000~1.0000 0.0001 0.0000
phase undervoltage
protection
The option of the calculation
voltage used by stage 2 of
Up phase undervoltage
27P2.Opt_Up/Upp Upp
Upp protection
Up: phase voltage
Upp: phase-to-phase voltage
The option of the voltage
criterion used by stage 2 of
3P phase undervoltage
27P2.Opt_1P/3P 3P
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of auxiliary
criterion mode for stage 2 of
phase undervoltage
protection
None: no check
None Curr: check current condition
Curr CBPos: check normally open

9 27P2.Opt_LogicMode CBPos
CurrOrCBPos
Curr auxiliary contact
CurrOrCBPos: check current
CurrAndCBPos condition or normally open
auxiliary contact
CurrAndCBPos: check
current condition and
normally open auxiliary
contact
The voltage setting for stage
27P2.U_Set 5.000~120.000 0.001 V 80.000 2 of phase undervoltage
protection

9-98 PCS-902S Line Distance Relay

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 9 Settings

Name Range Step Unit Default Description

The dropout coefficient for
27P2.K_DropOut 1.000~1.200 0.001 1.030 stage 2 of phase
undervoltage protection
The operating time delay for
27P2.t_Op 0.100~100.000 0.001 s 1.000 stage 2 of phase
undervoltage protection
The dropout time delay for
27P2.t_DropOut 0.000~100.000 0.001 s 0.000 stage 2 of phase
undervoltage protection
Enabling/disabling stage 2 of
phase undervoltage
Disabled protection is blocked by VT
27P2.En_VTS_Blk Disabled
Enabled circuit failure when VT circuit
supervision is enabled and VT
circuit fails
Enabling/disabling stage 2 of
Disabled
27P2.En Enabled phase undervoltage
Enabled
protection
Enabling/disabling stage 2 of
phase undervoltage
Trp protection operate to trip or
27P2.Opt_Trp/Alm Trp
Alm alarm
Trp: for tripping purpose
Alm: for alarm purpose
ANSIDefTime The option of operating
IECDefTime characteristics curve for stage
27P2.Opt_Curve IECDefTime
UserDefine 2 of phase undervoltage
InvTime_U protection
The option of dropout
characteristics curve for stage
2 of phase undervoltage
Inst protection
27P2.Opt_Curve_DropOut Inst
DefTime Inst: instantaneous dropout
characteristics
9
DefTime: definite-time
dropout characteristics
Time multiplier setting for
27P2.TMS 0.040~20.000 0.001 1.000 stage 2 of inverse-time phase
undervoltage protection
The minimum operating time
for stage 2 of inverse-time
27P2.tmin 0.030~10.000 0.001 s 0.030
phase undervoltage
protection

PCS-902S Line Distance Relay 9-99

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The constant “K” for stage 2 of
customized inverse-time
27P2.K 0.0010~120.0000 0.0001 0.1400
phase undervoltage
protection
The constant “α” for stage 2 of
customized inverse-time
27P2.Alpha 0.0100~3.0000 0.0001 0.0200
phase undervoltage
protection
The constant “C” for stage 2
of customized inverse-time
27P2.C 0.0000~1.0000 0.0001 0.0000
phase undervoltage
protection

9.2.18 Overfrequency Protection (81O)

Access path: MainMenuSettingsProtection SettingsFreqProt Settings

Name Range Step Unit Default Description

The phase-to-phase voltage setting used to
81.Upp_Blk 10.000~150.000 0.001 V 70.000
block overfrequency protection
The frequency setting for stage 1 of
81O1.f_Set 50.000~65.000 0.001 Hz 52.000
overfrequency protection
The time delay for stage 1 of overfrequency
81O1.t_Op 0.000~100.000 0.001 s 0.300
protection
Disabled Enabling/disabling stage 1 of overfrequency
81O1.En Enabled
Enabled protection
Enabling/disabling stage 1 of overfrequency
Trp protection operate to trip or alarm
81O1.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose
The frequency setting for stage 2 of
81O2.f_Set 50.000~65.000 0.001 Hz 52.000
overfrequency protection
The time delay for stage 2 of overfrequency
81O2.t_Op 0.000~100.000 0.001 s 0.300
protection
9 Disabled Enabling/disabling stage 2 of overfrequency
81O2.En Enabled
Enabled protection
Enabling/disabling stage 2 of overfrequency
Trp protection operate to trip or alarm
81O2.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose
The frequency setting for stage 3 of
81O3.f_Set 50.000~65.000 0.001 Hz 52.000
overfrequency protection
The time delay for stage 3 of overfrequency
81O3.t_Op 0.000~100.000 0.001 s 0.300
protection

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 9 Settings

Name Range Step Unit Default Description

Disabled Enabling/disabling stage 3 of overfrequency
81O3.En Enabled
Enabled protection
Enabling/disabling stage 3 of overfrequency
Trp protection operate to trip or alarm
81O3.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose
The frequency setting for stage 4 of
81O4.f_Set 50.000~65.000 0.001 Hz 52.000
overfrequency protection
The time delay for stage 4 of overfrequency
81O4.t_Op 0.000~100.000 0.001 s 0.300
protection
Disabled Enabling/disabling stage 4 of overfrequency
81O4.En Enabled
Enabled protection
Enabling/disabling stage 4 of overfrequency
Trp protection operate to trip or alarm
81O4.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

9.2.19 Underfrequency Protection (81U)

Access path: MainMenuSettingsProtection SettingsFreqProt Settings

Name Range Step Unit Default Description

The phase-to-phase voltage setting used to
81.Upp_Blk 10.000~150.000 0.001 V 70.000
block underfrequency protection
The frequency setting for stage 1 of
81U1.f_Set 45.000~60.000 0.001 Hz 48.000
underfrequency protection
The time delay for stage 1 of underfrequency
81U1.t_Op 0.000~100.000 0.001 s 0.300
protection
Disabled Enabling/disabling stage 1 of
81U1.En Enabled
Enabled underfrequency protection
Enabling/disabling stage 1 of
underfrequency protection operate to trip or
Trp
81U1.Opt_Trp/Alm Trp alarm
Alm

9
Trp: for tripping purpose
Alm: for alarm purpose
The frequency setting for stage 2 of
81U2.f_Set 45.000~60.000 0.001 Hz 48.000
underfrequency protection
The time delay for stage 2 of underfrequency
81U2.t_Op 0.000~100.000 0.001 s 0.300
protection
Disabled Enabling/disabling stage 2 of
81U2.En Enabled
Enabled underfrequency protection

PCS-902S Line Distance Relay 9-101

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling stage 2 of
underfrequency protection operate to trip or
Trp
81U2.Opt_Trp/Alm Trp alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose
The frequency setting for stage 3 of
81U3.f_Set 45.000~60.000 0.001 Hz 48.000
underfrequency protection
The time delay for stage 3 of underfrequency
81U3.t_Op 0.000~100.000 0.001 s 0.300
protection
Disabled Enabling/disabling stage 3 of
81U3.En Enabled
Enabled underfrequency protection
Enabling/disabling stage 3 of
underfrequency protection operate to trip or
Trp
81U3.Opt_Trp/Alm Trp alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose
The frequency setting for stage 4 of
81U4.f_Set 45.000~60.000 0.001 Hz 48.000
underfrequency protection
The time delay for stage 4 of underfrequency
81U4.t_Op 0.000~100.000 0.001 s 0.300
protection
Disabled Enabling/disabling stage 4 of
81U4.En Enabled
Enabled underfrequency protection
Enabling/disabling stage 4 of
underfrequency protection operate to trip or
Trp
81U4.Opt_Trp/Alm Trp alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose

9.2.20 Frequency Rate-of-change Protection (81R)

Access path: MainMenuSettingsProtection SettingsFreqProt Settings

Name Range Step Unit Default Description

The phase-to-phase voltage setting used to
9 81.Upp_Blk 10.000~150.000 0.001 V 70.000
block frequency rate-of-change protection
The frequency rate-of-change setting for
81R1.df/dt_Set -5.000~5.000 0.001 Hz/s 0.500 stage 1 of frequency rate-of-change
protection
The time delay for stage 1 of frequency rate-
81R1.t_Op 0.100~100.000 0.001 s 0.100
of-change protection
The pickup frequency setting for stage 1 of
81R1.f_Pkp 45.000~65.000 0.001 Hz 50.000
frequency rate-of-change protection
Disabled Enabling/disabling stage 1 of frequency
81R1.En Enabled
Enabled rate-of-change protection

9-102 PCS-902S Line Distance Relay

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 9 Settings

Name Range Step Unit Default Description

Enabling/disabling stage 1 of frequency
rate-of-change protection operate to trip or
Trp
81R1.Opt_Trp/Alm Trp alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose
The frequency rate-of-change setting for
81R2.df/dt_Set -5.000~5.000 0.001 Hz/s 0.500 stage 2 of frequency rate-of-change
protection
The time delay for stage 2 of frequency rate-
81R2.t_Op 0.100~100.000 0.001 s 0.100
of-change protection
The pickup frequency setting for stage 2 of
81R2.f_Pkp 45.000~65.000 0.001 Hz 50.000
frequency rate-of-change protection
Disabled Enabling/disabling stage 2 of frequency
81R2.En Enabled
Enabled rate-of-change protection
Enabling/disabling stage 2 of frequency
rate-of-change protection operate to trip or
Trp
81R2.Opt_Trp/Alm Trp alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose
The frequency rate-of-change setting for
81R3.df/dt_Set -5.000~5.000 0.001 Hz/s 0.500 stage 3 of frequency rate-of-change
protection
The time delay for stage 3 of frequency rate-
81R3.t_Op 0.100~100.000 0.001 s 0.100
of-change protection
The pickup frequency setting for stage 3 of
81R3.f_Pkp 45.000~65.000 0.001 Hz 50.000
frequency rate-of-change protection
Disabled Enabling/disabling stage 3 of frequency
81R3.En Enabled
Enabled rate-of-change protection
Enabling/disabling stage 3 of frequency
rate-of-change protection operate to trip or
Trp
81R3.Opt_Trp/Alm Trp alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose
The frequency rate-of-change setting for
9
81R4.df/dt_Set -5.000~5.000 0.001 Hz/s 0.500 stage 4 of frequency rate-of-change
protection
The time delay for stage 4 of frequency rate-
81R4.t_Op 0.100~100.000 0.001 s 0.100
of-change protection
The pickup frequency setting for stage 4 of
81R4.f_Pkp 45.000~65.000 0.001 Hz 50.000
frequency rate-of-change protection
Disabled Enabling/disabling stage 4 of frequency
81R4.En Enabled
Enabled rate-of-change protection

PCS-902S Line Distance Relay 9-103

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabling/disabling stage 4 of frequency
rate-of-change protection operate to trip or
Trp
81R4.Opt_Trp/Alm Trp alarm
Alm
Trp: for tripping purpose
Alm: for alarm purpose

9.2.21 Reverse Power Protection (32R)

Access path: MainMenuSettingsProtection SettingsRevPower Settings

Name Range Step Unit Default Description

The positive-sequence voltage setting used
32R1.U1_VCE 5.000~60.000 0.001 V 5.000
to block stage 1 of reverse power protection
The positive-sequence current setting used to
32R1.I1_CCE 0.010~1.000 0.001 p.u. 0.100
block stage 1 of reverse power protection
The negative-sequence voltage setting used
32R1.U2_VCE 8.000~60.000 0.001 V 8.000
to block stage 1 of reverse power protection
The power setting for stage 1 of reverse
32R1.P_Set 0.100~10.000 0.001 p.u. 0.150
power protection
The operating time delay for stage 1 of
32R1.t_Op 0.010~100.000 0.001 s 0.100
reverse power protection
Disabled Enabling/disabling stage 1 of reverse power
32R1.En Enabled
Enabled protection
Enabling/disabling stage 1 of reverse power
Trp protection operate to trip or alarm
32R1.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose
The positive-sequence voltage setting used
32R2.U1_VCE 5.000~60.000 0.001 V 5.000
to block stage 2 of reverse power protection
The positive-sequence current setting used to
32R2.I1_CCE 0.010~1.000 0.001 p.u. 0.100
block stage 2 of reverse power protection
The negative-sequence voltage setting used
32R2.U2_VCE 8.000~60.000 0.001 V 8.000
to block stage 2 of reverse power protection

9 32R2.P_Set 0.100~10.000 0.001 p.u. 0.150

The power setting for stage 2 of reverse
power protection
The operating time delay for stage 2 of
32R2.t_Op 0.010~100.000 0.001 s 0.100
reverse power protection
Disabled Enabling/disabling stage 2 of reverse power
32R2.En Enabled
Enabled protection
Enabling/disabling stage 2 of reverse power
Trp protection operate to trip or alarm
32R2.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

9-104 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

9.2.22 Thermal Overload Protection (49P)

Access path: MainMenuSettingsProtection SettingsThOvLd Settings

Name Range Step Unit Default Description

Base current setting for stage 1 of
49P1.Ib_Set 0.050~200.000 0.001 A 15.000
thermal overload protection
The tripping factor setting of thermal
49P1.K_Trp 1.000~3.000 0.001 1.200 capacity for stage 1 of thermal
overload protection
The alarm factor setting of thermal
49P1.K_Alm 1.000~3.000 0.001 1.100 capacity for stage 1 of thermal
overload protection
The time constant setting of the
49P1.Tau 0.100~100.000 0.001 min 1.000 thermal model for stage 1 of thermal
overload protection
The convertor coefficient from the
49P1.K_T_Diff 0.000~200.000 0.001 30.000 current to the temperature for stage
1 of thermal overload protection
The cooling mode setting for stage 1
of thermal overload protection
49P1.Alpha_Cold 1.000~2.000 0.001 2.000 Usually, for different cooling mode
Natural cooling: 1.6
Forced cooling: 2
The time constant of heat dissipation
for stage 1 of thermal overload
protection
49P1.C_Disspt 0.100~10.000 0.001 1.000 When the equivalent heating current
is lower than 0.04In, the thermal time
constant adopts the value of
[49Pi.Tau]×[49Pi.C_Disspt].
Disabled Enabling/disabling stage 1 of thermal
49P1.En_Trp Disabled
Enabled overload protection operate to trip
Disabled Enabling/disabling stage 1 of thermal
49P1.En_Alm Disabled
Enabled overload protection operate to alarm
The option to maintain or dissipate
9
Maintain the data in case of SV measurement
49P1.Opt_Accu_CurreLos Dissipate
Dissipate abonormality for stage 1 of thermal
overload protection
Base current setting for stage 2 of
49P2.Ib_Set 0.050~200.000 0.001 A 15.000
thermal overload protection
The tripping factor setting of thermal
49P2.K_Trp 1.000~3.000 0.001 1.200 capacity for stage 2 of thermal
overload protection

PCS-902S Line Distance Relay 9-105

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

The alarm factor setting of thermal
49P2.K_Alm 1.000~3.000 0.001 1.100 capacity for stage 2 of thermal
overload protection
The time constant setting of the
49P2.Tau 0.100~100.000 0.001 min 1.000 thermal model for stage 2 of thermal
overload protection
The convertor coefficient from the
49P2.K_T_Diff 0.000~200.000 0.001 30.000 current to the temperature for stage
2 of thermal overload protection
The cooling mode setting for stage 2
of thermal overload protection
49P2.Alpha_Cold 1.000~2.000 0.001 2.000 Usually, for different cooling mode
Natural cooling: 1.6
Forced cooling: 2
The time constant of heat dissipation
for stage 2 of thermal overload
protection
49P2.C_Disspt 0.100~10.000 0.001 1.000 When the equivalent heating current
is lower than 0.04In, the thermal time
constant adopts the value of
[49Pi.Tau]×[49Pi.C_Disspt].
Disabled Enabling/disabling stage 2 of thermal
49P2.En_Trp Disabled
Enabled overload protection operate to trip
Disabled Enabling/disabling stage 2 of thermal
49P2.En_Alm Disabled
Enabled overload protection operate to alarm
The option to maintain or dissipate
Maintain the data in case of SV measurement
49P2.Opt_Accu_CurreLos Dissipate
Dissipate abonormality for stage 2 of thermal
overload protection

9.2.23 Undercurrent Protection (37)

Access path: MainMenuSettingsProtection SettingsUC Settings

9 Name Range Step Unit Default Description
The current setting of undercurrent
37.I_Set (0.100~1.000)×In 0.001 A 0.500
protection
The time delay of undercurrent
37.t_Op 0.100~100.000 0.001 s 0.100
protection
The option of the current criterion
1P used by undercurrent protection
37.Opt_1P/3P 3P
3P 3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
37.Opt_LogicMode None CurrAndCBPos The option of auxiliary criterion

9-106 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Curr mode for undercurrent protection
CBPos None: no check
CurrOrCBPos Curr: check current condition
CurrAndCBPos CBPos: check normally open
auxiliary contact
CurrOrCBPos: check current
condition or normally open auxiliary
contact
CurrAndCBPos: check current
condition and normally open
auxiliary contact
Disabled Enabling/disabling undercurrent
37.En Enabled
Enabled protection
Enabling/disabling undercurrent
Trp protection operate to trip or alarm
37.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

9.2.24 Breaker Failure Protection (50BF)

Access path: MainMenuSettingsProtection SettingsBFP Settings

Name Range Step Unit Default Description

The phase current setting of
CBx.50BF.I_Set (0.050~40.000)×In 0.001 A 1.000
breaker failure protection
The zero-sequence current
CBx.50BF.3I0_Set (0.050~40.000)×In 0.001 A 1.000 setting of breaker failure
protection
The negative-sequence current
CBx.50BF.I2_Set (0.050~40.000)×In 0.001 A 1.000 setting of breaker failure
protection
The re-trip time delay of breaker
CBx.50BF.t_ReTrp 0.000~20.000 0.001 s 0.050
failure protection
The first time delay of breaker
CBx.50BF.t1_Op 0.000~20.000 0.001 s 0.100
failure protection 9
The second time delay of breaker
CBx.50BF.t2_Op 0.000~20.000 0.001 s 0.200
failure protection
Disabled Enabling/disabling breaker failure
CBx.50BF.En Enabled
Enabled protection
Disabled Enabling/disabling re-trip function
CBx.50BF.En_ReTrp Enabled
Enabled of breaker failure protection
Disabled Enabling/disabling first time delay
CBx.50BF.En_t1 Disabled
Enabled of breaker failure protection
CBx.50BF.En_t2 Disabled Disabled Enabling/disabling second time

PCS-902S Line Distance Relay 9-107

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Enabled delay of breaker failure protection
Enabling/disabling zero-
Disabled sequence overcurrent element of
CBx.50BF.En_3I0_1P Disabled
Enabled breaker failure protection via
single-phase initiating signal
Enabling/disabling phase
Disabled overcurrent element of breaker
CBx.50BF.En_Ip Disabled
Enabled failure protection via three-
phases initiating signal
Enabling/disabling zero-
Disabled sequence overcurrent element of
CBx.50BF.En_3I0_3P Disabled
Enabled breaker failure protection via
three-phases initiating signal
Enabling/disabling negative-
Disabled sequence overcurrent element of
CBx.50BF.En_I2_3P Disabled
Enabled breaker failure protection via
three-phases initiating signal
Enabling/disabling breaker failure
Disabled
CBx.50BF.En_CB_Ctrl Disabled protection be initiated by normally
Enabled
closed contact of circuit breaker
Enabling/disabling abnormality
Disabled
CBx.50BF.En_Alm_Init Disabled check of breaker failure initiating
Enabled
signal
Breaker failure check mode
None: no check
None Curr: check the current
Curr CBPos: check the normally open
CBx.50BF.Opt_LogicMode Curr
CBPos auxiliary contact
CurrAndCBPos CurrAndCBPos: check the
current and normally open
auxiliary contact
Enabling/disabling breaker failure
Disabled
9 CBx.50BF.En_InTrp_Init
Enabled
Enabled protection be initiated by internal
tripping

9.2.25 Stub Differential Protection (87STB)

Access path: MainMenuSettingsProtection SettingsStub Settings

Name Range Step Unit Default Description

Pickup current setting of stub
87STB.I_Pkp (0.050~40.000)×In 0.001 A 1.200
differential protection
Current setting of differential current
87STB.I_Alm (0.050~40.000)×In 0.001 A 0.100
alarm

9-108 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

87STB.Slope 0.300~1.000 0.001 0.500 Slope of current differential protection
87STB.t_Op 0.000~200.000 0.001 s 0.020 Time delay of stub differential protection
Disabled Enabling/disabling stub differential
87STB.En Enabled
Enabled protection
Disabled Enabling/disabling differential current
87STB.En_Diff_Alm Enabled
Enabled alarm function
Enabling/disabling stub differential
Disabled
87STB.En_CTS_Blk Disabled protection controlled by CT circuit
Enabled
failure

9.2.26 Dead Zone Protection (50DZ)

Access path: MainMenuSettingsProtection SettingsDZP Settings

Name Range Step Unit Default Description

The phase current setting of dead
CBx.50DZ.I_Set (0.050~40.000)×In 0.001 A 1.000
zone protection
CBx.50DZ.t_Op 0.000~30.000 0.001 s 0.100 Time delay of dead zone protection
Disabled Enabling/disabling dead zone
CBx.50DZ.En Enabled
Enabled protection

Disabled Enabling/disabling abnormality

CBx.50DZ.En_Alm_Init Disabled check of initiating signal for dead
Enabled
zone protection

9.2.27 Broken Conductor Protection (46BC)

Access path: MainMenuSettingsProtection SettingsBCP Settings

Name Range Step Unit Default Description

Minimum operating current setting of
46BC.I_Min (0.050~40.000)×In 0.001 A 1.000
broken conductor protection
Ratio setting (negative-sequence current
46BC.I2/I1_Set 0.000~5.000 0.001 0.500 to positive-sequence current) of broken
conductor protection
46BC.t_Op 0.000~100.000 0.001 s 1.000 Time delay of broken conductor protection

46BC.En
Disabled
Enabled
Enabled
Enabling/disabling
protection
broken conductor
9
Enabling/disabling broken conductor
Trp protection operate to trip or alarm
46BC.Opt_Trp/Alm Trp
Alm Trp: for tripping purpose
Alm: for alarm purpose

9.2.28 Pole Discrepancy Protection (62PD)

Access path: MainMenuSettingsProtection SettingsPDP Settings

PCS-902S Line Distance Relay 9-109

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Residual current setting of pole
CBx.62PD.3I0_Set (0.050~40.000)×In 0.001 A 1.000
discrepancy protection
Negative-sequence current setting
CBx.62PD.I2_Set (0.050~40.000)×In 0.001 A 1.000
of pole discrepancy protection
Time delay of pole discrepancy
CBx.62PD.t_Op 0.000~600.000 0.001 s 1.000
protection
Disabled Enabling/disabling pole
CBx.62PD.En Enabled
Enabled discrepancy protection
Enabling/disabling residual current
Disabled criterion and negative-sequence
CBx.62PD.En_3I0/I2_Ctrl Enabled
Enabled current criterion for pole
discrepancy protection
Enabling/disabling abnormality
Disabled
CBx.62PD.En_Init_Alm Disabled check of initiating signal for pole
Enabled
discrepancy protection

9.2.29 Flashover Protection (50F)

Access path: MainMenuSettingsProtection SettingsFOP Settings

Name Range Step Unit Default Description

Phase current setting of flashover
CBx.50F.I_Set (0.050~40.000)×In 0.001 A 1.000
protection
Residual current setting of flashover
CBx.50F.3I0_Set (0.050~40.000)×In 0.001 A 1.000
protection
Negative-sequence current setting of
CBx.50F.I2_Set (0.050~40.000)×In 0.001 A 1.000
flashover protection
CBx.50F.t1_Op 0.000~30.000 0.001 s 0.040 First time delay of flashover protection
CBx.50F.t2_Op 0.000~30.000 0.001 s 0.060 Second time delay of flashover protection
Disabled
CBx.50F.En - Enabled Enabling/disabling flashover protection
Enabled
Disabled Enabling/disabling phase current criterion
CBx.50F.En_Ip - Disabled
Enabled for flashover protection

9 CBx.50F.En_3I0
Disabled
Enabled
- Disabled
Enabling/disabling residual current criterion
for flashover protection
Disabled Enabling/disabling negative-sequence
CBx.50F.En_I2 - Enabled
Enabled current criterion for flashover protection

9.2.30 Transfer Trip (TT)

Access path: MainMenuSettingsProtection SettingsTT Settings

Name Range Step Unit Default Description

TT.t_Op 0.000~100.000 0.001 s 0.005 Time delay of transfer trip

9-110 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Disabled
TT.En Enabled Enabling/disabling transfer trip
Enabled
Disabled Enabling/disabling transfer trip controlled by local
TT.En_FD_Ctrl Enabled
Enabled fault detector element

Disabled Enabling/disabling transfer trip operate to block

TT.En_BlkAR Enabled
Enabled AR
Disabled Enabling/disabling transfer trip controlled by CB
TT.En_CB_Ctrl Enabled
Enabled position

9.2.31 Trip Logic (TRP)

Access path: MainMenuSettingsProtection SettingsTrip Logic Settings

Name Range Step Unit Default Description

Disabled Enabling/disabling auto-reclosing
En_MPF_Blk_AR Enabled
Enabled blocked when multi-phase fault happens
Disabled Enabling/disabling auto-reclosing
En_3PF_Blk_AR Enabled
Enabled blocked when three-phase fault happens
Time delay of confirming faulty phase
Line.t_PhSFail 0.000~100.000 0.001 s 0.200
selection failure
Disabled Enabling/disabling faulty phase
Line.En_PhSFail Disabled
Enabled selection failure
Disabled Enabling/disabling auto-reclosing
Line.En_PhSF_Blk_AR Enabled
Enabled blocked when faulty phase selection fails
The dwell time of tripping command,
empirical value is 0.04
t_Dwell_Trp 0.000~100.000 0.001 s 0.040 The tripping contact shall drop off under
conditions of no current or protection
tripping element drop-off.
Enabling/disabling three-phase tripping
Disabled
CBx.En_Trp3P Disabled mode of circuit breaker No.x for any fault
Enabled
conditions

9.2.32 Automatic Reclosure (79)

Access path: MainMenuSettingsProtection SettingsAR Settings

9
Name Range Step Unit Default Description
The control option of
synchronism check mode for AR
Config: select synchronism
Config
CBx.79.Opt_RSYN_ValidMode Setting check mode for AR by
Setting
configuration signals
Setting: select synchronism
check mode for AR by the

PCS-902S Line Distance Relay 9-111

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

settings
Disabled Enabling/disabling synchronism
CBx.79.En_SynChk Disabled
Enabled check for AR
Enabling/disabling dead
Disabled synchronization voltage and
CBx.79.En_SynDd_RefDd Disabled
Enabled dead reference voltage check for
AR
Enabling/disabling live
Disabled synchronization voltage and
CBx.79.En_SynLv_RefDd Disabled
Enabled dead reference voltage check for
AR
Enabling/disabling dead
Disabled
CBx.79.En_SynDd_RefLv Disabled synchronization voltage and live
Enabled
reference voltage check for AR
Disabled Enabling/disabling no check for
CBx.79.En_NoChk Disabled
Enabled AR
Maximum number of reclosing
CBx.79.Num 1~4 1 1
attempts
Dead time of first shot 1-pole
CBx.79.t_Dd_1PS1 0.000~600.000 0.001 s 0.800
reclosing
Dead time of first shot 3-pole
CBx.79.t_Dd_3PS1 0.000~600.000 0.001 s 0.600
reclosing
Dead time of second shot 3-pole
CBx.79.t_Dd_3PS2 0.000~600.000 0.001 s 0.600
reclosing
Dead time of third shot 3-pole
CBx.79.t_Dd_3PS3 0.000~600.000 0.001 s 0.600
reclosing
Dead time of fourth shot 3-pole
CBx.79.t_Dd_3PS4 0.000~600.000 0.001 s 0.600
reclosing
Time delay of circuit breaker in
CBx.79.t_CBClsd 0.000~600.000 0.001 s 5.000
closed position before reclosing
Time delay to wait for CB
healthy, and begin to timing

9 CBx.79.t_CBReady 0.000~600.000 0.001 s 5.000

when the
[CBx.79.CB_Healthy]
input
is
signal
de-
energized and if it is not
energized within this time delay,
AR will be blocked.
Maximum wait time for
CBx.79.t_Wait_Chk 0.000~600.000 0.001 s 10.000
synchronism check

CBx.79.t_Reclaim 0.000~600.000 0.001 s 15.000 Reclaim time of AR

Dropout time delay of blocking

CBx.79.t_DDO_Blk 0.000~600.000 0.001 s 5.000
AR, when blocking signal for AR

9-112 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

disappears, AR blocking
condition drops out after this
time delay

CBx.79.t_AddDly 0.000~600.000 0.001 s 0.500 Additional time delay for AR

Maximum wait time for reclosing

CBx.79.t_WaitMaster 0.000~600.000 0.001 s 3.000 permissive signal from master
AR
Time delay of discriminating
another fault, and begin to times
after 1-pole AR initiated, 3-pole
CBx.79.t_SecFault 0.000~600.000 0.001 s 0.300 AR will be initiated if another fault
happens during this time delay.
AR will be blocked if another fault
happens after that.
Time delay of excessive trip
CBx.79.t_PersistTrp 0.000~600.000 0.001 s 0.200
signal to block AR
Time delay allow for CB status
CBx.79.t_Fail 0.000~600.000 0.001 s 0.200 change to conform reclosing
successful

CBx.79.t_PW 0.000~600.000 0.001 s 0.120 Pulse width of AR closing signal

Enabling/disabling auto-
Disabled
CBx.79.En_AddDly Disabled reclosing with an additional dead
Enabled
time delay
Enabling/disabling confirm
Disabled
CBx.79.En_FailCheck Disabled whether AR is successful by
Enabled
checking CB state
Enabling/disabling auto-
Disabled reclosing blocked when a fault
CBx.79.En_PDF_Blk Disabled
Enabled occurs under pole disagreement
condition
Disabled Enabling/disabling adjust the
CBx.79.En_CutPulse Disabled
Enabled length of reclosing pulse

CBx.79.En
Disabled
Enabled
Enabling/disabling auto- 9
Enabled reclosing
Enabling/disabling AR by
external input signal besides
Setting logic setting [CBx.79.En]
CBx.79.Opt_Enable Setting
Setting&Config Setting: only the setting
Setting&Config: the setting and
configuration signal
Disabled Enabling/disabling AR be
CBx.79.En_CBInit Disabled
Enabled initiated by open state of circuit

PCS-902S Line Distance Relay 9-113

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

breaker
Option of AR priority
None: single-breaker
None arrangement
CBx.79.Opt_Priority High None High: master AR of multi-breaker
Low arrangement
Low: slave AR of multi-breaker
arrangement
Control option of AR mode
Config: select AR mode by
Config
CBx.79.Opt_ValidMode Setting configuration signals
Setting
Setting: select AR mode by the
settings
Disabled Enabling/disabling 1-pole AR
CBx.79.En_1P Disabled
Enabled mode
Disabled Enabling/disabling 3-pole AR
CBx.79.En_3P Enabled
Enabled mode
Disabled Enabling/disabling 1/3-pole AR
CBx.79.En_1P/3P Disabled
Enabled mode

9.2.33 Impedance-Based Fault Location (FL)

Access path: MainMenuSettingsProtection SettingsLine Settings

Name Range Step Unit Default Description

Positive-sequence reactance of the whole line
X1L (0.000~4Unn)/In 0.001 Ω 10.000
(secondary value)
Positive-sequence resistance of the whole line
R1L (0.000~4Unn)/In 0.001 Ω 1.000
(secondary value)
Zero-sequence reactance of the whole line
X0L (0.000~4Unn)/In 0.001 Ω 20.000
(secondary value)
Zero-sequence resistance of the whole line
R0L (0.000~4Unn)/In 0.010 Ω 3.000
(secondary value)
Zero-sequence mutual reactance (secondary
X0M (0.000~4Unn)/In 0.001 Ω 20.000
value)

9 R0M (0.000~4Unn)/In 0.001 Ω 3.000

Zero-sequence mutual resistance of the whole
line (secondary value)
LineLength 0.00~6000.00 0.01 km 100.00 Total length of the whole line
Voltage setting of MOV (Metal-oxide Varistor)
U_MOV_Prot 0.000~200.000 0.001 V 30.000
in series compensated line
Disabled Enabling/disabling series capacitor
En_SerCmp Disabled
Enabled compensation

9.3 Measurement and Control Settings

9.3.1 Function
Access path: MainMenuSettingsMeas Control SettingsFunction Settings

9-114 PCS-902S Line Distance Relay

Date: 2023-08-01
 9 Settings

Name Range Step Unit Default Description

Disabled Enabling/disabling residual overvoltage
Prot.En_Alm_ROV Disabled
Enabled supervision
The threshold of residual overvoltage
Prot.3U0_Alm_ROV 0.0~100.0 0.1 %Un 10.0 supervision, which is indicated by the
percentage of the rated value
Disabled Enabling/disabling phase undervoltage
Prot.En_Alm_UV Disabled
Enabled supervision
The threshold of phase undervoltage
Prot.U_Alm_UV 0.0~100.0 0.1 %Un 10.0 supervision, which is indicated by the
percentage of the rated value
Threshold to limit the zero-drift influence
of the protection voltage due to the
temperature or other environmental
Prot.ZeroDrift_U 0.00~1.00 0.01 % 0.20
factors. A measured value less than this
setting will be regarded as a zero drift and
ignored.
Disabled Enabling/disabling residual overcurrent
Prot.En_Alm_ROC Disabled
Enabled supervision (single CB application)
Enabling/disabling residual overcurrent
Disabled
Prot.CB1.En_Alm_ROC Disabled supervision of circuit breaker No.1 (double
Enabled
CBs application)
Enabling/disabling residual overcurrent
Disabled
Prot.CB2.En_Alm_ROC Disabled supervision of circuit breaker No.2 (double
Enabled
CBs application)
The threshold of residual overcurrent
supervision, which is indicated by the
Prot.3I0_Alm_ROC 0.0~100.0 0.1 %In 10.0
percentage of the rated value (single CB
application)
The threshold of residual overcurrent
supervision for circuit breaker No.1, which
Prot.CB1.3I0_Alm_ROC 0.0~100.0 0.1 %In 10.0
is indicated by the percentage of the rated
value (double CBs application)
The threshold of residual overcurrent
supervision for circuit breaker No.2, which
9
Prot.CB2.3I0_Alm_ROC 0.0~100.0 0.1 %In 10.0
is indicated by the percentage of the rated
value (double CBs application)
The option of CT wiring mode which used
by current measurement (single CB
Ia-Ib-Ic application)
Prot.Opt_CT_Measmt Ia-Ib-Ic
Ia-Ic If "Ia-Ic" is selected, in protection and logic

calculation, → = −(→ + →).

Ib Ia Ic

Prot.CB1.Opt_CT_Measmt Ia-Ib-Ic Ia-Ib-Ic The option of CT wiring mode for circuit

PCS-902S Line Distance Relay 9-115

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 9 Settings

Name Range Step Unit Default Description

Ia-Ic breaker No.1 which used by current
measurement (double CBs application)
If "Ia-Ic" is selected, in protection and logic

calculation, → = −(→ + →).

Ib Ia Ic

The option of CT wiring mode for circuit

breaker No.2 which used by current
Ia-Ib-Ic measurement (double CBs application)
Prot.CB2.Opt_CT_Measmt Ia-Ib-Ic
Ia-Ic If "Ia-Ic" is selected, in protection and logic

calculation, → = −(→ + →).

Ib Ia Ic

Threshold to limit the zero-drift influence

of the current due to the temperature or
other environmental factors. A measured
Prot.ZeroDrift_I 0.00~1.00 0.01 % 0.20
value less than this setting will be
regarded as a zero drift and ignored.
(single CB application)
Threshold to limit the zero-drift influence
of the current due to the temperature or
other environmental factors. A measured
Prot.CB1.ZeroDrift_I 0.00~1.00 0.01 % 0.20
value less than this setting will be
regarded as a zero drift and ignored.
(double CBs application)
Threshold to limit the zero-drift influence
of the current due to the temperature or
other environmental factors. A measured
Prot.CB2.ZeroDrift_I 0.00~1.00 0.01 % 0.20
value less than this setting will be
regarded as a zero drift and ignored.
(double CBs application)
Threshold to limit the zero-drift influence
of the power due to the temperature or
other environmental factors. A measured
Prot.ZeroDrift_PQ 0.00~1.00 0.01 % 0.50
9 value less than this setting will be
regarded as a zero drift and ignored.
(single CB application)
Threshold to limit the zero-drift influence
of the power due to the temperature or
other environmental factors. A measured
Prot.CB1.ZeroDrift_PQ 0.00~1.00 0.01 % 0.50
value less than this setting will be
regarded as a zero drift and ignored.
(double CBs application)
Threshold to limit the zero-drift influence
Prot.CB2.ZeroDrift_PQ 0.00~1.00 0.01 % 0.50
of the power due to the temperature or

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 9 Settings

Name Range Step Unit Default Description

other environmental factors. A measured
value less than this setting will be
regarded as a zero drift and ignored.
(double CBs application)
Threshold to limit the zero-drift influence
of the residual current from parallel line
due to the temperature or other
3I0Adj.ZeroDrift_I 0.00~1.00 0.01 % 0.20
environmental factors. A measured value
less than this setting will be regarded as a
zero drift and ignored.
Threshold to limit the zero-drift influence
of the synchronism voltage (UB1) due to
the temperature or other environmental
UB1.USyn.ZeroDrift_U 0.00~1.00 0.01 % 0.20
factors. A measured value less than this
setting will be regarded as a zero drift and
ignored.
Threshold to limit the zero-drift influence
of the synchronism voltage (UL2) due to
the temperature or other environmental
UL2.USyn.ZeroDrift_U 0.00~1.00 0.01 % 0.20
factors. A measured value less than this
setting will be regarded as a zero drift and
ignored.
Threshold to limit the zero-drift influence
of the synchronism voltage (UB2) due to
the temperature or other environmental
UB2.USyn.ZeroDrift_U 0.00~1.00 0.01 % 0.20
factors. A measured value less than this
setting will be regarded as a zero drift and
ignored.

9.3.2 Synchronism Check (25)

Access path: MainMenuSettingsMeas Control SettingsSyn Settings

Name Range Step Unit Default Description

Selection of decision 9
mode for
synchronism check
Setting: the mode
Setting depends on the
CBx.25.Opt_ValidMode Setting
Config settings
Config: the mode
depends on
configuration signals
("CBx.in_syn_chk"

PCS-902S Line Distance Relay 9-117

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 9 Settings

Name Range Step Unit Default Description

and
"CBx.in_vol_chk")
Enabling/disabling
synchro-check (valid
Disabled
CBx.25.En_SynChk Enabled only if the setting
Enabled
[CBx.25.Opt_ValidM
ode]=Setting)
Enabling/disabling
dead charge check
Disabled (valid only if the
CBx.25.En_DdChk Enabled
Enabled setting
[CBx.25.Opt_ValidM
ode]=Setting)
Percentage threshold
CBx.25.U_UV 0.00~100.00 0.01 % 80.00 of under voltage for
CB closing blocking
Percentage threshold
CBx.25.U_OV 100.00~170.00 0.01 % 170.00 of over voltage for CB
closing blocking
Under frequency
CBx.25.f_UF 45.000~65.000 0.001 Hz 45.000 threshold for CB
closing blocking
Over frequency
CBx.25.f_OF 45.000~65.000 0.001 Hz 65.000 threshold for CB
closing blocking
Ua
Ub
Selection of voltage
Uc
CBx.25.Opt_U_SynChk Ua for synchronism
Uab
check
Ubc
Uca
Threshold of voltage

9 CBx.25.U_Diff_Set 0.00~100.00 0.01 V 10.00

difference
synchronism
for
check
(first group)
Threshold of voltage
difference for
CBx.25.U_Diff_Set2 0.00~100.00 0.01 V 10.00
synchronism check
(second group)
Threshold of
frequency difference
CBx.25.f_Diff_Set 0.00~2.00 0.01 Hz 0.50
for synchronism
check (first group)

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 9 Settings

Name Range Step Unit Default Description

Threshold of
frequency difference
CBx.25.f_Diff_Set2 0.00~2.00 0.01 Hz 0.50
for synchronism
check (second group)
Threshold of rate-of-
change of frequency
CBx.25.df/dt_Set 0.00~2.00 0.01 Hz/s 1.00
difference for
synchronism check.
Threshold of phase
difference for
CBx.25.phi_Diff_Set 0.00~180.00 0.01 ° 15.00
synchronism check
(first group)
Threshold of phase
difference for
CBx.25.phi_Diff_Set2 0.00~180.00 0.01 ° 15.00
synchronism check
(second group)
Compensation angle
of phase difference
CBx.25.phi_Comp 0.00~360.00 0.01 ° 0.00
for synchronism
check
Selection of dead
charge check mode
SynDdRefDd:
synchronism voltage
is dead & reference
voltage is dead
SynLvRefDd:
synchronism voltage
SynDdRefDd is live & reference
SynLvRefDd voltage is dead
SynDdRefLv SynDdRefLv:
CBx.25.Opt_Mode_DdChk RefDd AnySideDd synchronism voltage
SynDd
SynLvRefDd/SynDdRefLv
is dead & reference
voltage is live
9
AnySideDd RefDd: reference
voltage is dead
SynDd: synchronism
voltage is dead
SynLvRefDd/SynDd
RefLv: synchronism
voltage is live &
reference voltage is
dead or synchronism

PCS-902S Line Distance Relay 9-119

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 9 Settings

Name Range Step Unit Default Description

voltage is dead &
reference voltage is
live
AnySideDd:
synchronism voltage
or reference voltage
is dead
Threshold for voltage
dead check
When the setting
[CBx.25.Opt_U_Syn
Chk] is set as "Uab",
CBx.25.U_DdChk 0.00~100.00 0.01 V 17.32
"Ubc" or "Uca", the
setting will be divided
by 1.732 to be used
as the threshold for
voltage dead check
Threshold for voltage
live check
When the setting
[CBx.25.Opt_U_Syn
Chk] is set as "Uab",
CBx.25.U_LvChk 0.00~100.00 0.01 V 34.64
"Ubc" or "Uca", the
setting will be divided
by 1.732 to be used
as the threshold for
voltage live check
Threshold of duration
CBx.25.t_Reset 0~60 1 s 5
for synchrocheck
Circuit breaker
closing time. It is the
time from receiving
CBx.25.t_Close_CB 0~2000 1 ms 20
9 closing command
pulse till the CB is
completely closed.
Enabling/disabling
Disabled
CBx.25.En_f_Diff_Chk Enabled frequency difference
Enabled
check
Enabling/disabling
Disabled
CBx.25.En_df/dt_Chk Enabled frequency variation
Enabled
difference check

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 9 Settings

9.3.3 Double Point Status

Access path: MainMenuSettingsMeas Control SettingsDPS Settings

Name Range Step Unit Default Description

The DPU (delay pick up) time of DPS, i.e. debounce
CB**.DPS.t_DPU 0~60000 1 ms 500
time (for circuit breaker No.**)
Disabled Enabling/disabling DPS alarm (for circuit breaker
CB**.DPS.En_Alm Disabled
Enabled No.**)
CB**.DPS.t_Alm 0~60000 1 ms 500 Time delay of DPS alarm (for circuit breaker No.**)
The DPU (delay pick up) time of DPS, i.e. debounce
DS**.DPS.t_DPU 0~60000 1 ms 500
time (for circuit breaker No.**)
Disabled Enabling/disabling DPS alarm (for circuit breaker
DS**.DPS.En_Alm Disabled
Enabled No.**)
DS**.DPS.t_Alm 0~60000 1 ms 500 Time delay of DPS alarm (for circuit breaker No.**)

9.3.4 Control
Access path: MainMenuSettingsMeas Control SettingsControl Settings

Name Range Step Unit Default Description

Pulse Width (PW), i.e. holding time, for opening
CB**.t_PW_Opn 0~60000 1 ms 500
output of circuit breaker No.**
Pulse Width (PW), i.e. holding time, for closing
CB**.t_PW_Cls 0~60000 1 ms 500
output of circuit breaker No.**
Pulse Width (PW), i.e. holding time, for opening
DS**.t_PW_Opn 0~60000 1 ms 500
output of disconnector switch No.**
Pulse Width (PW), i.e. holding time, for closing
DS**.t_PW_Cls 0~60000 1 ms 500
output of disconnector switch No.**
Pulse Width (PW), i.e. holding time, for opening
DirCtrl**.t_PW_Opn 0~60000 1 ms 500
output of direct control object No.**
Pulse Width (PW), i.e. holding time, for closing
DirCtrl**.t_PW_Cls 0~60000 1 ms 500
output of direct control object No.**

9.3.5 Interlocking Logic

Access path: MainMenuSettingsMeas Control SettingsInterlock Settings
9
Name Range Step Unit Default Description
Enabling/disabling open output of circuit
Disabled
CB**.En_CILO_Opn Disabled breaker No.** controlled by the interlocking
Enabled
logic
Enabling/disabling closing output of circuit
Disabled
CB**.En_CILO_Cls Disabled breaker No.** controlled by the interlocking
Enabled
logic
Disabled Enabling/disabling open output of disconnector
DS**.En_CILO_Opn Disabled
Enabled switch No.** controlled by the interlocking logic

PCS-902S Line Distance Relay 9-121

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 9 Settings

Name Range Step Unit Default Description

Enabling/disabling closing output of
Disabled
DS**.En_CILO_Cls Disabled disconnector switch No.** controlled by the
Enabled
interlocking logic
Disabled Enabling/disabling open output of direct control
DirCtrl**.En_CILO_Opn Disabled
Enabled object No.** controlled by the interlocking logic
Enabling/disabling closing output of direct
Disabled
DirCtrl**.En_CILO_Cls Disabled control object No.** controlled by the
Enabled
interlocking logic

9.3.6 AC Analog Input Calibration

Access path: Main MenuSettingsMeas Control SettingsAC Calbr Settings

Setting Default Range Step Unit Remark

Phase-A current input calibration
Prot.CBx.K_Calbr_Ia 10000 9000~11000 1
coefficients for circuit breaker No.x
Phase-B current input calibration
Prot.CBx.K_Calbr_Ib 10000 9000~11000 1
coefficients for circuit breaker No.x
Phase-C current input calibration
Prot.CBx.K_Calbr_Ic 10000 9000~11000 1
coefficients for circuit breaker No.x
Phase-A voltage input calibration
Prot.K_Calbr_Ua 10000 9000~11000 1
coefficients
Phase-B voltage input calibration
Prot.K_Calbr_Ub 10000 9000~11000 1
coefficients
Phase-C voltage input calibration
Prot.K_Calbr_Uc 10000 9000~11000 1
coefficients
Phase-AB voltage input calibration
Prot.K_Calbr_Uab 10000 9000~11000 1
coefficients
Phase-BC voltage input calibration
Prot.K_Calbr_Ubc 10000 9000~11000 1
coefficients
Phase-CA voltage input calibration
Prot.K_Calbr_Uca 10000 9000~11000 1
coefficients
Phase-A active power calibration
Prot.CBx.K_Calbr_Pa 10000 -900~11000 1

9 coefficients for circuit breaker No.x

Phase-B active power calibration
Prot.CBx.K_Calbr_Pb 10000 -900~11000 1
coefficients for circuit breaker No.x
Phase-C active power calibration
Prot.CBx.K_Calbr_Pc 10000 -900~11000 1
coefficients for circuit breaker No.x
Phase-A reactive power calibration
Prot.CBx.K_Calbr_Qa 0 -900~11000 1
coefficients for circuit breaker No.x
Phase-B reactive power calibration
Prot.CBx.K_Calbr_Qb 0 -900~11000 1
coefficients for circuit breaker No.x
Phase-C reactive power calibration
Prot.CBx.K_Calbr_Qc 0 -900~11000 1
coefficients for circuit breaker No.x

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 9 Settings

Setting Default Range Step Unit Remark

Single voltage input calibration
UB1.K_Calbr_U 10000 9000~11000 1 coefficient for synchronization check,
double bus, etc.

9.3.7 Energy Metering

Access path: MainMenuSettingsMeas Control SettingsEnergy Metering Settings

Name Range Step Unit Default Description

MMTR.U2n 0.00~200.00 0.01 V 100.00 Rated secondary voltage for metering
MMTR.I2n 1~5 1 A 5 Rated secondary current for metering

This device displays the energy metering data of one object. Thus, for an
application with multiple circuit breakers, for instance, one-and-half
breakers arrangement, these two settings should be set according to the
appointed object.

9.3.8 Circuit Breaker Supervision (SCBR)

Access path: Main MenuSettingsMeas Control SettingsSCBR Settings

Name Range Step Unit Default Description

The primary rated current for the
CBx.SCBR.I1n 1~60000 1 A 1000
circuit breaker supervision
The secondary rated current for
CBx.SCBR.I2n 1~5 1 A 5
the circuit breaker supervision
Initial counting number of CB's
CBx.SCBR.N_Opn_Init 0~1000000 1 0
trip counter
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Alm_N_Opn Disabled alarm for the counting result of
Enabled
CB's trip counter
The threshold of out-of-limit
CBx.SCBR.Th_Alm_N_Opn 0~1000000 1 1000 alarm for the counting result of
CB's trip counter 9
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Wrn_N_Opn Disabled warning for the counting result of
Enabled
CB's trip counter
The threshold of the out-of-limit
CBx.SCBR.Th_Wrn_N_Opn 0~1000000 1 5000 warning for the counting result of
CB's trip counter
The compensation factor for the
CBx.SCBR.t_Opn_Comp 0~500 1 ms 0 travel time of CB's opening
contact

PCS-902S Line Distance Relay 9-123

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 9 Settings

Name Range Step Unit Default Description

The compensation factor for the
CBx.SCBR.t_Cls_Comp 0~500 1 ms 0
travel time of CB's closing contact
Enabling/disabling the overtime
Disabled
CBx.SCBR.En_Alm_t_Opn Disabled alarm for the travel time of CB's
Enabled
opening contact
The threshold of overtime alarm
CBx.SCBR.Th_Alm_t_Opn 0~10000 1 ms 50 for the travel time of CB's opening
contact
Enabling/disabling the overtime
Disabled
CBx.SCBR.En_Wrn_t_Opn Disabled warning for the travel time of CB's
Enabled
opening contact
The threshold of overtime
CBx.SCBR.Th_Wrn_t_Opn 0~10000 1 ms 100 warning for the travel time of CB's
opening contact
Enabling/disabling the overtime
Disabled
CBx.SCBR.En_Alm_t_Cls Disabled alarm for the travel time of CB's
Enabled
closing contact
The threshold of overtime alarm
CBx.SCBR.Th_Alm_t_Cls 0~10000 1 ms 50 for the travel time of CB's closing
contact
Enabling/disabling the overtime
Disabled
CBx.SCBR.En_Wrn_t_Cls Disabled warning for the travel time of CB's
Enabled
closing contact
The threshold of overtime
CBx.SCBR.Th_Wrn_t_Cls 0~10000 1 ms 100 warning for the travel time of CB's
closing contact
CBx.SCBR.RemainLife_Init 0~100000 1 10000 Initial value of CB remaining life
Disabled Enabling/disabling the alarm of
CBx.SCBR.En_Alm_RemainLife Disabled
Enabled CB remaining life
The alarm threshold of CB
CBx.SCBR.Th_Alm_RemainLife 0~10000 1 ms 5000
remaining life
The rated current of the initial
CBx.SCBR.I_Rated_Life 0~1000 0.1 kA 1.0
9 point on CB maintenance curve
The characteristic current of the
CBx.SCBR.I_02_Life 0~1000 0.1 kA 2.0 point No.02 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_03_Life 0~1000 0.1 kA 2.0 point No.03 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_04_Life 0~1000 0.1 kA 2.0 point No.04 on CB maintenance
curve
CBx.SCBR.I_05_Life 0~1000 0.1 kA 2.0 The characteristic current of the

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 9 Settings

Name Range Step Unit Default Description

point No.05 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_06_Life 0~1000 0.1 kA 2.0 point No.06 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_07_Life 0~1000 0.1 kA 2.0 point No.07 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_08_Life 0~1000 0.1 kA 2.0 point No.08 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_09_Life 0~1000 0.1 kA 2.0 point No.09 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_10_Life 0~1000 0.1 kA 2.0 point No.10 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_11_Life 0~1000 0.1 kA 2.0 point No.11 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_12_Life 0~1000 0.1 kA 2.0 point No.12 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_13_Life 0~1000 0.1 kA 2.0 point No.13 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_14_Life 0~1000 0.1 kA 2.0 point No.14 on CB maintenance
curve
The characteristic current of the
CBx.SCBR.I_15_Life 0~1000 0.1 kA 2.0 point No.15 on CB maintenance
curve

CBx.SCBR.I_Fault_Life 0~1000 0.1 kA 10.0

The fault current of the terminal
point on CB maintenance curve
9
The operating times
corresponding to the rated
CBx.SCBR.Num_Rated_Life 0-100000 1 10000
current of the initial point on CB
maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_02_Life 0-100000 1 8000
characteristic current of the point
No.02 on CB maintenance curve
CBx.SCBR.Num_03_Life 0-100000 1 8000 The operating times

PCS-902S Line Distance Relay 9-125

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 9 Settings

Name Range Step Unit Default Description

corresponding to the
characteristic current of the point
No.03 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_04_Life 0-100000 1 8000
characteristic current of the point
No.04 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_05_Life 0-100000 1 8000
characteristic current of the point
No.05 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_06_Life 0-100000 1 8000
characteristic current of the point
No.06 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_07_Life 0-100000 1 8000
characteristic current of the point
No.07 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_08_Life 0-100000 1 8000
characteristic current of the point
No.08 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_09_Life 0-100000 1 8000
characteristic current of the point
No.09 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_10_Life 0-100000 1 8000
characteristic current of the point
No.10 on CB maintenance curve
The operating times

9 CBx.SCBR.Num_11_Life 0-100000 1 8000

corresponding to the
characteristic current of the point
No.11 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_12_Life 0-100000 1 8000
characteristic current of the point
No.12 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_13_Life 0-100000 1 8000
characteristic current of the point
No.13 on CB maintenance curve

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 9 Settings

Name Range Step Unit Default Description

The operating times
corresponding to the
CBx.SCBR.Num_14_Life 0-100000 1 8000
characteristic current of the point
No.14 on CB maintenance curve
The operating times
corresponding to the
CBx.SCBR.Num_15_Life 0-100000 1 8000
characteristic current of the point
No.15 on CB maintenance curve
The operating times
corresponding to the fault current
CBx.SCBR.Num_Fault_Life 0-100000 1 100
of the terminal point on CB
maintenance curve
The current exponent factor to
CBx.SCBR.CurrExponent 0.5~3.0 0.1 2.0 calculate CB's accumulated
abrasion
The initial value of CB's
CBx.SCBR.Abr_Init 0~10000000 0.01 0
accumulated abrasion
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Alm_Abr Disabled alarm of CB's accumulated
Enabled
abrasion
The threshold of out-of-limit
CBx.SCBR.Th_Alm_Abr 0~10000000 0.01 2000 alarm of CB's accumulated
abrasion
Enabling/disabling the out-of-limit
Disabled
CBx.SCBR.En_Wrn_Abr Disabled warning of CB's accumulated
Enabled
abrasion
The threshold of out-of-limit
CBx.SCBR.Th_Alm_Abr 0~10000000 0.01 5000 warning of CB's accumulated
abrasion

9.4 PMU Settings

9.4.1 PMU Global Settings

9
Access path: MainMenuSettingsPMU SettingsPMU Global Settings

Name Range Step Unit Default Description

Disabled Enabling/Disabling the synchrophasor
En_PMU Enabled
Enabled measurement function
PMU class option
P_Class P class: faster response time
Opt_Class_PMU M_Class
M_Class M class: higher measurement
precision
DataRate 10~120 1 fps 50 Data transmission rate (to PDC)

PCS-902S Line Distance Relay 9-127

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 9 Settings

Name Range Step Unit Default Description

Max. 16
Substation_PMU NR_Station1 Name of PMU substation
characters
To inform the update of version, this
number should be increased if any
N_Chgd_CFG 0~65535 1 1
configuration or setting has been
modified on a device in operation.
Port_TCP 0~65535 1 4712 PMU port TCP address
Port_UDP 1024~65535 1 4713 PMU port UDP address

9.4.1 PMU Comm Settings

Access path: MainMenuSettingsPMU SettingsPMU Comm SettingsPDC** Settings

Name Range Step Unit Default Description

PDC01 name that the
PDC01.Name WAMS1
device is connected to
Destination IP address
when the communication
between the PMU and
PDC01 is related with
PDC01.IP_TCP 0.0.0.0~255.255.255.255 198.120.0.20 TCP protocol.
When the setting
[PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
when the communication
between the PMU and
PDC01 is related with
UDP protocol.
PDC01.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-

9 UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when
the communication
between the PMU and
PDC01 is through UDP
PDC01.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1
protocol and multicast
mode.
When the setting
[PDC01.Opt_Protocol] is

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 9 Settings

Name Range Step Unit Default Description

set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP",
and the setting
[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
PDC01 communication
protocol
None: communication
protocol is null, the
communication between
PMU and PDC is not
established.
TCP: TCP for the
transmission of
configuration frame,
command frame and
data frame.
Spontaneous-UDP:
Spontaneous-mode
UDP for the transmission
of configuration frame,
None
and data frame. his
TCP
device sends data by
PDC01.Opt_Protocol Spontaneous-UDP None
UDP to a designated
TCP-UDP
destination without
Commanded-UDP
stopping, whether a
receiving device is
present or not.
TCP-UDP: TCP for the
transmission of

9
configuration frame,
command frame, and
UDP for the transmission
of data frame.
Commanded-UDP:
Commanded-mode UDP
for the transmission of
configuration frame,
command frame and
data frame. Commands
can be sent in UDP

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 9 Settings

Name Range Step Unit Default Description

frames. This device only
sends data when a client
requests it.
Unicast
Option of UDP broadcast
PDC01.Opt_UDP Broadcast Multicast
mode
Multicast
ID code of PDC01 that
PDC01.IDCODE 1~65534 1 the device is connected
to
PDC02 name that the
PDC02.Name WAMS2
device is connected to
Destination IP address
when the communication
between the PMU and
PDC02 is related with
PDC02.IP_TCP 0.0.0.0~255.255.255.255 198.121.0.20 TCP protocol.
When the setting
[PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
when the communication
between the PMU and
PDC02 is related with
UDP protocol.
PDC02.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when

9 the communication
between the PMU and
PDC02 is through UDP
protocol and multicast
mode.
PDC02.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1
When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP",
and the setting

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 9 Settings

Name Range Step Unit Default Description

[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
PDC02 communication
protocol
None: communication
protocol is null, the
communication between
PMU and PDC is not
established.
TCP: TCP for the
transmission of
configuration frame,
command frame and
data frame.
Spontaneous-UDP:
Spontaneous-mode
UDP for the transmission
of configuration frame,
and data frame. his
None device sends data by
TCP UDP to a designated
PDC02.Opt_Protocol Spontaneous-UDP None destination without
TCP-UDP stopping, whether a
Commanded-UDP receiving device is
present or not.
TCP-UDP: TCP for the
transmission of
configuration frame,
command frame, and
UDP for the transmission
of data frame.

9
Commanded-UDP:
Commanded-mode UDP
for the transmission of
configuration frame,
command frame and
data frame. Commands
can be sent in UDP
frames. This device only
sends data when a client
requests it.
PDC02.Opt_UDP Unicast Multicast Option of UDP broadcast

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 9 Settings

Name Range Step Unit Default Description

Broadcast mode
Multicast
ID code of PDC02 that
PDC02.IDCODE 1~65534 2 the device is connected
to
PDC03 name that the
PDC03.Name WAMS3
device is connected to
Destination IP address
when the communication
between the PMU and
PDC03 is related with
PDC03.IP_TCP 0.0.0.0~255.255.255.255 198.122.0.20 TCP protocol.
When the setting
[PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
when the communication
between the PMU and
PDC03 is related with
UDP protocol.
PDC03.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when
the communication
between the PMU and
PDC03 is through UDP
protocol and multicast

9 mode.
When the setting
PDC03.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1 [PDC01.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP",
and the setting
[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
PDC03.Opt_Protocol None None PDC03 communication

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 9 Settings

Name Range Step Unit Default Description

TCP protocol
Spontaneous-UDP None: communication
TCP-UDP protocol is null, the
Commanded-UDP communication between
PMU and PDC is not
established.
TCP: TCP for the
transmission of
configuration frame,
command frame and
data frame.
Spontaneous-UDP:
Spontaneous-mode
UDP for the transmission
of configuration frame,
and data frame. his
device sends data by
UDP to a designated
destination without
stopping, whether a
receiving device is
present or not.
TCP-UDP: TCP for the
transmission of
configuration frame,
command frame, and
UDP for the transmission
of data frame.
Commanded-UDP:
Commanded-mode UDP
for the transmission of
configuration frame,
command frame and
data frame. Commands 9
can be sent in UDP
frames. This device only
sends data when a client
requests it.
Unicast
Option of UDP broadcast
PDC03.Opt_UDP Broadcast Multicast
mode
Multicast
ID code of PDC03 that
PDC03.IDCODE 1~65534 3
the device is connected

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 9 Settings

Name Range Step Unit Default Description

to
PDC04 name that the
PDC04.Name WAMS4
device is connected to
Destination IP address
when the communication
between the PMU and
PDC04 is related with
PDC04.IP_TCP 0.0.0.0~255.255.255.255 198.120.0.100 TCP protocol.
When the setting
[PDC01.Opt_Protocol] is
set as "TCP" or "TCP-
UDP", the setting is valid.
Destination IP address
when the communication
between the PMU and
PDC01 is related with
UDP protocol.
PDC04.IP_UDP_Dest 0.0.0.0~255.255.255.255 198.120.0.20 When the setting
[PDC04.Opt_Protocol] is
set as "Spontaneous-
UDP", "Commanded-
UDP" or "TCP-UDP", the
setting is valid.
Source IP address when
the communication
between the PMU and
PDC04 is through UDP
protocol and multicast
mode.
When the setting
PDC04.IP_MulticastSrc 0.0.0.0~255.255.255.255 198.120.0.1 [PDC01.Opt_Protocol] is
set as "Spontaneous-

9 UDP",
UDP"
"Commanded-
or "TCP-UDP",
and the setting
[PDC01.Opt_UDP] is set
as "Multicast", the
setting is valid.
None PDC04 communication
TCP protocol
PDC04.Opt_Protocol Spontaneous-UDP None None: communication
TCP-UDP protocol is null, the
Commanded-UDP communication between

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 9 Settings

Name Range Step Unit Default Description

PMU and PDC is not
established.
TCP: TCP for the
transmission of
configuration frame,
command frame and
data frame.
Spontaneous-UDP:
Spontaneous-mode
UDP for the transmission
of configuration frame,
and data frame. his
device sends data by
UDP to a designated
destination without
stopping, whether a
receiving device is
present or not.
TCP-UDP: TCP for the
transmission of
configuration frame,
command frame, and
UDP for the transmission
of data frame.
Commanded-UDP:
Commanded-mode UDP
for the transmission of
configuration frame,
command frame and
data frame. Commands
can be sent in UDP
frames. This device only
sends data when a client
requests it. 9
Unicast
Option of UDP broadcast
PDC04.Opt_UDP Broadcast Multicast
mode
Multicast
ID code of PDC04 that
PDC04.IDCODE 1~65534 4 the device is connected
to

9.4.2 PMU Bay Settings

Access path: MainMenuSettingsPMU SettingsPMUBay Settings

PCS-902S Line Distance Relay 9-135

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 9 Settings

xx is determined by the setting [Name_PMUBay] in the submenu PMUBay

Settings.

Name Range Step Unit Default Description

STN- Configurable the name of PMU
Name_PMUBay Max. 12 characters
Bay01 bay
VT primary rated voltage for
xx.U1n 0.001~1000.000 0.001 kV 220.000
PMU bay
CT primary rated current for
xx.I1n 0.1~20000.0 0.1 A 1000.0
PMU bay
None
Bay
xx.Opt_UnitType 1 Bay Bay application scenario
Bus(U_3P)
Bus(U_1P)
U1
Ua Option of base voltage for
xx.Opt_U_MeasFreq 1 U1
Ub frequency measurement
Uc
Enabling/Disabling disturbance
Disabled
xx.En_TrigDFR Enabled fault recording function in case
Enabled
any following over limit situation
xx.Up_UpLmt 0.010~2.000 0.001 Un 1.200 Upper limit of phase voltage
Upper limit of positive
xx.U1_UpLmt 0.010~2.000 0.001 Un 1.200
sequence voltage
Upper limit of negative
xx.U2_UpLmt 0.010~2.000 0.001 Un 0.200
sequence voltage
Upper limit of zero sequence
xx.U0_UpLmt 0.010~2.000 0.001 Un 0.200
voltage
xx.Up_LowLmt 0.010~2.000 0.001 Un 0.900 Lower limit of phase voltage
Lower limit of positive
xx.U1_LowLmt 0.010~2.000 0.001 Un 0.900
sequence voltage

9 xx.Ip_UpLmt 0.010~2.000 0.001 In 1.200 Upper limit of phase current

Upper limit of positive
xx.I1_UpLmt 0.010~2.000 0.001 In 1.200
sequence current
Upper limit of negative
xx.I2_UpLmt 0.010~2.000 0.001 In 0.200
sequence current
Upper limit of zero sequence
xx.I0_UpLmt 0.010~2.000 0.001 In 0.200
current
xx.f_Diff_Lmt 0.01~10.00 0.01 Hz 0.50 Limit of frequency deviation
Limit of rate-of-change of
xx.df/dt_Lmt 0.01~50.00 0.01 Hz/s 1.00
frequency

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 9 Settings

9.4.3 PMU BI Settings

Access path: MainMenuSettingsPMU SettingsPMU BI Settings

Name Range Step Unit Default Description

STN- Configurable the name of PMU binary
Name_BI_** Max. 16 characters
Digital** signal
Enabling/Disabling disturbance fault
Disabled
Link_BI_TrigDFR Enabled recording function in case state
Enabled
change of any PMU binary signal
Enabling/Disabling disturbance fault
Disabled recording function in case state
BI_**.En_TrigDFR Enabled
Enabled change of the PMU binary signal
BI_**

9.4.4 PMU Label Settings

Access path: MainMenuSettingsPMU SettingsPMU Label Settings

Name Range Step Unit Default Description

Max. 4
Name_Amp_Ua -UAV Label for amplitude of phase A voltage phasor
characters
Max. 4
Name_Amp_Ub -UBV Label for amplitude of phase B voltage phasor
characters
Max. 4
Name_Amp_Uc -UCV Label for amplitude of phase C voltage phasor
characters
Max. 4 Label for amplitude of zero sequence voltage
Name_Amp_U0 -U0V
characters phasor
Max. 4 Label for amplitude of positive sequence voltage
Name_Amp_U1 -U1V
characters phasor
Max. 4 Label for amplitude of negative sequence voltage
Name_Amp_U2 -U2V
characters phasor
Max. 4
Name_Amp_Ia -IAV Label for amplitude of phase A current phasor
characters
Max. 4
Name_Amp_Ib
characters
-IBV Label for amplitude of phase B current phasor
9
Max. 4
Name_Amp_Ic -ICV Label for amplitude of phase C current phasor
characters
Max. 4 Label for amplitude of zero sequence current
Name_Amp_I0 -I0V
characters phasor
Max. 4 Label for amplitude of positive sequence current
Name_Amp_I1 -I1V
characters phasor
Max. 4 Label for amplitude of negative sequence current
Name_Amp_I2 -I2V
characters phasor

PCS-902S Line Distance Relay 9-137

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 9 Settings

Name Range Step Unit Default Description

Max. 4
Name_Ang_Ua -UAP Label for angle of phase A voltage phasor
characters
Max. 4
Name_Ang_Ub -UBP Label for angle of phase B voltage phasor
characters
Max. 4
Name_Ang_Uc -UCP Label for angle of phase C voltage phasor
characters
Max. 4
Name_Ang_U0 -U0P Label for angle of zero sequence voltage phasor
characters
Max. 4 Label for angle of positive sequence voltage
Name_Ang_U1 -U1P
characters phasor
Max. 4 Label for angle of negative sequence voltage
Name_Ang_U2 -U2P
characters phasor
Max. 4
Name_Ang_Ia -IAP Label for angle of phase A current phasor
characters
Max. 4
Name_Ang_Ib -IBP Label for angle of phase B current phasor
characters
Max. 4
Name_Ang_Ic -ICP Label for angle of phase C current phasor
characters
Max. 4
Name_Ang_I0 -I0P Label for angle of zero sequence current phasor
characters
Max. 4 Label for angle of positive sequence current
Name_Ang_I1 -I1P
characters phasor
Max. 4 Label for angle of negative sequence current
Name_Ang_I2 -I2P
characters phasor
Max. 4
Name_f -FRQ Label for bay frequency
characters
Max. 4
Name_df/dt -DFT Label for bay rate-of-change of frequency
characters
Max. 4
Name_P -00P Label for bay active power
characters
Max. 4
Name_Q -00Q Label for bay reactive power
characters

9 9.5 Logic Links

9.5.1 Function Links

Access path: MainMenuSettingsLogic LinksFunction Links

Name Range Step Unit Default Description

Disabled
Link_01 Enabled Function link setting 01
Enabled
Disabled
Link_02 Enabled Function link setting 02
Enabled

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 9 Settings

Name Range Step Unit Default Description

Disabled
Link_03 Enabled Function link setting 03
Enabled
Disabled
Link_04 Enabled Function link setting 04
Enabled
Disabled
Link_05 Enabled Function link setting 05
Enabled
Disabled
Link_06 Enabled Function link setting 06
Enabled
Disabled
Link_07 Enabled Function link setting 07
Enabled
Disabled
Link_08 Enabled Function link setting 08
Enabled

9.5.2 GOOSE Send Links

Access path: MainMenuSettingsLogic LinksGOOSE Send Links

These settings will be invisible unless the following operations are executed.

1. GOOSE communication in station level, "GOOSE (Slot 01)", or

GOOSE communication in process level, "GOOSE (Slot 02)" is
enabled by PCS-Studio. Please refer to "System Config in Application
Manual".

2. Instantiate the logic symbol of logic link for GOOSE sending. PCS-
Studio provides configurable logic symbols of logic link for sending
(single input or multiple input). The corresponding setting item (GOOSE
sending link) can be automatically added to "GOOSE Send Links"
when each adding a logic symbol, and its name can be defined by
editing the "English Description". Please refer to "Logic Symbols in
Application Manual"

Name Range Step Unit Default Description

**.GLink_Send
Disabled
Enabled
Enabling/disabling GOOSE sending, ** 9
Enabled is the user-defined description.

9.5.3 GOOSE Receive Links

Access path: MainMenuSettingsLogic LinksGOOSE Recv Links

These settings will be invisible unless GOOSE communication in station

level, "GOOSE (Slot 01)", or GOOSE communication in process level,

PCS-902S Line Distance Relay 9-139

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 9 Settings

"GOOSE (Slot 02)" is enabled by PCS-Studio. Please refer to "System

Config in Application Manual".

PCS-Studio provides configurable logic symbols of logic link for GOOSE

receiving (single input or multiple input). The corresponding setting item
(GOOSE receiving link) can be automatically added to "GOOSE Recv
Links" when each adding a logic symbol, and its name can be defined by
editing the "English Description". Please refer to "Logic Symbols in
Application Manual"

Name Range Step Unit Default Description

Enabling/disabling the
allowance for the acceptance
of simulated GOOSE
messages
Disabled
GLink_RecvSim Disabled Disabled: not receiving
Enabled
simulated message
(simulation=0)
Enabled: receiving simulated
message (simulation=1)
Disabled Enabling/disabling GOOSE
Bxx.Name_**_GCommLink.GLink_Recv Enabled
Enabled receiving link**

9.5.4 SV Receive Links

Access path: MainMenuSettingsLogic LinksSV Recv Links

These settings will be invisible unless "Sampling Mode" is chosen as "B:

Non-conventional instrument transformer" by PCS-Studio. Please refer to
"MOT Selection in Application Manual".

Name Range Step Unit Default Description

Enabling/disabling the
allowance for the
9 acceptance of simulated SV
messages
Disabled Disabled: not receiving
SVLink_RecvSim Disabled
Enabled simulated message
(simulation=0)
Enabled: receiving
simulated message
(simulation=1)
Disabled Enabling/disabling SV
Bxx.Name_**_SVCommLink.SVLink_Recv Enabled
Enabled receiving link**

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 Appendix A Glossary

Appendix A Glossary
The abbreviations adopted in this manual are listed as below.

BIM Binary Input Module

A
BNC Bayonet Nut Connector
"a" Contact is breaker auxiliary contact (ANSI
BO Binary Output
Standard Device Number 52A) that closes
when the breaker is closed and opens when BOM Binary Output Module
the breaker is open.
C
AC Alternating current

A/D converter Analogue-to-digital converter C37.94 IEEE/ANSI protocol used when

sending binary signals between IEDs
AI Analogue input
CB Circuit breaker
ALF Accuracy Limit Factor
CID Configured IED Description
ANSI American National Standards Institute
COMTRADE Standard Common Format for
AR Autoreclosing
Transient Data Exchange format for
ARP Address Resolution Protocol Disturbance recorder according to IEEE/ANSI
C37.111, 1999 / IEC 60255-24
ASDU Application Service Data Unit–An ASDU
can consist of one or more identical information CPU Central Processing Unit
objects. A sequence of the same information
CRC Cyclic Redundancy Check
elements, for example measured values, is
identified by the address of the information CSC Controllable Series Compensation
object. The address of the information object
CT Current Transformer
defines the associated address of the first
information element of the sequence. A CTS Current Circuit Supervision
consecutive number identifies the subsequent
information elements. The number builds on D
this address in integral increments (+1).
DBDL Dead Bus Dead Line
B
DBLL Dead Bus Live Line

"b" Contact is breaker auxiliary contact (ANSI DC Direct Current

Standard Device Number 52B) that closes
DFR Disturbance Fault Recorder
when the breaker is open and opens when the
breaker is closed. DLLB Dead Line Live Bus

BFP Breaker failure protection DNP Distributed Network Protocol as per IEEE
Std 1815-2012 A
BI Binary Input
DPFC Deviation of Power Frequency

PCS-902S Line Distance Relay 1

Date: 2023-08-01
 Appendix A Glossary

Component–In case of a fault occurred in the HVDC High-voltage Direct Current

power system, the fault component could be
analyzed into three parts: the power frequency I
components before the fault, the power
frequency variables during the fault and the ICD IED Capability Description
transient variables during the fault. DPFC is the
IEC International Electrotechnical Commission
power frequency variable during the fault.
IEC 60870-5-103 International standard
DPS: IEC 61850 data type: Double-point status
protocol for communication with IEDs
DSP Digital Signal Processor (especially protective equipment)

DTT Direct Transfer Trip Scheme IEC 61850 International standard for consistent
communication in substations. This standard
E defines the communication amongst devices in
substations and the related system
EHV Extra High Voltage requirements.

EMC Electromagnetic Compatibility IED Intelligent Electronic Device

IEEE 1588 Time-synchronization protocol

F
according to IEEE Std 1588-2008: Precision
Clock Synchronization Protocol for Networked
FL Fault Location
Measurement and Control Systems
FR Fault Recorder
IRIG-B InterRange Instrumentation Group
FSC Fixed Series Compensation Time code format B

G L

G.703 Electrical and functional description for LAN Local Area Network
digital lines used by local telephone companies.
LCD Liquid Crystal Display
Can be transported over balanced and
unbalanced lines LED Light-emitting Diode

GIS Gas-insulated Switchgear

M
GOOSE Generic Object-Oriented Substation
Event MAC Media Access Control

GPS Global Positioning System MCB Miniature Circuit Breaker

MMS Manufacturing Message Specification

H
Modbus Communication protocol, based on a
HMI Human-machine Interface Master/Slave or Client/Server architecture.

A HSR High-availability Seamless Redundancy MOV Metal-oxide Varistor

HV High-voltage
O

2 PCS-902S Line Distance Relay

Date: 2023-08-01
 Appendix A Glossary

OLTC On-load Tap Changer Language

OOS Out-of-Step SLD Single-line Diagram

SIR Source-to-line Impedance Ratio

P
SNMP Simple Network Management Protocol–
PD Pole Discrepancy An Internet standard protocol and serves for
the administration of nodes in an IP network.
PDC Phasor Data Concentrators
SNTP Simple Network Time Protocol–A
PDTT Permissive Direct Transfer Trip
protocol for the synchronization of clocks via
PL Programmable Logic the Internet. With SNTP, client computers can
synchronize their clocks via the Internet with a
PMU: Phasor Measurement Unit
time server.
POTT Permissive Overreaching Transfer Trip
SOE Sequence of Events–An ordered, time-
PPM Pulse Per Minute stamped log of status changes at binary inputs
(also referred to as state inputs). SOE is used
PPS Pulse Per Second
to restore or analyze the performance, or an
PRP Parallel Redundancy Protocol electrical power system itself, over a certain
period of time.
PUTT Permissive Underreaching Transfer Trip
SOTF Switch-Onto-Fault
R
SSD System Specification Description

RedBox Reduncancy box, used for the STP Rapid Spanning Tree Protocol
redundant connection of devices with only one
interface to both the LAN A and the LAN B PRP T
network
TCS Trip Circuit Supervision
RMS Root Mean Square
TCP/IP Transmission Control Protocol over
RSTP Rapid Spanning Tree Protocol
Internet Protocol
RTD Resistance Temperature Detector
U
RTU Remote Terminal Unit

UDP User Datagram Protocol

S
UTC Coordinated Universal Time
SA Substation Automation
W
SC Series Compensation

SCADA Supervision, Control And Data WI Weak end infeed

Acquisition

SCD Substation Configuration Description

V
A
SCL Substation Configuration Description VT Voltage transformer

PCS-902S Line Distance Relay 3

Date: 2023-08-01
 Appendix A Glossary

VTS Voltage Circuit Supervision

A list of function numbers used to represent electrical protection and control element. The device
function numbers used in this manual include the following:

21 Distance element 52 AC circuit breaker

25 Synchronism-check element 59 Overvoltage element

27 Undervoltage element 67 Directional overcurrent element

32 Power element 68 Power swing blocking element

37 Undercurrent element 78 Out-of-step element

46 Phase-balance current element 79 Reclosing element

49 Thermal overload element 81 Frequency element

50 Instantaneous overcurrent element 85 Pilot element

51 Definite-time or inverse-time overcurrent 87 Differential element

element

These numbers are frequently used within a suffix letter to further designate their application. The
suffix letters used in this instruction manual include the following:

P Phase element N Neutral/Ground element

G Residual/Ground element Q Negative-sequence element

4 PCS-902S Line Distance Relay

Date: 2023-08-01
 Appendix A Glossary

PCS-902S Line Distance Relay 1

Date: 2023-08-01