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Chapter 3: Using Digital Clock Managers (DCMs)
Table 3-6: DCM Connection Ports (Cont’d)
Functional Unit
Port Direction Description
DLL PS DFS
CLK0 Clock Same frequency as CLKIN, 0° phase shift (i.e., not phase shifted).
Output Always conditioned to a 50% duty cycle on
Extended Spartan-3A family FPGAs or on Spartan-3 FPGAs
when the DUTY_CYCLE_CORRECTION attribute is TRUE.
Either CLK0 or CLK2X is required as a feedback source for DLL
functions. See “Half-Period Phase Shifted Outputs,” and
“Quadrant Phase Shifted Outputs.”
CLK90 Clock Same frequency as CLKIN, 90° phase shifted (quarter period).
Output Not available if the DLL_FREQUENCY_MODE attribute is
HIGH. Always conditioned to a 50% duty cycle on
Extended Spartan-3A family FPGAs or on Spartan-3 FPGAs
when the DUTY_CYCLE_CORRECTION attribute is TRUE. See
“Quadrant Phase Shifted Outputs.”
CLK180 Clock Same frequency as CLKIN, 180° phase shifted (half period).
Output Always conditioned to a 50% duty cycle on
Extended Spartan-3A family FPGAs or on Spartan-3 FPGAs
when the DUTY_CYCLE_CORRECTION attribute is TRUE. See
“Half-Period Phase Shifted Outputs,” and “Quadrant Phase
Shifted Outputs.”
CLK270 Clock Same frequency as CLKIN, 270° phase shifted (three-quarters
Output period). Not available if the DLL_FREQUENCY_MODE attribute
is HIGH. Always conditioned to a 50% duty cycle on
Extended Spartan-3A family FPGAs or on Spartan-3 FPGAs
when the DUTY_CYCLE_CORRECTION attribute is TRUE. See
“Quadrant Phase Shifted Outputs.”
CLK2X Clock Double-frequency clock output, 0° phase shift. Not available if the
Output DLL_FREQUENCY_MODE attribute is HIGH. When available,
the CLK2X output always has a 50% duty cycle. Either CLK0 or
CLK2X is required as a feedback source for DLL functions. Clock
Doubler (CLK2X, CLK2X180) output. See “Half-Period Phase
Shifted Outputs.”
CLK2X180 Clock Double-frequency clock output, 180° phase shifted. Not available
Output if the DLL_FREQUENCY_MODE attribute is HIGH. When
available, the CLK2X180 output always has a 50% duty cycle.
Clock Doubler (CLK2X, CLK2X180) output. See “Half-Period
Phase Shifted Outputs.”
CLKDV Clock Divided clock output, controlled by the CLKDV_DIVIDE
Output attribute. The CLKDV output has a 50% duty cycle unless the
DLL_FREQUENCY_MODE attribute is HIGH and the
CLKDV_DIVIDE attribute is a non-integer value. The locking
time is longer when CLKDV_DIVIDE has a non-integer value.
See the Clock Divider (CLKDV) output.
F CLKIN
F CLKDV = -----------------------------------------------
-
CLKDV_DIVIDE
74 www.xilinx.com Spartan-3 Generation FPGA User Guide
UG331 (v1.8) June 13, 2011
