SUMEDHA COURSES WALKTHROUGH
Constructive
Projects
Core Courses
Bridge Courses
Foundation Courses
DESIGN VERIFICATION
Digital Design Fundamentals Advanced Digital Design System Verilog
Scripting Language Verilog UVM Projects
Week 1 Week 2 Week 3 Week 4 Week 5 Week 6
Continuous assignments, Equality and shift operators, Procedural Assignments
Introduction to HDL and RTL Conditional expressions,
Logical operators, Arithmetic vector operations, part and bit (Blocking and Non-Blocking), Abstraction Levels
design, Verilog constructs if-else and case statements
operators select, Parameters always block
Week 7 Week 8 Week 9 Week 10 Week 11 Week 12
System tasks,FSM, RTL coding
test bench,task and functions guidelines, Simulation and Introduction to System Verilog System Verilog data types Data types - Class Interface, mod port, Assertions
synthesis matches
Week 13 Week 14 Week 15 Week 16 Week 17 Week 18
Threads and Interprocess Universal Verification Methodology
Code Coverage, Data (UVM) Introduction, A Conventional
Randomization in system Communication Introduction, OOPs - Introduction,
Verilog, constraints Functional Coverage Measuring Coverage Testbench for the Tiny ALU, Object
events, semaphores, Inheritance and polymorphism Oriented Programming(OOP)
Statistics during simulation
Mailboxes Classes And Extension
Week 19 Week 20 Week 21 Week 22
Static Methods and Variables, A New Paradigm talking to
Parameterized Class Definitions, Multiple Objects using UVM Transactions, UVM
An Object Oriented Testbench, UVM components Agents, UVM sequences,
Analysis Ports in a
UVM tests Testbench, UVM reporting Onward with the UVM
Comprehensive
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Bridge Projects Certification
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