Chapter: 03

8086 Instruction set

Machine Language Instruction format:

A machine language instruction format has one or more number of fields’ associates with it. The first
field is called as operation code field or opcode which indicates the types of the operation to be
performed by CPU. The fields are known as operand field or data field on which CPU perform the
operation specified by the instruction opcode field.
There are six general formats of instruction in 8086. The length of an instruction may vary from one
bytes to six bytes.
 One byte instruction
 Register to Register
 Register to/ from memory with no displacement
 Register to/ from memory with displacement
 Immediate operand to Register
 Immediate operand to memory with 16 bit displacement.

Addressing modes of 8086:

Addressing modes indicates a way of locating data or operands. Depending upon the data types used in
the instruction and the addressing modes, any instruction may be belonging to one or more addressing
modes or some instruction may not belongs to any of the addressing modes.
Thus the addressing mode describes the types of operands and the way they are accessed for executing
an instruction.

Immediate Addressing Mode

In this addressing mode, the operand is stored as part of the instruction. The immediate operand, which
is stored along with the instruction, resides in the code segment -- not in the data segment. This
addressing mode is also faster to execute an instruction because the operand is read with the
instruction from memory.
Example: MOV AX, 0005H
In the above example, 0005H is the immediate data. 0005H is copied to register AX.

Direct Addressing Mode

In the direct addressing mode a 16 bit memory address (offset) is directly specified in the instruction as a
part of it.
Example: MOV AX,[5000H]
Here, data resides in a memory location in the data segment, whose effective address may be computed
using 5000H as the offset address and contents of DS as segment address. The effective address here is
10H*DS+5000H

Register addressing mode

In the register addressing mode, the data is stored in a register and it is referred using the particular
register. All the register except IP may be used in this mode.
Example: MOV AX, BX
Register indirect addressing mode:
Sometimes, the address of the memory location which contains data or operands is determined in an
indirect ways, using the offset registers. This mode of addressing is known as register indirect mode. In
this addressing mode, the offset address of data is in either BX or SI or DI registers. The default segment
is either DS or ES. The data is supposed to be available at the address pointed to by the content of any of
the above registers in the default data segments.
Example: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset address is in BX. The effective address of
the data is given as 10H*DS+[BX].
Indexed addressing mode:
In this addressing mode, offset of the operands is stored in one of the indexed registers. DS is the
default segments for index register SI and DI. In case of string instructions DS and ES are default
segments for SI and DI respectively.
Example: MOV AX, [SI]
Here, data available at an offset address stored in SI in DS. The effective address of the data is given as
10H*DS+ [SI].
Register Relative Addressing Mode:
In this addressing mode, the data is available at an effective address formed by adding an 8 or 16 bit
displacement with contents of any one of the register BX, BP, SI and DI in the default segments.
Example: MOV AX, 50H [BX]
The effective address is given as 10H*DS+50H+[BX]
Based Indexed Addressing Mode:
The effective address of data is formed, in this addressing mode, by adding contents of base register to
the content of an index register. The default segment register may be ES or DS.
Example: MOV AX, [BX][SI]
The effective address is given as 10H*DS+ [SI] + [BX]
Relative Based Indexed Addressing Mode:
The effective address is formed by adding an 8 or 16 bit displacement with the sum of contents of any
one of the base register and any one of the index register in a default segment.
Example: MOV AX, 50H[BX][SI]
The effective address is given as 10H*DS+50H+ [SI] + [BX]

Instruction set of 8086

The Instruction set of 8086 microprocessor is classified into 7, they are:-

1) Data transfer instructions

2) Arithmetical & logical instructions
3) Program control transfer instructions
4) Machine Control Instructions
5) Shift / rotate instructions
6) Flag manipulation instructions
7) String instructions
Data Transfer instructions
Data transfer instruction, as the name suggests is for the transfer of data from memory to internal
register, from internal register to memory, from one register to another register, from input port to
internal register, from internal register to output port etc.
 MOV : MOVE
General Form:
MOV destination, source
Operation:
Destination Source
This data transfer instruction transfer data from one register/ memory location to another register/
memory locations. The source may be any one of the segment register or other general purpose or
special purpose register or memory location and another register or memory location may act as
destination.
The source and destination both cannot be memory location at one time.
MOV instruction does not affect any flags
Example:-
MOV BX, 00F2H ; load the immediate number 00F2H in BX register
MOV CL, [2000H] ; Copy the 8 bit content of the memory location, 2000H
to the CL register
MOV [589H], BX ; Copy the 16 bit content of BX register to the memory
location, 589H
MOV DS, CX ; Move the content of CX to DS
 PUSH : push to stack
General Form:
PUSH Source
Operation:
SP SP-2
SS: [SP] Higher bytes of source
SS: [SP-1] Lower bytes of source
This instruction pushes the contents of the specified register/ memory location on to the stack. The
stack pointer is decremented by 2, after each execution of instruction. The actual current stack top is
always occupied by the previous pushed data. Hence, the push operation decrements SP by two and
then stores the two bytes contents of the operand onto stack. The higher bytes is pushed first and then
lower byte. Thus out of two decremented stack address the higher byte occupies the higher address and
lower byte occupies lower address.
PUSH instruction does not affect any flags
Example:-
PUSH CX ; Decrements SP by 2, copy content of CX to the stack
PUSH DS ; Decrement SP by 2 and copy DS to stack
 POP : POP FROM STACK
General Form:
POP Destination
Operation:
Lower bytes of destination SS: [SP]
Higher bytes of destination SS: [SP+1]
SP SP+2
The POP instruction copies a word from the stack location pointed by the stack pointer to the
destination. The destination can be a General purpose register, a segment register or a memory
location. Here after the content is copied the stack pointer is automatically incremented by two . POP
instruction does not affect any flags
Example:
POP CX ; Copy a word from the top of the stack to CX and increment SP by 2.
 IN: Input the Port
General Form:
IN Accumulator, Port
Operation:
AL [port Address] for byte
 AX [port Address]
This instruction is used for reading an input port. The address of the input port may be specified in the
instruction directly. AL or AX are the allowed destination for 8 and 16 bit input operation. DX is the only
register which is allowed to carry the port address. If the port address is of 16 bit it must be in DX.
IN instruction does not affect any flags
Example:
IN AL,03H ; This instruction reads data from an 8 bit port whose address is 03H& stores it in AL.
MOV DX, 0800H
IN AX, D The 16 bit address is taken in DX
Write the content of AX to a port of which address is in DX
 OUT: Output data to a port
General Form:
OUT Port, Accumulator
Operation:
[Port Address] for byte AL
[Port Address] AX
This instruction is used for writing to an output port. The OUT instruction copies a byte from AL or a
word from AX to the specified port. The address of the output port may be specified the instruction
directly or indirectly in DX register.
OUT instruction does not affect any flags.
Example:
OUT 047H, AL ; Copy contents of AL to 8 bit port 047H
MOV DX, 30F8H ; Copy port address in DX
OUT DX, AL ; Move 8 bit data to the 30F8H port

 XCHG: Exchange
General Form:
XCHG Destination, Source
Operation:
Destination Source
This instruction exchange the contents of the specified source and destination operands, which may be
register or one of them may be a memory location. Exchange of contents of two memory location is not
permitted. Immediate data is also not allowed in these instructions.
Example:
XCHG BX, CX ; exchange word in CX with the word in BX
XCHG AL, CL ; exchange byte in CL with the byte in AL

 LEA: Load Effective Address

General Form:
LEA Register, Source
Operation:
16 Bit Register Effective address of memory location.
The load effective address instruction loads the effective address formed by destination operand into
the specified source register.
Example:
LEA BX, ADR ; Effective address of label ADR i.e. offset of ADR will be transferred to register BX.

 LDS / LES : Load pointer To DS/ES

 General Form:
LDS / LES Register, Memory address of first word.
Operation:
For LDS
16 Bit Register [memory address]
DS [memory address+2]
For LES
16 Bit Register [memory address]
ES [memory address+2]
This instruction loads new values into the specified register and into DS/ES register from four successive
memory locations. The word from the first two memory locations is copied into specified register and
the word from the next two memory locations is copied into the ES/DS register.
Example:
LDS BX, [4326H]; copy the contents at displacement 4326H and 4327H to BX & then copies contents
Of memory location 4328H &4329H to register DS.

 LAHF : Load AH from Lower Byte of Flag

General Form:
LAHF
Operation:
AH lower byte of flag register
This instruction loads the AH register with the lower byte of flag register. This instruction may be used to
observe the status of all the conditional code flag at a time.

 SAHF : Store AH to Lower of Flag Register

General Form:
SAHF
Operation:
Lower byte of flag register AH
This instruction copies the contents of AH register to the lower byte of 8086 flag register. This
instruction reset the condition code flag in the lower byte of flag register depending upon the
corresponding bit position in AH.

 PUSHF : Push Flag to Stack

General Form:
PUSHF
This instruction decrements the stack pointer by 2 and copies the word in the flag register to the
memory location pointed to by stack pointer. The stack segment register is not affected.

 POPF : Pop from the stack

General Form:
POPF
This instruction copies a word from the two memory location at the top of stack to the flag register and
increments the stack pointer by 2. The stack segment register is not affected.

 XLAT : Translate
General Form:
XLAT
 Operation:
AL DS:[BX+AL]
The XLAT instruction is used to translate a byte from one code to another code. The instruction replaces
a byte in the AL register with a byte pointed to by BX in a lookup table in memory. Before the XLAT
instruction gets executed the lookup table containing the values for new code must be put in memory
and the offset of starting address of the lookup table must be loaded in BX. The code byte to be
translated is put in AL. to point to the desired byte in the lookup table, the XLAT instruction adds the
byte in AL to the offset of the start of the table in BX. If then copies the byte from the address pointed to
by [BX+AL] back into AL.
Example:
DATA SEGMENT
TABLE DB 00H,01H,02H,03H,04H,05H,06H
NUM DB 07
DATA ENDS

CODE SEGMENT
-----------
-----------
MOV BX, OFFSET TABLE
MOV AL, NUM
XLAT
-----------
---------
CODE ENDS
END

Arithmetic instructions
 ADD: Addition:
General Form:
ADD destination, source
Operation:
Destination Destination + Source
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction adds the contents of source operand with the contents of destination operand and place
the result in destination operand. The source operand may be register, memory location or immediate
number whereas the destination operand may be register or memory location. However, both source
and destination operands cannot be memory operands.
Example:-
ADD AL, 0FH ;Add the immediate content, 0FH to the content of AL and store the result in AL
ADD AX, BX ; AX <= AX+BX

 ADC: Add with Carry:

 General Form:
ADC destination, source
Operation:
Destination Destination + Source +CF
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction performs the same operation as ADD instruction. But ADC also adds the status of carry
flag into the result. Similar to an ADD instruction in ADC source and destination operands can be register
or memory location or an immediate data. However, both source and destination operands cannot be
memory operands.
Example:-
ADC AX, BX ; AX <= AX+BX+CF

 SUB : Subtract
General Form:
SUB destination, source
Operation:
Destination Destination - Source
Flag affected: AF, CF, OF, PF, SF, and ZF
The subtract instruction subtract the source operand from destination operand and the result left in the
destination operand. The source operand may be register, memory location or immediate number
whereas the destination operand may be register or memory location. However, both source and
destination operands cannot be memory operands.
Example:-
SUB AL, 0FH ; subtract the immediate content, 0FH from the content of AL and store
the result in AL
SUB AX, BX ; AX <= AX-BX
 SBB: Subtract with Borrow
General Form:
SUB destination, source
Operation:
Destination Destination - Source -CF
Flag affected: AF, CF, OF, PF, SF, and ZF
The subtract with borrow instruction subtract the source operand and borrow flag (CF) which may be
affected the result of previous operation from the destination operand. The result is stored in the
destination operand.
Example:-
SBB AX, BX ; AX <= AX-BX-CF

 INC : Increment
General Form:
INC destination
Operation:
Destination Destination + 1
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction increases the contents of the specified register or memory location by 1. This
instruction adds 1 to the contents of operand. Immediate data cannot be operand of this instruction.
Example:-
 INC AL ; AL<= AL + 1
INC AX ; AX<=AX + 1

 DEC :Decrement
General Form:
DEC destination
Operation:
Destination Destination -1
Flag affected: AF, CF, OF, PF, SF, and ZF
The decrement instruction subtracts 1 from specified contents of register or memory location.
Immediate data cannot be operand of this instruction.
Example:
DEC AL ; AL<= AL – 1
DEC AX ; AX<=AX – 1

 MUL : Unsigned Multiplication

General Form:
MUL Source
Operation:
For 8 bit source
AX AL* unsigned 8 bit source
For 16 bit source
DX: AX AX* unsigned 16 bit source
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction multiplies an unsigned bytes or word by the contents of AL. The unsigned byte or word
may be any one general purpose register or memory location. The most significant word of result is
stored in DX, while the least significant word of result is stored in AX.
Example:
MUL BH ; AX AL *BH
MUL CX ; DX: AX AX*CX

 IMUL: Signed Multiplication

General Form:
IMUL Source
Operation:
For 8 bit source
AX AL* unsigned 8 bit source
For 16 bit source
DX: AX AX* unsigned 16 bit source
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction multiplies an signed bytes or word by the contents of AL or a signed word in source
operand by signed word in AX. The source can be any one general purpose register or memory location
or index register or base register but it cannot be immediate data. The most significant word of result is
stored in DX, while the least significant word of result is stored in AX.
Example:
IMUL BH ; AX AL *BH
IMUL CX ; DX: AX AX*CX
  DIV: Unsigned Division
General Form:
DIV Source
Operation:
For 8 bit Source
AL AX/ unsigned 8 bit source
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction performs unsigned division. It divides an unsigned word or double word by a 16 bit or 8
bit operand. The dividend must be in AX for 16 bit operation and divisor may be specified using any one
of the addressing mode except immediate. The result will be in AL (Quotient) while AH will contain the
remainder. In case of a double word dividend (32 bit), the higher word should be in DX and lower word
should be in AX.

 IDIV : Signed Division

General Form:
IDIV Source
Operation:

Flag affected: AF, CF, OF, PF, SF, and ZF

This instruction performs the same operation as the DIV instruction, but with signed operands. The
results are stored similarly as in case of DIV instruction in both cases of word and double word divisions.
The result will also be signed numbers.

 CBW : Convert signed byte to signed word

General Form:
CBW
Operation:
AH filled with sign bit of AL
Flag affected: No flags are affected.
This instruction copies the sign of bytes in AL to all the bits in AH. AH is then said to be sign extension of
AL. The CBW operation must be done before signed bytes in AL can be divided by other signed bytes
with IDIV instruction.
Example:
AX= 00000000 10011011 =008BH
CBW
Then
AX=111111111 10011011 =FF8BH

 CWD: Convert signed word to double word

General Form:
CBW
Operation:
DX filled with sign bit of AX
Flag affected: No flags are affected.
This instruction copies the sign bit of a word in AX to all the bits of DX register. In other words, it extends
the sign of AX into all of AX. The CWD operation must be done before signed bytes in AL can be divided
by other signed bytes with IDIV instruction.
Example:
DX= 00000000 00000000
AX =10010110 10111101
CWD
Then
DX= 11111111 11111111
AX =10010110 10111101

 CMP: Compare byte or word

General Form:
CMP destination, Source
Operation:
a. IF destination > source
Then CF=0,ZF=0,SF=0
b. IF destination <source
Then CF=1,ZF=0,SF=1
c. IF destination = source
Then CF=0,ZF=1,SF=0
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction compares bytes from the specified source with a byte from the specified destination, or
a word from the specified source with word from the specified destination. The source can be an
immediate data, a register or memory location. The destination can be register or memory location.
The comparison is done by subtracting the source operand from the destination operand. The contents
of source and destination operand are not changed after subtraction, but only the flag are set or reset to
indicate the result of comparison.
Example:
CMP AX,BX

 NEG: Negate (2’s compliment)

General Form:
NEG destination
Operation:
Destination 2’s compliment of destination
Flag affected: AF, CF, OF, PF, SF, and ZF
This instruction forms 2’s compliment of the specified destination in the instruction. For obtaining 2’s
compliment, it subtract the contents of destination from zero. The result is stored back in the
destination operand which may be register or memory location
Example:
NEG BL
NEG AX

 DAA : Decimal adjust AL after BCD Addition

General Form:
DAA
 Operation:
a. IF lower nibble of AL > 9 or AF=1
Then AL=AL+6
b. IF higher nibble of AL>9 or CF=1
Then AL=AL+60
c. IF both above condition arte satisfied
Then AL=AL+66
Flag affected: AF, CF, PF, SF
This instruction is used to make sure the result of adding two packed BCD numbers is adjusted to be a
legal BCD number. The result of addition must be in al for DAA instruction to work correctly.
If the lower nibble in AL after addition is > 9 or auxiliary carry flag is set then add 6 to lower nibble of AL.
if the upper nibble in AL is > 9 or carry flag is set then adds 6 to upper nibble of AL.
Example:
ADD AL, BL
DAA
Now if AL=53, BL=29
Then add AL, BL will add
53+ 29 (BCD) =7C H
Now C is > 9 hence DAA will add 06 to 7C
7C+ 06 (BCD) =82 H
AL 82 (valid BCD)

 DAS: Decimal adjust AL after BCD Subtraction

General Form:
DAS
Operation:
a. IF lower nibble of AL > 9 or AF=1
Then AL=AL-6
b. IF higher nibble of AL>9 or CF=1
Then AL=AL-60
c. IF both above condition arte satisfied
Then AL=AL-66
Flag affected: AF, CF, PF, SF
This instruction is used to make sure the result of subtraction of two packed BCD numbers is adjusted to
be a legal BCD number. The result of subtraction must be in AL for DAS instruction to work correctly.
If the lower nibble in AL after subtraction is > 9 or auxiliary carry flag is set then subtract 6 to lower
nibble of AL. if the upper nibble in AL is > 9 or carry flag is set then subtract 6 to upper nibble of AL.
Example:
If AL= 86, BL=57
SUB AL, BL 86-57 =2FH
Then
DAS 2F-06= 29 Valid BCD

 AAA: ASCII adjust for addition

 General Form:
AAA
Operation:
AL=AL AND 0FH
If lower nibble of AL> 9 or AF=1
Then AL=AL+06
AH=AH+1
AF=CF=1
AL= AL AND 0FH
Flag affected: AF, CF
Numerical data coming into a computer from terminal is usually in ASCII code. In this code the number 0
to 9 are represented by the ASCII codes 30H to 39H. the 8086allows you to add the ASCII code for two
decimal digits without masking off the ‘3’ in the upper nibble of each.
After the addition the AAA instruction is used to make sure the result is the correct unpacked BCD.
Example:
Let AL= 0011 0101 ASCII 5
BL= 0011 1001 ASCII 9
ADD AL, BL AL= 35+39 = 6EH which is incorrect BCD
AAA Al= AL AND OF =6E AND F= OE
Then
AL= AL+06 AL=0E+06=14
AH=AH+1 AH= 00+01=01
AL= AL AND 0FH= 14AND 0FH= 04
Hence AH AL
01 04 correct unpacked BCD

 AAS: ASCII adjust for Subtraction

General Form:
AAS
Operation:
AL=AL AND 0FH
If lower nibble of AL> 9 or AF=1
Then AL=AL-06
AH=AH-1
AF=CF=1
AL= AL AND 0FH
Flag affected: AF, CF
This instruction corrects the result in AL register after subtracting two unpacked ASCII operands. The
result is in unpacked BCD format.
Example:
Let AL= 0011 1001 ASCII 9
BL= 0011 0101 ASCII 5
SUB AL, BL AL= 39-35 = 04H
AAS Since result is 04 no change

 AAM: ASCII adjust After Multiplication

General Form:
 AAM
Operation:
AL=AL MOD 10
AH=AH/10
Flag affected: PF, SF and ZF
This instruction corrects the result of multiplication of two valid unpacked BCD numbers.
Example:
If AL= 06 , BL= 08
MUL BL = Ax=30H (48 decimal)
AAM = AH= 04, AL=08

 AAD: ASCII adjust After Division

General Form:
AAD
Operation:
AL=AH*10 +AL
AH=00
Flag affected: PF, SF and ZF
This instruction can be used to convert the unpacked BCD digit in AH and AL registers to the equivalent
binary in the AL register.
Example:
If AX = 0205 and BL =07
AAD = AX=0019 (25 decimal)
DIV BL = AL=03 (Quotient)
AL=04 (Remainder)

Logical Instruction:
 AND : Logical AND
General Form:
AND destination, source
Operation:
Destination destination AND source
Flag affected: CF, OF, PF and ZF
This instruction AND’s each bit in source byte or word with the same number bit in a destination byte or
word. The result is put in destination.
Example:
AND BL, AL ;suppose BL=1000 0110 and AL = 1100 1010 then after the operation BL would be BL=
1000 0010.

AND CX, AX ;CX <= CX AND AX

AND CL, 08 ;CL<= CL AND (0000 1000)

 OR : Logical OR
 General Form:
OR destination, source
Operation:
Destination destination OR source
Flag affected: CF, OF, PF and ZF
This instruction logically ORs each bit of the source byte/word with the corresponding bit in the
destination and stores the result in destination. The source can be an immediate number, register or
memory location, register can be a register or memory location.

Example:-

OR BL, AL ;suppose BL=1000 0110 and AL = 1100 1010 then after the operation BL would be BL=
1100 1110.

OR CX, AX ;CX <= CX AND AX

OR CL, 08 ;CL<= CL AND (0000 1000)

 NOT: Logical Invert

General Form:
NOT destination
Destination NOT destination
Flag affected: No flags are affected.
The NOT instruction inverts each bit of bytes or word at the specified destination. That means it form
the 1’s compliment of the destination. The destination can be register or memory location.
Example:
NOT AX

 XOR :Logical Exclusive OR

General Form:
XOR destination, source
Operation:
Destination destination XOR source
Flag affected: CF, OF, PF and ZF
XOR performs a bit wise logical XOR of the operands specified by source and destination. The result of
the operand is stored in destination operand.
Example:
BX = 00111101 01101001 and CX = 00000000 11111111
XOR BX, CX ; Exclusive OR CX with BX and Result BX = 00111101 10010110

 TEST: Logical compare to update flags

General Form:
TEST destination, source
Operation:
Flags destination AND source
Flag affected: CF, OF, PF and ZF
 This instruction ANDs the contents of a source byte or word with the contents of specified destination
word. Flags are updated but neither operand is changed. TEST instruction is often used to set flags
before a condition jump instruction

Examples:

TEST AL, BH ;AND BH with AL. no result is stored . Update PF, SF, ZF

TESTCX,0001H;ANDCXwithimmediatenumber ;no result is stored, Update PF,SF

Example :

;AL=01010001
TEST Al, 80H ;AND immediate 80H with AL to test f MSB of AL is 1 or 0
;ZF = 1 if MSB of AL = 0 and AL = 01010001 (unchanged),PF = 0 , SF = 0,
;ZF = 1 because ANDing produced is 00
 SAL/SHL Instruction - Shift operand bits left, put zero in LSB(s)
Syntax
SAL/SHL destination, count
Operation:
CF MSB LSB 0
Flag Affected: CF, OF, PF, SF and ZF.
SAL instruction shifts the bits in the operand specified by op1 to its left by the count specified in op2. As
a bit is shifted out of LSB position a 0 is kept in LSB position. CF will contain MSB bit.
Example:
SHL BL, 01H
X 0 1 1 0 1 0 1 0
CF
1 1 0 1 0 1 0 0 0 Inserted
0

CF

 SHR : Shift operand bits rights, put zero in MSB(s)

Syntax
SHR destination, count
Operation:
0 MSB LSB CF
Flag Affected: CF, OF, PF, SF and ZF.
This instruction shift each bit in byte or word destination to the right and insert 0 in the newly
introduced MSB position. This instruction shifts the operand through carry flag.
Example:
SHR BL, 01H

0 1 1 0 1 0 1 0 X

CF
0 Inserted 0 0 1 1 0 1 0 1 0
 CF

SAR : Shift operand bit right, New MSB=Old MSB

Syntax
SAR destination, count
Operation:

MSB LSB CF

Flag Affected: CF, OF, PF, SF and ZF.

This instruction perform right shift on the operand word or byte that may be register or memory
location. As a bit is shifted out of the MSB position a copy of the old MSB is put in the MSB position.
Example:
SAR BL, 01H

0 1 1 0 1 0 1 0 X

CF
0 0 1 1 0 1 0 1 0

Old MSB Inserted CF

 ROR: Rotate right without Carry

Syntax
ROR destination, count
Operation:

CF MSB LSB

Flag Affected: CF, OF, PF, SF and ZF.

This instruction rotates the contents of the destination operand to right either by one or by the count
specified in CL excluding carry. The LSB is pushed into the CF and simultaneously it is transfers into MSB
position at each operation. The remaining bits are shifted to right by the specified position.
Example:
CF =0, BX = 00111011 01110101
ROR BX, ;Rotate all bits of BX of 1 bit position towards right and CF =1, BX = 10011101 10111010
 ROL: Rotate Left without Carry

Syntax
ROL destination, count
Operation:
CF MSB LSB
Flag Affected: CF, OF, PF, SF and ZF.
This instruction rotates the contents of the destination operand to left either by one or by the count
specified in CL excluding carry. The MSB is pushed into the CF and simultaneously it is transfers into LSB
position at each operation. The remaining bits are shifted to right by the specified position.
Example:
BX = 01011100 11010011 and CL = 8 bits to rotate
ROL BH, CL ;Rotate BX 8 bits towards left and CF =0, BX =11010011 01011100

 RCR: Rotate Right with Carry

Syntax
RCR destination, count
Operation:
CF MSB LSB

Flag Affected: CF, OF, PF, SF and ZF.

This instruction rotates the contents of destination operand to right by the specified count through the
carry flag. For each operation, the carry flag is pushed into the MSB of the operand and the LSB is
pushed into carry flag.
Example:
CF = 1, BL = 00111000
RCR BL, 1 ;Result: BL = 10011100, CF =0 OF = 1 because MSB is changed to 1.

 RCL: RotateLeftwith Carry

Syntax
RCL destination, count
Operation:
CF MSB LSB

Flag Affected: CF, OF, PF, SF and ZF.

This instruction rotates the contents of destination operand to left by the specified count through the
carry flag. For each operation, the carry flag is pushed into the LSB of the operand and the MSB is
pushed into carry flag.
Example:
RCL DX, 1

Program Control Transfer Instruction or Branching instruction:

The program control transfer instruction transfer the flow of execution of the program to new address
specified in the instruction directly or indirectly. When this type of instruction is executed the CS and IP
register get loaded with new values of CS and IP corresponding to the location where the flow of
execution is going to be transferred. These types of instruction are classified in two types:
 Unconditional control transfer (branch ) instruction
  Conditional control transfer (branch ) instruction
Unconditional control transfer (branch) instruction:
In this case, the execution control is transferred to the specified location independent of any status or
condition. The CS and IP are unconditionally modified to the new CS and IP.

 CALL – call a procedure

Syntax:
CALL procedure_name
Operation:
For Near CALL
SP SP-2
Save CS on Stack
IP Address of Procedure
For far CALL
SP SP-2
Save CS on Stack
CS New segment base containing procedure
SP SP-2
Save IP on Stack
IP Starting Address of Procedure
The CALL instruction is used to transfer execution to a subprogram or procedure. There are two basic
types of CALLs – Near and Far. A Near call is a call to a procedure which is in the same code segment as
the CALL instruction. It decrements the stack pointer by 2 and copies the offset of next instruction after
call instruction which is known as return address. A FAR call is a call to a procedure which is in a
different segment from one that contents of CS register to the stack. If then decrements the stack
pointers again by 2 and copies the contents of IP registers on to stack. The address of the procedure
may be specified directly or indirectly depending upon the addressing mode.
Example:
CALL DELAY

 RET – Return from procedure

Syntax:
RET
Operation:
For Near return
IP contents from top of stack
SP SP+2
For FAR return
IP contents from top of stack
SP SP+2
CS contents from top of stack
SP SP+2
This instruction will return execution from a procedure to the next instruction after the call instruction
which was used to call a procedure. If the procedure is Near RET instruction load IP with top of stack.
The stack pointer will be incremented by 2 after return address is popped off into IP. If the procedure is
FAR then the instruction pointer will be loaded with current top of stack. The stack pointer will be
incremented by 2 and CS is loaded with new top of stack. Again the stack pointer will be incremented by
2. At the end of the every procedure the RET instruction must be executed.
  INT – Interrupt program execution
Syntax:
INT Type (N)
In interrupt structure of 8086 , 256 interrupt are defined corresponding to the types from 00H to FFH.
When an INT N instruction is executed the type byte N is multiplied by 4 and the content of IP and CS of
the interrupt service Routine(ISR) will be taken from the hexadecimal multiplication(N*4) as offset
address and 0000 as segment address. That means multiplication of type N by 4 points to memory block
in 0000 segments which contents the IP and CS values of ISR. For the exe3cution of this instruction the
interrupt flag (IF) must be enable.
Example:
INT 20H ; New IP from 0080H and new CS from 0082H

 INTO – Interrupt on overflow

Syntax
INTO
If the overflow flag (OF)is set this instruction will cause the 8086 to do an indirect far call to a procedure
that you write to handle the overflow condition. The 8086 will read a new value for IP from the address
00010 H and a new value for CS from the address 00012H. This is an equivalent to type 4 interrupt
instruction.

 IRET- Interrupt Return

Syntax:
IRET
When ISR is called before transferring control to it, the IP, CS and flag register are stored onto the stack
to indicate the location from where the execution is to be continued after the ISR is executed. So at the
end of each ISR, when IRET is executed, the values of IP , CS and flag register are retrieved from the
stack is modified accordingly.

 JMP- Unconditional Jump

Syntax:
JMP Label
The JMP (jump) instruction unconditionally transfers control to specified address in the instruction. If
the destination is in the same code segment as the JMP instruction then only IP will be changed. This is
known as Near jump. If the destination is in the different segment as the JMP instruction then both CS &
IP will be changed. This is known as Far jump.
Example:
JMP NEXT
Conditional control transfer (branch) instruction:

Instruction Function
JC label Jump if carry , Carry = 1
JNC label Jump if no carry, Carry = 0
JZ label Jump if zero, Zero = 1
JNZ label Jump if not zero, Zero = 0
JS label Jump if sign ,Sign = 1
JO label Jump if overflow ,Overflow=1
 JP label Jump if parity, Parity = 1
JNP label Jump if no parity, Parity = 0
LOOP label Loop through a sequence of instruction until
CX=0
LOOPE/LOOPZ label Loop through a sequence of instruction while
ZF=1 and CX=0

Bit / flag Manipulation Instructions:

Instruction Description syntax Function

CLC Clear Carry Flag CLC This instruction reset the carry flag to 0
STC Set Carry Flag STC This instruction set the carry flag to 1
CMC Complement the CMC This instruction complements the carry flag.
carry flag If the CF=0 before this instruction it will set
to 1 after the instruction executed.
CLD Clear Direction Flag CLD This instruction reset the direction flag to 0.
STD Set Direction Flag STD This instruction set the direction flag to 1.
CLI Clear Interrupt Flag CLI This instruction reset the IF to 0.
STI Set Interrupt Flag STI This instruction set the IF to1.

String Instructions:

 REP- Repeat Instruction Prefix:

REP is a prefix which is written before one of the string instruction. It will cause the CX register to be
decremented and the string instruction to be repeated until CX=0.
For example the instruction REP MOVSB will continue to copy string bytes until the number of bytes
loaded in CX has been copied.
There are two more options of the REP Prefix:
REPE/ REPZ: repeat if equal or repeat if zero. It will cause the string instructions to be repeated as long
as the compared bytes or word are equal (ZF=1) and CX=0.
REPNE/REPNZ: repeat if not equal to repeat if not zero. It will cause the string instructions to be
repeated as long as the compared bytes or word are equal (ZF=0) or until CX=0.

 MOVS/MOVSB/MOVSW- Move string bytes or string word

Syntax:
MOVS Destination, Source
MOVSB
MOVSW
Operation:
ES:[DI] DS:[SI]
This instruction copies a byte or word from a location in the data segment to a location in the extra
segment. The offset of the source byte or word in the data segment must be in SI register and the offset
of destination byte or word in the extra segment must be in the DI register. For more than one move,
the counter should be loaded in CX.
Example:
LEA SI, Source
LEA DI, Destination
CLD
MOV CX, 04H
REP MOVSB

 CMPS/CMPSB/CMPSW- Compare string bytes or word

Syntax:
CMPS/CMPSB/CMPSW
Operation:
Flag affected DS:[SI] – ES: [DI]
This instruction compares a byte or word in one string with a byte or word in another string. SI is used to
hold offset of source string and DI is used to hold offset of destination string. The compare instruction
can be used with a REPE or REPNE prefix.
Example:
LEA SI, Source
LEA DI, Destination
CLD
MOV CX, 04H
REPE CMPSB

 SCAS/ SCASB/SCASW- Scan a string byte or string word

Syntax:
SCAS/ SCASB/SCASW
Operation:
Flag affected AL/AX – ES: [DI]
This instruction compares bytes in AL or a word in AX with byte or word pointed by DI in ES. Therefore
the string to be scanned must be in the extra segment and DI must contain the offset of the byte or
word to be compared. The length of the string is stored in CX. Whenever a match to be specified
operand is found in the string, execution stops and ZF=1. If no match is found then ZF=0.

Example:
LEA SI, Source
LEA DI, Destination
CLD
MOV CX, 04H
REPE SCASB

 LODS/LODSB/LODSW- Load string byte into AL or Load string word into AX

Syntax:
LODS/LODSB/LODSW
Operation:
AL/AX DS: [SI]
This instruction copies a byte from a string pointed by SI to AL or a word from a string location pointed
by SI to AX. If DF=0 then SI will be automatically incremented otherwise SI will be automatically
decremented.
Example:
LEA SI, Source
CLD
LODSB
  STOS/STOSB/STOSW- Store byte or word in AL/AX
Syntax:
STOS/STOSB/STOSW
Operation:
ES: [DI] AL/AX
This instruction copies a byte from AL or word from AX to a memory location in the extra segment
pointed by DI.
Example:
LEA DI, Destination
CLD
STOSW

Machine control Instructions:

Instruction Description syntax Function

HLT Halt HLT The instruction HLT causes the processor to
enter the halt state. The CPU stops fetching
and executing of instruction. The only ways
to get processor out of the halt state are-
a. An interrupt signal on the INTR pin.
b. An interrupt signal on NMI pin.
c. A reset signal on RESET pin.
WAIT Wait for Test signal WAIT This instruction causes processor to enter
into ideal state or await state and continues
to remain in that the processor receives
state until one of the following signal
a. Signal on TEST pin
b. Signal on INTR pin
c. Signal on NMI pin
NOP No operation NOP This instruction is used to add wait state of
three clock cycle and during these three
clock cycle CPU does not perform any
operation. This instruction used to add
delay loop in the program.
LOCK BUS LOCK LOCK The LOCK is a prefix which may appear with
instruction another instruction. The LOCK prefix allows
a microprocessor to make sure another
processor does not take control of the
system buses.
ESC Escape ESC This instruction is used to pass instruction
to a coprocessor, such as 8087.
Difference between Near & Far CALL
Sr. Near Call Far Call
01 A Near call refer to a procedure call A Far call refer to a procedure which is in the
which is in the same code segment different code segment from that of CALL instruction
as CALL instruction
02 Also called as Intra segment call Also called as Inter segment call.
03 A Near call replace the old IP with A far call replace old CS:IP pair with new CS:IP
new IP
04 The value of old IP is pushed on to The value of old CS:IP pair are pushed onto stack.
stack.
05 Less stack location is required. More stack location are required.