Encoders for Flash Analog-to-Digital Converters

Dmitry O. Budanov1, Mikhail M. Pilipko, Dmitry V. Morozov

Peter the Great St.Petersburg Polytechnic University
Saint-Petersburg, Russia
1
dmitriy.budanov@gmail.com

Abstract— Analog-to-digital converters (ADC) are used in thermometer code. The second part is a “fat-tree” of logical
modern high-performance telecommunication systems. The elements. It converts the one-hot code into the binary code.
fastest ADC is based on the flash architecture. The flash ADC Delay time of this circuit is defined by delay of (N+1) logical
speed is limited by two factors. The first one is the comparator elements. A 3-bit fat-tree encoder is shown in Fig. 3.
response time in the input analog part of ADC. The second factor
is the delay time of the encoder. The encoder converts the
thermometer code into the straight binary code. In this paper,
design of encoder circuits based on CMOS technology is
considered. New encoder circuits with reduced delay are
proposed. Comparative analysis of encoder main characteristics
based on the circuit simulation is presented.

Keywords— flash analog-to-digital converter; thermometer

code; thermometer-to-binary encoder

I. INTRODUCTION
Flash analog-to-digital converters are characterized by a
low resolution (up to 8 bits) and significant power consumption
(up to units of watts). This type of ADC has no alternative in
applications, which operate with sampling rates greater than
1 GS/s. Flash ADC consists of two parts (Fig.1). The first part
is a comparator array. The input signal is directly compared
with a set of reference voltages, that are usually generated by a
resistor ladder. If the input signal level is less (more) than an
appropriate reference voltage, the logical zero (one) appears at
the comparator output. At the output of the comparator array
the thermometer code is formed. The second part of ADC is a
thermometer-to-binary encoder. Fig. 1. A 3-bit flash ADC structure
There are several types of encoders for flash ADCs. They
differ in circuit complexity, power consumption and sampling
rate [1-8]. In this paper design of novel high speed low power
encoders and simulation for 180 nm CMOS are presented.
II. KNOWN ENCODER SOLUTIONS
There are three basic encoder types for sampling rate
1 GS/s and higher: a multiplexer-based encoder, a fat-tree
encoder and a ROM-based encoder [1-5].
In the multiplexer-based encoder [1-3] certain bits of the
thermometer code are used to implement appropriate the
output code bit. The input signal is passed through (N-1)
multiplexers to determine the least significant bit of the output
code, where N is encoder resolution. Examples of the 3-bit
multiplexer-based encoder are shown in Fig. 2 [1-2].
The fat-tree encoder [4] consists of two parts. The first part
converts the thermometer code into the one-hot code. This
code contains not more than one nonzero bit. The position of
this bit corresponds to the highest nonzero bit in the Fig. 2. Multiplexer-based encoder

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 are multiples of two. The value on k-th output depends on
thermometer code bits that are multiples of 2k. The most
significant output bit corresponds to 2N-1 thermometer code
bit. Thereby, the input bit numbers determine generation of
intermediate control signals and transistor array
implementation. The number of transistors in the array
decreased to 2N-1. Since each control signal is fed only to one
transistor’s gate, delay of the circuit also decreases.

Fig. 3. Fat-tree encoder

The ROM-based encoder [5] also consists of two parts.

Fig. 4. ROM-based encoder
The first part is a converter from the thermometer code into
the one-hot code. The second part is a MOS transistor array The encoder with logical function implementation in the
with N columns and 2N-1 rows (Fig. 4). A transistor array can transistor array (Fig. 6) [8] is an elaboration of the circuit from
be considered as a representation of columns of the output Fig. 5. Instead of generation of intermediate signals for the
binary code in the encoder truth table. Transistor presence in transistor array it is proposed to implement necessary logical
the array is the logical one, absence is the logical zero. Delay function by additional transistors into the array. As a result,
of such encoder doesn’t depend on resolution and is the total number of transistors in the circuit is decreased.
determined by delays of four elements: two logical gates in the
one-hot converter part, transistor in the array of the second Using both n-MOS and p-MOS transistors it is possible to
part and the output inverter. Thereby, the ROM-based encoder design the transistor array that implements all output logical
is the fastest one. However, the disadvantage of such circuit is states in the encoder truth table (Fig. 7). CMOS-based ROM
considerable static power consumption. encoder consists of N columns with 2N-1 n-MOS and 2N-1 p-
MOS transistors. Control signals for n-MOS transistors could
There are some approaches to improve performance and be generated by the one-hot encoder for the circuit from
power consumption of encoders. The most successful Fig. 4. However, control signals for p-MOS transistors have to
modifications of the basic ROM-based encoder are presented be inverted. This design, proposed in [6], allows to exclude
in the next section. resistive elements and eliminate the static current flow.

III. KNOWN ROM-BASED ENCODER MODIFIED IV. PROPOSED ENCODER MODIFICATIONS

CIRCUITS Using ideas from Fig. 6 and Fig. 7 one can obtain the
Modifications of the basic ROM-based encoder are: encoder with logical function implementation in CMOS
• Using the input bit numbers; transistor array. However, in the output circuit of the least
significant bit there are 2N–2 circuits connected to the input of
• Logical function implementation in a transistor array; CMOS inverter. Each of the circuits consists of two serial
• Using CMOS transistor array. transistors. The parasitic capacitance at the input of this
inverter is greater than the parasitic input capacitance of other
The idea of the encoder using the input bit numbers inverters. This fact limits an encoder circuit performance. In
(Fig. 5) [7] is taken from multiplexer-based circuits. In this the proposed encoder circuit (Fig. 8) the problem solution is
circuit, as in the circuit from Fig. 4, the least significant bit y0 presented. In order to implement the least significant bit y0, it
only depends on the odd output bits from the one-hot encoder is necessary to use a tree consisting of two stages based on
and the most significant odd bit of the thermometer code. The CMOS transistors, similar to the circuit, which generates the
next output bit y1 depends only on thermometer code bits that input signal for the inverter in y1. In this case, the maximum

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parasitic capacitance in the circuit nodes is decreased by the significant bit. Usig three- and more input NAND in the
factor of two. For encoder with resolution N•3, bits with the output circuit leads to decreasing of the encoder preformance
number less than (N-1)/2 must be implemented by tree-like because of larger delay time.
two-stage circuits.

Fig. 7. ROM-based encoder based on CMOS transistor array

Fig. 5. ROM-based encoder using the input bit numbers

Fig. 8. Proposed ROM-based encoder logical function implementation in

transistor array and tree-like circuit in the least significant bit

Fig. 6. ROM-based encoder with logical function implementation in transistor

array

Developing the circuit of Fig. 5 it is possible to propose

another circuit design for generation of intermediate control
signals and to decrease the parasitic capacitance at the inverter
input in the least significant bit. A circuit implementing Fig. 9. Logical element a ⋅ b (a) and its symbol (b)
logical function a ⋅ b (Fig. 9) is used for the first stage of the
encoder shown in Fig. 10. CMOS inverter is replaced by
NAND in the least significant bit in the transistor array. The
transistor array column, representing the least significant bit,
is implemented by two columns, whose signals are passed to
NAND inputs. For increased encoder resolution the proposed
circuit with NAND is used only for generating the output least

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 circuit using the input bit numbers [7] allows to reduce delay
time and dynamic power consumption while the transistor
number decreases by 1.4 times. The encoder with logical
functions implementation in the transistor array [8] is the most
compact, has lower power consumption, but worse delay. The
reason is that in each circuit with two serial transistors there is
an intermediate node that has the parasitic capacitance
required to be recharged on each control signals switching.
CMOS array based encoder [6] has no static power
consumption, but contains the large transistor number and has
large delay time, closed to the multiplexer-based circuit [2]
and the fat-tree one [5]. As a result, this circuit loses the main
advantage of the ROM-based architecture.

TABLE I. ENCODER CIRCUIT SIMULATION RESULTS

Transis Average Average dynamic Max.
tor static current, μA delay,
Encoder
number current, (FS=500 MS/s) ps
μA
Mux-based 114 0 261 817
(Fig. 2.a) [1]
Mux-based 136 0 219 441
(Fig. 2.b) [2]
Fig. 10. Proposed ROM-based encoder based on a ⋅ b logical element and
NAND in the least significant bit Fat-tree (Fig. 3) 392 0 286 471
[4]
V. ENCODER CIRCUIT SIMULATION ROM (Fig. 4) 274 314 235 310
The considered encoders have been simulated and ROM (Fig. 5) [7] 202 315 216 284
compared for resolution 5 bit using CAD Cadence Virtuoso ROM (Fig. 6) [8] 97 273 151 370
for UMC 180 nm technology with supply voltage 1.8 V. The ROM (Fig. 7) [6] 416 0 279 459
simulation circuit is presented in Fig. 11 and consists of the
input source V1, the array of ideal comparators with Proposed circuit 162 0 209 339
(Fig. 8)
appropriate reference voltage levels (comparator_31), the
buffer array (buffer_31), the encoder and the output load array Proposed circuit 127 303 130 231
(Fig. 10)
(load_5). The input source generates the piecewise linear
signal, which sets all 25 words of the thermometer code at the
comparator array outputs. Among circuits, which don’t consume static power, the
proposed encoder with logical function implementation in
CMOS transistor array and the tree-like circuit in the least
significant bit has the lowest delay and average dynamic
current while the transistor number increases by 1.2 times in
comparison with the circuit from [2]. With sampling rate
increased up to 1 GS/s dynamic power consumption will be
dominant. The second proposed circuit (Fig. 10) has the
lowest delay time and average dynamic current among all
other considered encoders. Therefore, this encoder is
recommended for high-speed flash ADCs.

VI. CONCLUSIONS
Fig. 11. Simulation circuit
The thermometer-to-binary encoders comparative analysis
Encoder comparison is based on the transistor number, the has been carried out. Results demonstrate that the ROM-based
average static and dynamic current and the maximum delay architecture has the highest performance. The reason is that the
time. Simulation results in comparison with known encoder input signal in these circuits have to be passed only through 3-4
circuits are presented in Table 1. Simulation has shown that logical gates regardless of encoder resolution, whereas in other
the multiplexer-based encoder based on circuit [1] (Fig. 2.a) circuits this number depends on resolution. Delay time is the
has the largest delay. Another multiplexer-based encoder main reason for choosing this encoder. The main disadvantage
architecture [2] (Fig. 2.b) has a two times less delay by the of ROM-based encoders is static power consumption.
cost of 20% transistor number increase. The fat-tree encoder However, with increase of sampling rate power consumption is
[4] is worse than the multiplexer-based circuit [2] for all mainly determined by dynamic current generated during
considered parameters. The basic ROM-encoder has static switching. The encoder circuit proposed in Fig. 10 has the
current consumption but allows to reduce delay time. The

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