Computer Architecture

Lab 0: Pre-lab

Jaewoong Sim
Electrical and Computer Engineering
Seoul National University
Overview
• Goal
• Learn how to use Verilog
• Set up the Verilog coding environment
• Implement your register file and validate it

• You need to complete the following tasks

• Task 0: Set up Verilog coding environment
• Task 1: Implement your register file

• We provide you skeleton code of register file, which you need to build on

• We also provide you with test code

2
Honor Code

DO NOT CHEAT!

Everyone who involved in violation

will get zero scores

3
Verilog 101

4
Hardware Description Language (HDL)
Two common hardware description languages

Verilog
• Developed by Gateway Design Automation in 1984; Gateway was acquired by
Cadence in 1990
• Became an IEEE Standard (IEEE 1364) in 1995
 Verilog-95, Verilog 2001, Verilog 2005 (minor revision), SystemVerilog (Industry)

VHDL (VHSIC-HDL: Very High Speed Integrated Circuit Hardware

Description Language)
• Developed by the US Department of Defense in 1983
• Became an IEEE Standard (1076-1987) in 1987
 Several revisions in 1993/2000/2002/2008

We will use Verilog HDL in labs

5
Best Way to Learn Verilog?
• Look at other Verilog code examples
• Do write code a lot!

• What prevents us from practicing Verilog?

• Oh.. Testbenches…

• HDLBits
• [Link]
• Highly recommend solving the problem sets there
• Created by my former colleague Henry Wong
 His Stanford seminar about x86 on FPGA is also interesting!
[Link]

• Verilog Tutorial & Language Reference Manual

• [Link]
• Verilog 1364-2005 LRM -- [Link]
• Online Verilog Simulators
 [Link]
 [Link] 6
Basic Unit: Module
A module is the main building block in Verilog!
• Every block of hardware with inputs and outputs is a module
• (e.g., AND/OR gates, multiplexer, decoder, …)

Each module consists of

• A core circuit (called internal or body) – performs the required function
• An interface (called ports) – carries out the required communication
between the core circuit and outside

a
y

b
Module
7
Implementing a Module in Verilog
module name
input/output ports

module test (input a,

input b,
output y); don’t forget a semicolon here!
module definition
// describe our circuit here!

endmodule

Format
module module_name (module interface list);
[list of interface ports]
...
[net and variable declarations]
Items enclosed in square
...
brackets are optional
[functional specification of module]
...
endmodule
8
Software Programming vs Hardware Description
• Software Programming Languages
• SW code executes statements in program order on given hardware

• Hardware Description Languages

• HDL code is more like a text form that describes a given circuit

module test (input a,

a input b,
x output x,
output y);
y
// describe our circuit here!
b assign x = a;
Module assign y = b;
endmodule

assign => describes ‘connections’ between things where data flows

from RHS to LHS; not the action of copying from RHS to LHS
9
Lexical Conventions

• Verilog uses almost the same lexical conventions as C language

• Identifiers consists of alphanumeric characters, _, and $

• Verilog is case-sensitive (just like C)
• First character can be a letter, _ or $ (cannot start with numbers)
• ex) counter, four_bit_adder, a, b, _4b_adder

• White space: blank space (\b), tabs (\t), and new line (\n)

• Keywords: some identifiers are reserved in Verilog

• and, assign, begin, case, else, end, nand, nor, not, or, repeat, …

• Comments
• //  used for single line comments
• /* ….*/  used for multi-line comments
10
Lexical Conventions
Number Representation

Format: <size>’<base>value ex) 16’b0101110000001101

• “<>” can be omitted

• size: size in terms of the exact number of bits

• If not given, 32-bit type assumed

• ’: single quote (not backtick)

• base: Binary (b or B), Octal (o or O), Decimal (d or D), Hexadecimal (h or
H)
• If omitted, it defaults to decimal

• value: constant value

• What if the value does not match the given size?

• Size is too small: MSBs are truncated (ex: 4’b11110010 ➔ 4’b0010)
• Size is too large:
 Leftmost '0' or '1' are filled with ‘0’
 Leftmost ’X’ or 'Z' are filled with ‘X’ or ‘Z’, respectively 11
Lexical Conventions
Number Representation

Sized number: <size>’<base>value

• 4’b1001 - a 4-bit binary number
• 16’habcd - a 16-bit hexadecimal number

Unsized number: ’<base>value ➔ 32-bit by default

• 2007 - a 32-bit decimal number by default
• ’habc - a 32-bit hexadecimal number

Negative number: -<size>’<base>value

• 2’s complement format by default
• -4’b1001 - a 4-bit binary number
• -16’habcd - a 16-bit hexadecimal number

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Lexical Conventions
Number Representation – Negative Values

module signed_number;
reg [31:0] a;

initial begin
a = 14'h1234;
$display ("Current Value of a = %h", a);
a = -14'h1234;
$display ("Current Value of a = %h", a);
a = 32'hDEAD_BEEF;
$display ("Current Value of a = %h", a);
a = -32'hDEAD_BEEF;
$display ("Current Value of a = %h", a);
#10 $finish;
end
endmodule

Current Value of a = 00001234

Current Value of a = ffffedcc
Current Value of a = deadbeef
Current Value of a = 21524111

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Lexical Conventions
Number Representation

• ”_” and “?”

• _ only for readability ➔ 16’b0101_1001_1110_0000
• ? equivalent to z ➔ 8’b01??_11?? = 8’b01zz_11zz

• x and z values: x denotes an unknown value; z denotes a

high impedance value
• Digital logic produces only 0 or 1
• Four-value logic system: 0, 1, x, z

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Lexical Conventions
Number Representation - Examples

Integer Stored as
1 00000000000000000000000000000001
8'hAA 10101010
6'b10_0011 100011
'hF 00000000000000000000000000001111
6'hCA 001010
6'hA 001010
16'bZ zzzzzzzzzzzzzzzz
8'bx xxxxxxxx

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Lexical Conventions
• Other data types
• String: “Back to School and Have a Nice Semester”
• Real number: 3.4, 294.872, 1.44E(or e)9
 Decimal and scientific notations accepted
 At least one digit on each side of the decimal point
 .2 (illegal)

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Value Sets
• 0 and 1 represent logic values low and high, respectively
• z indicates the high-impedance condition of a node or net
• x indicates an unknown value of a net or node

Value Meaning
0 Logic 0, false condition
1 Logic 1, true condition
x Unknown logic value
z High impedance

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Data Types
• Nets mean any hardware connection points (cannot store value!)
• Variables represent any data storage elements

• wire and reg are the most commonly used types

Nets Variables
wire supply0 reg
tri supply1 integer
wand tri0 real
wor tri1 time
triand trireg realtime
trior

Verilog’s wire is directional

Verilog’s reg does not necessarily correspond to the physical register!
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Data Types
• Nets
• Can be referenced anywhere in a module
• Must be driven by a primitive, continuous assignment, force …
release, or module port

• Variables
• Can be referenced anywhere in a module
• Can be assigned value only within a procedural statement, task, or
function
• Cannot be an input or inout port in a module

• Arrays and Vectors

• An array is a collection of objects with the same attributes
• A vector is a one-dimensional array of bit signals
• More on this later

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Verilog Ports
• Ports connect a module to the outside world

Module

net or var net net or var net

net

input port output port

net inout port

• input [net_type] [signed] [range] list_of_names;

• inout [net_type] [signed] [range] list_of_names;
• output [net_type or var_type] [signed] [range] list_of_names;

• Ports are by default considered as nets of type wire

• Ports are by default unsigned
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Port Connection
• Port connection by ordered list (not recommended unless necessary)
• port_expr1, …, port_expn

• Port connection by name (recommended)

• .port_id1(port_expr1),
.port_id2(port_expr2), …
• The order is irrelevant
• It is recommended to put each port connection in a separate line

• Each port_expr can be

• Identifier (a net or a variable)
• Bit-select or part-select of a vector
• Concatenation of the above
• Expression for input ports

• Unconnected/Floating ports: inputs are driven to z, outputs are floating

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Port Connection Examples

module half_adder (x, y, s, c);

input x, y;
output s, c;
// -- half adder body-- //
// instantiate primitive gates
xor xor1 (s, x, y); Can only be connected by using positional association
and and1 (c, x, y);
endmodule
Instance name is optional
module full_adder (x, y, cin, s, cout);
input x, y, cin;
output s, cout;
wire s1,c1,c2; // outputs of both half adders
// -- full adder body-- // Connecting by using positional association
// instantiate the half adder
half_adder ha_1 (x, y, s1, c1); Connecting by using named association
half_adder ha_2 (.x(cin), .y(s1), .s(s), .c(c2));
or (cout, c1, c2);
Instance name is necessary
endmodule

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Operator Precedence

Similar to the ones in

C language

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Verilog Assignments
• There are three forms of assignments in Verilog

• Continuous Assignments
• Drive a value into a net
• Used to model combinational logic
• (Explicit) Use assign keyword
 wire temp;
assign temp = a | b;
• (Implicit) combine declaration and assignment
 wire temp = a | b;

• Procedural Assignments
• Assign values to variables declared as regs in always blocks/tasks/functions
• Usually used to model registers and FSMs

• Procedural Continuous Assignments

• Assign & Deassign: Override all procedural assignments to a variable
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Module Modeling Levels
• Structural Modeling
• Dataflow Modeling
• Behavioral Modeling

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Module Modeling Levels
• Structural Level
• Gate level description of the circuit
• Connect built-in primitives, user-defined primitives, or other modules using
wires
• Describe a hierarchy

• Dataflow Level
• Describe hardware in terms of dataflow from inputs to outputs
• Use operators (+, -, &, |, …) that act on operands
• Use continuous assignment statements (keyword assign)

• Behavioral Level
• Typically used for sequential logic (but it can be used for combinational logic)
• Use procedural statements (keyword always)
• The target in procedural assignment statements must be a reg type

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Structural Modeling
// gate-level description of half adder
module half_adder(input x,
• Half Adder: S = X⨁Y, C = XY input y,
output s,
X Y SUM CARRY output c);

0 0 0 0 // half adder body

// instantiate primitive gates
0 1 1 0 xor (s, x, y);
1 0 1 0 and (c, x, y);

1 1 0 1 endmodule

pre-defined in Verilog
// gate-level description of full adder
• Full Adder module full_adder(input x,
input y,
input c_in,
Full Adder output sum,
output c_out);
c_in sum // internal nodes
Half // outputs of both half adders
wire s1, c1, c2;
x s1 Adder c2
c_out // full adder body
Half
// instantiate the half adder
y Adder c1 half_adder ha_1 (x, y, s1, c1);
half_adder ha_2 (c_in, s1, sum, c2);
or (c_out, c1, c2);
endmodule 27
Dataflow Modeling
• combinational logic
module full_adder_dataflow(input x,
input y,
input c_in,
output sum,
output c_out);
// specify the function of a full adder
assign #5 {c_out, sum} = x + y + c_in;
continuous assignment endmodule
continuously driven
by something

Full Adder
c_in sum
Half
x s1 Adder c2 - Use operators to compute sum and c_out
c_out
Half - Use continuous assignment to drive
y Adder c1 values onto nets

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Behavioral Modeling
• sequential & combinational logic

always block
Whenever the event in the sensitivity list occurs,
the always block is activated

module full_adder_behavioral(input x,
input y,
input c_in,
output reg sum,
output reg c_out);

// specify the function of a full adder

// can also use always @(*) or always@(x or y or c_in)
always @(x, y, c_in)
#5 {c_out, sum} = x + y + c_in;
endmodule

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Mixed-Style Modeling
module full_adder_mixed_style(input x,
input y,
input c_in,
output sum,
output reg c_out);
wire s1, c1, c2;

// structural modeling of HA 1.
xor xor_ha1(s1, x, y);
and and_ha1(c1, x, y);

// dataflow modeling of HA 2.
assign sum = c_in ^ s1;
assign c2 = c_in & s1;

// behavioral modeling of output OR gate.

always @(c1, c2) // can also use always @(*)
c_out = c1 | c2;
Full Adder endmodule
c_in sum
Half
Adder
x s1 2 c2
Half c_out
Adder
y c1
1

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Summary
• Number representation
• Format should be : <size>’<base format><number>
• Size : The size of the data with bit granularity
• Base format: radix (d : decimal , b : binary , h : hexadecimal )
• Number : The value of the data
assign a = 4’b0100; // 4bit binary, value: unsigned 4
assign a = 3’d100; // 3bit decimal, value: unsigned 100
assign a = 8’h0a; // 8bit hexadecimal, value: unsigned 11

• Vector & Array

Declaration → reg [bit index] register_name [array index];
reg register_1; // 1-bit reg
reg [7:0] register_2; // 8-bit reg

reg [7:0] reg_array_1[15:0]; // 8-bit x 16 array

reg_array_1[2] = register_2;

Computer Architecture Group @ SNU ECE 31

Summary
• Always block
• Starts running from simulation time 0
• Executes whenever signal changes (indicated in sensitivity list) during simulation
always @(A, B) // executes when A or B always @(*) // execute when any
changes signal changes
begin begin
… …
end end

• Conditional / Loop statement

• You can use conditional / loop statement (e.g., for, if, case) inside the “always block”

always @(A, B) integer i;

begin always @(A, B)
if(condition) begin begin
… for(i=0; i<8; i=i+1) begin
end …
end end
end

Computer Architecture Group @ SNU ECE 32

Summary
• Combinational logic design
• Continuous assignment : executes when right-value changes, regardless of the order in code
• ‘=‘ operator : blocking assignment
 It indicates continuous assignment outside of the always block
 It indicates that code is executed sequentially within the always block

// continuous assignment always@(*)

wire a; begin
assign a = 2’b00; b = 2’b00;
c = 2’b01; // Assignment to b and c is
executed sequentially
end

• Sequential logic design

• Procedural assignment : changes the value of variables in always block
• ‘<=‘ operator : non-blocking assignment
 It indicates that code is executed concurrently within the always block
always@(posedge CLK)
begin
b <= 2’b00;
c <= 2’b01; // Assignment to b and c is executed concurrently
end

Computer Architecture Group @ SNU ECE 33

Summary

always@(posedge CLK) always@(*)

begin begin
b <= a; b = a;
c <= b; c = b;
end end

• Rule of thumb
• Sequential logic → use a clocked always block with Nonblocking assignments. (<=)
• Combinational logic → use an always block with Blocking assignments. (=)
• Try not to mix the two ( = , <= ) in the same always block.

• Mixing the two …

• If it is possible that the signal will be read before being assigned, the tools will infer
sequential logic. If not, then the tools will generate combinational logic.
→ Just Don’t Mix them in a single always block!

Computer Architecture Group @ SNU ECE 34

Best Practices
• 1. Don’t mix Blocking assignments (=) and Non-blocking
assignments (<=) in the same always block.
• Sequential logic must use non-blocking assignments.
• Combinational logic must use blocking assignments.

• 2. Use always @(*) block or continuous assignment for combinational

logic.
• Don’t declare sensitivity lists for combinational logic.
• Use always @(*), if you need conditional / loop statements.

• 3. Only registers (reg) may be assigned in an always block.

• Also, use reg as a LHS in one always block.

• 4. Use <size>’<base><value> format for number representation.

Computer Architecture Group @ SNU ECE 35

Environment Setup

36
Setting Up the Verilog Coding Environment
• We recommend you use lightweight, open-source tools as shown below
• It is okay to use other tools such as Xilinx Vivado if you want or have them

• Icarus Verilog
• Open-Source Verilog compiler and simulator

• GTKWave
• Waveform viewer
• Use when we debug the Verilog code

37
Setting Up the Verilog Coding Environment
Windows

Windows Subsystem for Linux 2 (WSL2) for Windows 10

• WSL2 is supported on version 1903, 1909, 2004, 20H2, or higher
➔ Update Windows 10 accordingly
• Run Windows PowerShell as administrator (right click)
• Copy the command below
➢ [Link] /online /enable-feature /featurename:Microsoft-Windows-Subsystem-Linux /all /norestart
➢ [Link] /online /enable-feature /featurename:VirtualMachinePlatform /all /norestart

• Reboot
• Download WSL 2 kernel update package (click the link below)
[Link]
• Set WSL2 as a default version & Download Linux
➢ wsl --set-default-version 2

• Download ‘Ubuntu 20.04 LTS’ in Microsoft Store

• Open Ubuntu 20.04 LTS
& Enter your UNIX username
• $ sudo apt update
• $ sudo apt install iverilog gtkwave git

38
Setting Up the Verilog Coding Environment
Windows

• WSL screenshots

39
Setting Up the Verilog Coding Environment
Windows (WSL)

X11 Forwarding
• To enabling X11 forwarding, we can use Xming
• Download and Install Xming
• [Link]
• Open installed Xming’s file location.

40
Setting Up the Verilog Coding Environment
Windows (WSL)

X11 Forwarding
• To enabling X11 forwarding, we can use Xming
• Open Xming’s property.
• Add “-ac” at the end of target.
• Execute Xming. It will run at the background.

41
Setting Up the Verilog Coding Environment
Windows (WSL)

X11 Forwarding
• To enabling X11 forwarding, we can use Xming
• Unable the firewall with this command outside the wsl environment.
➢ Set-NetFirewallRule -DisplayName "Xming X Server" -Enabled True -Profile Any

• If it doesn’t work, try this command outside the wsl environment.

➢ New-NetFirewallRule -DisplayName "Xming X Server" -Enabled True -Profile Any

• If you have any problem, refer this website.

42
Setting Up the Verilog Coding Environment
Windows (WSL)

X11 Forwarding
• To enabling X11 forwarding, we can use Xming
• After installation, edit your configuration file (~/.bashrc or ~/.zshrc) at wsl
 1) Check your shell: $ echo $SHELL
 2) Open your configuration file: $ vim ~/.bashrc (or $ vim ~/.zshrc)
 3) Write & Save: export DISPLAY=“nameserver_ip:0”
 You can check the nameserver ip by cat /etc/[Link]
 4) Apply your change: source ~/.bashrc
 If you have any problem, refer this website
o [Link]

43
Setting Up the Verilog Coding Environment
Linux/Mac OS

Linux (Ubuntu 20.04/18.04 LTS)

• $ sudo apt-get install iverilog gtkwave git

Mac OS
• You can use “homebrew” to install icarus verilog
• Install Homebrew,
 /bin/bash -c “$(curl -fsSL
[Link]
• Install icarus Verilog & GTKWave
 brew install icarus-verilog
 brew install gtkwave
• X11 forwarding: Install xquartz ([Link]
mountain-lion-mavericks-install-xquartz-server/)

44
Test Your Framework
• Type the code on the right
and save it as “hello.v”

• Compile “hello.v” and run it

• iverilog –o hello hello.v
• vvp hello
• gtkwave [Link]

• in case of mac, if gtkwave GUI

doesn’t show up, try
open –a gtkwave [Link]

45
Lab 0: Register File

46
Background

47
Background #1 : RISC Processor
• RISC (Reduced Instruction Set Computer)
• Computer design that reduces the number of CPU instructions in order to
simplify the internal structure

• Execution of the instruction can be classified into 2 stages

• Fetch stage: Reads the instruction from instruction memory
• Execute stage: Executes the right work based on the read instruction in the
fetch stage

48
Background #1 : RISC Processor
• Fetch Stage : Reads the instruction from instruction memory
• PC (Program counter)
 Register that holds the address of the next instruction (which is stored in instruction
memory)
• Instruction Memory
 A part of memory that stores the instructions to be executed
• Instruction Register
 Register that stores the instruction which is fetched from instruction memory
1) Fetch instruction from instruction memory

2) Store fetched instruction in the instruction register

49
Background #1 : RISC Processor
• Execute stage: Executes the instruction fetched in fetch stage
• Register file
 A group of registers that temporarily hold the data required by the instruction
• Decoder
 A combinational logic that determines the action to be executed by decoding opcode
• Data Memory
 A part of memory that stores the data
• ALU/Shifter
 A combinational logic that executes ALU / shifter operations depending on the
decoder’s result

1) Store the data required by instruction in the register file

3) Execute the operation depending on the

decoder’s result

2) Decode the opcode of the instruction

50
Background #2 : Register File
• Register file temporarily stores data required by instructions
• It stores operand, memory address, etc.
• It also passes data to the functional unit

• Register file reads / writes data to the input address

• Register file consists of multiple registers

• Each register has a unique ID

Data_in r7 Data 7

… …
Addr_A Data_A

r2 Data 2
Register File
Addr_B Data_B
r1 Data 1

r0 Data 0
WR, CLK, RSTn
Example of register file with 16 registers
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Background #2 : Register File
• Input / Output of register file
• Input
 Addr_A , Addr_B : Input address
 WR : Signal to notify register file that data write is in progress. Generated by decoder
 CLK : Clock Signal
 RSTn : Active-low Reset Signal
 Data_in : Input data
• Output
 Data_A : Data stored in Addr_A
Data_in
 Data_B : Data stored in Addr_B

Addr_A Data_A

Register File
Addr_B Data_B

WR, CLK, RSTn

52
Register File Operation Example
• Behavior of register file with actual assembly instruction
• Read Operation
 Read r3 / r4 from register file, then pass to ALU
• Write Operation
 Write the result (r3+r4) to r4

ADD r4, r3, r4 r4 = r3 + r4

Data_in
• Specification
• 8 registers (each register is 16bit wide)
r7
• Rising CLK edge triggered writes
r6
Addr_A r5 Data_A
r4
r3
r2 Data_B
Addr_B
r1
r0

CLK WR RSTn
53
Register File Operation Example
• Read Operation
 Data in Addr_A register → Data_A
 Data in Addr_B register → Data_B
 Combinational logic (not affected by CLK)

Data_in

r7
r6

r5 Data_A a+b
Addr_A r4 b
0011
r3 a
AL
r2 U
Data_B
Addr_B r1
0100
r0

CLK WR RSTn

54
Register File Operation Example
• Write Operation
 Destination : Addr_B register
 Data: Data_in (from ALU adder in this example)
 Condition : Rising edge CLK, Positive WR
 Sequential logic (affected by CLK)
Data_in

r7
r6

r5 Data_A a+b
Addr_A r4 a+b

r3 a
AL
r2 U
Data_B
Addr_B r1
0100
r0

CLK WR RSTn

55
Design Your Register File

56
Specification of Register File
• You need to design a register file with 8 registers
• Each register should be 16 bit

• Below operations should be supported

• Read: Reads Addr_A / Addr_B register then outputs to DATA_A /
DATA_B
• Write : Writes Data_in to Addr_B register
• Reset : Resets all registers to 0x00 when RSTn is negative Data_in

r7
• Input / Output specification r6
• CLK, RSTn, WR (1-bit) Addr_A r5 Data_A
r4
• Addr_A, Addr_B (3-bit)
r3
• Data_in (16-bit) r2 Data_B
Addr_B
• Data_A, Data_B (16-bit) r1
r0

CLK WR RSTn
57
FIXME
• What you need to modify in testbench code
(Register_file_tb.v)
1. Name of a module instance
2. Name of ports

58
FIXME
• What you need to modify in source code (Register_file.v)
1. Sensitivity list of always block
2. Reset appropriately when reset signal is asserted
3. Write the data to appropriate register when write signal is asserted
4. Read two register values in a combinational method

59
Compile & Run
• How to compile & run your code
• Run “iverilog -o Register_file Register_file_tb.v Register_file.v” inside your project
directory
• this will generate a “Register_file” inside your project directory
• “vvp Register_file” will execute the test
• Then, you can check the results

60
Test Your Code
• If you implemented correctly, you will see…
• “Correctly Write!”
• “Correctly Read!”

• Else, you will see…

• “Incorrectly Written to Reg[#]..”
• “Incorrectly Read from Reg[#]..”

61
Waveform
• Also you can check the waveform
• Running “vvp Register_file” will generate “Register_file.vcd” in your project
directory.
• Run “gtkwave Register_file.vcd” will execute gtkwave.
 Click “Register_file_tb” at SST
 Choose signal whose waveform you want to see
 Click Zoom Fit
 Now, you can see the waveforms

62
Result & Submission

63
Submission
• Due: 4/2 (Tuesday) 11:59 PM

• Late Policy
• 20% discounted per day (4/3 12:00 AM is a late submission!)
• After 4/6 12:00 AM, you will get a zero score for the assignment

• What to submit?
• Your code that we can simulate and run

• How to submit?
• Upload your compressed file (zip/tar/etc) to eTL
• Format: Your student ID_YOURLASTNAME_lab#
 e.g.) 2024-12345_KIM_lab0.zip
├── Register_file.v
└── Register_file_tb.v
• Please make sure you follow the format.
 10% penalty for the wrong format

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