Verification using System Verilog
Duration – 60 Hrs
Eligibility – B.E, B. Tech, M.E, M. Tech.
Project stream:
Modules SV Verification of Digital Controller/CPU
Core/Protocols such as UART, SPI, I2C, AXI4
.
VLSI Verification Specialization
System Verilog Programming (7th Semester) Platform:
XILINX ISE/VIVADO
Questasim/EDA Playground
Spartan 6 FPGA Board
Artix7 FPGA Board
VLSI Verification Specialization
Design and Verification using System Verilog
Introduction of System Verilog, Need of Environment of Verification Data types -2satete, 4 state, enum ,
system Verilog string, structure, union, class
Array- Fixed array- packed and unpacked Dynamic Array, Associative array Queues
array
Process: - Fork-join, Fork-join any, Fork- OOPS- Inheritance, Polymorphism, Data Class- Deep copy, shallow copy,
join none, Wait-fork hiding, Encapsulation Overriding class, Coverage: Functional
Coverage, Cross coverage.
Explanation of assertion with example Explanation of coverage with example Working on verification environment
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