Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Unit – 4
Number representation

A number can be represented with different base values. We are familiar with the
numbers in the base 10 (known as decimal numbers), with digits taking values 0,1,2,
…,8,9.

A computer uses a Binary number system which has a base 2 and digits can have only
TWO values: 0 and 1.

A decimal number with a few digits can be expressed in binary form using a large
number of digits. Thus the number 65 can be expressed in binary form as 1000001.

The binary form can be expressed more compactly by grouping 3 binary digits together to
form an octal number. An octal number with base 8 makes use of the EIGHT digits
0,1,2,3,4,5,6 and 7.

A more compact representation is used by Hexadecimal representation which groups 4

binary digits together. It can make use of 16 digits, but since we have only 10 digits, the
remaining 6 digits are made up of first 6 letters of the alphabet. Thus the hexadecimal
base uses 0,1,2,….8,9,A,B,C,D,E,F as digits.

To summarize
Decimal : base 10
Binary : base 2
Octal: base 8
Hexadecimal : base 16

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Decimal, Binary, Octal, and Hex Numbers

Decimal Binary Octal Hexadecimal

0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Conversion of binary to decimal ( base 2 to base 10)

Each position of binary digit can be replaced by an equivalent power of 2 as shown

below.

n-1 n-2 …… …… 3 2 1 0
2 2 2 2 2 2

Thus to convert any binary number replace each binary digit (bit) with its power and add
up.
Example: convert (1011)2 to its decimal equivalent
Represent the weight of each digit in the given number using the above table.

n-1 n-2 …… …… 3 2 1 0
2 2 2 2 2 2

1 0 1 1

Now add up all the powers after multiplying by the digit values, 0 or 1
(1011)2
= 23 x 1 + 22 x 0 + 21 x 1 + 20 x 1
=8 + 0 +2 +1
= 11

Example 2
Find the decimal equivalent of the binary number (1 1 1 1 1)2.

Solution
The equivalent decimal number is
= 1 × 24 + 1 × 23 + 1 × 22 + 1 × 21 + 1 × 20
= 16 + 8 + 4 + 2 + 1
= (31)10

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Conversion of decimal to binary ( base 10 to base 2)

Here we keep on dividing the number by 2 recursively till it reduces to zero. Then we
print the remainders in reverse order.

Example: convert (68)10 to binary

68/2 = 34 remainder is 0
34/ 2 = 17 remainder is 0
17 / 2 = 8 remainder is 1
8 / 2 = 4 remainder is 0
4 / 2 = 2 remainder is 0
2 / 2 = 1 remainder is 0
1 / 2 = 0 remainder is 1
We stop here as the number has been reduced to zero and collect the remainders in
reverse order.
Answer = 1 0 0 0 1 0 0
Note: the answer is read from bottom (MSB, most significant bit) to top (LSB
least significant bit) as (1000100)2 .
You should be able to write a recursive function to convert a binary integer into its
decimal equivalent.

Example
Convert (13)10 to an equivalent base-2 number.

Soluti
on Quotient Remainder
13 1
6
2
6 0
3
2
3 1
1
2
1 1
0
2
1 1 0 1
Thus, (13)10 = (1101)2

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Conversion of binary fraction to decimal fraction

In a binary fraction, the position of each digit(bit) indicates its relative weight as was the
case with the integer part, except the weights to in the reverse direction. Thus after the
decimal point, the first digit (bit) has a weight of ½ , the next one has a weight of ¼ ,
followed by 1/8 and so on.

0 . -1 -2 -3 -4 … .... …
2 2 2 2 2
. 1 0 1 1 0 0 0

Example
Convert (0.65625)10 to an equivalent base-2 number.

1 0 1 0 1

Thus, (0.65625)10 = (0.10101)2

The decimal equivalent of this binary number 0.1011 can be worked out by considering
the weight of each bit. Thus in this case it turns out to be

(1/2) x 1 + (1/4) x 0 + (1/8) x 1 + (1/16) x 1.

Conversion of decimal fraction to binary fraction

To convert a decimal fraction to its binary fraction, multiplication by 2 is carried out
repetitively and the integer part of the result is saved and placed after the decimal point.
The fractional part is taken and multiplied by 2. The process can be stopped any time
after the desired accuracy has been achieved.

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Example: convert ( 0.68)10 to binary fraction.

0.68 * 2 = 1.36 integer part is 1

Take the fractional part and continue the process
0.36 * 2 = 0.72 integer part is 0
0.72 * 2 = 1.44 integer part is 1
0.44 * 2 = 0.88 integer part is 0

The digits are placed in the order in which they are generated, and not in the reverse
order. Let us say we need the accuracy up to 4 decimal places. Here is the result.
Answer = 0. 1 0 1 0…..

Example: convert ( 70.68)10 to binary equivalent.

First convert 70 into its binary form which is 1000110. Then convert 0.68 into binary
form upto 4 decimal places to get 0.1010. Now put the two parts together.

Answer = 1 0 0 0 1 1 0 . 1 0 1 0….

Octal Number System

• Base or radix 8 number system.

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

• 1 octal digit is equivalent to 3 bits.

• Octal numbers are 0 to7. (see the chart down below)

• Numbers are expressed as powers of 8. See this table

n-1 n-2 …… …… 3 2 1 0
8 8 8 8 8 8
6 3 2

Conversion of octal to decimal ( base 8

to base 10)
Example: convert (632)8 to decimal
= (6 x 82) + (3 x 81) + (2 x 80)
= (6 x 64) + (3 x 8) + (2 x 1)

= 384 + 24 + 2

= (410)10

Conversion of decimal to octal ( base 10 to base 8)

Example: convert (177)10 to octal equivalent
177 / 8 = 22 remainder is 1
22 / 8 = 2 remainder is 6
2 / 8 = 0 remainder is 2

Answer = 2 6 1

Note: the answer is read from bottom to top as (261)8, the same as with the binary case.

Conversion of decimal fraction to octal fraction is carried out in the same manner as
decimal to binary except that now the multiplication is carried out by 8.

Example: convert (0.523)10 to octal equivalent up to 3 decimal places

0.523 x 8 = 4.184 ,its integer part is 4
0.184 x 8 = 1.472, its integer part is 1

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

0.472 x 8 = 3.776 , its integer part is 3

So the answer is (0.413..)8

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Conversion of decimal to binary (using octal)

When the numbers are large, conversion to binary would take a large number of division
by 2. It can be simplified by first converting the number to octal and then converting each
octal into its binary form:
Example: convert (177)10 to its binary equivalent using octal form
Step 1: convert it to the octal form first as shown above
This yields (2 6 1)8
Step 2: Now convert each octal code into its 3 bit binary form, thus 2 is replaced by 010,
6 is replaced by 110 and 1 is replaced by 001. The binary equivalent is
( 010 110 001)2

Example: convert (177.523)10 to its binary equivalent up to 6 decimal places using octal
form.
Step 1: convert 177 to its octal form first, to get (2 6 1)8 and then convert that to the
binary form as shown above, which is ( 010 110 001)2
Step 2: convert 0.523 to its octal form which is (0.413..)8
Step 3: convert this into the binary form, digit by digit. This yields (0.100 001 011…)
Step 4: Now put it all together
( 010 110 001 . 100 001 011…)2

Conversion of binary to decimal (using octal)

First convert the binary number into its octal form. Conversion of binary numbers to octal
simply requires grouping bits in the binary number into groups of three bits

• Groups are formed beginning with the Least Significant Bit and progressing to the MSB.
Start from right hand side and proceed to left. If the left most group contains only a
single digit or a double digit, add zeroes to make it 3 digits.

• Thus
11 100 1112
= 011 100 1112
= 3 4 78

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

And
1 100 010 101 010 010 0012
= 001 100 010 101 010 010 0012
= 14252218
Now it can be converted into the decimal form.

Hexadecimal Number System

• Base or radix 16 number system.

• 1 hex digit is equivalent to 4 bits.

• Numbers are 0,1,2…..8,9, A, B, C, D, E, F.

B is 11, E is 14
• Numbers are expressed as powers of 16.

•160 = 1, 161 = 16, 162 = 256, 163 = 4096, 164 = 65536, …

Conversion of hex to decimal ( base 16 to base 10)

Example: convert (F4C)16 to decimal

= (F x 162) + (4 x 161) + (C x 160)
= (15 x 256) + (4 x 16) + (12 x 1)

Conversion of decimal to hex ( base 10 to base 16)

Example: convert (4768)10 to hex.

= 4768 / 16 = 298 remainder 0

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

= 298 / 16 = 18 remainder 10 (A)

= 18 / 16 = 1 remainder 2

= 1 / 16 = 0 remainder 1

Answer: 1 2 A 0

Note: the answer is read from bottom to top , same as with the binary case.

= 3840 + 64 + 12 + 0
= (3916)10

Conversion of binary to hex

• Conversion of binary numbers to hex simply requires grouping bits in the binary numbers
into groups of four bits.

• Groups are formed beginning with the LSB and progressing to the MSB.

• 1110 01112 = E716

• 1 1000 1010 1000 01112
= 0001 1000 1010 1000 01112
= 1 8 A 8 716
BCD Code
BCD stands for Binary Coded Decimal. This code is used to represent a decimal number into a
binary number. In BCD each number is expressed in 4-bits i.e. a string of nibble. Let me give you
an example. Let’s say, for example, we want to convert a decimal number 2945 to BCD number.
We will simply start with a truth table, consisting of the decimal numbers and their equivalent
Binary (BCD) codes.
BCD Codes Table:

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Now we can write the binary (BCD) equivalent codes of each number.

2 = 0010
9 = 1001
4 = 0100
5 = 0101
So,
(2945)Decimal = (0010100101000101)BCD
BCD numbers are useful for the places where decimal information are transferred into or out of a
digital system. For example the circuit inside the pocket calculators can process BCD numbers,
because you enter a decimal number through a keypad, and see the decimal result on the display.

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Other examples of the BCD systems are electronic counters, digital clocks, Medical equipments,
Electronic voltmeters, etc.
The following table shows the BCD numbers.

From 10 to 15 it is considered as the don’t care, because if we want to enter (10) with the keyboard
or keypad, first we press 1 who’s binary value is sent and then we press 0, a binary value of zero is
sent. So that’s why in BCD we consider numbers and their codes from 0 to 9.
Excess-3 Code in Digital Electronics:
A decimal code that has been used in some old computers is the Excess-3 code. This is an
unweighted code; its code assignment is obtained from the corresponding value of BCD after the
addition of 3.
The following table shows the representation/conversion of the BCD code into Excess-3 code.

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Error Detecting Code

Data/information is transmitted in the form of binary numbers (1 or 0) through some form of
communication medium, such as wires or Radio waves. During this transmission errors can occur
in the binary information i.e. ( 0 to 1 or 1 to zero) 0 may become 1 or 1 may become 0. An error
detecting code can be used to detect errors during transmission. The detected error cannot be
corrected, but its presence is indicated.
This is done with the help of Parity bit. A parity bit is an extra bit included with a message for the
purpose of detecting errors and making the total number of 1’s either odd or even. We have two
types of parity bits Odd Parity and Even Parity.
Odd Parity:
The total number of 1’s in an odd must be odd.
Even Parity:
The total number of 1’s in an even parity must be even.
From one location to another location, the parity bit is handled as follows.

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

On the sending side, the message ( in this case the first four bits) is applied to a parity generator,
where the required parity bit is generated. The message including the parity bit is transferred to its
destination.
On the receiving end, all the incoming bits are applied to a “Parity Checker”, the parity bit is
inhaled by the parity checker and the message is transferred to the destination
ASCII Code:
ASCII stands for the American standard code for information interchange. ASCII has been adopted
by several American computer manufacturers as their computer’s internal code. ASCII is of two
types ASCII-7 and ASCII-8.
ASCII-7 is a 7-bit code that allows 128 (2) 7 different characters. The first three bits are used as
zone bits and the last 4-bits indicate the digit.
ASCII-8 is an extended version of ASCII-7. It is an 8-bit code that is, it uses eight bits to represent
a letter or a punctuation mark. Eight bits are called a byte. A binary code with eight digits, such as
1001 10112, can be stored in one byte of computer memory.
Possible combinations 28 = 256
From 0 to 255.

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

2.1.1 One’s Complement Representation

In a binary number, if each 1 is replaced by 0 and each 0 by 1, the resulting number is known as
the one’s complement of the first number. In fact, both the numbers are complement of each
other. If one of these numbers is positive, then the other number will be negative with the same
magnitude and vice-versa. For example, (0101)2 represents (+5)10, whereas (1010)2 represents
( 5)10 in this representation. This method is widely used for representing signed numbers. In this
representation also, MSB is 0 for positive numbers and 1 for negative numbers.

Example 2.8
Find the one’s complement of the following binary numbers.

(a) 0100111001 (b) 11011010

Solution
(a) 1011000110 (b) 00100101

From the above examples, it can be observed that for an n-bit number, the maximum positive
number which can be represented in 1’s complement representation is (2 n 1 1) and the
maximum negative number is (2n 1 1).
2.1.2 Two’s Complement Representation
If 1 is added to 1’s complement of a binary number, the resulting number is known as the two’s
complement of the binary number. For example, 2’s complement of 0101 is 1011. Since 0101
represents (+5)10, therefore, 1011 represents ( 5)10 in 2’s complement representation. In this
representation also, if the MSB is 0 the number is positive, whereas if the MSB is 1 the number
is negative. For an n-bit number, the maximum positive number which can be represented in 2’s
complement form is (2n 1 1) and the maximum negative number is 2n 1. Table 2.3 gives sign-
magnitude, 1’s and 2’s complement numbers represented by 4-bit binary numbers. From the
table, it is observed that the maximum positive number is 0111 = + 7, whereas the maximum
negative number is 1000 = 8 using four bits in 2’s complement format.

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Logic gates
Positive and Negative logic System
There are two types of representations used in digital systems, the positive logic and the negative
logic representations.
In positive logic representation Bit 1 represents Logic high and Bit 0 represent a Logic low as
shown in bellow figure. High is represented by +5 Volts and low is represented by -5 Volts or 0
Volts.

In Negative logic representation Bit 1 represents logic low and Bit 0 represents logic high as shown
in bellow figure. In terms of voltage level, bit 1 can be represented as +5V and bit 0 can be
represented as 0 V or -5 Volts

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Truth Tables
Truth tables are used to help show the function of a logic gate.
Truth tables help understand the behaviour of logic gates.

 They show how the input(s) of a logic gate relate to its output(s).
 The gate input(s) are shown in the left column(s) of the table with all the different possible
input combinations. This is normally done by making the inputs count up in binary.
 The gate output(s) are shown in the right hand side column.

Definition of a Logic Gate:

"A logic gate is an electronic circuit which makes logic decisions". It has one output and one or
more inputs. The output signal appears only for certain combinations of input signals.
Logic expression of symbol: input variables are A, B and the output variable is Y, then the
logic expression for particular gate.
Truth Table: Truth table is table, which represents all the possible values of logical
variable/statements along with all the possible results of given combinations of values.
Boolean algebra: it is Boolean expression for particular gate.
These gates are available today in the form of various IC families. The most popular families are:
 Transistor-transistor logic (TTL),
 Emitter-coupled logic (ECL),
 Metal-oxide-semiconductor (MOS) and
 Complementary metal-oxide-semiconductor (CMOS).

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Types Of Logic Gates:

Logic gates can be broadly classified as

Representing Logic Functions

There are several ways of representing logic functions
 Symbol to represents the gates
 Truth tale
 Boolean algebra

OR gate symbol is

Boolean expression is A+B

Logic expression: Input variable are A,B and the output variable is Y, then the logic
expression for OR gate is Y = A+B.

Circuit diagram:

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 Unit – 4 BOOLEAN ALGEBRA, LOGIC GATES COMBINATIONAL SYSTEM

Truth table:
Input (A) Input (B) Output (Y= A+B)
0 0 0
0 1 1
1 0 1
1 1 1

 This circuit will give high output (1), if any input is high (1),
otherwise the output is low (0)

The pin configuration of IC 7432 is shown below in the figure.

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 AND – GATE

AND gate symbol is

Boolean expression is A.B

Logic expression: Input variable are A, B and the output variable is Y, then the logic
expression for AND gate is Y = A .B.

Circuit diagram:

Truth table:
Input (A) Input (B) Output (Y= A .B)
0 0 0
0 1 0
1 0 0
1 1 1

 This circuit will give high o utput (1), if both inputs is high (1) , otherwise
the output is low(0)

IC7408 is a 14 pin TTL integrated circuit with four AND gates inside. It is therefor called as Quad
AND gate IC.

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 NOT – GATE

NOT gate symbol is

YA
Boolean expression is A invert
Logic expression: Input variable is A and the output variable is Y, then the
logic expression for NOT gate is

YA

Circuit diagram:

Truth table:
Input (A) Output (Y= A )

0 1
1 0

 This is the simplest gate it just inverts the input, if input is high the output
will be low and conversely

The pin configuration of IC 7404 is shown below figure:

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 XOR -
Gate

 XOR gate also refer to represented as exclusive -OR gate

 it is a digital logic gate with two or more inputs and one output that performs exclusive
disjunction

 One element clearly missing from the set of Boolean operations is that of Exclusive -OR,
often represented as XOR. Whereas the OR function is equivalent to Boolean addition,
the AND function to Boolean multiplication, and the NOT function (inverter) to Boolean
complementation, there is no direct Boolean equivalent for Exclusive -OR.

Logic Symbol :
A
Y = A B

Truth Table:

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 Input (A) Input (B) Output
Y =A B

0 0 0
0 1 1
1 0 1
1 1 0

The output of an XOR gate is high (1) only when exactly one of its inputs is high (1) .
If both of an XOR gate's inputs are low (0) , or if both of its inputs are high (1) , then the output
of the XOR gate is low.

IC 7486 is the standard packaging of EX-OR gate. It consist of four two input EX-OR gates.
The pin configuration of IC 7486 is as shown in the figure below:

Universal Gates:
The NAND and NOR gates are called as “Universal gates” because it is possible to implement any
Boolean expression with the help of only NAND or only NOR gates.
Hence a user can build any combinational circuit with the help of only NAND gates or only NOR
gates.

 NOR is a combination of OR gate and NOT gate

 i.e., OR gate +NOT gate = NOR gate
 The NOR gate works opposite to the OR gate

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  Its Boolean algebra representation is
Logic Symbol :
Y AB
or
Y A B

Truth table:

Y A B

Input (A) Input (B)

Output (Y  A  B )
0 0 1
0 1 0
1 0 0
1 1 0

 This circuit will give high output (1), if both inputs is low (0) ,
otherwise the output is low (0)
 The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.

IC 7402 is a 14 pin TTL IC that consists of 4, two-input NOR gates.

The pin configuration of IC 7402 is also shown in the below figure.

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  NAND is a combination of AND gate and NOT gate
 i.e., AND gate +NOT gate = NAND gate
 The NAND gate works opposite to the AND gate

 Its Boolean algebra representation is

Logic Symbol : Y  A B

or

Or

Truth table:

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 Input (A) Input (B) Output Y  A. B
0 0 1
0 1 1
1 0 1
1 1 0

 This circuit will give high outpu t (1), if any inputs is low (0),
otherwise the output is low(0)
 The symbol is an AND gate with a small circle on the output. The
small circle represents inversion.

IC 7400 is a 14 pin TTL integrates circuit four, two input NAND gates inside.
The pin configuration of IC 7400 is also as shown in the figure.

Implementation of Basic Logic Gates using Universal Logic Gates

1. NOT Gate using NAND Gate
The following figure shows a NOT gate using a NAND gate.

2. NOT Gate using NOR Gate

3. AND Gate using NAND Gate

The following figure shows an AND gate using a universal NAND gate.

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 4. AND Gate using NOR Gate
The following figure shows an AND gate using a universal NOR gate.

5. OR Gate using NAND Gate

The following figure shows an OR gate using a universal NAND gate.

6. OR Gate using NOR Gate

The following figure shows an OR gate using NOR gate.

4.3Boolean Algebra

Boolean Algebra
Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It
uses only the binary numbers i.e. 0 and 1. It is also called as Binary Algebra
or logical Algebra. Boolean algebra was invented by George Boole in 1854.

Rule in Boolean Algebra

Following are the important rules used in Boolean algebra.

 Variable used can have only two values. Binary 1 for HIGH and Binary
0 for LOW.

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  Complement of a variable is represented by an overbar (-). Thus,
complement of variable B is represented as . Thus if B = 0 then
= 1 and B = 1 then = 0.
 ORing of the variables is represented by a plus (+) sign between
them. For example ORing of A, B, C is represented as A + B + C.
 Logical ANDing of the two or more variable is represented by writing
a dot between them such as A.B.C. Sometime the dot may be
omitted like ABC.

Boolean Laws
There are six types of Boolean Laws.

1. Commutative law
Any binary operation which satisfies the following expression is referred to
as commutative operation.

Commutative law states that changing the sequence of the variables does
not have any effect on the output of a logic circuit.

2. Associative law
This law states that the order in which the logic operations are performed
is irrelevant as their effect is the same.

3. Distributive law
Distributive law states the following condition.

4. AND law
These laws use the AND operation. Therefore they are called as AND laws.

5. OR law
These laws use the OR operation. Therefore they are called as OR laws.

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 6. INVERSION law
This law uses the NOT operation. The inversion law states that double
inversion of a variable results in the original variable itself.

De Morgan's Theorems
De Morgan has suggested two theorems which are extremely useful in
Boolean Algebra. The two theorems are discussed below.

Theorem 1

 The left hand side (LHS) of this theorem represents a NAND gate with
inputs A and B, whereas the right hand side (RHS) of the theorem
represents an OR gate with inverted inputs.
 This OR gate is called as Bubbled OR.

Table showing verification of the De Morgan's first theorem

Theorem 2

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  The LHS of this theorem represents a NOR gate with inputs A and B,
whereas the RHS represents an AND gate with inverted inputs.
 This AND gate is called as Bubbled AND.

Table showing verification of the De Morgan's second theorem −

Duality theorem:
It says, Start with the Boolean expression. We can drive another relation by
changing each OR sign to AND sign. Changing each AND to OR sign
Then complementing any 0 or 1 in the expression.
Example
A. (B+C)=A.B+A.C
A+(B.C)=(A+B).(A+C)

SUM-OF-PRODUCTS METHOD
Fundamental product:
The four possible ways of two input AND gate that are in
complemented and uncomplemented form. These output are called
fundamental products. This idea of fundamental products applies to
three or more inputs variables. For 3 input AND gate there are eight
possible output states. Those are shown in bellow truth table.

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 Truth table
A B C Y
0 0 0 A B C
0 0 1 A B C
0 1 0 A B C
0 1 1 A B C
1 0 0 A B C
1 0 1 A B C
1 1 0 A B C
1 1 1 A B C

Sum of product equation:

The logical sum of those fundamental products that produce output
1’s in the truth table. The corresponding logic circuit is an AND-OR circuit.
For instance, the output appears 1 for input A=0,B=1 and C=1. The
corresponding fundamental product is ABC. The next output 1 is appear for
input A=1, B=0 and C=1. The corresponding fundamental product is ABC.
Continuing like this we can identify all fundamental products. To get the
sum-of-products equation we have to do OR the fundamental products it is
show in logic equation.

Logic Equation: Y=ABC + ABC + ABC +ABC

KARNAUGH MAP
Karnaugh map is drawing that shows all the fundamental products
and the corresponding output values of the truth table.

Two Variable mapping:

Truth table
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Karnaugh map:

The variables are A and B and the components are 0 and 1. The vertical
column consists A followed by A. The horizontal column consists followed by
B. Now In the truth table the first output 1 appears for A=0 and B=1. The
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 fundamental product for this is AB. Enter this fundamental products on the
Karnaugh map shown above figure.

This 1’s represents AB, because 1’s is in row A and in column B. Similarly
the truth table, next high output in truth table is appear in fundamental
products are AB and the next high output in AB and placed it in the
Karnaugh map.

Finally in the Karnaugh map, enter 0’s in the remaining space.

Three variables Karnaugh map
Truth table
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1 ABC
0 1 1 0
1 0 0 1 AB C
1 0 1 1 ABC
1 1 0 0
1 1 1 1 ABC

Karnaugh map:

In the three variable Karnaugh map, the vertical column lists A ,

A and the horizontal column lists BC ,BC, BC, BC. Only one variable
changes with this order complemented to uncomplemented as vice versa.
Look for output 1’s in the table. The first output 1 found in ABC and the next
remaining output for ABC, ABC and ABC. Enter 1’s in the Karnaugh map for
this product. The final step is entering 0’s for the remaining space.

Four variables mapping :

Truth table

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 A B C D Y
0 0 0 0 0
0 0 0 1 1 ABCD
0 0 1 0 1 ABCD
0 0 1 1 0
0 1 0 0 1 ABCD
0 1 0 1 0
0 1 1 0 1 ABCD
0 1 1 1 1 ABCD
1 0 0 0 0
1 0 0 1 1 ABCD
1 0 1 0 1 ABCD
1 0 1 1 1 ABCD
1 1 0 0 0
1 1 0 1 1 ABCD
1 1 1 0 0
1 1 1 1 0

Karnaugh map:

In the four variable column map the vertical column has AB, AB, AB
and AB and the horizontal row has CD, CD, CD and CD. The truth table have
output1’s appearing for A,B,C,D inputs of
01,0010,0100,010,0111,1001,1010,1011and 1101 and the fundamental
products for this input condition are ABCD, ABCD, ABCD,ABCD, ABCD,
ABCD, ABCD, ABCD, ABCD, ABCD and then enter 1’s in the Karnaugh map
as shown in above figure. Final step is enter remaining spaces are 0’s.
KARNAUGH MAP REDUCTION:
1) Pairs
2) Quads
3) Octet
Pairs:
The two horizontally or vertically adjacent 1’s are in the Karnaugh
map. In the pair of horizontally or vertically adjacent 1’s you can eliminate
the variables that appears in both complemented and uncomplemented
form. The remaining variables will be only 0’s appearing in single product

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 term corresponding to the pair of 1’s Therefore the encircled pair of 1’s as
shown in below figure. Represent the product BCD.
CD CD CD CD
AB 0 0 0 0
AB 0 0 0 1
AB 0 0 0 1
AB 0 0 0 0
Quads:
It is the group of four 1’s that are horizontally or vertically adjacent
1’s may be end to end as shown in the figure or in the form of the square.
When you see a Quad on the Karnaugh map always encircled it because it
reaches simple product. A Quad eliminates two variables and their
components.

CD CD CD CD
A B 0 0 0 0
A B 0 1 1 0
A B 0 1 1 0
A B 0 0 0 0

Octet:
Besides Pairs and Quads there is one more group of adjacent 1’s to
look for Octet. This is group of eight 1’s like those of below figure. An Octet
eliminates three variables and their complements.

CD CD CD CD
A B 0 0 0 0
A B 0 0 0 0
A B 1 1 1 1
A B 1 1 1 1

Redundant group:
A group of 1’s on Karnaugh map that are all the parts of other groups. You
can eliminate redundant group. In the (A) table all the 1s of the quad are
used by the pairs by overlapping. Because of , the quad is redundant and
can be eliminated to get (B) table. In that the pairs cover all the 1s.

(A) (B)
CD CD CD CD CD CD CD CD
AB 0 0 1 0 AB 0 0 1 0

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 AB 1 1 1 0 AB 1 1 1 0
AB 0 1 1 1 AB 0 1 1 1
AB 0 1 0 0 AB 0 1 0 0

Summary of the Karnaugh map for simplify the Boolean equation.

1) Enter 1’s on Karnaugh map for ea h fundamental product that produce a

one output in the truth table. Enter 0’s is elsewhere.
2) Encircled the octets and quads and pairs remember to roll or over lock to
set the largest group possible.
3) If any isolated 1’s remaining encircled it.
4) Eliminate any redundantly group.
5) Write the Boolean equation by ORing the products corresponding to the
encircled group.

DON’T CARE CONDITION:

In some digital system certain input condition not occur during normal
operation. Therefore the corresponding output never occurs. Since, the
output never appears which is indicating by an x in the truth table.

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

For instance, the above truth table when the output is low all output is
increasing from 0000 to 1000, high for 1001 and an x for 1010 through
1111. The x is called the don’t care condition. Whenever you see an x in the
truth table, you can see let it equal either 0 or 1 which produce the simple

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 logic circuit.

PRODUCT OF SUM:
The logical product of those fundamental sums that produce output 0 in
the truth table. The corresponding logic circuit is an OR-AND circuit, or the
equivalent NOR-NOR circuit.
The product of sum method is similar and vice versa of sum of product.
A B C Y
0 0 0 0 A+B+C
0 0 1 1
0 1 0 1
0 1 1 0 A+B+C
1 0 0 1
1 0 1 1
1 1 0 0 A+B+C
1 1 1 1

The product of sum method is the fundamental sum produce output 0 for
the corresponding input condition. Above truth table is want to get the
product of sum equation is to locate each output in that Truth table and
write down this fundamental sum. The first output appears for A=0,B=0 and
C=0 . Then fundamental sum of this input A+B+C. This produces an output
0 for the corresponding input condition.
Y=A+B+C=0+0+0=0
Similarly, for 2,3 output 0 occurs for A=0,B=1,C=1 and A=1,B=1,C=0.
Therefore its fundamental sum is
I Y=A+B+C=0+1+1=0
II Y=A+B=C=1+1+0=0
To get the product of sum equation we have to this AND the
fundamental sum.
Y=(A+B+C). (A+B+C). (A+B+C)

Arithmetic Circuits
Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs.
The half adder circuit is designed to add two single bit binary number A
and B. It is the basic building block for addition of two single bit numbers.
This circuit has two outputs carry and sum.

Block diagram

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 Truth Table

Circuit Diagram

Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It
can add two one-bit numbers A and B, and carry c. The full adder is a three
input and two output combinational circuit.

Block diagram

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 Truth Table

S=A⊕B⊕Cin
cout=AB+(A⊕B)cin

Circuit Diagram

This adder is called as Full adder because for implementing one Full
adder, we require two Half adders and one OR gate. If C in is zero, then Full
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 adder becomes Half adder.

Half Subtractors
Half subtractor is a combination circuit with two inputs and two outputs
(difference and borrow). It produces the difference between the two binary
bits at the input and also produces an output (Borrow) to indicate if a 1 has
been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is
called as Subtrahend bit.

Truth Table

Circuit Diagram

Full Subtractors
The disadvantage of a half subtractor is overcome by full subtractor. The
full subtractor is a combinational circuit with three inputs A,B,C and two
output D and C'. A is the 'minuend', B is 'subtrahend', C is the 'borrow'
produced by the previous stage, D is the difference output and C' is the
borrow output.

Truth Table
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 Circuit Diagram

Combinational logic circuits

A logic circuit consisting of two or more logic gates that has
no feedback and no memory is called a combinational logic
circuit.
A combinational logic circuit is constructed using OR, AND and NOT
gates. Therefore, the basic building block for combinational circuits is
the logic gate. Since a combinational logic circuit has no feedback and
no memory, its output depends only on the current value of its inputs.

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 Combinational logic circuit is a type of digital logic circuit which is
implemented by Boolean circuits, where the output is a pure function of
the present input only. In a combinational logic circuit, the output
depends on the combination of its inputs.
Combinational logic is about combining logic gates together to
process two or more signals in order to produce at least one output
signal according to the logical function of each logic gate. Common
combinational circuits include Multiplexers, De-multiplexers, Encoders,
Decoders, adders and Comparators.

Some of the characteristics of combinational circuits are

 The output of combinational circuit at any instant of time depends
only on the levels present at input terminals.
 The combinational circuit does not use any memory. The previous
state of input does not have any effect on the present state of the
circuit.
 A combinational circuit can have an n number of inputs and m
number of outputs.

Block diagram

Parity Generator and Parity Checker

What is Parity Bit?

The parity generating technique is one of the most widely used error detection techniques for
the data transmission. In digital systems, when binary data is transmitted and processed, data
may be subjected to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.
Hence, parity bit is added to the word containing data in order to make number of 1s either
even or odd. Thus it is used to detect errors during the transmission of binary data .The
message containing the data bits along with parity bit is transmitted from transmitter node to
receiver node. At the receiving end, the number of 1s in the message is counted and if it
doesn’t match with the transmitted one, then it means there is an error in the data.

Parity generator and checker

A parity generator is a combinational logic circuit that generates the parity bit in the
transmitter. On the other hand, a circuit that checks the parity in the receiver is called parity
checker. A combined circuit or devices of parity generators and parity checkers are
commonly used in digital systems to detect the single bit errors in the transmitted data word.
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 The sum of the data bits and parity bits can be even or odd. In even parity, the added parity
bit will make the total number of 1s an even amount whereas in odd parity the added parity
bit will make the total number of 1s odd amount. The basic principle involved in the
implementation of parity circuits is that sum of odd number of 1s is always 1 and sum of even
number of 1s is always zero. Such error detecting and correction can be implemented by
using Ex-OR gates (since Ex-OR gate produce zero output when there are even number of
inputs). To produce two bits sum, one Ex-OR gate is sufficient whereas for adding three bits
two Ex-OR gates are required as shown in below figure.

Parity Generator
It is combinational circuit that accepts an n-1 bit stream data and generates the additional bit
that is to be transmitted with the bit stream. This additional or extra bit is termed as a parity
bit. In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data
stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream. In odd
parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and
the parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us discuss both even
and odd parity generators.

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 Even Parity Generator
Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three
inputs A, B and C are applied to the circuits and output bit is the parity bit P. The total
number of 1s must be even, to generate the even parity bit P. The figure below shows the
truth table of even parity generator in which 1 is placed as parity bit in order to make all 1s as
even when the number of 1s in the truth table is odd.

The K-map simplification for 3-bit message even parity generator is

From the above truth table, the simplified expression of the parity bit can be written as

The above expression can be implemented by using two Ex-OR gates. The logic diagram of
even parity generator with two Ex – OR gates is shown below. The three bit message along
with the parity generated by this circuit which is transmitted to the receiving end where parity

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 checker circuit checks whether any error is present or not. To generate the even parity bit for
a 4-bit data, three Ex-OR gates are required to add the 4-bits and their sum will be the parity
bit.

Odd Parity Generator

Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three inputs
are A, B and C and P is the output parity bit. The total number of bits must be odd in order to
generate the odd parity bit. In the given truth table below, 1 is placed in the parity bit in order
to make the total number of bits odd when the total number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified by using K-map as

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 The output parity bit expression for this generator circuit is obtained as

P = (A ⊕ B ⊕C)’

Parity Check
It is a logic circuit that checks for possible errors in the transmission. This circuit can be an
even parity checker or odd parity checker depending on the type of parity generated at the
transmission end. When this circuit is used as even parity checker, the number of input bits
must always be even. When a parity error occurs, the ‘sum even’ output goes low and ‘sum
odd’ output goes high. If this logic circuit is used as an odd parity checker, the number of
input bits should be odd, but if an error occurs the ‘sum odd’ output goes low and ‘sum even’
output goes high.

Even Parity Checker

Consider that three input message along with even parity bit is generated at the transmitting
end. These 4 bits are applied as input to the parity checker circuit which checks the
possibility of error on the data. Since the data is transmitted with even parity, four bits
received at circuit must have an even number of 1s. If any error occurs, the received message
consists of odd number of 1s. The output of the parity checker is denoted by PEC (parity
error check). The below table shows the truth table for the even parity checker in which PEC
= 1 if the error occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no
error occurs, i.e., if the 4-bit message has even number of 1s.

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 The above truth table can be simplified using K-map as shown below.

The above logic expression for the even parity checker can be implemented by using three
Ex-OR gates as shown in figure. If the received message consists of five bits, then one more
Ex-OR gate is required for the even parity checking.

Odd Parity Checker

Consider that a three bit message along with odd parity bit is transmitted at the transmitting
end. Odd parity checker circuit receives these 4 bits and checks whether any error are present
in the data. If the total number of 1s in the data is odd, then it indicates no error, whereas if
the total number of 1s is even then it indicates the error since the data is transmitted with odd
parity at transmitting end. The below figure shows the truth table for odd parity generator

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 where PEC =1 if the 4-bit message received consists of even number of 1s (hence the error occurred)
and PEC= 0 if the message contains odd number of 1s (that means no error).

The expression for the PEC in the above truth table can be simplified by K-map as

After simplification, the final expression for the PEC is obtained as

PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)

The expression for the odd parity checker can be designed by using three Ex-NOR gates as shown
below.

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 Multiplexer
A multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input lines and n selection lines whose bit
combinations determine which input is selected.
A multiplexer or MUX, also called a data selector, is a combinational circuit
with more than one input line, one output line and more than one selection
(control) lines. A multiplexer selects binary information present on any one of the
input lines, depending upon the logic status of the selection inputs, and routes it
to the output line. If there are n selection lines, then the number of maximum
possible input lines is 2n and the multiplexer is referred to as a 2n -to- 1
multiplexer or 2n ×1 multiplexer.

General diagram of a Multiplexer

Fig. (a) Block diagram of 4 – to – 1 multiplexer

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 Fig.(b) Logic circuit and the truth table of a basic 4-to-1 multiplexer
The above Figures (a) and (b) respectively show the block diagram and the logic
circuit with truth table of a basic 4-to-1 multiplexer. The input combinations 00, 01, 10
and 11 on the select lines (S1S0) respectively switch I0, I1, I2 and I3 to the output. The
operation of the circuit is governed by the following Boolean function

Fig. Multiplexer (8 – to – 1) with 8 input lines and 3 control lines.

 Multiplexer is a combinational logic circuit used to select only one input
among several inputs based on selection lines.
 This can act as a digital switch.
 This is also called as data selector.
 For a multiplexer, there can be 2n inputs, n selection lines and only one output.
 It is a Many-to-One selector circuit.
De-multiplexer
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 A de-multiplexer is a combinational logic circuit with an input line, n control
lines and 2n output lines. It routes the information present on the input line to any of
the output lines.The output line that gets the information present on the input line is
decided by the bit status of the selection lines. Demultiplexer is also called data
distributor that is the data is distributed to any one of the selected output lines.
The bellow Figure (a) shows the circuit representation of a 1-to-4
demultiplexer. Figure (b) shows the truth table of the demultiplexer when the input
line is held HIGH.

Fig. 1-to-4 Demultiplexer (a) Circuit representation (b) Truth table.

Logic diagram of 1- to - 8 demultiplexer is shown in the bellow figure. It contains 3

control lines, 8 output lines and only one data input line. The data input line is labeled
as x. The control and address bits are labeled as c 0,c1 and c2. The output bits are
labeled as D0, D1,… , D7. The data input x is transmitted to the selected output line.
When the control lines c0c1c2 = 000, only the AND gate 0 is enabled, other AND gates
are disabled. Therefore the data input x is transmitted through D0. The outputs of all
other gates are 0.

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 1-to-8 Demultiplexer (a) Logicdiagram (b) truth table

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