1

Lab 1 – Virtuoso - Inverter Design and Simulation

Introduction
This lab has you design an inverter using MOSFETs from gpdk045, Cadence’s fictitious 45nm
process PDK. You would place components and perform routing manually, and observe the
resulting electrical characteristics. In addition, you have to repeat this process for a NAND gate.
The schematic and initial simulation are to be done today, followed by layout which should be
finished within tomorrow.

Design Example: Inverter - Schematic and Simulation

1. Do not take any Cadence-related materials outside the lab! This applies to this manual as
well!
2. Create a new folder, in Documents, for this lab. Name it training_inverter. Right-click on
this folder and select Open in Terminal. Run pwd to make sure you are in the folder
training_inverter.
3. Run command virtuoso & to open virtuoso. After a few minutes, the Command
Interpreter Window (CIW) appears towards the bottom of the screen (don’t close the
terminal where you ran the virtuoso & command; closing this terminal will close Virtuoso).

Note: If, while running any Cadence tool (including virtuoso), you see “command not
found”, open a new terminal and run command sudo mount -a. After this command
completes without any errors or warnings, run the Cadence tool. If running the Cadence
tool still results in the error “command not found”, request lab staff to assist in mounting
Cadence tools.

Create new library

1. From the CIW, choose Tools > Library Manager.

1
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2. Choose File > New > Library. The New Library form is displayed.
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3. In the Name field, enter Labvlsi, then click OK. The Technology File for New Library
dialogue box opens. Select the Attach to an existing technology library radio button,
then click OK.

4. In the Attach Library to Technology Library form, choose gpdk045, then click OK. The
Labvlsi library will appear in Library Manager in Library column.
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Create new schematic

5. In the Library Manager, click on Labvlsi library to select it.

6. In menu bar, choose File > New > Cellview.
7. In the New File form, make sure Labvlsi is selected in the Library field and enter inverter
in the Cell field.

8. Choose Schematics L as the application to open with, then click OK. If following dialogue
box appears,

Click Always. If this dialogue box reappears, select Always again, and keep doing so until
this dialogue box stops appearing). After license check out succeeds (i.e. above dialogue
box stops appearing), a blank schematic canvas for the inverter design should open.
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Adding Components to a Schematic

9. In Virtuoso Schematic Editor L window, choose Create > Instance OR click on create

instance icon OR press i.

10. In Add Instance form, click the Browse button.
11. In the Library Browser, select gpdk045 in the Library column, select nmos1v in the Cell
column and select symbol in the View column as shown below:
 6

12. Switch to the Schematic Editor window and move your cursor in it; a highlighted symbol
should appear. Left-click to place the symbol on the schematic. Observe that the device
nmos1v has been added to the schematic and the symbol has an instance name.
13. Switch back to the Library Browser and select pmos1v in Cell column and symbol in View
column. Place it in the schematic.
14. The current command that is running is stated at the bottom of the schematic window.
Press the Esc key to end the adding instance command.
15. Click on the pmos1v symbol; the transistor properties are shown in the Property Editor
column (bottom-left of Schematic Editor L Editing window). You can modify the dimensions
(l and w) of your transistor here. Set the property total width = 240n M. You can also press
q to open the Edit Object Properties box, modify the values here, and click OK.

Note: Press f for better view scale. You can also scroll up or down the middle mouse
button for a suitable view scale.

Adding Source and Ground to the Schematic

16. Press i to open Add Instance form. Click Browse.

17. In the Library Browser, select analogLib in the Library column, select vdd in the Cell
column (OR type vdd in the box at the top of Cell column) and select symbol in the View
column, as shown below:
 7

18. Now you can place the vdd symbol in the schematic above the source of pmos1v symbol
with a single click. Repeat this procedure for “gnd”; place gnd below drain of nmos1v.
Press Esc when done.

Adding Pins to the Schematic

19. In Virtuoso Schematic Editor L window, choose Create > Pin OR click on create pin icon

OR press P.
20. In Add Pin form, type in in Pin Names and select input for Direction. Switch to Schematic
Editor window and place the pin to the left of the transistors.
21. Switch to Add Pin form, type out in Pin Names and select output for Direction. Place this
pin in schematic to the right of the transistors.

Adding Wires to the Schematic

22. In Virtuoso Schematic Editor L window, choose Create > Wire (narrow) or click on Create

Narrow Wire icon or press W.

23. To start wiring, click once at the starting point of the wire, move your mouse, click once
again to corner up or down the wire and click once again at the ending point of the wire. Do
the wiring in the schematic as shown in the following snapshot:
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24. When finished wiring, press Esc with your cursor in the schematic window to cancel the
wiring command.

Saving a Design

25. Click the Check and Save icon in the schematic editor window OR choose File >
Check and Save OR press Shift + X to try to save. You will get a warning:

26. You will also see a yellow blinking box around all unconnected pins and wires in the
Schematic Editor window. Close the warning message and connect drain of pmos1v with
source of nmos1v, as shown in the below snapshot:
 9

27. Press Shift + X to save. Now there should be no errors or warnings.

Simulating the Schematic using ADE-L

28. In Virtuoso Schematic Editor L window, choose Launch > ADE L to open the Virtuoso
Analog Design Environment L simulation window. If “Failed to check out license” dialogue
box appears as shown in step 8, click Always, and keep clicking Always until this dialogue
box stops appearing.
29. In the ADE L menu, choose Setup > Model Libraries.
30. In the Model Library Setup window, verify that a model file has already been included in the
Global Model Files. In the Section column, click twice on mc and change it to tt, then click
OK.
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Choose Analyses

31. In ADE L menu, select Analyses > Choose.

32. In Choosing Analyses menu, select tran, set the Stop Time field to 2n, and check the
Enabled check box as shown below.

33. Click Apply. The selected analysis will appear under the Analyses section in ADE L
window.

Note: You can setup multiple analyses if required (for this lab, there is only this one, that
you have set up). When finished, click OK.
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Select Outputs for Plotting

34. In ADE L menu, select Outputs > To Be Plotted > Select on Design. Your inverter
schematic will appear.
35. Click wire of input and out from schematic design, then press Esc.
36. Now the ADE L window will show all of the signals that have been selected under Outputs
section as shown in the snapshot below:

Choose Stimuli

37. In ADE L menu, choose Setup > Stimuli.

38. In Setup Analog Stimuli menu, for Stimulus Type, choose Inputs.

Note: Inputs sets the stimulus for the signals with input pins in the schematic. Global
Sources lets you assign DC voltages to global signals that represent power supplies in the
design.

Note: If, during simulation in ADE, in Stimuli, “Global Sources” list is empty, close Stimuli
and first, select Outputs > To be plotted, then open Stimuli.

39. Check the Enabled check box.

40. For Function, select Pulse.
41. Enter the value 1.2 for Voltage 1, 0 for Voltage 2, 1n for Period and 0.5n for Pulse Width,
as shown below:
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42. Click Apply. Make sure that the selected input is changed to ON in the box below Stimulus
Type. (If there are more input pins in the schematic, click on the other input(s) in the box
below Stimulus Type and repeat the previous two steps with appropriate values. For this
schematic, there is only one input pin, that you have configured).
43. For Stimulus Type, select Global Sources.
44. Check the Enabled check box, choose dc for Function and enter 1.2 in DC Voltage.
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45. Click Apply and confirm that the selected Global Source is changed to ON in the box below
Stimulus Type. Then click OK.

Running Simulation

46. In ADE L menu, select Simulation > Netlist and Run or click on Netlist and Run icon .
After this, wait up to 5 minutes for it to complete. If it does not, save your work and close all
windows, then launch virtuoso again and run simulation again. If it hangs again, call
instructor.
47. When the simulation is complete, the waveform window with the selected signals appears.

Choose Graph > Split All Strips or click on Split All Strips icon to separate the
waveforms. Click Simulation > Netlist > Display to see the schematic netlist.
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Generating Symbol

48. In Virtuoso Schematic Editor L window, choose Create > Cellview > From Cellview. The
Cellview From Cellview form opens as shown in the following snapshot.

49. Verify the name of the library in the Library Name text field. Also verify the name in the Cell
Name text field and click OK. The Symbol Generation Options form opens.

Observe that the input pin input (same name as in your schematic) appears in the Left
Pins text field. The out pin (same name as in your schematic) is in the Right Pins text field.

50. Click OK. The Virtuoso Symbol L Editing window opens and displays the automatically
generated symbol.
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This symbol would work “as is” in a schematic where the inverter symbol is needed.
However, you can edit the symbol if you want it to have a more traditional appearance in a
schematic. To save and use the automatically generated symbol, skip the next two steps.

51. You can change the green box into an inverter symbol as follows:

In Virtuoso Schematic Editor L window, choose Create > Shape > Line to create the lines
and choose Create > Shape > Circle to create the inverter bubble.

Tip: Click once to start drawing the line, move your mouse to draw the line, click once again
to corner the line and double click to end drawing the line. If at any point you make a
mistake, you can click on the Undo button to erase your action.

52. Make the following symbol:

53. Choose File > Check and Save. Check for any warnings and errors in CIW window. If there
is no error, close the Virtuoso Symbol Editor.
54. In the Library Manager window, notice that your inverter symbol has been listed in View
section of your inverter cell.
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Inverter Testbench

After creating a symbol, you can place your inverter as a component in a schematic, like you
placed nmos1v and pmos1v. To test the inverter as a component in a new schematic,

55. In Library Manager, choose your design library i.e. Labvlsi, then select File > New > Cell
View; a New File form appears. Type inverter_tb in the Cell field, as shown in the following
snapshot, then click OK.

56. In Virtuoso Schematic Editor L Editing window, choose Create > Instance.
57. In Add Instance form, click Browse and select Library/Cell/View sections as
Labvlsi/inverter/symbol.
58. Point your mouse cursor into the Virtuoso Schematic Editor page; your inverter symbol
appears. Then place your inverter symbol there by a single click (if you did not change
inverter symbol, you will see the automatically generated symbol).
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59. Add vdd, gnd and pins for input Vin and output Vout as done in schematic of inverter, and
perform connections as shown below:

Note: There is no need to connect vdd and gnd to anything in this schematic, so long as
they are added in the same fashion as they were added in schematic of inverter i.e. added
from same library.
 19

60. Press Shift + X to check and save.

Simulating the Inverter Test Bench

61. Repeat the steps for running simulation to simulate inverter_tb using ADE L (these steps
start from the Simulating the Schematic using ADE-L heading and end at the Running
Simulation heading). You should obtain results similar to the following:

62. Close the Virtuosos (R) Visualization & Analysis window, ADE window and Virtuoso
Schematic Editor window.
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Lab 2 – Virtuoso - Digital Gate Custom Layout

Introduction

This lab is a continuation of the previous lab.

Design Example: Inverter - Layout, DRC and LVS

1. Open a terminal and navigate to the folder in which you did the previous lab’s work i.e. the
/home/student/Documents/training_inverter folder using the command:

cd /home/student/Documents/training_inverter

2. Run command virtuoso & to open virtuoso.

Creating the Layout

3. From Library Manager, open your inverter schematic cell view. Double click on schematic
in View section. Your inverter schematic will appear in Virtuoso Schematic Editor.
4. Click Launch > Layout XL. Startup Option form will appear. Click OK.

5. New File form will appear. Click OK.

6. A blank Virtuoso Layout Suite XL window will appear next to Virtuoso Schematic Editor L
window as shown below.
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7. In Virtuoso Layout Suite XL, Click Connectivity > Generate > All From Source... A Generate
Layout form will appear.

8. Click on the I/O Pins tab.

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9. Under Pin Label, check Create Label As and click on the Options button.

10. Set the options as shown in the form below, then click OK. Click OK in Generate Layout
form.

11. An inverter layout will appear automatically in Virtuoso Layout Suite XL window as shown
below.
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Press Shift + F to view layout. Press Ctrl + F to return to black-box view.

12. Select the nmos1v layout by left clicking on it and press q on the keyboard. The Edit
Instance Properties form appears.
13. In the Parameter tab, select Integrated for the Bodytie Type and check Left Tap, as shown
below.
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14. Repeat the previous two steps for pmos1v layout. Your layout is as shown as below.
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Creating VDD and GND Rails

15. In Virtuoso Layout Suite XL, click Place > Pin Placement. A Pin Placement window will
appear as shown below.
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16. Select the vdd pin’s name by clicking on vdd!:vdd!:vdd!. In the Attributes section, select
Top for Edge and click Apply. Then click the HRail button in Create section. Notice that the
VDD rail has been created in the layout window.
17. Select the gnd pin’s name by clicking on gnd!:gnd!:gnd!. In the Attributes section, select
Bottom for Edge and click Apply. Then click the HRail button in Create section. Notice that
the GND rail has been created in the layout window.
18. Close the Pin Placement window. Your layout will be as shown below.
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Connecting the Terminals

19. In Virtuoso Layout Suite XL, click Window > Assistants > Annotation Browser. The
Annotation Browser toolbox will appear in the left box as shown below in the red circle.
Click on the Incomplete Nets in the Annotation Browser toolbox to list down all of the
unconnected nets. You can change the toolbox size (or pull out the toolbox) as shown in
the figure.
 28

20. Click on the gnd! net; the net terminals are highlighted in the Virtuoso Layout page as
shown below.
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21. Select Create > Wiring > Point to Point (or press Ctrl + Shift + D) and then click once at the
highlighted gnd! rail and move the mouse pointer. You will see a pre-connection net (a
solid line and a dotted line) from gnd! rail to the bulk of the nMOS terminal in the layout
window.
22. Click once again at the bulk of the nMOS terminal (where you see the B). You will see the
net has been routed in the layout window as shown below. You will also see that the gnd!
net is not listed anymore in the Annotation Browser.
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23. Repeat the previous step to complete the connectivity of the nets connected to the out
terminal.
24. Now, we will connect the poly (green part) of nMOS and pMOS manually. Click Create >
Wiring > Wire (or press P) and point your mouse pointer to bottom of poly of pMOS and
move the mouse pointer. You will see a pre-connection net to poly of nMOS. Move your
mouse pointer to top of poly of nMOS and click once. Both poly are now connected.
25. Complete the connectivity of the remaining nets using point-to-point wiring, because when
you use point-to-point wiring to connect input to poly, you will see that virtuoso has
automatically created a via for this connection. The complete inverter layout is shown
below.
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Note: Sometimes, when performing point-to-point wiring, virtuoso may create a route that
is too large, inefficient and/or may cause shorts with other nets. To avoid these problems,
you may create a part of the route using manual wiring, and then use point-to-point wiring
to complete it. You can redo the connections for any net in this fashion, for practice.

26. Make sure to save your layout by selecting File > Save or click on Save icon.

Running DRC using PVS

27. Before running DRC, you have to create new folders in your working directory to place the
files created when doing DRC. Open a new terminal, type pwd to verify that you are in your
working directory. Then run mkdir -p phyver/drc, then close the terminal; this command
has created the phyver directory and also the drc directory inside the phyver directory. You
can also use Files browser to create these folders.
28. In the Virtuoso Layout Suite XL Editing window, navigate to Launch > Plugins > PVS. If
PVS is unchecked, check it. The PVS menu will appear in the menu bar of layout window.
29. Click PVS > Run DRC. A PVS DRC Run Submission Form appears as below.
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30. Set your Run Directory to the phyver/drc folder (which has been created above). Click the
... button to set the Run Directory.
31. Click the Rules button. A Rules Form appears as shown below.
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32. To set Technology mapping file, click the ... button, browse to the folder
/mnt/Cadence/PDK/gpdk045_v_6_0 and double-click on [Link]. Set Technology to
gpdk045_pvs and Rule Set to default.
33. In the Rules box, remove the entries other than the one entry shown in the above image.
34. Near the left-bottom corner, select DRC DE radio button.
35. Click Submit button. A PVS DRC Debug Environment window and a PVS DRC Reports
window appear as shown below.
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36. Right now, there should be no DRC violation. Now create a violation by creating a wire very
close to another wire. To do this, press P, click at the starting point and double-click at the
ending point. An example is shown highlighted in the figure below:

37. Save the layout. In the PVS Reports window, click the ReRun button.
38. Now PVS Debug window shows that there is one DRC error. The top section tells the
location of the error and the bottom section tells why the error occurred. Click on the error
in the top section, then switch to Virtuoso Layout window; it has zoomed in to the location
of the error as shown below.
 35

Note: This is a DRC violation because this is 45nm technology, and the distance between
the two wires is smaller than 45nm. To study what else constitutes DRC, google it.
39. Correct your layout as suggested in the bottom section in the PVS Debug window, then
save your layout. In PVS Reports window, click ReRun button.
40. Repeat the previous two steps until no DRC error appears in the PVS Debug Window.
Then close PVS Debug window and PVS Reports window.

Running LVS using PVS.

41. Before running LVS, you have to create a new folder in your working directory to place the
files created when doing LVS. Open a new terminal, type pwd to check for the current
directory. Then run command mkdir phyver/lvs. Then, close the terminal. You can also
use the Files Browser to create this folder.
42. In Virtuoso Layout Suite, click PVS > Run LVS. A PVS LVS Run Submission Form
appears.
43. Set the Run Directory to the lvs folder created above.
44. Click the Rules button. Set up the Rules form as done in the DRC form.
45. Click the Input button. Scroll down. Under the Schematics section, click on the dropdown
menu showing Create CDL and select auCDL.
46. Click the Submit button.
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47. If all steps have been performed correctly, you should see the following box:

48. Click Yes to open PVS LVS Debug Environment. There should be no errors, so close this
window.
49. Now delete a wire to create an error that will be caught by LVS e.g. the wire between vdd
and source of pmos1v. This wire is highlighted in the figure below; click on it and press
delete, then save your layout.
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50. In the PVS Reports window, click ReRun. The Comparison Results will show Mismatch.

51. Click Yes in the PVS LVS Run Status window. An LVS Debug Window will appear which
states the mismatch between Schematic and Layout. Expand Inverter to see the detail of
the errors.

52. Correct your layout and save it. In PVS Reports window, click ReRun.
53. Repeat steps 55 to 57 until Clean and Match status appears, as it did before. Then, Close
the PVS Debug window and PVS Reports window.

Running Parasitic Extraction using QRC-L.

54. Before running QRC, you have to create a new folder in your working directory to place the
files created when doing QRC. Open a new terminal and run pwd to check the current
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directory. Then run command mkdir phyver/qrc. Then, close the terminal. You can also
use Files Browser to create this folder.
55. Select PVS > Run LVS. Change Run Directory to qrc folder as created above. Click Rules
button and set the Rules Form as you did before.
56. Click Input button. Verify that auCDL is selected.
57. Click Output button. Scroll down the Output form until you see the Additional Output
section. Check Create Quantus Input Data as shown below.

58. Click Submit button. Make sure you get the Clean and Match status. Then close the PVS
Run Status, PVS Debug and PVS Reports windows.
59. Select Quantus > Run PVS - Quantus. A Quantus (PVS) Interface form appears as shown
below.

60. Click OK. Then a Quantus (PVS) Parasitic Extraction Run Form appears as below. Set
Technology, RuleSet and Output as shown below. In the View field, enter pvs_extracted.
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61. Click the Extraction tab. Set the Extraction form as shown below.
 40

62. Click OK. A Quantus Progress Form appears. Wait until you see the below dialogue box:

63. Click Close. Notice that the pvs_extracted view is listed in View section of inverter cell in
Library Manager. Double click the pvs_extracted view. A Virtuoso Layout Suite window
which contains your inverter layout with parasitic resistances and capacitances appears.
Zoom in to see the parasitic components.
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Press Shift + F to switch to component view.

64. Close the pvs_extracted layout, and inverter layout if it is still open.

Simulating Extracted Layout using ADE-L.

65. Create symbol for inverter (no need to draw triangle and circle for this lab), then create
inverter_tb schematic done on day 11. The result is shown below:
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66. Launch ADE L and repeat the steps for performing simulation as done on day 11, but do
not click Netlist and Run button yet.
67. Select Setup > Environment. An Environment Options form appears. In Switch View List,
type pvs_extracted in between [Link] and schematic as shown below. Then click OK.

68. In ADE L window, click Netlist and Run button. After this, wait up to 5 minutes for
simulation to complete. If it does not, save your work and close all windows, then launch
virtuoso again and run simulation again. If it hangs again, call instructor.
69. When the waveform window appears, make sure that the output waveform is correct. Close
the waveform window and the simulation output log window.
70. In ADE L window, select Simulation > Netlist > Display to see the created netlist. Make
sure that the netlist is created from the pvs_extracted view. You can also see all of the
parasitic components in the netlist.
 43

Hint: Selecting “Integrated” for Bodytie Type of an NMOS shorts its body with its source terminal. If
the body of an NMOS is not connected to its source terminal in the schematic, you may have to
select “Detached” for Bodytie Type instead of “Integrated”.
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Lab 3 – Draw MOSFET’s Layout

Comparing an IC design to a building, the layers in an IC design are like the floors of a plaza, and
the layout you make in virtuoso is a top-down view of this plaza (3D structure). Rectangles are
used to indicate presence of a layer (floor) in a given area; outside the rectangles, that layer is
absent. In this lab, you will draw the pmos layout yourself, by drawing rectangles of various layers.

1. (Reminder) Do not take any Cadence-related materials outside the lab. This applies to this
manual as well! If you or anyone else has copied this manual anywhere, please delete it.
2. Open the inverter’s layout. Press Ctrl + A and then Delete to delete everything.
3. Use Connectivity > Generate > All From Source… to generate the PRboundary
(Place-and-Route boundary), but delete the pmos. Change the nmos’ Bodytie Type to
Integrated.
4. Since a layout is essentially a huge number of rectangular shapes with specific sizes, the
first thing we need to do is to setup the grid dimensions that help make drawings easy.
Click Options > Display to bring out the Display Options dialog. The options we need to
change are located in the Grid Control panel to the top-right corner. Keep Type as dot.
Change Minor Space to 0.01 and Major Space to 0.1. Since the unit of length here is um,
this setting will create a grid with bigger dots spaced at 100 nm and smaller dots spaced at
10 nm. Change both X Snap Spacing and Y Snap Spacing to 0.01 so that everything you
draw is aligned to a grid of 10 nm -- this is also known as the manufacturing grid. Save the
settings by choosing Library from the bottom row and clicking Save To button.

Note: The actual manufacturing grid of Cadence’s fictitious 45 nm PDK is 5 nm, but we
are using 10 nm for simplicity; this is valid because 10 nm is an integer multiple of 5
nm.

5. In order to manually create the pmos shown in the figure below step 6, we start by creating
its N-well. In the list of layers you can see on the left side, click on Nwell, then press r to
create a rectangle. Click once to set its upper left corner and click a second time to set its
lower-right corner, completing the rectangle. Make it 600 nm (6 big blocks) wide and 360
nm (3 big blocks + 6 small blocks) tall as shown in the following figure:
 45

6. Now change the length of this rectangle from 600 nm to 620 nm :) For this purpose, click

the Full Select button to switch to Partial Select. Click on the right edge of the
Nwell’s rectangle to select this edge. Drag it to the right to stretch the rectangle by two
small blocks.
7. Complete the pmos layout shown in the below figure by utilizing the layers Nimp, Pimp,
Poly, Oxide, Metal1 and Cont, by creating and stretching rectangles of these layers. You
can see the color and style of each layer in the list of layers on the left side. Do try to match
the sizes down to the number of small blocks, but mistakes will probably be caught by the
DRC and LVS checks. You can view the small dots by zooming in to 200%.

Note: The highlighted rectangle is that of Oxide layer, but it’s made obscure by the Pimp,
Nimp and Metal1 rectangles.
 46

8. Now complete the rest of the connections for the inverter, and run DRC (Design Rule
Check) check. You will see some DRVs (Design Rule Violations; DRVs are also called
DRC errors). If you’ve followed the above layout accurately, your list of errors will match the
following:

9. Open a new terminal and run the following command to open a document:

gio open /mnt/Cadence/PDK/gpdk045_v_6_0/docs/gpdk045_drc.pdf

Read this document’s pages 4-8, 10 and 17.

10. Go back to the DRC Debug Environment window. Write down the errors’ names and
descriptions, using pen and paper.
11. Click on the first DRC error; your layout window will zoom in on it. Read the description of
the DRV and fix it. Do the same for the two remaining DRVs (and any others as well if
you’ve more than 3).
 47

12. Now run LVS check. If you haven’t made mistakes, there should be only one mismatch: the
pmos’ finger length; it is defined by the Width of the Poly (green bar) in the middle of the
pmos. Note that this parameter is called Length in the pmos’ properties in the schematic.
13. There are two ways to fix this LVS mismatch: either change the schematic, or change the
layout. For the time being, we change the layout. To change this parameter to 45 nm in the
layout without changing the manufacturing grid, click on the pmos’ poly and press Q.
Change Width to 45 nm.

Note: Usually, going against the manufacturing grid is a BAD idea, but in this case, we
know that the actual manufacturing grid is 5 nm, hence it is fine to set the width to
45 nm. Don’t violate the Snap To values if you don’t know what you are doing!

Note: You can’t make the width smaller than 45 nm for this PDK! Guess why?

14. Once DRC and LVS (Layout Versus Schematic) checks have been passed, you’re more
than halfway done. Now draw the layout of nmos using pen and paper and label its various
rectangles. To be able to select the individual rectangles of the nmos, right click the nmos,
select Hierarchy > Flatten, check all checkboxes and click OK. The layout doesn’t have to
be exactly to scale, but enclosures, overlapping and butting should be understandable.
15. Compare the top-down view of the inverter's layout (this is the layout you just made in
virtuoso) with the various regions in the cross-sectional view of inverter given in chapter 1
of your textbook (no need to write down this comparison, but you should be able to relate
the two diagrams).
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Lab 4a – TCL Introduction

TCL is a scripting language that has traditionally been used in VLSI design for decades. Though
some of the scripting has been shifted to python, many commercial tools still use TCL. Although
most commands of the VLSI tools are tool-specific and the knowledge of their usage has little to
do with TCL, you still need to know the basics of TCL syntax. The TCL tutorial will cover the
following use cases:

1. Set and print variable values, and perform computation.

2. If-then-else statement, and for and while loops
3. Creating and indexing lists
4. File IO
5. Accessing shell environment variables

There should only be a single student using each computer for TCL practice.
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Lab 4b – Synthesis in Genus

Introduction

The material below borrows from copyrighted Cadence Documents, and thus, is not to be
distributed.
The tool used for synthesis (converting RTL to a gate-level netlist) is Genus TM Synthesis Solution
(Genus) in Stylus Common UI mode. The necessary inputs to perform synthesis are RTL,
standard cell library and constraints. The outputs of synthesis are the gate-level netlist and
detailed SDC (Synopsys Design Constraints); these are, in turn, the inputs of the placement and
routing step. An optional output of synthesis is the SDF (standard delay format) file, which helps in
performing gate-level simulation.

Basic Commands

The description of various commands in a basic synthesis flow is given below. First, read the next
2 pages, then continue with the instructions on the third page.

1. To set the search path for libraries, enter:

set_db init_lib_search_path <library path>
This command will set the path for the standard cell library.

2. To set the search path for HDL/RTL, enter:

set_db init_hdl_search_path <rtl path>
This command will set the path for rtl files.

3. To load the libraries, enter:

read_libs <library name>
This command will read the specified standard cell library from the specified library path.

4. To read the design, enter:

read_hdl <rtl design>
This command will read the rtl design.

Note:
If the design consists of multiple files, you can use curly braces “{ }” to mention all of
these files. e.g.,
read_hdl {top.v sub1.v sub2.v}

5. Elaborate the design:

elaborate
The elaborate command constructs design hierarchy and connects the signals.

6. To read the constraints, enter:

read_sdc <sdc file name with path>
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This command reads in the timing constraints file. Using SDC, we define clock period,
pulse width, rise and fall times, uncertainty and also input and output delays for different
signals. The basic commands used in the SDC file for this purpose include:
create_clock -name -period 10 -waveform {0 5} {get_port “clk”}
This command will define a clock with period 10ns and 50% duty cycle and the
signal is high in the first half.
set_clock_transition -rise/fall
This command defines the transition delay for the clock.
set_clock_uncertainty
This command will set the uncertainty (due to clock skew and jitter).
set_input/output_delay
This command will specify the input and output delays used for timing slack
calculations.

7. To run the synthesis, enter:

set_db syn_generic_effort <effort level>
set_db syn_map_effort <effort level>
set_db syn_opt_effort <effort level>
syn_generic
syn_map
syn_opt
These commands will perform synthesis by combining the generic, mapped and
optimization synthesis and the attributes syn_generic_effort, syn_map_effort and
syn_opt_effort specify the synthesis effort. The effort can be set to “low”, “medium” or
“high” depending on the scenario.

8. Finally, the following commands can be used to generate the gate-level netlist, detailed
SDC constraints and the SDF file:
write_netlist > netlist.v
write_sdc > sdc_cons.sdc
write_sdf -timescale ns > [Link]
The redirection “>” operator writes the output of a shell command to a file (this operator is
not specific to Genus).
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Synthesis of RISC-V Processor in Genus

The Verilog code for a simple RISC-V processor is provided in the file

/mnt/Cadence/0_Trainings_Labs_Documents/VLSI_lab_manuals/lab4_riscv_code/riscv.v

You have to synthesize it using Genus. Note down the answers to the red questions using pen and
paper.

1. Open a terminal. Create a new folder /home/student/Documents/riscv_practice by running

command mkdir /home/student/Documents/riscv_practice and change your work
directory to it by running command “cd /home/student/Documents/riscv_practice”.
Confirm your work directory with "pwd”.

Useful terminal shortcut: Pressing TAB after typing a few letters in the terminal asks the
shell to auto-complete the word, to the best of the knowledge of the shell. Try it while typing
the command cd /home/student/Documents/riscv_practice by hand; after typing cd /ho,
press TAB; it should auto-complete to cd /home/. You can auto-complete student/ similarly.
After typing the D of Documents, press TAB once; nothing will happen. Press TAB again to
see auto-complete options (if there are multiple possible completions, pressing TAB once
does not auto-complete; in this case, TAB has to be pressed twice to see possible options
for auto-complete). Type o and press TAB to auto-complete it to Documents/. This shortcut
works in Genus shell as well, and it is not limited to paths; this shortcut also works for
command names and command options etc., to the extent of the knowledge of the shell.

2. From the folder /mnt/Cadence/counter_design_database_45nm, copy the folders

constraints, lib, rtl and synthesis to the folder /home/student/Documents/riscv_practice.
Run ls to confirm that your riscv_practice folder has these four folders in it: constraints, lib,
rtl and synthesis.
3. Copy the file riscv.v to your rtl folder; you can do this using command

cp \
/mnt/Cadence/0_Trainings_Labs_Documents/VLSI_lab_manuals/lab4_riscv_code/ris
cv.v \
rtl/riscv.v

Delete the file counter.v using command “gio trash rtl/counter.v”. Run ls rtl to make sure
that the file riscv.v is in the folder rtl.

4. Read the code in riscv.v; you will have to use the names of the inputs and outputs of the
module RISCVCPU.
5. Run command gedit constraints/constraints_top.sdc to open the constraints file
contraints_top.sdc. You have to change the set_input_delay and set_output_delay
commands; replace “rst” with “Instr DMem_in” and replace “count” with “DMem_out
DMem_addr IMem_addr”. Why was this change made?
6. cd to synthesis folder. Open the file genus_script.tcl and replace all occurrences of the
word counter with the word riscv. At the end of the file, add the following lines:

report_timing > riscv_timing_report

report_power > riscv_power_report
report_qor > riscv_qor_report
gui_show
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7. Maximize the terminal window and run command “genus” and wait a few minutes for the
Genus shell to launch. Once you see the command prompt, run command gui_show to
open the Genus GUI.
8. Run the commands in the script genus_script.tcl in the Genus terminal one by one,
observing the output of each command. The commands for synthesis (starting with syn_)
have large outputs. In these outputs, focus on the summary tables. In these tables, the
INFO and WARNING messages are summarized; read these tables.
9. Exit Genus by entering command “exit”; the command prompt will change from the genus
prompt to the bash prompt.
10. Display contents of file riscv_timing_report using command “cat riscv_timing_report” and
read this report. Which two registers is the critical path between? (see Startpoint and
Endpoint).
11. Read the report riscv_power_report. Note total power consumed (it is the 2nd last value in
the “Total” column, the last being the percentage).
12. Read the report riscv_qor_report. Use the Critical Path Slack to determine the upper bound
of the clock frequency for your synthesized module (upper bound means, your chip cannot
possibly operate at a clock frequency higher than the upper bound) (Hints: the units of
slack are ps; subtract slack from time period of clock and reciprocate the result).
13. Rename the files riscv_timing_report, riscv_power_report and riscv_qor_report to
riscv_timing_report.old, riscv_power_report.old and riscv_qor_report.old respectively. You
can do this using the following commands:

mv riscv_timing_report riscv_timing_report.old
mv riscv_power_report riscv_power_report.old
mv riscv_qor_report riscv_qor_report.old

14. Modify the RTL code in riscv.v by adding the line

1: EXMEMALUOut <= Ain * Bin; // mul operation

below the line

0: EXMEMALUOut <= Ain + Bin; // add operation

Doing so adds the multiply R-type instruction, with wrong opcode, to the processor
(previously, the only R-type instruction was add). The opcode of multiply does not matter
much here, as you are not simulating this design; rather, you are changing the design only
to see the effects on the timing, power and area.

15. Run the TCL script of genus, using the command “genus -f genus_script.tcl”. If there are
any errors, Genus will terminate at the error. If there are no errors, Genus will remain open
and the last command, gui_show, will open the GUI of Genus. Once the script’s execution
has finished without any error, run the exit command to exit Genus. This run has generated
the timing, power and qor reports for the modified processor.
a. Which two registers is the critical path between now?
b. Calculate percentage increase in total power. Use formula (new - old)/old*100%.
The units of power are W; note it in mW for readability.
c. Calculate percentage increase in total area. Use formula (new - old)/old*100%. The
units of area are µm2.
d. Calculate the new upper bound on clock frequency.

Note: The timing, power and area reports at this stage are not completely
physical-aware i.e. since placement and routing has not been done yet, the delays
introduced by distances between cells after placement and routing, as well as the
additional area consumed by placement and routing, are not included in the reports you’ve
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generated from Genus in this lab. It is possible to generate such reports again after
placement and routing, and that will be done later using Innovus.

16. Comment the following line in the riscv.v code:

1: EXMEMALUOut <= Ain * Bin; // mul operation

17. Run “genus -f genus_script.tcl”. Once it completes, use the following command to see
summary of the gates used in the design:

report_gates

What is the total instance count?

18. In the latest log file in the synthesis folder, search for “cost group”. At each occurrence, a
target slack for Cost Group ‘clk’ should be mentioned. First, in the output of command
syn_generic, there should be an initial value of target slack, and later, in output of
command syn_map, the target is mentioned again, multiple times. Under Global mapping
status, note the values of Target and Slack (Target is the target that the tool will try to
achieve through optimizations; Slack is the actual slack that has been achieved). Next,
under Global incremental optimization status, note the new values of Target and Slack.
Keep searching for “cost group” and note values of Target and Slack every time they have
changed.
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Lab 5 – Innovus: Floorplan Design and Layout for

RISC-V Processor
The material below borrows from copyrighted Cadence documents, and thus, is not to be
distributed.

For the RISC-V processor’s module you worked on in lab 4, following are the instructions for
continuing work on the synthesized netlist in Innovus, for placement and routing:

1. cd to directory /home/student/Documents/riscv_practice (this should be the folder you

worked in, in the previous lab; if it is not, copy it to this location). Create directory
physical_design using command mkdir physical_design and cd to it. Run pwd to confirm
that your current directory is /home/student/Documents/riscv_practice/physical_design.
2. From the folder /mnt/Cadence/counter_design_database_45nm, copy the folders captable,
lef and QRC_Tech to the folder /home/student/Documents/riscv_practice. You can do this
using the following commands:

cp -r /mnt/Cadence/counter_design_database_45nm/captable .
cp -r /mnt/Cadence/counter_design_database_45nm/lef .
cp -r /mnt/Cadence/counter_design_database_45nm/QRC_Tech .

3. Run command innovus -stylus to open Innovus; wait for its GUI to open. Remember NOT
to exit Innovus, from GUI or from terminal, until you’ve saved your work.

Importing the Design

4. Select File > Import Design. The Design Import form appears. Fill it as shown below. You
can select the lef files using the browse button, but remember to Add the [Link] file
before the [Link] file. To obtain the .view file, switch to terminal, press CTRL + SHIFT +
N to open new terminal window and run command:

cp /mnt/Cadence/counter_design_database_45nm/physical_design/[Link]
[Link]

Also, in file [Link], replace “counter_sdc.sdc” with “../synthesis/riscv_sdc.sdc”.

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5. Keep the terminal window of Innovus in front of you and press OK in the Design Import
form. Note that this action in the Innovus GUI has executed commands in the Innovus
terminal.
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Note: Later actions in the GUI will also execute commands in the terminal. You do not
need to memorize these commands, but you should be able to tell which commands in the
terminal were executed by which action in GUI.

6. View the contents of the [Link] file. It sets up corners and modes by setting up pointers
to the timing libraries (.lib files) and constraints files (.sdc files).

7. In Innovus GUI, after design import, select the Floorplan view .

8. Fit the design to the window by pressing the f key.
9. Zoom out by pressing Shift + Z or by clicking the Zoom Out icon. You can also zoom in and
out using the mouse wheel.
10. Move your cursor over the icons and notice that their functions are displayed in text boxes,
as shown here.

11. To zoom to a particular area, press and drag the right mouse button over a rectangular
area. The window zooms to that area.
12. To view the hierarchical design that you imported, choose Tools > Design Browser. To
expand the modules, click the plus sign ( + ) next to the categories of design objects.

Note: Some pictures are from a smaller design called counter; you’ll see bigger figures for
the RISCV processor design.

13. To view the I/O terminals, click the Terms’ plus sign (+). When you are finished, close the
Design Browser window.

Floorplanning the Design

14. Choose Floorplan > Specify Floorplan. The Specify Floorplan form appears.
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15. For Aspect Ratio, enter 1.

16. Select Core to Die Boundary.
17. Enter 2.5 for the Core to Left, Core to Right, Core to Top and Core to Bottom values.

Note: To display more information about the options, in the Specify Floorplan form, click
Help.

18. To initialize the floorplan, click OK.

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19. To measure the distance between the core area and the I/O boundary, click the Ruler icon
or press k.

20. To delete the ruler, click the Clear All ruler icon or press Shift + K.

Power Planning

21. Choose Power > Power Planning > Add Ring.

Note: The Add Rings form is displayed. There are 11 metal layers available for routing in
the horizontal and vertical directions, and you will be selecting some of them for creating
rings in subsequent steps.

22. To select the VDD and VSS nets, click the folder icon in the Net(s) field. The Net
Selection form is displayed.
23. In the Possible Nets pane, select VDD and VSS, then click Add. The selected nets appear
in the Chosen Nets pane. Click OK.
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24. Fill the Add Rings form as shown above, then click OK.
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25. Choose Power > Power Planning > Add Stripe. The Add Stripes form appears. Fill it as
shown below.

26. Click OK. Notice the power stripes and the vias connecting the rings to the stripes are
created.
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27. Save the floorplan by selecting File > Save > Floorplan. Specify [Link] for the File Name.

Creating Power Rails with Special Route

28. Before creating followpin routing (also known as power rails), associate the global VDD
and VSS nets’ names to the standard cell pin names by entering the following commands:

connect_global_net VDD -type pg_pin -pin VDD -inst_base_name *

connect_global_net VSS -type pg_pin -pin VSS -inst_base_name *

29. Choose Route > Special Route. The SRoute form appears. Fill it as shown below, then
click OK.
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30. In the Physical view, zoom in to the followpin routes.

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Notice that the power routes have been connected to the power planned targets with
relevant vias.

Note: For the steps you’ve carried out in GUI, approximately equivalent commands are
given in the script
/mnt/Cadence/0_Trainings_Labs_Documents/VLSI_lab_manuals/lab5_riscv_code/\
innovus_script.tcl. You can copy this file to the physical_design directory and run it using
command innovus -stylus -files innovus_script.tcl to reproduce your work later.

Running Placement Optimization

31. Run the command “place_opt_design”.

32. The place_opt_design command should’ve placed the cells, but in this case, there is an
error about some instances requiring rows with SITE ‘CoreDoubleSite’. To create these
rows, select Floorplan > Row > Create Core Row… Fill this dialogue box as shown below:
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33. Click Ok and run place_opt_design command again.

The command takes a few minutes to finish. After placement, post-placement setup
optimization is run if the slack is negative. During the optimization stage of the command,
the following operations may be performed to close timing:

a. Adding buffers
b. Resizing gates
c. Reconstructing the circuit
d. Remapping the logic
e. Swapping the pins
f. Deleting the buffers
g. Moving the instances

Note: Notice that the status of the design on the lower-right corner has changed.

34. After the placement run completes, what is the status of the design that is displayed?

Answer: _____________________

The status field is a convenient way to check where you are in the flow. The timing
summary is output to the log file, which contains the Total Negative Slack (TNS) and the
Worst Negative Slack (WNS).

35. What is the Worst Negative Slack (WNS) at this stage?

Answer: ____________________
0.43

Is it a positive or a negative number?

Answer: ____________________
Positive

36. To display the Physical view, click the Physical View button .
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You will see the standard cell placements. Notice that in addition to cell placement, Trial
Route has been run on the design.

37. To save the design, enter “write_db placeOpt” (you can load it later by running read_db
placeOpt).

After running placement or pre-CTS optimization, you run clock tree synthesis with
constraints on what buffers to use and the type of clock routing to implement.

Fun Fact: You can view the layout in 3D by using the Layout 3D button. Click
on the arrow and select Select Area By Mouse… Click and drag the mouse pointer to
select a square around the center area of the design. A small window will appear, showing
the design’s 3D view.
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Running Clock Tree Synthesis

38. Generate the clock tree spec file constraints from the .sdc file by running
“create_clock_tree_spec”.
39. Create a clock tree by running “ccopt_design”. You will see an error message about the
clock net being not completely routed. Ignore this error as later on, when you run the
NanoRouteTM tool for the remaining nets, this error will be fixed.
40. View the .log file for this session. Were there any timing violations after ccopt_design?

No
Answer: __________________________

41. Save your design as postCTSopt by running “write_db postCTSopt”.

Routing the Nets

42. To route the nets, choose Route > NanoRoute > Route. The NanoRoute form is displayed.
Fill it as shown below, then click OK.
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Extraction and Timing Analysis

43. Run RC extraction on the routed design by selecting Timing > Extract RC. Unselect all
options except Save SPEF to. In the field next to it, enter “[Link]”, then click OK.
44. Set the timing analysis mode by running “set_db timing_analysis_type ocv”.
45. Run setup-and-hold timing analysis by running the following commands:

time_design -post_route
time_design -post_route -hold

46. Are there any setup violations?

Answer: _________________

Running Physical Verification

Verifying Geometry

47. Choose Check > Check DRC. The Verify Geometry form is displayed. Click OK.
48. Are there any violations?
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Answer: _________________

Verifying Connectivity

49. Choose Check > Check Connectivity. The Verify Connectivity form is displayed. Click OK.
50. Are there any violations?

Answer: _________________

51. Close innovus by entering command exit at innovus terminal.

52. Copy the folder
/mnt/Cadence/0_0_Trainings_Labs_Documents/riscv_test/riscv_with_scan_chains/
to your /home/student/Documents folder using command

cp -r
/mnt/Cadence/0_Trainings_Labs_Documents/riscv_test/riscv_with_scan_chains/ \
/home/student/Documents/riscv_with_scan_chains

53. cd to its physical_design folder i.e. run command cd

/home/student/Documents/riscv_with_scan_chains/physical_design and run innovus
script innovus_script.tcl using command

innovus -stylus -files innovus_script.tcl

54. You can open the script in sublime text using command “subl innovus_script.tcl”.
55. You must familiarize yourself with the commands in the script innovus_script.tcl; you
should know what each command, and each flag of each command, does, and why. You
can open help about any command in the terminal using the man command e.g.

man set_db

But you may be more comfortable with GUI help files; for this purpose, you can go to Help
menu of Innovus and search using command name and/or command flag. You may also
search using the statement of an action to find out about relevant commands.

56. After going through the script, play with the layers (e.g. Metal1, Metal2, …, Metal11)
selected for routing various parts of the design. You can see that selecting different ranges
of layers has an effect on the number of DRC errors shown in GUI (the crosses are the
DRC errors; you can zoom in at the location of the cross and click on the cross; this will
display the reason for the DRC error in the status bar at the bottom). Also play with other
commands; manually execute them one at a time if necessary, to help understand the
change caused by each command in the design (shown in GUI). You can be asked
questions like “What will happen if this parameter is changed to this value?” in viva, so
make sure to play with them thoroughly. Don’t try to read complete output of optimization
commands because it is too large; instead, search for “ERROR” and “WARN” to see the
error and warning messages. The suspend command pauses execution of script; use
resume command to resume it.
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Lab 6 - Genus PPA Trade-Offs

The material below borrows from copyrighted Cadence documents, and thus, is not to be
distributed.

1. If you have the folder riscv_with_scan_chains that you created in the previous lab, go to
the next step; otherwise, create a copy of:
/mnt/Cadence/0_Trainings_Labs_Documents/riscv_test/riscv_with_scan_chains in
/home/student/Documents. You can do so using command

cp -r \
/mnt/Cadence/0_Trainings_Labs_Documents/riscv_test/riscv_with_scan_chains \
/home/student/Documents/riscv_with_scan_chains

2. In riscv_with_scan_chains, go to directory synthesis. Open genus_script.tcl using

command “subl genus_script.tcl”. Change genus_script.tcl to store reports in files
riscv_timing_report_run1, riscv_power_report_run1 and riscv_qor_report_run1. Also
change name of netlist to run1_riscv_netlist.v.
3. Run command genus -f genus_script.tcl. This script has some additional commands as
compared to the script from lab 4; these commands are relevant to DFT (Design For
Testability).
4. Make a table in which you will note critical path slack, area and power after running script
for different parameters. Make 5 columns in the table, Effort, Clock Period, Critical Path
Slack, Area, Power. Note down these five things for the synthesis run performed just now.
The units of power, for the values displayed by Genus, are watts. In your table, note power
in mW for readability.
5. For the second synthesis run, change run1 to run2 in genus_script.tcl. Open the
constraints_top.sdc file (you can do so using command gedit
../constraints/constraints_top.sdc). Modify the first line to have clock with time period
4ns, with 50% duty cycle.
6. Run genus_script.tcl again. Note the results of this synthesis run in the aforementioned
table. Observe how critical path has changed from run1 to run2.
7. Answer in pen & paper work, Has run2 achieved non-negative slack?
8. For third synthesis run, change run2 to run3. Change clock period to 2ns, with 50% duty
cycle. Run genus_script.tcl again, and note results in table.
9. Has run3 achieved non-negative slack? (non-negative slack is necessary because if slack
is negative, there would be setup time violations and our chip wouldn’t run at the clock
frequency we specified in SDC constraints). If non-negative slack has not been achieved,
what useful conclusion can we infer from whatever value of slack has been achieved?
10. Compare the results of run2 and run3; how has the attempt to achieve better slack affected
area and power?
11. Let’s squeeze the lemon even harder: For the fourth synthesis run, change effort levels in
genus_script.tcl from medium to high, and change run3 to run4. Run genus_script.tcl
again; this will take a long time (15~20 minutes). When it’s done, note results in table.
12. Compare the results of run3 and run4; how has the attempt to achieve even better slack
than run3 affected area and power?
13. From the results of run4, what is the minimum time period and the maximum frequency
achievable?
14. Compare critical paths of run1, run2, run3 and run4; particularly, the two columns named
Timing Point and Cells. Comment on the differences among the critical paths of the various
runs.
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Lab 7: Innovus - OA Library Format, DRC & Timing

Analysis
Timing violations discussion.

1. Run the following commands:

cp -r \
/mnt/Cadence/0_Trainings_Labs_Documents/riscv_test/riscv_with_scan_chains_v2 \
/home/student/Documents/riscv_with_scan_chains_v2
cd /home/student/Documents/riscv_with_scan_chains_v2/physical_design

2. To include formats of libraries instead of lef files, open a new terminal using CTRL + SHIFT
+ N and look for files with name [Link] in the folder /mnt/Cadence/PDK using the following
command:

find /mnt/Cadence/PDK -name [Link]

3. Look at the first result. It should be the path of the [Link] file in “gpdk045_v_6_0”. To
include this in innovus, create a file [Link] in physical_design. To add aforementioned path
to the [Link] programmatically, run grep on the output of above command to get the line
with gpdk in it as follows:

find /mnt/Cadence/PDK -name [Link] | grep gpdk

Note: Redirection operator ‘|’ uses output of one command as input of another command
i.e. redirects output to the second command instead of terminal.

4. Store this path in a bash variable using command:

gpdk_oa_path=$(find /mnt/Cadence/PDK -name [Link] | grep gpdk)

You can print the variable to confirm its value:

echo ${gpdk_oa_path}

5. Write a line to a new file “[Link]” using command:

echo INCLUDE ${gpdk_oa_path} > [Link]

6. Add a line to the existing file [Link] for library “gsclib045_all_v4.4/[Link]” using command:

echo INCLUDE $(find /mnt/Cadence/PDK -name [Link] | grep \

gsclib045_all_v4.4/[Link]) >> [Link]

Note: Redirection operator ‘>>’ writes output of a command to a file. Double greater-than
sign ‘>>’ appends to existing file, and creates a new file if it does not exist. Single
greater-than sign ‘>’ always creates a new file i.e. if file exists, it will be overwritten.

7. Rerun previous command after changing it to search for “giolib” using the grep command,
i.e. grep giolib, then run cat [Link] to confirm that the contents of [Link] are:
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8. Open innovus_script.tcl using command:

subl innovus_script.tcl

9. Comment the read_physical -lef command and insert following line below it:

read_physical -oa_ref_libs {gsclib045 giolib045} -oa_tech_lib {gsclib045_tech}

Also man read_physical to understand the meaning of the above command and its flags.

10. Run innovus_script.tcl.

11. After the script’s execution is finished, run DRC by selecting in GUI Check > Check DRC….
and clicking OK in the Verify DRC dialogue box. Note the commands executed by this
dialogue box in innovus terminal and add them to innovus_script.tcl.
12. There are many DRC violations. Zoom in on any cross in the GUI and click on it to see the
description of the selected violation in the status bar at the bottom. Write down the
descriptions of any two DRC violations.
13. Change the check_drc command to store its output in a file drc_report. Man check_drc to
see how.
14. Now add stripes to layer Metal10 instead of Metal1 and run innovus_script.tcl again; there
should be no DRC violations.
15. Run timing analysis by using commands:

set_db timing_analysis_type ocv

time_design -post_route

It should show that there are no setup time violations.

16. Run timing analysis for hold time conditions using command:

time_design -post_route -hold

You will see that there are 1291 hold time violations.

17. To debug hold timing violations, select Timing > Debug Timing…, select Check Type hold
instead of setup and click OK. Timing Debug window opens.
18. In Path List, click on the Slack column’s header to sort paths in ascending order by slack.
You can see that the Startpoint Pin for most of the violations is SE (scan enable input).
19. In Path List, click on the second arrow icon at the end of the Page list to go the last page.
Double-click on the first path in this page. Study the Slack Calculation. In the Delay Bar at
the bottom, clicking on each part of the bar highlights the corresponding cell in the Data
Delay. See how each cell, net, wire etc. causes a delay.
20. Click on Launch Clock. It displays information about the clock of the launching register i.e.
the register whose output is the starting point of this path. Note the delay caused by wire
length and clock buffer.
21. Similarly, Capture Clock displays information about the clock of the capturing register i.e.
the register whose input is the ending point of this path.
22. Schematic shows the schematic of the selected path.
23. Close Timing Path Analyzer. Go back to the first page in Path List and double-click on the
first path. Note Type, Slack, Start and End.
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24. In Data Path, right-click on SE and select Interactive ECO/Whatif > Add Repeater. The
Interactive ECO dialogue box appears.
25. Next to the Net field, click Get Selected to automatically fill the field with SE. Click on the
New Cells drop-down menu and check BUFX20. Click Apply. Once execution in terminal is
complete, close Interactive ECO and Timing Path Analyzer.
26. In Timing Debug window, click on the folder button next to the Reports : field, select hold
instead of setup and click OK. Once execution is finished, double-click on the first path in
the Path List. Click on Schematic; see that a BUFX20 cell has been inserted but delay is
still 0 (negligibly small).
27. Add 3 BUFX20 cells (click Apply thrice) and generate report again. Now the hold time
violations due to the SE input should have been resolved. The commands for inserting
these ECO cells can be seen from the terminal and added to script to be done
automatically, but don’t add these commands for the SE pin. Instead, have innovus fix it
automatically during placement and routing by creating the pin for the SE input. For this
purpose, insert the following command after the create_physical_pin command of clk pin in
innovus_script.tcl:

create_physical_pin -name SE -layer Metal1 -net SE -rect {6.5 0.2 7.5 1.2}

Also add the following two commands after the route_design -global_detail command:

set_db timing_analysis_type ocv

opt_design -post_route -hold

28. Run innovus_script.tcl again. Now the hold time violations due to the SE input should have
been fixed automatically. For the second path in Path List (first path with Startpoint Pin SE),
open and draw the schematic. Which buffer cells has innovus automatically inserted?
29. Similarly, create a pin for the scan_in input to have innovus fix the hold time violation(s) due
to this pin automatically.
30. Add following command below init_design:

create_basic_path_groups -expanded

Run innovus_script.tcl again and see the tables of setup and hold time analyses again.
What has changed?
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Lab 8: Innovus - IO File, Connectivity, Power Analysis,

GDS
The material below borrows from copyrighted Cadence documents, and thus, is not to be
distributed.

31. Run following commands to copy folder riscv_with_scan_chains_v3:

cp -r \
/mnt/Cadence/0_Trainings_Labs_Documents/riscv_test/riscv_with_scan_chains_v3 \
/home/student/Documents/riscv_with_scan_chains_v3
cd /home/student/Documents/riscv_with_scan_chains_v3/physical_design

32. Open innovus_script.tcl using command

subl innovus_script.tcl

33. Run innovus_script.tcl using command

innovus -stylus -files innovus_script.tcl

34. Once the script has finished execution, select Check > Check Connectivity… and click OK.
Write down the first of the warnings displayed by the connectivity check.

35. Select File > Save > I/O File… In the Save IO File dialog box, check Generate template IO
File and click OK. Note the name of the IO file. Also note the corresponding command in
terminal.

36. Determine the command to read IO file (by now, you should know how to look for
commands in Innovus) and add it in the script innovus_script.tcl at appropriate location. In
innovus_script.tcl, which location have you placed the command at, and why at this
location?

37. Exit innovus, and run innovus_script.tcl again. After the script has finished execution, check
connectivity again; this time, by running its command in the terminal. Are there any errors
or warnings?

Running Power Analysis

38. To display the power analysis setup form, choose Power > Power Analysis > Setup. Fill the
Set Power Analysis Mode form as shown below, then click OK.
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39. Run the following commands to complete global net power connections:

connect_global_net VDD -type pg_pin -pin VDD -inst *

connect_global_net VSS -type pg_pin -pin VSS -inst *
connect_global_net VDD -type tie_hi
connect_global_net VSS -type tie_lo
connect_global_net VDD -type tie_hi -pin VDD -inst *
connect_global_net VSS -type tie_lo -pin VSS -inst *

40. To run power analysis, select Power > Power Analysis > Run. Fill the Run Power Analysis
form as shown below, then click OK. This will run power analysis and generate power
consumption values.
 75

41. Open the report file run1/[Link] and answer the following questions:
a. What is the total internal power and its percentage to total power?
b. What is the total switching power and its percentage to total power?
c. What is the leakage power and its percentage to total power?
d. What is the total power consumed?
e. What is the total capacitance? Why does it matter?
f. What is the power density of our design? (Hint: Find out the die area first!)
42. To run rail analysis, first, select Power > Rail Analysis > Setup. This will bring up the Set
Rail Analysis Mode form. Fill the form as shown below, then click OK.
 76

43. Select Power Analysis > Rail Analysis > Run. This will bring up the Run Rail Analysis form.
44. Out of the five sections in this form, fill the first two (i.e. the part above Power Pads) as
shown below:
 77

45. Now you have to create an XY file which will contain the x and y coordinates of the power
rails. In front of Power Pads, select the XY File radio button, then click the Create button.
This will bring up the Edit Pad Location form.
 78

46. Enter VDD for Net Name.

47. Make sure Auto Fetch radio button is selected.
48. In the Pad Location section, click the Get Coord button.
49. Switch to the main Innovus design window. The mouse pointer will change into a crosshair.
Now click on the yellow VDD rail at the left or right side of the die; the coordinates of the
clicked location will appear in the Pad Location section of the Edit Pad Location form.
50. Go back to the Edit Pad Location form and change the Layer, next to the coordinates, to
Metal10 (because you clicked on the part of the rails in the Metal10 layer).
51. Click Add. Notice that the Pad Location List field is populated with the coordinate as
VDDvsrc1.
52. Add another location for a VDD source.
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53. Click Save.

54. Enter [Link] for file name.
55. Click Cancel to close the Edit Pad Location form.
56. In the Run Rail Analysis form, under Power Pads, specify the name of the XY file you just
created, i.e. [Link], in the File field.
57. Enter VDD for the Net Name.
58. Click Add so that the pane under the fields is populated with the type of file, net name and
file name.
59. Enter ./run1 for the Results directory.
60. Click OK to run rail analysis.

Viewing Power Analysis Results

61. To display the results of rail analysis, select Power > Report > Power Rail Result.
62. Double-click the icon shown below to bring up the Power Rail Plot:

63. Notice that the pane on the left of the design window contains options to display the
results.
 80

64. Click Rail, then click DB Setup. This will bring up the Power & Rail Setup form.
 81

65. In Power Database, enter “run1/[Link]”.

66. In the Rail Database field, enter the path to the directory

run1/VDD_25C_avg_<#>

where <#> indicates a number that increments every time you rerun the step. For example,
this directory name might be run1/VDD_25C_avg_1.

67. Select ir – IR Drop from the dropdown list.

 82

Note: Notice that the Innovus design display window shows color-coded voltage ranges
that match the heat map ( shown on the left side.

Are there any red areas displayed in the main Innovus window?

68. What is the lowest voltage provided to any cell in the entire chip? (Hint: search for “IR Drop
(Limit) Report” in the log file).
69. Looking at the color plot, tell which color denotes the largest voltage drop? Which general
location in the chip has the largest voltage drop and why?
70. Enter the following command to save the Innovus database:

write_db [Link] -lib

Generating a Stream File

71. Select File > Save > GDS/OASIS… This will bring up the GDS/OASIS Export form.
 83

72. Enter riscv in the Output File field and click OK.
 84

Lab 9: Gate-Level Simulation and Conformal

Equivalence Checking
1. Run following commands to copy folder riscv_with_scan_chains_v4:

cp -r \
/mnt/Cadence/0_Trainings_Labs_Documents/riscv_test/riscv_with_scan_chains_v4 \
/home/student/Documents/riscv_with_scan_chains_v4
cd /home/student/Documents/riscv_with_scan_chains_v4

2. In the rtl directory, there is a mem.v file that defines two simple memory modules: one for a
tiny instruction memory and one for a tiny data memory. Both are word-addressable with
word size of 4 bytes i.e. address 1 refers to the second word in memory. Three instructions
have been hard-coded in the instruction memory. The riscv_tb.v file connects the memories
to the CPU and runs these instructions.

3. Go to the simulation directory and run the first command in the makefile by running “make
all”. Note the xrun command run here. The “-mess” flag displays messages in more detail.

4. Now close SimVision, then run command make restore which adds the flag -input
[Link] to the xrun command. This restores a layout that has been previously saved
using the File > Save Command Script… option in SimVision.

5. Press F2 to run simulation. The changes in Regs[1], Regs[2] and DMem[0] are in
accordance with the instructions described in mem.v; you are not required to understand
the instructions themselves. Note that the updates to Regs[1], Regs[2] and DMem[0] occur
1 ns after the clock edge because the #1 delay has been used in riscv.v as well as in
“mem.v”.

6. Close all windows of SimVision. Go to the gate_level_simulation directory. In makefile, note

that riscv.v has been replaced by “riscv_netlist.v”. What is riscv_netlist.v? Also, to perform
gate-level simulation, a verilog file for the used library is required; this has been specified
using the -v flag. Additionally, SDF_TEST has been defined; it is explained later.

7. Open genus_script.tcl. Find the command starting with write_sdf and man it, in genus, to
see and note what the command is doing, including the meanings of its flags.

8. Open the file riscv_tb.v located in the rtl directory. The $sdf_annotate directive has been
used to assign the cell delays to the standard cell instances in “riscv_netlist.v” and this
directive has been placed inside an ifdef block which requires “SDF_TEST” to be defined.
Four arguments have been specified in the $sdf_annotate directive; Write down one
sentence describing each of the four arguments i.e. a total of four sentences; you can refer
to pages 112-113 of RTLtoGDSII_3_0.[Link] for help (this documents is in
0_Trainings_Labs_Documents).

9. Understand the makefile, then run make restore to run the gate-level simulation. The
waveforms are similar to those of RTL simulation. Now the delay in update of value of
Regs[1] to 3, after the clock edge, is not 1 ns; rather, it has been provided by the sdf file.
Zoom in and note this delay, in ps.
 85

10. Close all windows of SimVision. Go to the equivalence_checking directory. Read pages
69-73 of document “RTLtoGDSII_3_0.[Link]”. Run Conformal for equivalence
checking, using the [Link] script, using command

lec -LPGXL -color -64 -dofile [Link]

11. This will open GUI; click “Non-equivalent” in the lower half of the window to see the points
which are different between the RTL model and the gate-level netlist.

12. In synthesis directory, open the last log file for genus and read the “Message Summary”
tables to determine what could be the reasons for the small mismatch (if it does not contain
“Message Summary”, search in the second-last log file). You can search for a relevant
message’s statement in the log file to go to the message’s original location and see further
details. Write one sentence to describe each of the relevant Info/Warn/Error messages.
Hint: There are 3 such messages.

Skywater PDK

Hammer generated mmmc script discussion.

13. Copy the folder /mnt/Cadence/0_Trainings_Labs_Documents/skywater_hammer_riscv to

/home/student/skywater_hammer_riscv.
14. cd to synthesis folder and run “riscv_using_skywater_genus_script.tcl”. It has some
new commands, e.g.

add_tieoffs

15. cd to physical_design folder and run “riscv_using_skywater_innovus_script.tcl”. It has

some new commands, e.g.

add_endcaps
add_welltaps

add_fillers
 86

CEP - Placement & Routing of CPU + SRAMs

The project’s input are the verilog files provided in the folder

/mnt/Cadence/0_Trainings_Labs_Documents/VLSI_lab_manuals/CEP_rtl

You are required to synthesize and place-and-route (PnR) the top module called RISCVTOP,
which should contain one CPU and two SRAM modules. In the files given to you, only one SRAM
of size 2 KB has been employed; you have to use a second SRAM to increase total data memory
size to 4 KB, after running PnR for one SRAM. Start by copying the following folder to Documents:

/mnt/Cadence/0_Trainings_Labs_Documents/VLSI_lab_manuals/skywater_example_for_students

This folder contains an example project that utilizes the skywater 130 nm PDK for synthesis and
PnR of Sermo, an SoC designed by the department’s faculty. You have to modify this project for
simulation, synthesis and PnR of the verilog provided to you in the CEP_rtl folder. Copy the
contents of CEP_rtl to skywater_example_for_students, and then modify the makefile in the
simulation directory to simulate the rtl and run make to run the simulation. Modify the [Link] script
in the synthesis directory and, in the synthesis directory, run the command genus -f [Link] to
synthesize the rtl.

Change the current directory to physical_design and modify the [Link], floorplan_config.tcl and
power_spec.cpf files for PnR of your synthesized netlist, and run innovus -stylus -files [Link] to
perform the PnR.

Now, use a second SRAM to increase data memory size from 2 KB to 4 KB. Change relevant
scripts as required. Enclose the RISCVCPU module in a specified rectangular area. You can do so
using a “fence” (search “fence” in Innovus help and add commands for it to the script). The “fence”
part has 2.5 marks, so you can skip it now and do it later.

Next, change die area to a comfortable value (e.g. twice of the area reported by Genus), and
squeeze time period as much as possible. Multiply the minimum possible time period with 1.2 and
use this value as time period. Make sure there are no violations after PnR, except the 12 violations
per SRAM. You may have to comment the add_fillers command; it can introduce DRC violations.
It’s a must to run add_fillers in the final design, but you may keep it commented while you’re
exploring the design space. Note down the values of time period and the effort levels you used,
and mention them in your report.

After the appropriate time period has been determined, spread pins evenly across the chip border
and make sure there are no violations. Now, decrease die area as much as possible without
violations, and note the die size and macro coordinates used as you decrease the area (macro
refers to the pre-hardened cells such as SRAM). Next, analyse power consumption and maximum
IR drop, and also perform gate-level simulation.

Marks: 50

Synthesis
Correctness (verified by post-syn gate-level simulation) 5
Apt time period 5

PnR
Correctness
CPU in fence 2
 87

Correctness (post-par gate-level simulation) 3

Correctness 2 (No violations, except 12 per SRAM) 5
Apt area 5
Power analysis (including max IR drop) 5

Report 5

Viva (what you did + brief knowledge of scripts’ commands) 15

Bonus: up to 2 marks for implementing hierarchical design.

You can make groups of 3 members max. Project and report are group-wise; viva is individual.
Make and show me the report in lab; you should not take away materials from the lab. Due date is
in first week of exams; exact date will be announced after datesheet is released.

If there are any confusions, besides asking me, you can try searching in Cadence help. If you turn
on the internet, you can search online as well, which gives better results.
 88

References
[Wishbone B4] Cores, Architecture for Portable IP. "Wishbone B4." (2010).

[Cadence Documents]
RTLtoGDSII_3_0.[Link] (copyrighted; not to be distributed)
Virtuoso Inverter (schematic and layout) tutorial - new version