Module 1 : The Intel Microprocessor of 8086
Architecture
• 8086 Architecture
• Programmer’s Model
• Pin Diagram 8086
• Memory Segmentation
• Memory Bank
• Demultiplexing of Address/Data bus in 8086
• Minimum mode & Maximum mode of 8086
• Timing diagram for Read & Write operations for Minimum mode & Maximum
mode.
• Interrupt Structure and its servicing
Block diagram of Computer
System Bus
1. Address Bus
• It carries the address where the operations
to be performed.
• An address bus if 1-bit can give total of two
address: 0 and 1. Hence can access a total
memory of two locations.
• 2-bit address bus can generate a total of 4
address 00,01,10,11 and hence can access a
total of four locations.
• N-bit address can access a total of 2N Bytes.
2. Data Bus
- These lines are used to carry data to and from the processor.
3. Control Bus
- It carries control signals like RD (read) and WR (write).
Salient features of 8086
1. Buses
• Address Bus: 20-bit address bus, 220 byte memory i.e. 1MB, address range 00000H to FFFFFH.
• Data Bus: 16-bit data bus.
• Control Bus: Carries control signals to perform various operations like RD, WR.
2. Pipelining
• Fetching the next instruction, while executing the current instruction.
3. Operating Modes
• Minimum Mode: 8086 is the only processor (Uniprocessor).
• Maximum Mode: 8086 with 8087-Math Co-Processor , 8089-IO Processor.
4. Memory Bank
• 1MB is divided into 2 banks of 512KB each.
• Lower bank (even) and Higher bank (odd).
5. Memory Segmentation
• Means dividing the memory in logical components.
• 4 Segments: Code, Stack, Data, Extra
6. 256 Interrupts
7. 16-bit IO address
• 216 IO ports = 65536 i.e. 64KB IO ports
8086 Architecture
BIU (Bus Interface Unit)
• Segment Register (CS, DS, SS, ES)
• IP Register
• ADC (Address Generation Circuit)
• 6 Byte Pre Fetch Queue
EU (Execution Unit)
• Control Section
• General Purpose Register
(AX, BX, CX, DX)
• ALU
• Offset Register (SP, BP, SI, DI)
• Flag Register
Flag Register of 8086
Flag Register of 8086
• 16-bit flag register.
• 9 flags: 6 status (condition) flags & 3 control flags.
• Status flag are affected by ALU, after every arithmetic or logic operation.
• It gives status of current result.
• Control flag are used to control certain operations.
• They are changed by programmer.
Programmer’s
Model
of 8086
Memory
Segmentation
Memory Banking
Memory Banking
BHE Ao Operation
(Higher/odd) (Lower/even)
0 0 R/W 16-bit from both bank
0 1 R/W 8-bit from higher bank
1 0 R/W 8-bit from lower bank
1 1 No operation
8086 Pin Configuration
Demultiplexing of Address/Data Bus in 8086
Minimum mode
of 8086
DEN’ DT/R’ ACTION
1 X disable
8286
0 0 Receive data
0 1 Transmit data
M/IO’ RD’ WR’ OPERATION
0 0 0 Invalid
0 0 1 I/O read (IOR’)
74138 0 1 0 I/O write (IOW’)
0 1 1 No operation
1 0 0 Invalid
1 0 1 Memory read (MEMR’)
1 1 0 Memory write (MEMW’)
1 1 1 No operation
Maximum mode
of 8086
DEN’ DT/R’ ACTION
0 X Disable
8288
1 0 Receive data
1 1 Transmit data
S2 S1 S0 STATE OPERATION
0 0 0 Interrupt acknowledge INTA’
0 0 1 Read IO port IORC’
0 1 0 Write IO port IOWC’ & AIOWC’
0 1 1 Halt NONE
1 0 0 Instruction Fetch MRDC’
1 0 1 Memory read MRDC’
1 1 0 Memory write MWTC’ & AMWTC’
1 1 1 Inactive NONE
Timing diagram of read & write operations of Minimum
mode
Timing diagram of read & write operations of Maximum
mode
ISR (Interrupt
Service Routine)
IVT (Interrupt
Vector Table)
