Computer Arithmetic
Module 4
Integer Representation
• Variables such as integers can be represent in two ways, i.e., signed and unsigned.
• Signed numbers use sign flag or can be distinguish between negative values and positive
values.
• Whereas unsigned numbers stored only positive numbers but not negative numbers
• When an integer binary number is positive, the sign is represented by 0 and the magnitude
by a positive binary number.
• When the number is negative, the sign is represented by 1 but the rest of the number may
be represented in one of three possible ways:
1. Signed-magnitude representation
2. Signed-1' s complement representation
3. Signed 2' s complement representation
• Sign-Magnitude form:
• For n bit binary number, 1 bit is reserved for sign symbol.
• If the value of sign bit is 0, then the given number will be positive, else if the value of
sign bit is 1, then the given number will be negative.
• Remaining (n-1) bits represent magnitude of the number.
• Since magnitude of number zero (0) is always 0, so there can be two representation of
number zero (0), positive (+0) and negative (-0), which depends on value of sign bit.
• Hence these representations are ambiguous generally because of two representation of
number zero (0). Generally sign bit is a most significant bit (MSB) of representation.
• For example, range of 6 bit Sign-Magnitude form binary number is from -(25 -1) to
(25-1) which is equal from minimum value -31 (i.e., 1 11111) to maximum value +31
(i.e., 0 11111).
• And zero (0) has two representation, -0 (i.e., 1 00000) and +0 (i.e., 0 00000).
• 1’s complement form:
• Since, 1’s complement of a number is obtained by inverting each bit of given
number.
• So, we represent positive numbers in binary form and negative numbers in 1’s
complement form.
• There is extra bit for sign representation. If value of sign bit is 0, then number
is positive and you can directly represent it in simple binary form, but if value
of sign bit 1, then number is negative and you have to take 1’s complement of
given binary number.
• In this representation, zero (0) can have two representation, that’s why 1’s
complement form is also ambiguous form.
• And zero (0) has two representation, -0 (i.e., 1 11111) and +0 (i.e., 0 00000).
• 2’s complement form:
• Since, 2’s complement of a number is obtained by inverting each bit of given
number plus 1 to least significant bit (LSB).
• So, we represent positive numbers in binary form and negative numbers in 2’s
complement form.
• There is extra bit for sign representation. If value of sign bit is 0, then number
is positive and you can directly represent it in simple binary form, but if value
of sign bit 1, then number is negative and you have to take 2’s complement of
given binary number.
• If value of most significant bit (MSB) is 1, then take 2’s complement from,
else not.
• The signed-magnitude representation of a negative number consists of
the magnitude and a negative sign.
• In the other two representations, the negative number is represented in
either the 1's or 2's complement of its positive value.
• As an example, consider the signed number 14 stored in an 8-bit
register.
• +14 is represented by a sign bit of 0 in the leftmost position followed
by the binary equivalent of 14: 00001110.
• -14 is represented by
• In signed-magnitude representation: 1 0001110
• In signed-1's complement representation: 1 1110001
• In signed-2's complement representation: 1 1110010
Addition and Subtraction of Signed Number
Addition and Subtraction of Signed Number
• The carry-out function, ci+1, is implemented with an AND-OR circuit, as
shown.
• A convenient symbol for the complete circuit for a single stage of addition,
called a full adder (FA), is shown in the figure.
• A cascaded connection of n full-adder blocks can be used to add two n-bit
numbers, as shown in Figure.
• Since the carries must propagate, or ripple, through this cascade, the
configuration is called a ripple-carry adder.
• The carry-in, c0, into the least-significant-bit (LSB) position provides a
convenient means of adding 1 to a number.
• For instance, forming the 2’s-complement of a number involves adding 1 to
the 1’s-complement of the number.
Addition/Subtraction Logic Unit
• In order to perform the subtraction operation X −Y, we form the 2’s-
complement of Y and add it to X.
• The logic circuit shown in Figure 9.3 can be used to perform either
addition or subtraction based on the value applied to the Add/Sub
input control line.
• This line is set to 0 for addition, applying Y unchanged to one of the
adder inputs along with a carry-in signal, c0, of 0.
• When the Add/Sub control line is set to 1, the Y number is 1’s-
complemented (that is, bit-complemented) by the XOR gates and c0 is
set to 1 to complete the 2’s-complementation of Y.
Multiplication of Unsigned Numbers
• The product of two, unsigned, n-digit numbers can be accommodated in 2n
digits, so the product of the two 4-bit numbers in this example is
accommodated in 8 bits, as shown.
• In the binary system, multiplication of the multiplicand by one bit of the
multiplier is easy.
• If the multiplier bit is 1, the multiplicand is entered in the appropriate
shifted position.
• If the multiplier bit is 0, then 0s are entered, as in the third row of the
example.
• The product is computed one bit at a time by adding the bit columns from
right to left and propagating carry values between columns.
Array Multiplier
Array Multiplier
Array Multiplier - Example
Sequential Multiplier
• The combinational array multiplier just described uses a large number of
logic gates for multiplying numbers of practical size, such as 32-or 64-bit
numbers.
• Multiplication of two n-bit numbers can also be performed in a sequential
circuit that uses a single n-bit adder.
• The block diagram in Figure 9.7a shows the hardware arrangement for
sequential multiplication.
• This circuit performs multiplication by using a single n-bit adder n times to
implement the spatial addition performed by the n rows of ripple-carry
adders in Figure 9.6b.
• Registers A and Q are shift registers, concatenated as shown.
• Together, they hold partial product PPi while multiplier bit qi generates the
signal Add/Noadd
Multiplication of Signed Numbers
• First, consider the case of a positive multiplier and a negative multiplicand.
• When we add a negative multiplicand to a partial product, we must extend
the sign-bit value of the multiplicand to the left as far as the product will
extend.
• Figure 9.8 shows an example in which a 5-bit signed operand, −13, is the
multiplicand.
• It is multiplied by +11 to get the 10-bit product, −143.
• The sign extension of the multiplicand is shown in blue.
• The hardware discussed earlier can be used for negative multiplicands if it
is augmented to provide for sign extension of the partial products.
Multiplication of Signed Numbers
• For a negative multiplier, a straightforward solution is to form the 2’s-
complement of both the multiplier and the multiplicand and proceed
as in the case of a positive multiplier.
• This is possible because complementation of both operands does not
change the value or the sign of the product.
Multiplication of Signed Numbers
The Booth Algorithm- Multiplying Signed
numbers
Example
Example
