Introduction to Verilog HDL
How it started!
• Developed by Gateway Design Automation Limited in 1983.
•
• Cadence purchased Gateway in 1989.
• Verilog was placed in the public domain.
•Open Verilog International (OVI) was created to develop the
Verilog Language as IEEE standard.
The Verilog Language
• Preferred in the commercial electronics industry
• Now, one of the two most commonly-used languages in
digital hardware design (VHDL is the other)
• Virtually every chip (FPGA, ASIC, etc.) is designed in
part using one of these two languages
• Best for configuring large designs produced by large design teams
Best for describing low-level logic (more concise )
• HW description language competing with VHDL
Standardized:
IEEE 1364-1995 (Verilog version 1.0)
IEEE 1364-2001 (Verilog version 2.0)
• Features similar to VHDL: but Case-Sensitive ( only lower-case
letters)
• Designs described as connected entities
• Bit-vectors and time units are supported
• Features that are different:
• Built-in support for 4-value logic and for logic with 8 strength
levels encoded in two bytes per signal.
• More features for transistor-level descriptions
• Less flexible than VHDL.
• More popular in the US (VHDL common in Europe)
SIMPLE VERILOG PROGRAM
QUICK TUTORIAL OF VERILOG LANGUAGE
• Module is the basic design unit.
• Module describes the functionality or structure of the design
Module declaration
module module_name (list of ports);
// in, out, inout port declarations
// signal/wire/reg declarations
// data variable declarations
// sub-module instantiation and connection
// functional blocks: initial, always, function, task
Endmodule
For Ex :
Within a module, a design can be described in the following
styles
Data-flow style
Behavioral style
Structural style
Any mix of above
An example
Half adder structural model (gate-level)
Half adder data-flow model
Half adder behavioral model
structural model (gate-level)
instantiation of primitives and modules.
Half adder data-flow model
Continuous assignments.
Half adder behavioral model
procedural assignments.
Language elements
A single line comment begins with ‘//’ and ends with a newline.
A block comment begins with ‘/*’ and ends with ‘*/’.
Identifiers
Equivalent to variable names
Identifiers can be up to 1024 characters.
Logic Values and Signal Strengths
The Verilog HDL has 4 logic values:
0 zero, low, false
1 one, high, true
z or Z high impedance, floating
x or X unknown or uninitialized
Nets
Represents a hardware wire
Driven by logic
Value `z’ (high-impedance) when unconnected
Initial value is x (unknown)
Types of nets
‘wire’
Register
Variable that stores value
Can be a register (value holding unit) in real hardware
NOTE: It can be also combinational logic according to the description
Only one type: ‘reg’
Vector and array data type
Vector represents bus
Left number is MS bit
Vector assignment by position
Array is a collection of the same data type
Multi-dimensional array is not supported
Cannot access array subfield or entire array at once
Array for real data type is not supported
a <= 2’x7A; // bit string hex “01111010”
a <= 3’o172; // octal (base 8)
a <= 8’b01111010; // binary
OPERATORS
Logical operators
Result in one bit value
Bitwise operators (infix):
Operation on bit by bit basis
Reduction operators (prefix):
Result in one bit value
Shift operators
Result in the same size, always fills zero
Concatenation operators: {, }
Replication: {n{X}}
Relational operators: >, <, >=, <=
Equality operators: = =, ! =,
Arithmetic operators: +, -, *, /, %
Unary : +, -
Behavioral constructs
Continuous assignment with ‘assign’ keyword.
Inside a module, but outside procedures.
LHS of continuous assignment must be a `net’ type.
‘ timescale 1ns / 1ns
For ex : assign #2 SUM = A ^ B;
#2 refers to 2 time units
SUM must be “net” type
Time Units for #delay
Specify by:
`timescale <time_unit> / <time_precision>
Unit of Abbreviation
Measurement
seconds s
milliseconds ms
microseconds us
nanoseconds ns
picoseconds ps
femtoseconds fs
Example: `timescale 10 ns / 1 ns
// Each time unit is 10 ns, maintained to a precision of 1
ns
‘initial’ block
One-time sequential activity flow from simulation start.
Initial blocks start execution at simulation time zero and finish
when their last statement executes.
LHS of procedural assignment must be a
reg’,`integer’,`real’,`time’ type.
‘always’ block
Cyclic (repetitive) sequential activity flow
Always blocks start execution at simulation time zero and continue
until simulation finishes.
LHS of procedural assignment must be a
reg’,`integer’,`real’,`time’ type.
Events @
When the control meet `Event’, it waits until required event occurs.
2 : 1 mux Example
Write a verilog code for 8 : 1 mux ( in syllabus)
Control Statements
If-else-if
Case
‘(expression) ? statement : statement;’
For Loops
A increasing sequence of values on an output
reg [3:0] i, output;
for ( i = 0 ; i <= 15 ; i = i + 1 ) begin
output = i;
#10;
end
While Loops
A increasing sequence of values on an output
reg [3:0] i, output;
i = 0;
while (I <= 15) begin
output = i;
#10 i = i + 1;
end
T Flip-Flop
module tff_logic (input t, input
clk, output q);
always @(posedge clk)
begin
if (t == 1’b1)
q <= not (q);
else
q <= q;
end
endmodule
8-bit Register, Asynchronous Reset, Synchronous Preset
module reg_logic (input d [0:7], input reset, input init, input
clk, output q [0:7]);
always @(posedge clk, posedge reset)
begin
if (reset == 1’b1)
q <= 8’b0;
else
begin
if (init == 1’b1)
q <= 8’b11111111; // decimal -1
else
q <= d;
end
end
endmodule
Full Adder from Logical Operations
module ADD_FULL_RTL (sum,cout,x,y,cin);
output sum,cout;
input x,y,cin;
//declaration for continuous assignment wire cin,x,y,sum,cout;
//logical assignment
assign sum = x ^ y ^ cin;
assign cout = x & y | x & cin | y & cin;
endmodule
VERILOG CODE FOR 1 BIT FULL ADDER
Some More Gate Level Examples
An adder
instance
instancenames
names
and delays
and delays
module adder optional
optional
(output carryOut, sum ,
input aInput, bInput, carryIn);
sum
xor (sum , aInput, bInput, carryIn);
or (carryOut, ab, bc, ac); ab
and (ab, aInput, bInput), carr yOut
bc
(bc, bInput, carryIn),
ac
(ac, aInput, carryIn);
endmodule
aInput carr yIn
list
listof
ofgate
gateinstances implicit
instances implicitwire
wire bInput
of same function
of same function declarations
declarations
8/20/2 007 Thom as: Digi tal Sy stem s Design 19
Lecture 8
Verilog code for a 8-bit Up counter with
asynchronous clear.
module counter (C, CLR, Q);
input C, CLR;
output [7:0] Q;
reg [7:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 8'b00000000;
else
tmp = tmp + 1'b1;
end
assign Q = tmp;
endmodule
In Conclusion
• Verilog is widely used because it solves a problem
• Good simulation speed that continues to improve
• Designers use a well-behaved subset of the language
• Makes a reasonable specification language for logic
synthesis
• Logic synthesis one of the great design automation
success stories
