FPGA based system

design
Dr.P.Kalpana
Digital design flow
 IC Implementation
Technologies

STANDARD
ASIC
IC

FULL FIELD
SEMI-
PROGRAMMABLE
CUSTOM CUSTOM

STANDARD GATE ARRAY,

FPGA PLD
CELL SEA OF GATES

3
ASIC Design Flow - Traditional

Write Draw Datapath

Specifications Schematics *

Define System Define State Integrate

Architecture Diag/Tables Design*

Partition - Data- Draw Control

Do Physical
path &Control Schematics *
Design*

Implement*

4
HDL/Synthesis Design Flow - 1

Design Verification: Pre-Synthesis

Specification Functional Sign-Off

Design
Integration
Partition Synthesis and

Technology Map

Design Entry:
Verification:
HDL Behavioral To next page
Functional

5
HDL/Synthesis Design Flow - 2

Extract
Test Generation
From prior page Parasitics
& Fault Simulation

Verification:

Post-Synthesis Physical Design

Verification:
Timing Verification:
Physical &
Post-Synthesis
Electrical Design Sign-Off

6
Role of FPGA in digital
design
 FPGA
• It is primarily a semiconductor device that can be configured by the
user (customer or designer) after the manufacturing process has been
completed
• The term "field-programmable" means the device is programmed by
the customer, not the manufacturer.
• Can be programmed using a logic circuit diagram or source code in
VHDL or Verilog
• It offers partial re-configuration of a portion of design
 Benefits of FPGA’s
• Real-time analysis of high-rate data streams
(Performance)
• Deterministic hardware dedicated to every task
(Reliability)
• Nonrecurring engineering expenses
(Reconfigurability )
• Radiation Hardened and Program Integrity.
(Durability)
• Flexible and rapid prototyping
(Development)
 Purpose of FPGAs
• Permits elaborate digital logic designs to be implemented by
the user on a single device.
• Is capable of being erased and reprogrammed with a new
design.
 Advantages of FPGAs

• Cost effective in lower

FPGA volumes
ASIC • Short design time
(Application Specific
Integrated Circuit) • Well suited for academics
Cost

and prototyping

Volume
FPGA/ASIC Crossover Changes

90nm / 300mm ASICs

Cost

/ 2 00m m A SICs
150nm s s
G A G A
FP FP
m m m
30 0
00m /
/2 9 0n m
nm
0
15
FPGA FPGA FPGA
Cost Advantage
Cost Cost Advantage
Advantage ASIC Cost
ASICAdvantage
Cost Advantage

Production Volume
Hierarchical Digital design
Hierarchical design
Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
FPGA design flow
 Standard FPGA Design Flow
• Design Entry
• Synthesis
• Design abstracted as a list of operations and dependencies
• Transformed into state diagrams and then logic networks (netlist)
• Design Implementation
• Translate – merges multiple design files into a single netlist
• Map – groups logical components from netlist into IOBs and CLBs
• Place & Route – place components on the FPGA and connect them
• Device File Programming
• Generates a bitstream containing CLB/IOB configuration and routing information to
be directly loaded onto the FPGA
FPGA Design Flow (Xilinx)
Design Entry

Functional HDL files,

Simulation schematics

Synthesis

EDIF/XNF
netlist

Implementation

Timing NGD Xilinx

Simulation primitives file
Device
Programming
FPGA bitstream
 Design Flow with Test
Design and implement a simple unit permitting to speed
up encryption with RC5-similar cipher with fixed key set
on 8031 microcontroller. Unlike in the experiment 5, this Specification
time your unit has to be able to perform an encryption
algorithm by itself, executing 32 rounds…..

Library IEEE;
use ieee.std_logic_1164.all; VHDL
use ieee.std_logic_unsigned.all; Functional simulation
entity RC5_core is
description
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end RC5_core;

Synthesized Post-synthesis simulation

Circuit
 Implementation
Synthesis

Circuit netlist Timing Constraints

Constraint Editor
Electronic Design Native
Interchange Format Constraint
File
EDIF NCF UCF User Constraint File

Implementation

NGD Native Generic Database file

October 4, 2007 CprE 583 – Reconfigurable Computing

Circuit Netlist and Mapping
LUT0
LUT4

LUT1
FF1
LUT5

LUT2

FF2
LUT3
Placing and Routing FPGA
Programmable Connections

October 4, 2007 CprE 583 – Reconfigurable Computing

Configuration
• Once a design is implemented, you must create a file that the FPGA can
understand
• This file is called a bit stream: a BIT file (.bit extension)

• The BIT file can be downloaded directly to the FPGA, or can be converted
into a PROM file which stores the programming information
FPGA Architecture
 FPGA Architecture
(With Multiplexer As Functionally Complete Cell)
• Basic building block
 Interconnection
Framework

 FPGA
– Fine grained
– Variable length
interconnect segments
– Timing in general is not
predictable; Timing
extracted after placement
and route
 Interconnection
Framework
• CPLD
– Coarse grained
(SPLD like blocks)
– Programmable crossbar
interconnect structure
– Interconnect structure uses
continuous metal lines
– The switch matrix may or may not
be fully populated
– Timing predictable if fully
populated
– Architecture does not scale well
 Field Programmability
• Field programmability is achieved through switches (Transistors
controlled by memory elements or fuses)
• Switches control the following aspects
• Interconnection among wire segments
• Configuration of logic blocks
• Distributed memory elements controlling the switches and
configuration of logic blocks are together called “Configuration
Memory”
 Xilinx FPGAs
 Generic Xilinx Architecture • Symmetric Array based; Array
consists of CLBs with LUTs and D-
Flipflops
• N-input LUTs can implement any
n-input boolean function
• Array embedded within the
periphery of IO blocks
• Array elements interleaved with
routing resources (wire
segments, switch matrix and
single connection points)
• Employs SRAM technology
XC 4000
 3 LUTs and 2 Flip-flops in a
two stage arrangement
 2 Outputs: Can be registered or
combinational
 External signals can also be
registered
 More of internal signals are
available for connections
 Can implement any two
independent functions of four
variables or any single function
of five variables
 XC4000
• XC4000 Routing Architecture
 XC 4000
 XC4000 Routing Architecture
 Wire segments
 Single length lines
 Spans single CLB
 Connects adjacent CLBs
 Used to connect signals that do not have critical timing requirements
 Double length lines
 Spans two CLBs
 Uses half as much switch as a single length connection
 Long lines
 Low skew; Used for signals such as clock
 Relatively rare resource

 Switch Matrix
 Every line is connected to lines on the other three direction
 Each connection requires six transistors
 An Example
• Modulo-4 counter:  Modulo-4 counter: Logic
Specification Implementation
FPGA Implementation of
Modulo-4 Counter
 ALTERA CPLDS
• Hierarchical PLD structure
 Altera generic architecture • First level: LABs (Functional
blocks); LAB is similar to SPLDs
• Second Level: Interconnections
among LABs
• LAB consists of
• Product term array
• Product term distribution
• Macro-cells
• Expander product terms
• Interconnection region: PIA
• EPROM/EEPROM based
• Example: MAX5K, MAX7K
 MAX 5000
 MAX5K Macrocell

• Three wide AND gate feed an OR gate (Sum of products)

• XOR gate may be used in arithmetic operations or in polarity selection
• One flipflop per macrocell; Outputs may be registered
• Flipflop preset and clear are via product terms; Clock may be either system clock or
internally generated
• Output may be driven out or fedback
• Feedback is both local and global; Local feedback is within macrocell and is quicker
 MAX 5000
 MAX5000 Expander Product Term

• Number of product terms to macrocell limited

• Wider functions implemented via expander product terms
• Foldback NAND structure
• Inputs are from PIA, expander product term and macrocell
feedback
• Outputs of expander product term are sent to other macrocell
and to itself
 MAX 5000
 MAX5000 Architecture

• Second level of hierarchy:

connections among LABs
• LABs are connected via PIA
• Interconnections may be
global or local; Global
interconnects uses PIA
• PIA consists of long wiring
segments:
• Spans entire length of chip and
passes adjacent to each LAB
• PIA fully populated
• Predictable timing
The Virtex CLB
Details of One Virtex Slice
 CLB Slice Structure
 Each slice contains two sets of the
following:
◦ Four-input LUT
 Any 4-input logic function,
 or 16-bit x 1 sync RAM (SLICEM only)
 or 16-bit shift register (SLICEM only)
◦ Carry & Control
 Fast arithmetic logic
 Multiplier logic
 Multiplexer logic
◦ Storage element
 Latch or flip-flop
 Set and reset
 True or inverted inputs
 Sync. or async. control
Implements any Two 4-input
Functions

4-input
function

3-input
function;
registered
Implement Some Larger Functions

e.g. 9-input
parity
LUT (Look-Up Table) Functionality
x1
• Look-Up tables
x2
x1 x2 x3 x4 y x3
x4
LUT y
x1 x2 x3 x4 y are primary
0 0 0 0 1 0 0 0 0 0
0 0 0 1 1 0 0 0 1 1 elements for
0 0 1 0 1 0 0 1 0 0
0
0
0
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
logic
0
0
1
1
0
1
1
0
1
1
0
0
1
1
0
1
1
0
1
0 implementation
0 1 1 1 1 0 1 1 1 1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
• Each LUT can
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
0
1
0
0 implement any
1 1 0 0 0 1 1 0 0 1
1
1
1
1
0
1
1
0
0
0 x1 x2 x3 x4
1
1
1
1
0
1
1
0
1
0
function of
1 1 1 1 0 1 1 1 1 0
4 inputs

x1 x2

y
Carry & Control Logic COUT

YB

G4 Y
G3 S
Look-Up Carry D Q
G2 O
Table
G1 &
CK
Control
Logic EC
R
F5IN
BY
SR

XB
X S
F4
F3 Look-Up Carry D Q
F2 Table O
F1 & CK
Control
Logic EC
R

CIN
CLK
CE
SLICE
 Carry & Control Logic in Xilinx FPGAs

x y
COUT
0 0 y x
0 1 y
1 0 CIN

1 1 yCIN

Propagate = x  y
Generate = y
Sum= Propagate  CIN = x  y  CIN
Carry & Control Logic

LUT

Hardwired (fast) logic

Critical Path for an
Adder Implemented Using
Xilinx Spartan 3 FPGAs
Technology of Programmable
Elements
• Vary from vendor to vendor. All share the
common property: Configurable in one of the two
positions – ‘ON’ or ‘OFF’
• Can be classified into three categories:
• SRAM based
• Fuse based
• EPROM/EEPROM/Flash based
• Desired properties:
• Minimum area consumption
• Low on resistance; High off resistance
• Low parasitic capacitance to the attached wire
• Reliability in volume production
Programming Technologies
SRAM Programming
Technology
• Employs SRAM (Static RAM) cells to
control pass transistors and/or
transmission gates
• SRAM cells control the configuration
of logic block as well
• Volatile
• Needs an external storage
• Needs a power-on configuration
mechanism
• In-circuit re-programmable
• Lesser configuration time
• Occupies relatively larger area
Anti-fuse Programming
Technology

• Though implementation differ, all anti-fuse

programming elements share common property
• Uses materials which normally resides in high
impedance state
• But can be fused irreversibly into low impedance state
by applying high voltage
Anti-fuse Programming Technology
• Very low ON Resistance (Faster implementation of circuits)
• Limited size of anti-fuse elements; Interconnects occupy relatively
lesser area
• Offset : Larger transistors needed for programming
• One Time Programmable
• Cannot be re-programmed
• (Design changes are not possible)
• Retain configuration after power off
EPROM, EEPROM or Flash Based
Programming Technology

• EPROM Programming Technology

• Two gates: Floating and Select
• Normal mode:
• No charge on floating gate
• Transistor behaves as normal n-channel transistor
• Floating gate charged by applying high voltage
• Threshold of transistor (as seen by gate) increases
• Transistor turned off permanently
• Re-programmable by exposing to UV radiation
EPROM Programming
Technology
• Used as pull-down
devices
• Consumes static
power
EPROM Programming Technology

• No external storage mechanism

• Re-programmable (Not all!)
• Not in-system re-programmable
• Re-programming is a time consuming task
EEPROM Programming Technology
• Two gates: Floating and Select
• Functionally equivalent to EPROM; Construction and structure differ
• Electrically Erasable: Re-programmable by applying high voltage
(No UV radiation expose!)
• When un-programmed, the threshold (as seen by select gate) is
negative!
EEPROM Programming Technology
EEPROM Programming Technology

• Re-programmable; In general, in-system re-

programmable
• Re-programming consumes lesser time compared
to EPROM technology
• Multiple voltage sources may be required
• Area occupied is twice that of EPROM!