Digital System Design Verilog: FSMD Concepts and Example

Dr. Bassam Jamil

FSMD
FSMD

is Finite State Machine (FSM) with datapath

is computational blocks

Datapath

Adders/Subtractors

Shifters/Rotators Multipliers Dividers etc

FSDM
In

the design process, start first with algorithm in high level language
convert the algorithm to FSDM

Then

Sometimes, a behavioral model substitute FSDM\

Then

Implement the design in Verilog

Example
We

will consider two implementations of GCD

Both are correct Just learn how different approaches lead to different implementations.

First

Implementation uses state diagrams implementations start with behavioral

Second

model
Now

to the FIRST

IMPLEMTATION

Greatest Common Divisor (GCD)

Inputs :

ld : load
m and n : numbers

Output

gcd: great common divisor result

done: operation is complete
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GCD Example: FSM and Datapath

GCD Example: FSM and Datapath

CGD Example: I/O and State

GCD Example: Single-case Design

end

GCD Design
SECOND

IMPLEMETNATION

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GCD In C

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Behavioral Model for GCD

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Testing Behavioral Model

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Deriving RTL

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RTL Design- Step 1: Define Port Interface

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RTL Design- Step 2: Define Datapath Functional Units

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RTL Design- Step 2: Define Control Unit

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Datapath Module Interface

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Connect The Modules

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Connect the Modules

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Control Block

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Control Unit: FSM Implementation

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FSM Implementation

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FSM Implementation: Outputs

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Testing: Design the Testbench

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Testing: Checking the RTL

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