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Semiconductor Memories
1. Mask programmed
2. Programmable ROM (PROM) Static RAM Dynamic RAM
b. Fuse ROM (SRAM) (DRAM)
a. Erasable PROM (EPROM)
c. Electrically Erasable PROM
(EEPROM)
d. Flash Memory
e. Ferroelectric RAM (FRAM)
Kenneth R. Laker, University of Pennsylvania
3
Row 2N
AN
Memory
DATA DATA LINE CONTROL CKTS
Block
COLUMN ADDRESS DECODER
CHIP
CNTL I/O B1 B2 B3 BM
N+M
COLUMN ADDRESS BITS
Kenneth R. Laker, University of Pennsylvania
ROM CIRCUITS 4 X 4 BIT NOR BASED ROM ARRAY 5
WORD BIT
LINES LINES
R1 R2 R3 R4 C1 C2 C3 C4
R1 1 0 0 0 0 1 0 1
0 1 0 0 0 0 1 1
0 0 1 0 1 0 0 1
R2 0 0 0 1 0 1 1 0
default “0” default “1”
All word lines Ri are kept
R3 at logic “0” level, except
the selected line is pulled
up to “1” level.
C1 C2 C3 C4
Kenneth R. Laker, University of Pennsylvania
6
R3
diffusion to GND
R2 poly
metal-diff
contact
R3 poly
diffusion to GND
R4 poly
poly
rows (word)
WORD BIT
C1 C2 C3 C4
LINES LINES
R1 R1 R2 R3 R4 C1 C2 C3 C4
0 1 1 1 0 1 0 1
1 0 1 1 0 0 1 1
R2 1 1 0 1 1 0 0 1
1 1 1 0 0 1 1 0
default “1” default “0”
R3
poly
R4 R2
poly
R3
poly
R4
diffusion to GND
threshold voltage
implant to make VT0
Kenneth R. Laker, University of Pennsylvania negative to store “0”
DESIGN OF ROW AND COLUMN DECODERS 11
RA1 R1
ROW R2
DECODER R3
RA2 R4
RA1 RA2 R1 R2 R3 R4
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
2 address bits plus Select 1 of 4 rows or
complements word lines
R1
VDD
off off
(2N) nMOS + (N )pMOS =
(2N + N) Xstrs
R2
VDD PLUS 2N INVERTERS
on off
R3
VDD
off on
R4
0 0
on on For N = 2
RA2 1 RA1 1 RA1 RA2 R1 R2 R3 R4
0 0 1 0 0 0
0 0 1 0 1 0 0
0
RA2 RA1 1 0 0 0 1 0
Kenneth R. Laker, University of Pennsylvania
1 1 0 0 0 1
13
REALIZATION OF ROW DECODER AND ROM ARRAY AS
TWO ADJACENT NOR PLANES
2N ROWS (WORD LINES)
R1
R2
NOR ROW NOR ROM
DECODER ARRAY
R2N
For N = 2
RA1 RA2 R1 R2 R3 R4
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
Kenneth R. Laker, University of Pennsylvania 1 1 0 0 0 1
REALIZATION OF ROW DECODER AND ROM ARRAY AS 14
ROM ARRAY
C1
CA1 NOR
C2 2M pass
CA2 COLUMN transistors
ADDRESS C3
DECODER
(2M+M)Transistors
CAM C2M
M column DATA
address bits SAME AS ROW OUTPUT
DECODER serial (as
shown)
Kenneth R. Laker, University of Pennsylvania
COLUMN DECODER FOR 8 BIT LINES IMPLEMENTED AS BINARY16
TREE
C1 C2 C3 C4 C5 C6 C7 C8
COLUMN
ADDRESS BITS DATA OUTPUT
serial or parallel
ADVG: Decoding is realized by tree structure; much reduced Xstr count.
DISADVG: Large number of series connected nMOS pass Xstrs.
Fix with buffers or use of a combined tree and pass-transistor design.
Kenneth R. Laker, University of Pennsylvania
EXAMPLE 10.1: 17
2. Calculate row access time trow -> delay associated with selecting and
activating 1 of 128 word lines in ROM array
V
VOH Emperical Delay Formulas
Vin V256
V50%
t
trow = 15.5 ns (at VG256)
Kenneth R. Laker, University of Pennsylvania
19
3. Calculate column access time tcolumn -> worst case delay τPHL associated with
discharging the precharged bit line when a row is activated.
R1
R2
Up to 128-input NOR gate VDD
rep of column in the ROM R127
array. (4/1.5) column output CJ R128
C1
Ccolumn
R1 R2 R3 R128 (2/1.5)
(4/1.5)
column output CJ
tcolumn = τPHL = 18 ns
CC 2 VT 0 n 4(VOH − VT 0 n )
τ PHL = + ln − 1 = 18 ns
column load
k n (VOH − VT 0 n ) VOH − VT 0 n VOH + VOL
VDD
bit line bit line
R R
SRAM cell is accessed
via two bit (column)
word line word line lines C and its
complement for more
reliable and much
faster operation
pass transistors to
activated by a row select basic cross-coupled
(RS) signal to enable 2-inverter latch with 2
read/write ops stable op points for
storing one-bit
VDD
bit line bit line
CC M1 M2 CNOT-C
RS
word line
1. WHEN THE WORD LINE NOT SELECTED, i.e. RS = 0: M3 & M4 are OFF
a. One data-bit is HELD, i.e. latch preserves one of its two stable states.
b. If RS = 0 for ALL rows, the bit lines capacitances CC and CNOT-C are
charged-up to near VDD by pull-up of MP1 and MP2 (both in SAT).
VNOT-C =
EX: VC = VNOT-C = 3.5 V for VDD = 5 V, VT0 = 1 V, |2φF| = 0.6 V, γ = 0.4 V1/2.
Kenneth R. Laker, University of Pennsylvania
25
VDD pull-up transistors VDD
(one per column)
MP1 VDD MP2
bit line
bit line
R R
VC M3 V1 V2 M4 VNOT-C
CC M1 M2 CNOT-C
RS
2. WHEN THE WORD LINE IS SELECTED, i.e. RS = 1: M3 & M4 are ON
Four basic ops can be performed in this SRAM Mode:
a. WRITE “1” OP (@ t = 0− V1n-1 = VOL, V2n-1 = VOH) RS -> 1 at t = 0:
VNOT-C -> VOL by the DATA-WRITE CIRCUITRY. Hence V2n -> VOL, then
M1 turns OFF => V1n -> VOH and M2 turns ON pulling V2n -> VOL.
b. READ “1” OP (@ t = 0− V1n-1 = VOH, V2n-1 = VOL) RS -> 1 at t = 0:
VC retains precharge level, while VNOT-C -> VOL by ON M2. DATA-READ
CIRCUITRY detects small voltage difference VC - VNOT-C > 0, and amplifies
it as a “1” data output.
Kenneth R. Laker, University of Pennsylvania
26
VDD pull-up transistors VDD
(one per column)
MP1 VDD MP2
bit line
bit line
R R
VC M3 V1 V2 M4 VNOT-C
CC M1 M2 CNOT-C
RS
2. WHEN THE WORD LINE IS SELECTED, i.e. RS = 1: M3 & M4 are ON
Four basic ops can be performed in this SRAM Mode:
c. WRITE “0” OP (@ t = 0− V1n-1 = VOH, V2n-1 = VOL) RS -> 1 at t = 0:
VC -> VOL by the DATA-WRITE CIRCUITRY. Since V1 -> VOL, M2 turns
OFF => V2 -> VOH and M1 turns ON pulling V1n -> VOL.
d. READ “0” OP (@ t = 0− V1n-1 = VOL, V2n-1 = VOH) RS -> 1 at t = 0:
VNOT-C retains precharge level, while VC -> VOL by ON M1. DATA-READ
CIRCUITRY detects small voltage difference VC - VNOT-C < 0, and amplifies
it as a “0” data output.
Kenneth R. Laker, University of Pennsylvania
VDD pull-up transistors VDD 27
CC M1 M2 CNOT-C
RS
CC M1 M2 CNOT-C
RS
ASSUME: 1 bit is stored in the cell => M1 OFF, M2 ON => V1 = VOH, V2 = VOL.
i.e. ONE LOAD RESISTOR IS ALWAYS CONDUCTING NON-ZERO
CURRENT.
with R = 100 MΩ (undoped poly), Pstandby < 0.25 µW per cell for VDD = 5V
RS
word line
-> VERY LOW STANDBY POWER CONSUMPTION
-> LARGER NOISE MARGINS THAN R-LOAD SRAMS
-> OPERATE AT LOWER SUPPLY VOLTAGES THAN R-LOAD SRAMS
VDD MP2
MP1
bit line
bit line M6
M5 VDD M4
M3 0V V2
V1
CC M2 CNOT-C
M1
RS
RS = VDD
a. @ t = 0−: M3, M4 OFF; M2, M5 OFF & M1, M6 LIN
b. @ t = 0: M3 SAT, M4 LIN; M2, M5 OFF & M1, M6 LIN
slow discharge of large Cc and V1 increases
REQUIRE V1 < VT02 => LIMITS M3 W/L wrt M1 W/L
Kenneth R. Laker, University of Pennsylvania
VDD 31
VDD
VDD MP2
MP1
bit line
bit line M6
M5 VDD M4
M3 0V V2
V1
CC M2 CNOT-C
M1
RS
RS = VDD
DESIGN CONSTRAINT: i.e. KEEP M2 OFF
M3 SAT, M1 LIN =>
kn 3
2
2 k n1
( VDD − V1 − VT 0 n ) =
2
(
2( VDD − VT 0 n ) V1 − V12 )
SYMMETRY:
kn 4
SAME for
kn 2
(M1 & M6 OFF
Kenneth R. Laker, University of Pennsylvania for Read ‘1”)
32
2. CONSIDER DATA-WRITE “0” OP with “1” STORED IN CELL:
VDD
VDD
0V bit line
bit line M6
M5
V 0V M4
0V M3 DD V2
V1
CC M2 CNOT-C
M1
RS
RS = VDD at t =0
VC IS SET “0” BY DATA-WRITE CIRCUIT
a. @ t = 0−: M3, M4 OFF; M2, M5 LIN & M1, M6 OFF (“1” stored)
b. @ t = 0: M3 SAT, M4 SAT; M2, M5 LIN & M1, M6 OFF
WRITE “0” => V1: VDD -> 0 (< VT0n) AND V2: 0 -> VDD (M2 -> OFF)
DESIGN CONSTRAINT: i.e. KEEP M2 OFF
WHEN V1 = VT0n: M3 LIN & M5 SAT =>
( ) ( )
kp 5 2 kn 3
0 − VDD − VT 0 p = 2( VDD − VT 0 n ) VT 0 n − VT 0n 2
2 2
Kenneth R. Laker, University of Pennsylvania
33
V1 < VT0n, i.e. M2 (M1) forced OFF
kp 5 kp 6 2(VDD −1.5VT 0 n ) VT 0 n
= < =>
kn 3 kn 4 (VDD + VT 0p ) 2
W W
L 5 L 6 µ n 2( VDD − 1.5VT 0 n ) VT 0 n
= <
W
W
L 3 L 4
µp (
VDD + VT 0 p )
2
DATA M1
from COLUMN M3
DECODER
Write OP: force VC or VNOT-C to a logic low level when W = 0.
NOT-W DATA NOT-WB WB OPERATION (M3 ON)
0 1 0 1 M1 OFF, M2 ON ->VNOT-C LOW
0 0 1 0 M1 ON, M2 OFF ->VC LOW
1 X 0 0 M1 OFF, M2 OFF ->VC = VNOT-C HIGH
Kenneth R. Laker, University of Pennsylvania
SRAM READ CIRCUIT 35
VDD
R R
SOURCE Vo1 Vo2
COUPLED
DIFFERENTIAL VNOT-C
VC M1 Vx M2
AMPLIFIER
ISS
CC CNOT-C
CK M3
word line
(read/write select)
1 - Transistor
explicit DRAM Cell
C storage (most widely
bit line capacitor used cell)
(data read/write)
VDD
Precharge devices
MP1 MP2
PC 1 - Bit
read select
DRAM Cell
(RS)
M1 M3
CC M2 CNOT-C
C
write select
(WS)
bit line
DATA Data_in bit line
Data_out
Precharge devices
MP1 MP2
1 - Bit
read select PC DRAM Cell
(RS)
M1 M3
CC M2 CNOT-C
C
write select
(WS)
bit line
bit line
DATA Data_in
Data_out write read write read
PC “1” PC “1” PC “0” PC “0”
1 2 3 4 5 6 7 8
PC
WS
DATA
Data_in
Stored Data
RS
Data_out
Kenneth R. Laker, University of Pennsylvania
41
VDD
Precharge devices
MP1 MP2
PRECHARGE CYCLE
PC
CC CNOT-C
RS
VDD - VTMP1
M1 M3 WRITE “1” OP
CC M2 C3
DATA = 0
C WS = 1; RS = 0
WS CC, C SHARE
bit line CHARGE DUE TO
DATA Data_in bit line M1 ON
Data_out
RS
VDD - VTMP1
M1 M3 WRITE “0” OP
CC M2 C3
DATA = 1
C WS = 1; RS = 0
WS CC, C DISCHARGED
bit line TO 0 THROUGH M1
DATA Data_in bit line AND DATA-IN nMOS
Data_out
Kenneth R. Laker, University of Pennsylvania
43
RS
VDD - VTMP1
M1 0V M3 READ “0” OP
C2 M2 CNOT-C
DATA = 1
C WS = 0; RS = 1
WS CNOT-C DOES NOT
bit line DISCHARGE
DATA Data_in bit line DUE TO M2 OFF
Data_out
R (R/W select)
Bit-line
1-Bit
M1
CC C DRAM
Cell
D (data in/out)
CC >> C
Uses two-phase non-overlapping clock scheme where φ1 = bit-line is
precharged and φ2 = R = read/write.
WRITE “1” OP: D = 1, R = 1 (M1 ON) => C CHARGES TO “1”
WRITE “0” OP: D = 0, R = 1 (M1 ON) => C DISCHARGES TO “0”
READ OP: DESTROYS STORED CHARGE ON C => REFRESH IS
NEEDED AFTER EVERY DATA READ OP
+
trans
+
o
+
+ trans
o
o