Memory Technology

Topics
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Memory Hierarchy Basics

Static RAM
Dynamic RAM
Magnetic Disks
Introduction to FLASH

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Elements of Memory Organization

The technologies (SRAM, DRAM, FLASH etc)

The components
l Cache (L1,L2)
l Main memory
l Virtual memory

Computer System

Processor
Reg

Cache

Memory-I/O bus

Memory

I/O
controller

Disk

Disk

I/O
controller

I/O
controller

Display

Network

Levels in Memory Hierarchy

cache

CPU
regs

Register

size:
200 B
speed:
2 ns
$/Mbyte:
block size: 8 B

8B

C
a
c
h
e

32 B

Cache

Memory

8 KB

Memory

32KB - 4MB
4 ns

$100/MB
32 B

larger, slower, cheaper

virtual memory

128 MB
60 ns
$1.50/MB
8 KB

disk

Disk Memory
20 GB
8 ms
$0.05/MB

Static RAM (SRAM)

Fast
l ~4 nsec access time
Persistent
l as long as power is supplied
l no refresh required
Expensive
l ~$100/MByte
l 6 transistors/bit
Stable
l High immunity to noise and environmental disturbances
Technology for caches

bit line
b

Anatomy of an SRAM Cell

bit line
b
word line

Stable Configurations

(6 transistors)

Write:
1. set bit lines to new data value
b is set to the opposite of b
2. raise word line to high
sets cell to new state (may involve
flipping relative to old state)

1 1

Terminology:
bit line: carries data

word line: used for addressing

Read:
1. set bit lines high

2. set word line high

3. see which bit line goes low

Example SRAM Configuration (16 x 8)

W0

A0
A1
A2
A3

b7

b7

b1

b1

b0

b0

W1
Address
decoder

memory
cells

W15

sense/write
amps

Input/output lines d7

sense/write
amps

d1

sense/write
amps

d0

R/W

Dynamic RAM (DRAM)

Slower than SRAM

l access time ~60 nsec
Nonpersistant
l every row must be accessed every ~1 ms (refreshed)
Cheaper than SRAM
l ~$1.50 / MByte
l 1 transistor/bit
Fragile
l electrical noise, light, radiation
Workhorse memory technology

Anatomy of a DRAM Cell

Bit
Line

Word Line
Access
Transistor

Storage Node
Cnode

CBL

Writing

Reading

Word Line

Word Line

Bit Line
Storage Node

Bit Line
V ~ Cnode / CBL

DRAM Operation

Row Address (~50ns)

l Set Row address on address lines & strobe RAS
l Entire row read & stored in column latches
l Contents of row of memory cells destroyed
Column Address (~10ns)
l Set Column address on address lines & strobe CAS
l Access selected bit
l READ: transfer from selected column latch to Dout
l WRITE: Set selected column latch to Din
Rewrite (~30ns)
l Write back entire row

Observations About DRAMs

Timing
l Access time (= 60ns) < cycle time (= 90ns)
l Need to rewrite row
Must Refresh Periodically
l Perform complete memory cycle for each row
l Approximately once every 1ms
l Sqrt(n) cycles
l Handled in background by memory controller
Inefficient Way to Get a Single Bit
l Effectively read entire row of Sqrt(n) bits

Enhanced Performance DRAMs

Conventional Access
l Row + Col
l RAS CAS RAS CAS ...
Page Mode
l Row + Series of columns
l RAS CAS CAS CAS ...
l Gives successive bits
Other Acronyms
l EDORAM
l Extended data output
l SDRAM
l Synchronous DRAM

RAS

Row
address
latch

Row
decoder

256x256
cell array

row

A7-A0

sense/write

amps

col

Column
address
latch

column
latch and
decoder

CAS

Entire row buffered here

R/W

Video RAM

Performance Enhanced for Video / Graphics Operations

l Frame buffer to hold graphics image
Writing
l Random access of bits
l Also supports rectangle fill operations
l Set all bits in region to 0 or 1
Reading
l Load entire row into shift register
l Shift out at video rates
Performance Example
l 1200 X 1800 pixels / frame
l 24 bits / pixel
l 60 frames / second
l 2.8 GBits / second

256x256
cell array

column
sense/write
amps

Shift Register

Video Stream Output

DRAM Driving Forces

Capacity
l 4X per generation
l Square array of cells
l Typical scaling
l Lithography dimensions 0.7X
l Areal density 2X
l Cell function packing 1.5X
l Chip area 1.33X
l Scaling challenge
l Typically Cnode / CBL = 0.10.2
l Must keep Cnode high as shrink cell size
Retention Time
l Typically 16256 ms
l Want higher for low-power applications

DRAM Storage Capacitor

Planar Capacitor
l Up to 1Mb
l C decreases linearly with feature
size
Trench Capacitor
l 4256 Mb
l Lining of hole in substrate
Stacked Cell
l > 1Gb
l On top of substrate
l Use high

Plate
Area A
Dielectric Material
Dielectric Constant
d

C = A/d

Trench Capacitor

Process
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Etch deep hole in substrate

Becomes reference plate
Grow oxide on walls
Dielectric
Fill with polysilicon plug
Tied to storage node

SiO2 Dielectric

Storage Plate
Reference Plate

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IBM DRAM Evolution

IBM J. R&D, Jan/Mar 95

Evolution from 4 256 Mb
256 Mb uses cell with area 0.6 m2

4 Mb Cell Structure

Cell Layouts

4Mb

16Mb

64Mb

256Mb

Mitsubishi Stacked Cell DRAM

IEDM 95
l Claim suitable for 1 4 Gb
Technology
l 0.14 m process
l Synchrotron X-ray source
l 8 nm gate oxide
l 0.29 m2 cell
Storage Capacitor
l Fabricated on top of everything else
l Rubidium electrodes
l High dielectric insulator
l 50X higher than SiO2
l 25 nm thick
l Cell capacitance 25 femtofarads
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Cross Section of 2 Cells

Mitsubishi DRAM Pictures

Disk surface spins at

36007200 RPM

Magnetic Disks

read/write head
arm

The surface consists

of a set of concentric
magnetized rings
called tracks

Each track is divided

into sectors

The read/write
head floats over
the disk surface
and moves back
and forth on an
arm from track
to track.

Parameter 18GB Example

l Number Platters 12
l Surfaces / Platter 2
l Number of tracks 6962
l Number sectors / track
213
l Bytes / sector
512
Total Bytes 18,221,948,928

Disk Capacity

Disk Operation

Operation
l Read or write complete sector
Seek
l Position head over proper track
l Typically 6-9ms
Rotational Latency
l Wait until desired sector passes under head
l Worst case: complete rotation
l 10,025 RPM 6

l #

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.., 213 512 10,025 = 18 /.

80 /

Disk Performance

Getting First Byte

l Seek + Rotational latency = 7,000 19,000 sec
Getting Successive Bytes
l ~ 0.06 sec each
l roughly 100,000 times faster than getting the first byte!
Optimizing Performance:
l Large block transfers are more efficient
l Try to do other things while waiting for first byte
l switch context to other computing task
l processor is interrupted when transfer completes

Magnetic Disk Technology

Seagate ST-12550N Barracuda 2 Disk

l Linear density
52,187. bits per inch (BPI)
l Bit spacing 0.5 microns
l Track density3,047.
tracks per inch (TPI)
l Track spacing
8.3 microns
l Total tracks 2,707.
tracks
l Rotational Speed 7200.
RPM
l Avg Linear Speed
86.4kilometers / hour
l Head Floating Height 0.13microns
Analogy:
l put the Sears Tower on its side
l fly it around the world, 2.5cm above the ground
l each complete orbit of the earth takes 8 seconds

CD Read Only Memory (CDROM)

Basis
l Optical recording technology developed for audio CDs
l 74 minutes playing time
l 44,100 samples / second
l 2 X 16-bits / sample (Stereo)
l = 172 /
288 2048
,

l 172 2048 / (288 + 2048) = 150 /
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l 74 150 / 60 / = 650

Disk Drive vs. Flash Memory

Read / Write

Read / Program / Erase

(+) Lost cost per bit

(+) Random Access

(+) Non-volatile
(+) Low Power Consumption (2W)

(-) Mechanical movement (SPM & VCM)

(-) High power consumption (10-15W)
(-) Heavy weight compared to flash

(-) Erase before Write

(-) Erasing operation in the unit of block
(not page)
(-) Maximum # of erase operations per cell
(-) High cost per bit

FLASH Memory

Floating gate transitor

l Presence of charge => 0
l Erase Electrically or UV (EPROM)
Performance
l Reads like DRAM (~ns)
l Writes like DISK (~ms). Write is a complex operation

 How does a Flash memory cell work?

How does a MOS transistor work?

What is a semiconductor?

 Semiconductor essentials: properties

Metallic conductor:
typically 1 or 2 freely moving electrons per atom
Semiconductor:
typically 1 freely moving electron per 109-1017 atoms

 Semiconductor essentials - resistivity

 Semiconductors in the periodic table

Elemental semiconductors:
C, Si, Ge (all group IV)
Compound semiconductors:
III-V: GaAs, GaN
II-VI: ZnO, ZnS,
Group-III and group-V
atoms are dopants

 Semiconductor essentials: impurities

Small impurities can dramatically change conductivity:

slight phosphorous contamination in silicon gives many extra free electrons
in the material (one per P atom!)
slight aluminum contamination gives many extra holes (one per Al atom)

Al

 (silicon lattice is of course 3D!)

 Silicon dopants

Boron most widely used

as p-type dopant;
Phosphorous and arsenic
both used widely as n-type
dopant

 Semiconductor essentials: n and p type

n-type doped semiconductor

p-type doped semiconductor
e.g. silicon with phosphorus impurity e.g. silicon with Al impurity
electrons determine conductivity
holes determine conductivity
p-n junction:
current can only flow one way!
Semiconductor diode

 The field effect

accumulation

depletion

inversion

++++++++

----------

 FET ( Field Effect Transistor)

Few important advantages of FET over conventional
Transistors

1.Unipolar device i. e. operation depends on only one type of

charge carriers (h or e)
2.Voltage controlled Device (gate voltage controls drain current)
3.Very high input impedance (109-1012 )
4.Source and drain are interchangeable in most Low-frequency
applications
5.Low Voltage Low Current Operation is possible (Low-power
consumption)
6.Less Noisy as Compared to BJT
7.No minority carrier storage (Turn off is faster)
8.Self limiting device
9.Very small in size, occupies very small space in ICs
10.Low voltage low current operation is possible in MOSFETS
11.Zero temperature drift of out put is possiblek

Types of Field Effect Transistors

(The Classification)
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n-Channel JFET
p-Channel JFET

JFET
FET

MOSFET

(IGFET)

Enhancement
MOSFET
nChannel
EMOSFET

pChannel
EMOSFET

Depletion
MOSFET
n-Channel
DMOSFET

p-Channel
DMOSFET

 Current Controlled vs Voltage Controlled

Devices

 The Junction Field Effect Transistor (JFET)

Figure: n-Channel JFET.

 p-Channel JFETs

p-Channel JFET operates in a similar manner as the n-channel JFET except the
voltage polarities and current directions are reversed

 JFET Symbols

 Biasing the JFET

Figure: n-Channel JFET and Biasing Circuit.

 Operation of JFET at Various Gate Bias Potentials

Figure: The nonconductive depletion region becomes broader with increased reverse bias.
(Note: The two gate regions of each FET are connected to each other.)

 Operation of a JFET
Drain

N
Gate
-

N
Source

+
DC Voltage Source

 Output or Drain (VD-ID) Characteristics of n-JFET

Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.

 Simple Operation and Break down of n-Channel JFET

Figure: n-Channel FET for vGS = 0.

 p-Channel JFETs

p-Channel JFET operates in a similar manner as the n-channel JFET except the
voltage polarities and current directions are reversed

 P-Channel JFET Characteristics

As VGS increases more positively

the depletion zone increases

ID decreases (ID < IDSS)
eventually ID = 0A
Also note that at high levels of VDS the JFET reaches a breakdown situation. ID increases uncontrollably if VDS > VDSmax.

 The Potential (Voltage) Divider Bias

 A Simple CS Amplifier and Variation in IDS with Vgs

 Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.

 Figure: For vGS < Vto the pn junction between drain and body is reverse biased and iD=0.

 Figure: For vGS >Vto a channel of n-type material is induced in the region under the gate.
As vGS increases, the channel becomes thicker. For small values of vDS ,iD is proportional to vDS.
The device behaves as a resistor whose value depends on vGS.

 Figure: As vDS increases, the channel pinches down at the drain end and iD increases more slowly.
Finally for vDS> vGS -Vto, iD becomes constant.

Current-Voltage Relationship of
n-EMOSFET

Locus of points where

 Concept of the floating-gate memory cell

MOS transistor: 1 fixed threshold voltage

Flash memory cell: VT can be changed by program/erase

MOS transistor

Id

VT

Vgs

Floating gate transistor

Id

programming

erasing

Vgs

 Floating Gate Fundamentals

Floating Gate is isolated.

Floating gate not charged: Functions like normal MOSFET
Floating gate charged: Charge shields channel region from control gate
and prevents the formation of a channel between source and drain

 Floating Gate Fundamentals

Charging / Discharging Floating Gate:

Channel Hot Electron Injection
Fowler-Nordheim Tunneling

Both approaches use high voltages for operations

 Floating Gate Fundamentals

F-N Tunneling
Usage
Used for erasing (removing charge)
Sometimes used for programming (placing charge)

Quantum Mechanical Effect that allows electrons to pass

from the conducting band of one silicon region to that of
another region through an intervening barrier of SiO2.
Needs a high value of the injection field ~10MV/cm

 Floating Gate Fundamentals

Channel Hot Electron Injection (CHEI)
Usage
Sometimes used for programming (placing charge)
Hot Carrier injection occurs when the electrons are accelerated high enough to
surmount the SiO2 barrier
Sometimes facilitated with a separate injection gate.

 Floating Gate Metal Oxide

Semiconductor FAMOS Structure

 Stacked Gate Avalanche Injection Type MOS (SAMOS

 Stacked Gate Avalanche Injection Type MOS (SAMOS

 Array Designs
Different Array Designs
NOR (used)
NAND (used)
AND
DINOR
T-Poly

 NOR Array

Reading:
Assert a single word line. The
source lines are asserted and
the read of the bitline gives
the contents of the cell.

 NOR Array

ul: High Voltage Source

Erase
ur: Negative Gate
Source Erase
ll: Channel Erase
lr: Programming

 NOR Array

Erasure:
Set sources to 12V
Set word lines to Ground

 NOR Array

Write:
Set sources to 12V
Set source line to -5V

 NAND Array

NAND array cell is much smaller

than NOR cell.
Arranged in a line of typically 16
gates.
NAND cell has threshold voltage
higher than 0V if programmed and a
negative threshold voltage
otherwise.

 NAND Array
Programming
Uses F-N tunneling.
Substrate is grounded.
High voltage on wordline.

 NAND Array
Erasure
Substrate is charged with 19-21V.
Control gate is grounded.

 NAND vs. NOR Layout

NAND arrays have densities at which there are more errors.
Programming NAND through F-N takes longer (200 )
, ,
.

 NAND vs. NOR Layout

NAND is read per page (512B)
NOR is read individually.
Both erase blocks (8KB 64KB)
Using NAND is closer to using disk
Using NOR is closer to using RAM

 Multi-Levels
By charging the floating gates at different levels, a single cell can store
multiple data, typically 2b.
These correspond to different threshold values at which the gate
becomes conductive.

 Multi-Levels
By using reference cells set at given levels and
comparing them to the value from the bitline, we
can determine the value stored.

MOS (Metal-Oxide

Semiconductor) Memory Hierarchy

History of Flash Memory

(a) NOR

NOR and NAND Flash Array

(b) NAND

NOR and NAND Flash Array

NAND Flash Memory Program/Erase

F-N tunneling
l Give a higher voltage and electrons are trapped through gate into floating gate
transistor.

NOR (Code Executable in Place like Memory)

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Flash Memory Comparison

Fast read and slow write

NAND (Data-storage)
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Fast write and lower cost

Flash Type

Performance

Application

Code
Storage

NOR
-Intel/Sharp
-AMD/Fujitsu/Toshiba

Important:
-High Random Access
-Byte Programming
Acceptable:
-Slow Programming
-Slow Erasing

Program Storage
- Cellular Phone
- DVD, Set TOP Box for
BIOS

File
Storage

NAND
-Samsung/Thoshiba

Important:
-High Sped Programming
-High Speed Erasing
-High Speed Serial Read
Acceptable:
-Slow Random Access

Small form factor

-Digital Still Camera
Silicon Audio, PDA
Mass storage as Silicon
Disk-Drive

NAND Flash Non-Volatile Flash Cards

Various Standard Memory Cards

Functional Block Diagram for SAMSUNG K9K8G08U0M NAND Flash

Array Organization for SAMSUNG K9K8G08U0M NAND Flash

Block: Erasing Unit

Page: Addressable Unit

NAND Flash Technology

http://www.samsung.com/Products/Semiconductor/NANDFlash/index.htm

Comparison for Different Memory Types

Design and evaluation of the compressed flash translation layer for high-speed and large-scale flash
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memory storages Proc. SoC Design Conference, pp. 740-745, September, 2003