UNIT- III Synchronous Sequential Networks

Sequential Network Model

Sequential Logic Networks Combinational logic networks

Outputs at any given time depends only on the input at that time Each output is represented by an algebraic function of the inputs

Sequential logic networks

Outputs depend on past and present inputs Past inputs must be stored memory! Synchronous sequential network
behavior determined by values of the signal at discrete instants of time (clock)

Asynchronous sequential networks

behavior immediately affected by the inputs changes

Clocked Synchronous Sequential Network

Mealy Model
Outputs are only a function of the external inputs and the present state Z = g(X,Q)

Mealy model of a clocked synchronous sequential network.

Figure 7.3

Moore Model
Outputs are only a function of the present state
Z = g(Q)

Moore model of a clocked synchronous sequential network.

Figure 7.4

Analysis of Clocked Synchronous Sequential Networks

Logic Diagram Excitation and Output Expressions Transition Equations Transition Tables Excitation Tables State Tables State Diagrams

Logic diagram for Example 7.1

Excitation and Output Expressions

From example 7.1

D1 xQ2 Q1Q2
D2 xQ1 Q1Q2

z xQ1 xQ1 Q2

Transition Equations
From example

Q xQ2 Q1Q2 Q2 xQ1 Q1Q2

Transition Table
Present state (Q1Q2) Next state (Q1+Q2+) Output (z)

Input (x)
0 1

Input (x)
0 1

Transition Table
Present state (Q1Q2) Next state (Q1+Q2+) Output (z)

Input (x) 0 1
00 01 10 11

Input (x) 0 1

Transition Table
Present state (Q1Q2) Next state (Q1+Q2+) Output (z)

00 01 10 11

Input (x) 0 1 1

Input (x) 0 1

Transition Table
Present state (Q1Q2) Next state (Q1+Q2+) Output (z)

00 01 10 11

Input (x) 0 1 10

Input (x) 0 1

Transition Table
Present state (Q1Q2) Next state (Q1+Q2+) Output (z)

00 01 10 11

Input (x) 0 1 10 01 11 11 10 00 00 00

Input (x) 0 1 0 1 0 0 1 0 1 0

Excitation Table
Present state (Q1Q2) Excitation (D1D2) Output (z)

Input (x) 0 1
00 01 10 11

Input (x) 0 1

Excitation Table
Present state (Q1Q2) Excitation (D1D2) Output (z)

00 01 10 11

Input (x) 0 1 10 01 11 11 10 00 00 00

Input (x) 0 1 0 1 0 0 1 0 1 0

State Table
Present state Next state Output (z)

Input (x) 0 1 00A 01B 10C 11D

Input (x) 0 1

State Table
Present state Next state Output (z)

00A 01B 10C 11D

Input (x) 0 1 C

Input (x) 0 1

State Table
Present state Next state Output (z)

00A 01B 10C 11D

Input (x) 0 1 C B D D C A A A

Input (x) 0 1 0 1 0 0 1 0 1 0

State Table
Present state Next state, Output (z)

Input (x) 0 A B C D 1

State Table
Present state Next state, Output (z)

Input (x) A B C D 0 C,0 1

State Table
Present state Next state, Output (z)

Input (x) A B C D 0 C,0 D,0 C,1 A,1

Example 7.1

1 B,1 D,0 A,0 A,0

State diagram

Logic diagram for Moore Network

Excitation and Output Expressions

From example

J1 y
J2 xQ1 xyQ1
z1 Q1Q2

K1 y xQ2

K 2 x y yQ1

z2 Q1 Q2

Transition Equations
From example

Q yQ1 x yQ1 yQ1Q2

Q2 xQ1 Q2 xyQ1 Q2 x yQ2 xQ1Q2 yQ1Q2

Transition Table
Present state (Q1Q2) Next state (Q1+Q2+) Output (z1z2)

00 01 10 11

00 00 01 10 11

Input (xy) 01 10 10 01 11 00 01 00 00 10

11 11 11 00 00

01 00 11 01

Excitation Table
Present state (Q1Q2) Excitation (J1K1,J2K2) Output (z1z2)

00 01 10 11

00 00,00 00,00 00,00 00,00

Input (xy) 01 10 11,00 01,11 11,00 00,11 11,11 01,01 11,11 00,01

11 11,10 11,10 11,01 11,01

01 00 11 01

State Table
Present state Next state Output (z1z2)

00A 01B 10C 11D

00 A B C D

Input (xy) 01 10 C B D A B A A C

11 D D A A

01 00 11 01

State diagram

The serial binary adder

Figure 7.11

The serial binary adder

State A no carry was generated from the previous order addition. State B carry was generated from the previous order addition.

State diagram for a Mealy serial binary adder

(a) Partial state diagram

State diagram for a Mealy serial binary adder

(b) Completed state diagram

A sequence recognizer

Figure 7.14

A sequence recognizer An output 1 is produced if the three input symbols following two consecutive input 0s consist of aleast one 1
x = 0100010010010010000000011

A sequence recognizer

x = 01 00010 01 00100 1 00000 00011 z = 00 00001 00 00001 0 00000 00001

State diagram for a sequence recognizer