IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO.

1, JANUARY 2008 89
Operation Modes and Characteristics of the
Z-Source Inverter With Small Inductance
or Low Power Factor
Miaosen Shen, Member, IEEE, and Fang Zheng Peng, Fellow, IEEE
AbstractThe Z-source inverter, utilizing a unique LC network
and previously forbidden shoot-through states, provides unique
features, such as the ability to buck and boost voltage with a simple
single-stage structure. The analysis and control methods provided
in the literature are based on an assumption that the inductor
current is relatively large, continuous, and has small ripple. This
assumption becomes invalid when the load power factor is low or
the inductance is small in order to minimize the inductors size and
weight for some applications where volume and weight are crucial.
Under these conditions, the inductor current has high ripple or
even becomes discontinuous. As a result, the Z-source inverter
exhibits new operation modes that have not been discussed before.
This paper analyzes these new operation modes and the associated
circuit characteristics.
Index TermsDCAC power conversion, inverters, power
factor.
NOMENCLATURE
V
o
Input voltage of the Z-source inverter.
v
i
Voltage across the inverter bridge.
L Inductance of inductors in the Z-source network.
C Capacitance of the capacitors in the Z-source network.
V
s
Voltage stress across the device, which is equal to
maximum value of v
i
.
V
c
Voltage across the capacitors in the Z-source network.
i
L
Current through the inductors in the Z-source network.
i
i
Current fed to the inverter bridge.
i
in
Input current to the Z-source inverter.
T
0
, T
7
Zero states in space vector pulsewidth modu-
lation (SVPWM)/sinusoidal pulsewidth modulation
(SPWM).
T
0+7
Total traditional zero state in one switching cycle.
T
1
, T
2
Active states in SVPWM/SPWM.
G Voltage gain dened by the ratio of the output peak
phase voltage and half of the input voltage.
M Modulation index.
cos Load power factor.
T
st
Shoot-through period in one switching cycle.
Manuscript received December 15, 2005; revised September 12, 2007. This
work was supported by the National Science Foundation under Grant 0424039.
M. Shen was with the Department of Electrical and Computer Engi-
neering, Michigan State University, East Lansing, MI 48824 USA. He is
now with Siemens VDO Automotive, Dearborn, MI 48120 USA (e-mail:
miaosen.shen@siemens.com).
F. Z. Peng is with the Department of Electrical and Computer Engineering,
Michigan State University, East Lansing, MI 48824 USA.
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TIE.2007.909063
Fig. 1. Z-source inverter.
T
s
Switching cycle.
Z Load impedance per phase.
I
pk
Load peak current.
V
out
Output-phase rms voltage.
I. INTRODUCTION
T
HE TRADITIONAL voltage source inverter (VSI) [7][9]
is a buck converter and can only produce a voltage that is
lower than the dc bus voltage. Despite many different types of
pulsewidth modulation methods [10][15], a three-phase VSI
basically has six active states and two zero states. A zero state
is produced when the upper three or lower three switches are
turned on at the same time, shorting the output terminals. The
upper and lower two switches of any phase leg can never be
gated on at the same time; otherwise, a shoot-through short
circuit would occur and destroy the inverter. The shoot-through
is a forbidden switching state for the traditional VSI.
The Z-source inverter intentionally utilizes the shoot-through
zero states to boost dc voltage and produces an output voltage
that is greater than the original dc voltage [1]. At the same
time, the Z-source structure greatly enhances the reliability of
the inverter, because the momentary shoot-through states that
might be caused by electromagnetic interference noise can no
longer destroy the inverter. Fig. 1 shows the conguration of the
Z-source inverter. The operating principle has been described
in detail in [1]. Several control methods have been proposed
in [2][4]. The design procedure of the LC network has been
presented in [5]. A small-signal model has been proposed for
the Z-source inverter in [6].
However, all the descriptions and analysis are based on an
assumption that the inductor current is relatively large and
the circuit has only two operation modes. However, in some
cases, when the inductances of the inductors are small or the
load power factor is low, there can be extra operation modes.
This paper analyzes the Z-source inverter operation when the
inductance is very small or the load power factor is low. The
analysis reveals new operation modes and characteristics.
0278-0046/$25.00 2008 IEEE
90 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
II. OPERATING PRINCIPLE AND OPERATION
MODE ANALYSIS
As previously mentioned, the Z-source inverter utilizes the
shoot-through zero states to boost voltage in addition to the
traditional six active states and two zero states. The basic
operating principle described in [1] assumes that the inductor
current is relatively high and almost constant. When the in-
ductance is small or the load power factor is low, the inductor
current can have high ripple or even become discontinuous.
Instead of having the two operating modes described in [1],
the Z-source inverter may have ve different operation modes,
as shown in Fig. 2, when viewed from the Z-source network.
Modes 1 and 2 have been described in [1], whereas modes 35
are new modes that may exist for small-inductance and low-
power-factor cases.
Mode 1: The circuit is in a switch shoot-through zero state
when the two switches in any of the three phase legs are turned
on at the same time, the sum of the two capacitors voltage is
greater than the dc source voltage (V
C1
+V
C2
> V
0
), the diode
is reverse biased, and the capacitors charge the inductors. The
voltages across the inductors are
V
L1
= V
C1
V
L2
= V
C2
. (1)
The inductor current linearly increases, assuming that the
capacitor voltage is constant during this period. Because of the
symmetry (L
1
= L
2
= Land C
1
= C
2
= C) of the circuit, one
has v
L1
= v
L2
= v
L
, i
L1
= i
L2
= i
L
, and V
C1
= V
C2
= V
C
.
Mode 2: The inverter is in a nonshoot-through state (one of
the six active states and two traditional zero states), and the
inductor current meets the following inequality:
i
L
>
1
2
i
i
. (2)
Again, because of the symmetry of the circuit, capacitor
currents i
C1
and i
C2
and inductor currents i
L1
and i
L2
should
be equal to each other, respectively. In this mode, the input
current from the dc source becomes
i
in
= i
L1
+i
c1
= i
L1
+ (i
L2
i
i
) = 2i
L
i
i
> 0. (3)
Therefore, the diode is conducting, and the voltage across the
inductor is
v
L
= V
o
V
C
(4)
which is negative (the capacitor voltage is higher than the
input voltage during boost operation when there are shoot-
through states); thus, the inductor current linearly decreases,
assuming that the capacitor voltage is constant. As time goes
on, the inductor current keeps decreasing to a level wherein the
condition of (2) can no longer be met and the input current i
in
or the diode current is decreased to zero; mode 2 ends, and the
inverter enters to a new mode.
Mode 3: The inverter is in one of the six active states, and
the inductor current is equal to half of the inverter dc side
current i
i
. As a result, the input current becomes zero, and the
diode becomes reverse biased. Assuming that the inverter load
is inductive and has a much larger inductance than inductors L
1
Fig. 2. Possible operation modes of the Z-source inverter: (a) mode 1,
(b) mode 2, (c) mode 3, (d) mode 4, and (e) mode 5.
SHEN AND PENG: CHARACTERISTICS OF Z-SOURCE INVERTER WITH SMALL INDUCTANCE OR LOW POWER FACTOR 91
and L
2
, the voltage drop across L
1
and L
2
is negligible, and the
inductor current and inverter voltage v
i
are
i
L
=
1
2
i
i
(5)
v
i
=V
c
(6)
respectively.
Mode 4: The inverter is in one of the two traditional zero
states (i
i
= 0), and at the end of mode 2, the inductor current
decreases to zero; thus, a new operation mode appears. In
mode 4, the diode stops conducting, and the inverter is an
open circuit to the Z-source network because of i
i
= 0. The
inductor current becomes zero and maintains at zero until the
next switching action. Therefore, in this mode, the Z-source
circuit is isolated from both the dc source and the load. The
load terminals are shorted by the upper three switches or the
lower three switches, as shown in Fig. 2(d).
Mode 5: Freewheeling diode shoot-through state: The in-
verter is switched to an active state, and the inductor current
at that instant is less than i
i
/2. After having been switched
to an active state, the inverter cannot immediately enter the
active state, because the available current from the dc side 2i
L
is not enough to supply the load current i
i
; the inverter enters a
freewheeling state, as described in Fig. 2(e). The two diodes in
the equivalent circuit are the freewheeling diodes of the inverter
phase legs. This diode freewheeling state turns the inverter into
a shoot-through state. During this shoot-through state, all the
equations of mode 1 hold true, and the inductor current lin-
early increases. This mode continues until the inductor current
reaches i
i
/2 or another switching action happens. The differ-
ence between this mode and mode 1 is that this mode is not
intentionally created by the control signal and depends on the
load current and the inductor current at the time of switching.
III. CIRCUIT ANALYSIS AND CHARACTERISTICS
The Z-source inverter can be operated with both traditional
SPWM/SVPWM without any shoot-through states and with
shoot-through to boost the output voltage. Under both cases,
the new operation modes may or may not occur, depending
on the inductance and load conditions. The combination and
sequence of the operation modes can be different for different
circuit parameters. In this section, the circuit will be analyzed
under both traditional SVPWM control and that with boost by
giving the operation conditions including the combination and
sequence of the new modes and the critical conditions for the
new modes to happen.
A. Traditional SVPWM Control
Under traditional SVPWM control and simple operation,
when only modes 1 and 2 occur, the capacitor voltage is always
equal to the input voltage, and the inductor current is a pure dc.
However, under certain conditions, new operation modes can
also occur.
1) Operation Conditions: For SVPWM control, one switch-
ing cycle consists of four switching states, two zero states T
0
and T
7
, and two of the six active states T
1
and T
2
for instance.
During T
0
and T
7
, the load terminals are shorted by the upper or
lower three switches, and there is no current feeding the inverter
Fig. 3. Inductor current waveforms for different operation conditions:
(a) CCM and (b) DCM.
bridge from the dc side. To simplify the analysis, assume that
the currents from the dc side to the inverter bridge i
i
during
the two active states are the same and that the capacitor voltage
is always constant. Under these assumptions, there can be two
different operation conditions termed as continuous current
mode (CCM) and discontinuous current mode (DCM) with the
inductor current shown in Fig. 3(a) and (b), respectively. In both
cases, because of mode 5, the capacitor voltage is higher than
the input voltage. For the CCM condition, the inductor current
decreases in zero state T
0
. When active state T
1
starts, the
inductor current is less than i
i
/2; thus, the freewheeling diode
shoot-through mode (mode 5) happens, and the inductor current
linearly increases until it reaches i
i
/2. The inductor current
then remains by entering mode 3 afterward. The inductor
current will decrease again when the inverter enters the second
part of zero state T
7
. In some cases, when the inductance is
extremely low, the inductor current can reach zero during the
zero states and stay at zero in mode 4 until the next switching
action, as shown in Fig. 3(b), which forms a DCM operation
condition.
It is noteworthy that the currents to the inverter bridge at
different active states are actually different, which will make
the operation condition more complicated, and there could also
be more different operation conditions; however, the basic prin-
ciple and the possible operation modes are the same. Because
of the variation of the line current in a line cycle, more than one
operation condition can occur in one line cycle.
Under a simple operation condition, when only modes 1
and 2 occur, the capacitor voltage is always equal to the input
voltage. With these new operation modes, the capacitor voltage
is boosted, and the voltage across the device is also increased.
Because some part of the active states becomes the freewheel-
ing diode shoot-through state, the output voltage can be higher
or lower than the output voltage under a simple operation with
the same modulation index. In addition, the time duration of the
freewheeling diode shoot-through state depends on the current
to the inverter bridge, which changes over a line cycle; this can
cause slight harmonics in the output voltage.
2) Critical Condition: As previously discussed, the new
modes will bring different characteristics to the inverter; it
is important to know under what condition these new modes
will happen. The critical condition of the new modes to hap-
pen under traditional SVPWM without any controlled shoot-
through is
M cos <
2
3
. (7)
92 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
Fig. 4. Z-source inductor current for different operation conditions: (a) CCM
operation and (b) DCM operation.
From (7), when the load power factor is low, there will be
new operation modes. The detailed derivation can be found in
Appendix A.
B. Maximum Constant Boost Control With
Third-Harmonic Injection
When the circuit starts to boost the voltage by introducing
shoot-through states, the newmodes can also happen depending
on the load condition and the inductance of the inductors. As
previously stated, different control methods might yield differ-
ent circuit characteristics; therefore, a specic control method is
required for the analysis. The maximum constant boost control
method with third-harmonic injection [3] is employed here
to analyze the circuit characteristics as an example. Circuit
characteristics under other control methods can also be derived
by following the provided procedure.
1) Operation Conditions: The maximum constant boost
control with third-harmonic injection is quite similar to tradi-
tional SVPWM. In each switching cycle, there are two active
states T
1
and T
2
, for instance, two zero states T
0
and T
7
, and
one shoot-through state T
st
, with the following sequence: T
st
,
T
0
, T
1
, T
2
, T
7
. To simplify the analysis, the currents feeding to
the inverter bridge in the two active states are assumed to be
the same, and the capacitor voltage is assumed to be constant.
Under these assumptions, there are two possible operation
conditions, as shown in Fig. 4(a) and (b), respectively.
Fig. 4(a) shows the CCM operation condition. In each
switching cycle, the circuit starts with a shoot-through zero
state T
st
, during which the inductor current linearly increases.
After T
st
, the inverter switches into traditional zero state T
0
and then active states with operation mode 2, during which the
inductor current keeps decreasing and is reduced to half of the i
i
in the middle of the active states. Then, mode 3 comes into play
by keeping the inductor current almost constant and turning off
diode D. When the active states are over and the circuit is turned
into traditional zero state, mode 2 appears again, and the in-
ductor current linearly decreases until another switching action,
turning the circuit into a switch shoot-through state again (mode
1). During this whole cycle, the inductor current is continuous;
therefore, this operation condition is termed as the CCM condi-
tion. In the second half of the traditional zero state, it is also pos-
sible that the inductor current decreases to zero before another
switch shoot-through state starts and stays in mode 4 for the rest
of the cycle until the next switching action. Fig. 4(b) shows this
operation condition, which is termed as the DCM condition.
In the practical case, the current fed to the inverter bridge is
different for different active states, which will make the opera-
tion condition more complicated; however, the basic principles
and the possible operation modes are the same, and it will
be shown in the following example that the analysis with the
simplication still predicts the circuit behavior very well. In
addition, there can be more than one operation condition during
one line cycle because of the variation of i
i
over a line cycle.
2) Critical Condition: Using a small inductor can reduce
the cost, volume, and weight, but at the same time, new op-
eration modes might occur. On the other hand, using a small
inductor causes higher current stress to the switches, and more
importantly, under the new operation conditions with new op-
eration modes, the voltage to the inverter v
i
is no longer always
a constant during active states, which is always 2V
c
V
o
in the
simple operation condition. This might cause some unexpected
output harmonics. Thus, in some applications where harmonic
regulation is very crucial, one might not want the new operation
modes to appear. The critical condition of the new operation
modes becomes important to the design of the inductors.
The critical condition of the new operation modes under
maximum constant boost control with third-harmonic injection
can be described by the following inequation:
_
3M cos
2Z(

3M1)

3T
st
L
<
1
Z
cos
1
2
3M cos
2Z(

3M1)

3T
st
L
<
1
Z
cos
_


3
_
cos <
1
2
_
. (8)
When this inequation is met, the circuit starts to have new op-
eration modes. The detailed derivation of the critical condition
can be found in Appendix B.
IV. ANALYSIS EXAMPLE
The circuit characteristics will be different when the new
operation modes happen. In addition, it can be different for
different operation conditions with different combinations and
sequences of the new modes. In this section, we will analyze
the circuit characteristics under the CCM condition under max-
imum constant boost control with third-harmonic injection as
an example. A detailed process will be provided, which can also
be used to analyze the circuit under other conditions.
A. Voltage Gain
Assume that the circuit is operated under the CCM condition
throughout the whole line cycle. The voltage across the capaci-
tors in the Z-source network satises
V
c
V
o
T
0+7
T
st
T
2
st
V
c
V
o
T
0+7
T
st
V
2
o
LT
s
V
o
2T
0+7
LV
o
+ 2T
0+7
V
c
L V
c
LT
s
=
0.455M cos
Z
T
s
V
c
2T
0+7
V
c
+T
0+7
V
o
T
s
T
st
T
0+7
. (9)
With this equation and all known parameters, one can cal-
culate the output voltage and voltage stress across the inverter
switches based on the following equations:
Output rms phase voltage : V
out
=
(2V
c
V
o
)T
a1
+V
c
T
a2
2

2(T
a1
+T
a2
)
M
(10)
Switch voltage stress : V
s
=2V
c
V
o
(11)
SHEN AND PENG: CHARACTERISTICS OF Z-SOURCE INVERTER WITH SMALL INDUCTANCE OR LOW POWER FACTOR 93
where T
a1
and T
a2
are shown in Fig. 4(a) and can be calculated
by (29) and (30) in Appendix C.
B. Relationship of Voltage Gain Versus Voltage Stress
From [2] and [3], one important criterion in judging the
inverter performance is the relationship of voltage gain and
voltage stress. To evaluate the new operation conditions, a com-
parison of the voltage stress versus voltage gain relationship of
the CCM condition with the simple operation condition under
maximum constant boost control with third-harmonic injection
is provided.
For the simple operation condition, the voltage stress V
s
versus voltage gain G relationship is provided in [3], which is
V
s
= (

3G1)V
o
. (12)
For the CCM condition under maximum constant boost control,
where T
st
= (1 0.866M)T
s
and T
0+7
= 0.0386MT
s
, from
(10), the voltage gain can be calculated by
G=

2V
out
V
o
/2
=
2(V
c
(1 0.0772M) + 0.0386MV
o
)
3

3V
o
. (13)
With this voltage gain, the value of (

3G1)V
o
is
(

3G1)V
o
=(2.09 0.16M)V
c
+ (0.08M 1)V
o
. (14)
The modulation index M ranges from 0.58 to 1.15 [3],
and the voltage stress under the CCM condition can be
approximated as
V
s
= 2V
c
V
o
(

3G1)V
o
. (15)
Therefore, the voltage stress versus voltage gain relationship
of the CCM condition under maximum constant boost control
with third-harmonic injection is about the same as that in the
simple operation condition.
C. Design Guidelines
In some applications, one might want to avoid the new
modes. When the load power factor and modulation index are
not very low, one could design the inductor of the Z-source
network according to (8) to avoid the unwanted operating
modes. However, from (8), it is obvious that, when the load
power factor is very low, for example, 0, the critical condition
is always met, and the new operation condition is inevitable.
Under these extreme conditions, it is still possible to avoid
the DCM by properly choosing the parameters of the Z-source
network. The basic design method of the Z-source inverter for
the simple operation condition is given in [5]. Further rules have
to be followed to avoid the DCM condition. In all preceding
analyses, the voltage across the capacitor is assumed to be a
constant; thus, as long as the capacitance is large enough, so
that the voltage ripple across the capacitor is reasonably low,
the capacitor does not have any effect on the operation modes.
From Fig. 4, the main difference between CCM and DCM is
whether the inductor current decreases to zero during T
7
. The
inductor current during T
a2
when it almost remains constant in
the CCM condition can be calculated from
I
i
2
=
V
c
V
o
T
0+7
T
st
T
2
st
V
c
V
o
T
0+7
T
st
V
2
o
LT
s
V
o
2T
0+7
LV
o
+ 2T
0+7
V
c
L V
c
LT
s
. (16)
The detailed derivation can be found in Appendix C.
Assuming that the inverter is operating under the CCM
condition, during T
7
, the inverter is under operation mode 2,
and the voltage across the inductor is V
o
V
c
. The current drop
during this period is
I
T7
=
V
c
V
o
L
T
7

V
c
V
o
L
T
0+7
. (17)
T
7
changes over time, however, it never exceeds T
0+7
.
The following inequation is a sufcient condition to avoid
the DCM condition:
I
i
2
>
V
c
V
o
L
T
0+7
. (18)
However, this is not a very straightforward way to design the
inductor, because the capacitor voltage that is needed in the
inequation is also inductance related. A simple trial-and-error
procedure has to be followed in the design: Starting from the
initial inductance value from the design process provided in [5],
for a given load and operation condition, calculate capacitor
voltage V
c
according to (9). With the resulting V
c
, one can
calculate I
i
/2 and I
T7
from (16) and (17) and check whether
(18) is met. One needs to increase the inductance and go
through the process again if (18) is not met.
V. SIMULATION AND EXPERIMENTAL VERIFICATIONS
To verify the analysis, simulation of the Z-source inverter
with L = 50 H, V
o
= 100 V, f
s
= 10 kHz, f = 60 Hz (output
frequency), and Z = 10 + 1 mH per phase Y-connection
under maximum constant boost control with third-harmonic
injection and modulation index of 0.9 is performed. This circuit
operates in the CCM condition under these parameters. The
simulation results are shown in Fig. 5(a) and (b). Experimental
results with the same setup are shown in Fig. 6(a) and (b). In
both cases, the output line-to-line voltage V
Lab
is the voltage
across the load resistors. Comparison of simulation results
and the calculated value of the capacitor voltage at different
modulation indexes is shown in Fig. 7. From the simulation
and experimental results, we can see that the inductor current
remains constant while the dc bus voltage across the inverter
bridge decreases to the capacitor voltage in some period, which
clearly demonstrates the new operation mode 3. In addition, the
analysis results meet the simulation and experimental results
very well in terms of voltage boost. The actual operation of the
circuit is more complicated than the CCM condition previously
analyzed because of the inverter current variation over a whole
line cycle. However, from Fig. 7, the simplied analysis also
provides a quite accurate estimation of the real performance.
Fig. 7 also shows that the circuit characteristics of the CCM
conditions are quite different from those of the simple operation
condition, and the voltage boost effect of the CCM condition is
signicantly higher than the simple operation condition with
the same modulation index and the same control method.
94 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
Fig. 5. Simulation results when operating at the CCM condition (V
o
: input
voltage, i
Lz
: inductor current, V
i
: dc-link voltage across the inverter bridge,
V
Lab
: output line-to-line voltage, V
c
: capacitor voltage, I(La): load current).
VI. METHOD TO ELIMINATE THE UNWANTED
OPERATION MODES
From the preceding analysis, by proper design of the
Z-source network and proper control, one can avoid oper-
ation modes 35 to a certain degree, e.g., avoid the DCM
condition. However, it is impossible to completely avoid these
modes with the conguration shown in Fig. 1. Fig. 8 shows a
conguration where the input diode is replaced by a switch. By
using this conguration, the inverter is able to completely avoid
the unwanted operation modes by turning on switch S during
all active states and traditional zero states. Furthermore, this
conguration provides circuit bidirectional power ow ability.
VII. CONCLUSION
Analysis of the Z-source inverter with small inductance
or low power factor is given. Three new operation modes
are discussed. It is noted that, with a small inductor in the
Z-source and low load power factor, there can be very different
Fig. 6. Experimental results of the CCM condition (i
a
: load current,
V
c
: capacitor voltage, V
o
: input voltage, V
Lab
: load line-to-line voltage, V
i
:
dc-link voltage across the inverter bridge).
Fig. 7. Comparison of analyzed results and simulation results of capacitor
voltage.
SHEN AND PENG: CHARACTERISTICS OF Z-SOURCE INVERTER WITH SMALL INDUCTANCE OR LOW POWER FACTOR 95
Fig. 8. Bidirectional Z-source inverter.
operation conditions. Circuit operation conditions under tradi-
tional SVPWM control and maximum constant boost control
with third-harmonic injection are both analyzed. This paper
also analyzed the Z-source inverter performance with a small
inductor under maximum constant boost control with third-
harmonic injection as an example and provided the capacitor
voltage, output voltage, and voltage-stress/voltage-gain rela-
tionship. The analysis is veried by simulation and experimen-
tal results. It is noteworthy that the circuit can have different
combinations and sequences of operation modes with different
control methods and different circuit parameters, which yields
different circuit characteristics. However, the analysis method
and the detailed derivation method for the equations in the
appendixes can also be applied to analyze the circuit with
different control methods and different circuit parameters. A
simple method to totally eliminate the new operation modes by
replacing the diode with a switch is proposed as an option. This
conguration also provides bidirectional power ow ability.
APPENDIX A
CRITICAL CONDITION OF NEW MODES UNDER SVPWM
In the simple operation when only modes 1 and 2 occur, the
inductor currents are pure dc. The new modes only happen
when the inductor current is less than half of the current to
the inverter bridge i
i
. From the circuit, it is obvious that the
average inductor current in the Z-source is equal to the average
input current. Based on the power balance, the average inductor
current can be calculated by

I
L
=
P
V
o
. (19)
For modulation index M, load peak current I
pk
, and power
factor cos , the inductor current is
I
L
=
P
V
o
=
3
4
M cos I
pk
. (20)
The maximum current fed to the inverter bridge is
I
ipk
=
_
I
pk
cos
1
2
I
pk
cos
_


3
_
cos <
1
2
_
. (21)
The new modes happen when I
L
< (1/2)I
ipk
. As a result,
the critical condition is
_
M cos <
2
3
cos
1
2
M cos <
2
3
cos
_


3
_
cos <
1
2
_
. (22)
However, when cos < 1/2, for 0 /2 and M <
1.15, the inequation is always true; therefore, the critical condi-
tion is reduced to M cos < 2/3.
APPENDIX B
CRITICAL CONDITION OF NEW MODES UNDER
MAXIMUM CONSTANT BOOST CONTROL
WITH THIRD-HARMONIC INJECTION
Under maximum constant boost control with third-harmonic
injection, the shoot-through time T
st
in one cycle is always con-
stant. For the simple operation condition, the inductor current
linearly increases during shoot-through and linearly decreases
otherwise. The current ripple is
I
L
=
T
st
V
c
L
. (23)
The average inductor current can be calculated by (19), and
the minimum inductor current with shoot-through time of T
st
is
I
Lmin
=
P
V
o

T
st
V
c
2L
. (24)
For modulation index M in the simple operation condition, the
output-phase rms voltage V
out
can be calculated by
V
out
=
MV
o
2

2(

3M 1)
. (25)
The output power P can be expressed as
P =
3

2
V
out
I
pk
cos
=
3 cos
_
MV
o
2(

3M1)
_
2
2Z
=
3 cos
8Z
_
MV
o

3M 1
_
2
. (26)
Under this control method [3], the relationship of the modu-
lation index and the shoot-through period T
st
is
M =
2

3
_
1
T
st
T
s
_
. (27)
The new modes happen when the minimum inductor current
is less than half of the maximum current feeding to the inverter
bridge expressed in (21).
Put all these equations together, and we can get the following
critical condition:
_
3M cos
2Z(

3M1)

3T
st
L
<
1
Z
cos
1
2
3M cos
2Z(

3M1)

3T
st
L
<
1
Z
cos
_


3
_
cos <
1
2
_
. (28)
APPENDIX C
CHARACTERISTIC ANALYSIS OF THE CIRCUIT
UNDER THE CCM CONDITION
For the operation condition shown in Fig. 4(a), T
a1
is the
active state with operation mode 2, and T
a2
is the active state
with operation mode 3. For a given control method and a
modulation index, T
st
, T
0
, and T
7
are already determined. To
simplify the analysis, assume that T
st
, T
0
, T
a1
, T
a2
, and T
7
are constants throughout a whole line cycle, and T
0
= T
7
; and
the current to the inverter during active states i
i
is always a
constant. For the CCM operation condition shown in Fig. 4(a)
96 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
I
i
=
3

2
_

2V
out
Z
sin(t)
_
sin tsin
_
t
4
3

_
+ sin
_
t
2
3

__
sin
_
t
4
3

_
sin
_
t
2
3

_
sin tsin
_
t
2
3

_
=
1.29V
out
Z
cos (36)
and the voltagesecond balance of the inductor, we have the
following equations:
T
a1
=
I
n
L +V
c
T
st

i
i
2
L
V
c
V
o
T
0
(29)
T
a2
=T
s
T
st
T
0
T
a1
T
7
(30)
I
n
=
i
i
2

T
0
+T
7
2
V
c
V
o
L
(31)
where I
n
is shown in Fig. 4(a).
In the shoot-through state, the current to the inverter is
i
i
= 2i
L
. (32)
In the steady state, the capacitor voltage is constant, and
the average current that goes through the capacitor is zero;
therefore
I
n
(T
st
+T
0
+T
7
+T
a1
)+
1
2
V
c
L
T
st
(T
st
+T
0
+T
7
+T
a1
)+
i
i
2
T
a2
= 2I
n
T
st
+
V
c
L
T
2
st
+ (T
a1
+T
a2
)i
i
. (33)
Putting all equations together and solving for I
i
, we have
i
i
=
2
_
V
c
V
o
T
0+7
T
st
T
2
st
V
c
V
o
T
0+7
T
st
V
2
o
_
LT
s
V
o
2T
0+7
LV
o
+ 2T
0+7
V
c
L V
c
LT
s
. (34)
The dc-link voltage of the inverter during T
a1
is 2V
c
V
i
and V
c
during T
a2
; therefore, the output-phase rms voltage of
the inverter can be calculated by
V
out
=
(2V
c
V
o
)T
a1
+V
c
T
a2
2

2(T
a1
+T
a2
)
M. (35)
Based on the output voltage, we can calculate the average i
i
in the active states from the load side. The average current to the
inverter during the active state can be calculated as (36), shown
at the top of the page.
Putting (35) into (36) and equalizing (34) and (36), one
can get
V
c
V
o
T
0+7
T
st
T
2
st
V
c
V
o
T
0+7
T
st
V
2
o
LT
s
V
o
2T
0+7
LV
o
+ 2T
0+7
V
c
L V
c
LT
s
=
0.455M cos
Z
T
s
V
c
2T
0+7
V
c
+T
0+7
V
o
T
s
T
st
T
0+7
. (37)
One can solve (37) to get capacitor voltage V
c
under this
operation condition with maximum constant boost control with
third-harmonic injection.
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Miaosen Shen (S04M07) received the B.S. and
M.S. degrees from Zhejiang University, Hangzhou,
China, in 2000 and 2003, respectively, and the Ph.D.
degree from the Department of Electrical and Com-
puter Engineering, Michigan State University, East
Lansing, in 2007.
Since 2007, he has been with Siemens VDO Auto-
motive, Dearborn, MI, as a Senior Engineer.
Fang Zheng Peng (M92SM96F05) received
the B.S. degree from Wuhan University, Wuhan,
China, in 1983 and the M.S. and Ph.D. degrees
from Nagaoka University of Technology, Nagaoka,
Japan, in 1987 and 1990, respectively, all in electrical
engineering.
Dr. Peng is a Full Professor with the Department
of Electrical and Computer Engineering, Michigan
State University, East Lansing.