Verilog Interview Questions

How to model Transport and Inertial Delays in Verilog? Author : Rajesh Bawankule Following simple example can illustrate the concept. module delay(in,transport,inertial); input in; output transport; output inertial; reg wire transport; inertial;

// behaviour of delays always @(in) begin transport <= #1 in; end assign #1 inertial = in;

endmodule // delay The timing Diagram for input and outputs _______ __ in _____| |_____||_______ !!!!!!! !! !!!!!!!!!" "!!!!!""!!!!! !!!!!!! !!!!!!!!!" "!!!!!!!!!!!!

transport

inertial

Non blocking assignment gives you transport delay. Whenever input changes, output is immediately evaluated and kept in a event ueue and assigned to output after specified !transport! delay. "n #ontinuous assign statement the latest event overrides the earlier event in the ueue. " am attaching rudimentary testbench and its output. $ope this helps. module test; reg in; wire transport, inertial; // instantiate delay module delay my!delay(in,transport,inertial); // apply inputs initial begin in = ;

## ## #$ #% #$ #$

in = 1; in = ; in = 1; in = ; in = 1; &finish;

end // monitor signals initial begin &monitor(&time,' in = (b transport = (b inertial = (b', in,transport, inertial); end endmodule // test log file )ompiling sour*e file 'delay+v' ,ighest level modulestest in = transport = 1 in = transport = # in = 1 transport = $ in = 1 transport = / in = transport = % in = transport = 0 in = 1 transport = 0% in = transport = 1 in = transport = 1% in = transport = 1 % in = 1 transport = 11% in = 1 transport = 2$% 'delay+v'- &finish at simulation time 11 simulation events . inertial inertial inertial 1 inertial 1 inertial inertial inertial inertial 1 inertial inertial inertial 1 inertial 1$% = = = = = = = = = = = = . 1 1

How to display the system date in $display or $write?

%&nswers contributed by 'wapna(it )ittra and Noman $assan* 'upport of +system%* task in ,erilog-./, N#-,erilog and ,#' not only allows you to display the system date but also gives you the ability to call any command that you would normally type on the 0N". prompt %# executable, script, standard 0N". command etc.*, and would make sense in executing from within ,erilog source code. +system is not an "111 'tandard%2345-2667*, but is supported by both ./ and ,#'. 8ou could read back in the output of +system, by writing it to another file and reading it back in using +readmemh%* as illustrated in following example. module top; reg 3#$- 4 today 3 -14;

initial begin &system('date 5(m(d(y 6 date!file'); // output is 0$177 for 8uly $1st 1777 &readmemh('date!file', today); &display('9oday is- (.', today3 4); end endmodule

How to display bold characters? 0sing following program bold characters can be displayed. Note that this program takes help of 0N". facilities. This may not work on 9# based simulators. module bold; initial begin &display &display &display &display &display (':ormal 9e.t'); ('; $$31m<old 9e.t'); ('; $$3m=wit*h ba*> to :ormal 9e.t+++++'); ('; $$30m?nverse 9e.t+'); ('; $$3m=wit*h ba*> to :ormal 9e.t+++++');

&display ('; $$31m<old 9e.t ; $$3mfollowed by ; $$30m?nverse te.t ; $$3m'); end

endmodule Sample Verilog Questions asked in Interviews. Please contribute with your questions. I you are looking or answers please re er to website Site !"Q #i erentiate between Inter assignment #elay and Inertial #elay. $hat are the di erent State machine Styles % $hich is better % &'plain disadvantages and advantages. $hat is the di erence between the ollowing lines o code %

reg()* +(, reg- . reg/ * + (, reg0 . $hat is the value o Var( a ter the ollowing assignment %

reg Var(. initial begin Var()* 121

end In the below code3 "ssume that this statement models a lop with async reset. In this3 how does the synthesis tool3 igure out which is clock and which is reset. Is the statements within the always block is necessary to ind out this or not %
1 2 3 4 5 6 # % + 1* 11 12 module which_clock (x,y,q,d); input x,y,d; output q; reg q; lw y! " (po!edge x or po!edge y) i$ (x) q &' 1()*; el!e q &' d; endmodule

$hat is the output o the two codes below %

1 2 3 4 5 6 # % + 1* 11 12 13 14 15 16 1# 1% 1+ 2* 21 22 1 2 3 4 5 6 # % + 1* 11 module que!t_$or_out(); integer i; reg clk; initi l )egin clk ' *; ,4 -$ini!h; end lw y! ,1 clk ' . clk;

lw y! " (po!edge clk) )egin / 012_134 $or (i'*; i & %; i ' i 5 1) )egin i$ (i '' 5) )egin di! )le 012_134; end -di!pl y (67urrent i / 8g6,i); end end endmodule module que!t_$or_in(); integer i; reg clk; initi l )egin clk ' *; ,4 -$ini!h; end lw y! ,1 clk ' . clk;

12 13 lw y! " (po!edge clk) 14 )egin 15 $or (i'*; i & %; i ' i 5 1) )egin / 012_9: 16 i$ (i '' 5) )egin 1# di! )le 012_9:; 1% end 1+ -di!pl y (67urrent i / 8g6,i); 2* end 21 end 22 endmodule

$hy cannot initial statement be synthesi4eable % 5onsider a -6( mu'. what will the output ! be i the Select 7sel8 is 191 %

$hat is the di erence between blocking and nonblocking assignments % $hat is the di erence between wire and reg data type % $rite code or async reset #2!lip2!lop. $rite code or -6( :;9 using di erent coding methods. $rite code or a parallel encoder and a priority encoder. $hat is the di erence between *** and ** % $hat is de param used or % $hat is the di erence between unary and logical operators % $hat is the di erence between tasks and unctions % $hat is the di erence between transport and inertial delays % $hat is the di erence between case' and case statements % $hat is the di erence between <monitor and <display % $hat is the di erence between compiled3 interpreted3 event based and cycle based simulators % $hat is code coverage and what are the di erent types o code coverage that one does %

How do I generate clock in Verilog ?

=here are many ways to generate clock in Verilog. you could use one o the ollowing methods6 Method #1
1 initi l )egin 2 clk ' *; 3 end 4 5 lw y! )egin 6 ,5 clk ' ;clk; # % end

Method #2
1 initi l )egin 2 clk ' *; 3 $ore<er )egin 4 ,5 clk ' ;clk; 5 end 6 end

Method #3
1 initi l )egin 2 clk ' *; 3 end 4 5 lw y! )egin 6 ,5 clk ' *; # ,5 clk ' 1; % end

=here are many ways to generate clocks6 you may introduce >itter3 change duty cycle. How do I test my design xy ? =o test or veri y or validate any design3 you need to have a test bench. writing test benches is as di icult as designing itsel . Please re er to the Verilog tutorial section in 1"rt o $riting =est ?ench1 or more details. !hat is the di""erence #etween wire and reg ? Please re er to tidbits section or the di erence between wire and reg.

!hat is the di""erence #etween #locking and non#locking assignment ?

Please re er to tidbits section or di erence between blocking and nonblocking statement. How do I write a state machine in Verilog ? Please re er to tidbits section or 1writing !S: in Verilog1. How do I avoid $atch in Verilog ? @atches are always bad 7I donAt like that statement8. latches are caused when all the possible cases o assignment to variable are not covered. $ell this rule applies to combinational blocks 7blocks with edge sensitive lists are sequential blocks8. letAs look at the ollowing e'ample. %ad &ode
1 2 3 4 5 6 lw y! " () or c) )egin i$ ()) )egin ' c; end end

In the code above3 value o a is retained3 and it gets changed only when b is set to A(A. =his results in a latch. 7Beed to phrase it right8 'ood &ode #1
1 2 3 4 5 6 # lw y! " () or c) )egin ' *; i$ ()) )egin ' c; end end

In the code above3 no matter what the value o b is3 a gets value o A,A irst and i b is set to A(A and c is set to A(A3 only then a gets A(A. =his is the best way to avoid latches. 'ood &ode #2
1 2 3 4 5 6 # % lw y! " () or c) )egin i$ ()) )egin ' c; end el!e )egin ' *; end end

In the above code3 all the possible cases are covered 7i.e. b * ( and b * , case8. How does this xy code get synthesi ed ? $ell it is a long story. let me cover that in the synthesis part o Verilog tutorial. Cou can re er to "ctel D#@ coding Style. Ene simple logic is6 any code inside always blocks with edge sensitive sensitivity list3 results in lip2 lops and assign. inside level sensitive always blocks results in combo logic. How do I im(lement Memories in Verilog ? Cou can implement them by declaring -2dimension arrays. :ore details can be ound in the Verilog tutorial section 1:odeling memories and !S:1. How do I read and write "rom a "ile ? =o Fead rom a ile we use <readmemh3 where h stands or he' decimal. !or writing we use <writememh3 < display3 < monitor. Cou could re er to the Verilog tutorial section or more details. !hat is this )timescale com(iler directive ? Gtimescale is used or speci ying the re erence time unit or the simulator. Synta' o the Gtimescale is as below6 Gtimescale )re erence_time_unitHI)time_precisionH e'ample 6 Gtimescale (,nsI(ns =imescale directive tends to make more sense at gatelevel simulation than at F=@ simulation. &an we mix #locking and non#locking in one always #lock ? Ces3 we can have both blocking and nonblocking code in same always block. Some things that one should know to use this are6

?locking assignments are treated as combinational logic. Ene should not assign a variable in the same always block with both blocking and nonblocking assignments. Bot all synthesis tools support this. 7#esign compiler supports this8.

$hat is the output o "B# gate in the circuit below3 when " and ? are as in wave orm% =p is the gate delay o respective gate.

Identi y the circuit below3 and its limitation.

$hat is the current through the resistor F( 7Ic8 %

Fe erring to the diagram below3 brie ly e'plain what will happen i the propagation delay o the clock signal in path ? is much too high compared to path ". Dow do we solve this problem i the propagation delay in path ? can not be reduced %

$hat is the unction o a # lip2 lop3 whose inverted output is connected to its input %

#esign a circuit to divide input requency by -.

#esign a divide2by2/ sequential circuit with J,K+/L. duty cycle.

#esign a divide2by2J sequential circuit with J,K+/L. duty cycle.

$hat are the di erent types o adder implementations %

#raw a =ransmission Mate2based #2@atch.

Mive the truth table or a Dal "dder. Mive a gate level implementation o it.

$hat is the purpose o the bu er in the circuit below3 is it necessaryIredundant to have a bu er %

$hat is the output o the circuit below3 assuming that value o A9A is not known %

5onsider a circular disk as shown in the igure below with two sensors mounted 93 C and a blue shade painted on the disk or an angle o 0J degree. #esign a circuit with minimum number o gates to detect the direction o rotation.

#esign an EF gate rom -6( :;9.

#esign an 9EF gate rom -6( :;9 and a BE= gate

$hat is the di erence between a @"=5D and a !@IP2!@EP %

@atch is a level sensitive device while lip2 lop is an edge sensitive device. @atch is sensitive to glitches on enable pin3 whereas lip2 lop is immune to glitches. @atches take less gates 7also less power8 to implement than lip2 lops. @atches are aster than lip2 lops.

#esign a # !lip2!lop rom two latches.

#esign a - bit counter using # !lip2!lop.

$hat are the two types o delays in any digital system %

#esign a =ransparent @atch using a -6( :u'.

#esign a 06( :u' using -6( :u'es and some combo logic.

$hat is metastable state % Dow does it occur %

$hat is metastability %

#esign a /6N decoder

#esign a !S: to detect sequence 1(,(1 in input sequence.

5onvert B"B# gate into Inverter3 in two di erent ways.

#esign a # and = lip lop using -6( mu'. use o other components not allowed3 >ust the mu'.

#esign a divide by two counter using #2@atch.

#esign # @atch rom SF lip2 lop.

#e ine 5lock Skew 3 Begative 5lock Skew3 Positive 5lock Skew.

$hat is Face 5ondition %

#esign a 0 bit Mray 5ounter.

#esign 02bit Synchronous counter3 "synchronous counter.

#esign a (O byte "synchronous !I!E.

$hat is the di erence between an &&PFE: and a !@"SD %

$hat is the di erence between a B"B#2based !lash and a BEF2based !lash %

Cou are given a (,, :D4 clock. #esign a //./ :D4 clock with and without J,K+/L. duty cycle.

#esign a Fead on Feset System %

$hich one is superior6 "synchronous Feset or Synchronous Feset % &'plain.

#esign a State machine or =ra ic 5ontrol at a !our point Punction.

$hat are !I!EAs% 5an you draw the block diagram o !I!E% 5ould you modi y it to make it asynchronous !I!E % Dow can you generate random sequences in digital circuits%

@- Ahat is the differen*e between a Berilog task and a Berilog functionC D-=he

ollowing rules distinguish tasks rom unctions6

D $unction shall e.e*ute in one simulation time unit; a t !k *an *ontain timeE*ontrolling statements+ D $unction *annot enable a tas>; a t !k *an enable other tas>s or fun*tions+ D $unction shall have at least one input type argument and shall not have an output or inout type argument; a t !k *an have Fero or more arguments of any type+ D $unction shall return a single value; a t !k shall not return a value+ Verilog Answer 2 @- Given the following Berilog *ode, what value of 'a' is displayedC always @(*l>) begin a = ; a <= 1; &display(a); end D- 9his is a tri*>y oneH Berilog s*heduling semanti*s basi*ally imply a fourElevel deep Iueue for the *urrent simulation time-

1#$/-

D*tive Jvents ?na*tive Jvents :onE<lo*>ing Dssign Kpdates Lonitor Jvents

(blo*>ing statements) (# delays, et*) (nonEblo*>ing statements) (&display, &monitor, et*)+

=in*e the ' ' *' is an a*tive event, it is s*heduled into the 1st 'Iueue'+ 9he ' &' 1' is a nonEblo*>ing event, so itMs pla*ed into the $rd Iueue+ Ninally, the display statement is pla*ed into the /th Iueue+ Only events in the a*tive Iueue are *ompleted this sim *y*le, so the ' ' *' happens, and then the display shows a = + ?f we were to loo> at the value of a in the ne.t sim *y*le, it would show 1+

Verilog Answer 3 @- Given the following snipet of Berilog *ode, draw out the waveforms for *l> and a always @(*l>) begin a = ; #% a = 1; end D1 *l> !!!" a !!! $ "!!!" !!! % "!!!" !!! 0 "!!!" !!! 7 "!!!" !!! 11 "!!!" !!! 1$ "!!!" !!! "!!!

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

9his obviously is not what we wanted, so to get *loser, you *ould use ' lw y! " (po!edge clk)' instead, and youMd get 1 *l> !!!" a !!! $ "!!!" !!! % "!!!" !!! 0 "!!!" !!! !!!!!!!!!!!!!!!!!!!!!!!" "!!!!!!!!!!!!!!!!!!!" Verilog Answer 4 @- Ahat is the differen*e between the following two lines of Berilog *odeC #% a = b; !!! 7 "!!!" !!! 11 "!!!" !!! 1$ "!!!" !!! "!!!!!!! !!! "!!!

a = #% b; D,5 ' ); Aait five time units before doing the a*tion for 'a = b;'+ 9he value assigned to will be the value of ) % time units 9he value of ) is *al*ulated and stored in an internal temp Dfter five time units, assign this stored value to +

hen*e+ ' ,5 ); register+

Verilog Answer 6 @- Ahat is the differen*e between-

* = foo C a - b; and if (foo) * = a; else * = b; D9he C merges answers if the *ondition is '.', so for instan*e if foo = 1Mb., a = Mb1 , and b = Mb11, youMd get * = Mb1.+ On the other hand, i$ treats Ps or Qs as ND2=J, so youMd always get * = b+ (<a*>) Verilog Answer 7 @- Ksing the given, draw the waveforms for the following versions of a (ea*h version is separate, i+e+ not in the same run)reg *l>; reg a; always #1 *l> = R*l>;

(1) always @(*l>) a = #% *l>; (#) always @(*l>) a = #1 *l>; ($) always @(*l>) a = #1% *l>; :ow, *hange a to wire, and draw for(/) assign #% a = *l>; (%) assign #1 a = *l>; (S) assign #1% a = *l>;

D1 *l> !!!" !!! $ "!!!" !!! % "!!!" !!! 0 "!!!" !!! 7 "!!!" !!! 11 "!!!" !!! 1$ "!!!" !!! "!!! "! !!!

!!! (1)a !!!!" (#)a !!!!!!" "!!!" !!!

!!! "!!!" !!!

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!!! "!!!" !!!

!!! "!!!" !!!

!!! "!!!" !!!

!!!

"!!!"

"!!!"

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($)a !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! =in*e the #delay *an*els future events when it a*tivates, any delay over the a*tual 1/# period time of the *l> flatlines+++ Aith *hanging a to a wire and using 8ust a**omplish the same thing+++ 1 *l> !!!" (/)a !!!!" !!! !!! $ "!!!" "!!!" !!! !!! % "!!!" "!!!" !!! !!! 0 "!!!" "!!!" !!! !!! !!ign, we 7 "!!!" "!!!" 11 "!!!" !!! "!!!" 1$ "!!!" !!! "!!!"

!!!

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!!! (%)a !!!!!!" "!!!"

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(S)a !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Vera Answer 1 @- Ahat is the differen*e between a Vera tas> and a Verilog tas>C DVera Answer 2 @- Ahat is the differen*e between running the following snipet of *ode on Berilog vs BeraC for> T tas>!one(); #1 ; tas>!one(); U tas> tas>!one() T

*nt = ; for (i = ; i < % ; i55) T *nt55; U U D(<a*>) Programming Answer 1

@- Given &a = '%,E$,0, ,E%,1#'; Arite a program to find the lowest number in the string+ D== >?@9: A?2B C:9A?4 &a = '%,E%,E1, ,1#,E$'; (@temp) = split (/,/, &a); &lowest = &temp3 4; for (&i= ; &i<S; &i55) T if (&temp3&i4 < &lowest) T &lowest = &temp3&i4; U U print '2owest value found was- &lowest;n'; == ?:D A?2B C:9A?4 :14?- Vou *ould also repla*e the for loop with thisforea*h &value (@temp) T if (&value < &lowest) T &lowest = &value; U U Programming Answer 2 @- Arite the *ode to sort an array of integers+ D=E >?@9: 7 C:9A?4 E= void bubblesort (int .34, int lim) T int i, 8, temp; for (i = ; i < lim; i55) T for (8 = ; 8 < limE1Ei; 855) T

if (.384 6 .38514) T temp = .384; .384 = .38514; .38514 = temp; U U /W /W /W /W end end end end if for j for i bubblesort W/ W/ W/ W/

U U

=E ?:D 7 C:9A?4 E= =ome optimiFations that *an be made are that a singleEelement array does not need to be sorted; therefore, the 'for i' loop only needs to go from to limF1+ :e.t, if at some point during the iterations, we go through the entire array A?9,OK9 performing a swap, the *omplete array has been sorted, and we do not need to *ontinue+ Ae *an wat*h for this by adding a variable to >eep tra*> of whether we have performed a swap on this iteration+ Programming Answer 3 @- Arite the *ode for finding the fa*torial of a passed integer+ Kse a re*ursive subroutine+ D== >?@9: A?2B C:9A?4 sub fa*torial T my &y = shift; if ( &y 6 1 ) T return &y W Xfa*torial( &y E 1 ); U else T return 1; U U == ?:D A?2B C:9A?4 Programming Answer 4 @- ?n ), e.plain the differen*e between the G operator and the E operator+ DG is the address operator, and it *reates pointer values+ E is the indire*tion operator, and it dereferen*es pointers to a**ess the ob8e*t pointed to+ Example:

?n the following e.ample, the pointer ip is assigned the address of variable i (Gi)+ Dfter that assignment, the e.pression Eip refers to the same ob8e*t denoted by iint i, H, Eip; ip ' Gi; i ' 22; H ' Eip; =E H now h ! the < lue 22 E= Eip ' 1#; =E i now h ! the < lue 1# E= Programming Answer 5 @- Arite a fun*tion to determine whether a string is a palindrome (same forward as reverse, su*h as 'radar' or 'mom')+ D=E >?@9: 7 C:9A?4 E= #in*lude <string+h6 void is!palindrome ( *har Win!str ) T *har Wtmp!str; int i, length; length = strlen ( Win!str ); for ( i = ; i < length; i55 ) T Wtmp!str3lengthEiE14 = Win!str3i4; U if ( == str*mp ( Wtmp!str, Win!str ) ) printf ('=tring is a palindrome'); else printf ('=tring is not a palindrome'); U =E ?:D 7 C:9A?4 E= Programming Answer 6 @- Arite a fun*tion to output a diamond shape a**ording to the given (odd) input+ Examples?nput is % E EEE EEEEE EEE E ?nput is 0 E EEE EEEEE EEEEEEE EEEEE

EEE E D,,, >?@9: A?2B C:9A?4 ,,, for (&i = 1; &i <= ((&input W #) E 1); &i 5= #) T if (&i <= &input) T &stars = &i; &spa*es = (&input E &stars) / #; while (&spa*esEE) T print ' '; U while (&starsEE) T print 'W'; U U else T &spa*es = (&i E &input) / #; &stars = &input E (&spa*es W #); while (&spa*esEE) T print ' '; U while (&starsEE) T print 'W'; U U print ';n'; U ,,, ?:D A?2B C:9A?4 ,,, General Answer 1 @- Given the following N?NO and rules, how deep does the N?NO need to be to prevent underflowing or overflowingC

YK2J=1) freIuen*y(*l>!D) = freIuen*y(*l>!<) / / #) period(en!<) = period(*l>!D) W 1 $) duty!*y*le(en!<) = #%( DDssume *l>!< = 1 L,F (1 ns)

Nrom (1), *l>!D = #%L,F (/ ns) Nrom (#), period(en!<) = / ns W 1 = / ns, but we only output for 1 ns, due to ($), so $ ns of the enable we are doing no output wor>+ 9herefore, N?NO siFe = $ General Answer 2 @- Zraw the state diagram to output a '1' for one *y*le if the seIuen*e ' 11 ' shows up (the leading used in more than one seIuen*e)+ Ds *annot be ns// ns = 0% entries+

General Answer 3 @- J.plain the differen*es between 'Zire*t Lapped', 'Nully Dsso*iative', and '=et Dsso*iative' *a*hes+ D-

?f ea*h blo*> has only one pla*e it *an appear in the *a*he, the *a*he is said to be direct mapped+ 9he mapping is usually (blo*>Eframe address) modulo (number of blo*>s in *a*he)+ ?f a blo*> *an be pla*ed anywhere in the *a*he, the *a*he is said to be f ll! associati"e+ ?f a blo*> *an be pla*ed in a restri*ted set of pla*es in the *a*he, the *a*he is said to be set associati"e+ D set is a group of two or more blo*>s in the *a*he+ D blo*> is first mapped onto a set, and then the blo*> *an be pla*ed anywhere within the set+ 9he set is usually *hosen by bit sele*tion; that is, (blo*>Eframe address) modulo (number of !et! in *a*he)+ ?f there are n blo*>s in a set, the *a*he pla*ement is *alled n#wa! set associati"e+ General Answer 4 @- Zesign a fourEinput :D:Z gate using only twoEinput :D:Z gates+ D<asi*ally, you *an tie the inputs of a :D:Z gate together to get an inverter, so+++

(<a*>) General Answer 5 @- Zraw the state diagram for a *ir*uit that outputs a '1' if the aggregate serial binary input is divisible by %+ is 1, , 1, we Nor instan*e, if the input stream

output a '1' (sin*e 1 1 is %)+ ?f we then get a ' ', the aggregate total is 1 , so we output another '1' (and so on)+ DAe donMt need to >eep tra*> of the entire string of numbers E if something

is divisible by %, it doesnMt matter if itMs #% or , so we *an 8ust reset to + =o we really only need to >eep tra*> of ' ' through '/'+

*rom +,I&-co-in
1. !rite a verilog code to swa( contents o" two registers with and without a tem(orary register? $ith temp reg . always Q 7posedge clock8 begin temp*b. b*a. a*temp. end $ithout temp reg. always Q 7posedge clock8 begin a )* b. b )* a. end 2. /i""erence #etween #locking and non0#locking?7Verilog interview questions that is most commonly asked8 =he Verilog language has two orms o the procedural assignment statement6 blocking and non2blocking. =he two are distinguished by the * and )* assignment operators. =he blocking assignment statement 7* operator8 acts much like in traditional programming

languages. =he whole statement is done be ore control passes on to the ne't statement. =he non2blocking 7)* operator8 evaluates all the right2hand sides or the current time unit and assigns the le t2hand sides at the end o the time unit. !or e'ample3 the ollowing Verilog program II testing blocking and non2blocking assignment module blocking. reg R,6LS "3 ?. initial begin6 init( " * /. +( " * " T (. II blocking procedural assignment ? * " T (. <display71?locking6 "* Ub ?* Ub13 "3 ? 8. " * /. +( " )* " T (. II non2blocking procedural assignment ? )* " T (. +( <display71Bon2blocking6 "* Ub ?* Ub13 "3 ? 8. end endmodule produces the ollowing output6 ?locking6 "* ,,,,,(,, ?* ,,,,,(,( Bon2blocking6 "* ,,,,,(,, ?* ,,,,,(,, =he e ect is or all the non2blocking assignments to use the old values o the variables at the beginning o the current time unit and to assign the registers new values at the end o the current time unit. =his re lects how register trans ers occur in some hardware systems. blocking procedural assignment is used or combinational logic and non2blocking procedural assignment or sequential &lick to view more

3. /i""erence #etween task and "unction? !unction6 " unction is unable to enable a task however unctions can enable other unctions. " unction will carry out its required duty in 4ero simulation time. 7 =he program time will not be incremented during the unction routine8 $ithin a unction3 no event3 delay or timing control statements are permitted In the invocation o a unction their must be at least one argument to be passed. !unctions will only return a single value and can not use either output or inout

statements. =asks6 =asks are capable o enabling a unction as well as enabling other versions o a =ask =asks also run with a 4ero simulation however they can i required be e'ecuted in a non 4ero simulation time. =asks are allowed to contain any o these statements. " task is allowed to use 4ero or more arguments which are o type output3 input or inout. " =ask is unable to return a value but has the acility to pass multiple values via the output and inout statements . 1. /i""erence #etween inter statement and intra statement delay? IIde ine register variables reg a3 b3 c. IIintra assignment delays initial begin a * ,. c * ,. b * +J a T c. II=ake value o a and c at the time*,3 evaluate IIa T c and then wait J time units to assign value IIto b. end II&quivalent method with temporary variables and regular delay control initial begin a * ,. c * ,. temp_ac * a T c. +J b * temp_ac. II=ake value o a T c at the current time and IIstore it in a temporary variable. &ven though a and c IImight change between , and J3 IIthe value assigned to b at time J is una ected. end 2. !hat is delta simulation time? 3. /i""erence #etween 4monitor54dis(lay 6 4stro#e? =hese commands have the same synta'3 and display te't on the screen during simulation. =hey are much less convenient than wave orm display tools like cwaves%. <display and <strobe display once every time they are e'ecuted3 whereas <monitor displays every time one o its parameters changes.

=he di erence between <display and <strobe is that <strobe displays the parameters at the very end o the current simulation time unit rather than e'actly where it is e'ecuted. =he ormat string is like that in 5I5TT3 and may contain ormat characters. !ormat characters include Ud 7decimal83 Uh 7he'adecimal83 Ub 7binary83 Uc 7character83 Us 7string8 and Ut 7time83 Um 7hierarchy level8. UJd3 UJb etc. would give e'actly J spaces or the number instead o the space needed. "ppend b3 h3 o to the task name to change de ault ormat to binary3 octal or he'adecimal. Synta'6 <display 7V ormat_stringW3 par_(3 par_-3 ... 8. <strobe 7V ormat_stringW3 par_(3 par_-3 ... 8. <monitor 7V ormat_stringW3 par_(3 par_-3 ... 8. 7. !hat is di""erence #etween Verilog "ull case and (arallel case? " 1 ull1 case statement is a case statement in which all possible case2e'pression binary patterns can be matched to a case item or to a case de ault. I a case statement does not include a case de ault and i it is possible to ind a binary case e'pression that does not match any o the de ined case items3 the case statement is not 1 ull.1 " 1parallel1 case statement is a case statement in which it is only possible to match a case e'pression to one and only one case item. I it is possible to ind a case e'pression that would match more than one case item3 the matching case items are called 1overlapping1 case items and the case statement is not 1parallel.1 8. !hat is meant #y in"erring latches5how to avoid it? 5onsider the ollowing 6 always Q7s( or s, or i, or i( or i- or i/8 case 7Xs(3 s,Y8 -Ad, 6 out * i,. -Ad( 6 out * i(. -Ad- 6 out * i-. endcase in a case statement i all the possible combinations are not compared and de ault is also not speci ied like in e'ample above a latch will be in erred 3a latch is in erred because to reproduce the previous value when unknown branch is speci ied. !or e'ample in above case i Xs(3s,Y*/ 3 the previous stored value is reproduced or this storing a latch is in erred. =he same may be observed in I! statement in case an &@S& I! is not speci ied. =o avoid in erring latches make sure that all the cases are mentioned i not de ault condition is provided. 9. :ell me how #locking and non #locking statements get executed? &'ecution o blocking assignments can be viewed as a one2step process6

(. &valuate the FDS 7right2hand side equation8 and update the @DS 7le t2hand side e'pression8 o the blocking assignment without interruption rom any other Verilog statement. " blocking assignment 1blocks1 trailing assignments in the same always block rom occurring until a ter the current assignment has been completed &'ecution o nonblocking assignments can be viewed as a two2step process6 (. &valuate the FDS o nonblocking statements at the beginning o the time step. -. ;pdate the @DS o nonblocking statements at the end o the time step. 1;. Varia#le and signal which will #e <(dated "irst? Signals 11. !hat is sensitivity list? =he sensitivity list indicates that when a change occurs to any one o elements in the list change3 beginZend statement inside that always block will get e'ecuted. 12. In a (ure com#inational circuit is it necessary to mention all the in(uts in sensitivity disk? i yes3 why% Ces in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch. 13. :ell me structure o" Verilog code you "ollow? " good template or your Verilog ile is shown below. II timescale directive tells the simulator the base units and precision o the simulation Gtimescale ( ns I (, ps module name 7input and outputs8. II parameter declarations parameter parameter_name * parameter value. II Input output declarations input in(. input in-. II single bit inputs output Rmsb6lsbS out. II a bus output II internal signal register type declaration 2 register types 7only assigned within always statements8. reg register variable (. reg Rmsb6lsbS register variable -. II internal signal. net type declaration 2 7only assigned outside always statements8 wire net variable (. II hierarchy 2 instantiating another module re erence name instance name 7 .pin( 7net(83 .pin- 7net-83

. .pinn 7netn8 8. II synchronous procedures always Q 7posedge clock8 begin . end II combinatinal procedures always Q 7signal( or signal- or signal/8 begin . end assign net variable * combinational logic. endmodule 11. /i""erence #etween Verilog and vhdl? 5ompilation VD#@. :ultiple design2units 7entityIarchitecture pairs83 that reside in the same system ile3 may be separately compiled i so desired. Dowever3 it is good design practice to keep each design unit in itAs own system ile in which case separate compilation should not be an issue. Verilog. =he Verilog language is still rooted in itAs native interpretative mode. 5ompilation is a means o speeding up simulation3 but has not changed the original nature o the language. "s a result care must be taken with both the compilation order o code written in a single ile and the compilation order o multiple iles. Simulation results can change by simply changing the order o compilation. #ata types VD#@. " multitude o language or user de ined data types can be used. =his may mean dedicated conversion unctions are needed to convert ob>ects rom one type to another. =he choice o which data types to use should be considered wisely3 especially enumerated 7abstract8 data types. =his will make models easier to write3 clearer to read and avoid unnecessary conversion unctions that can clutter the code. VD#@ may be pre erred because it allows a multitude o language or user de ined data types to be used. Verilog. 5ompared to VD#@3 Verilog data types a re very simple3 easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. ;nlike VD#@3 all data types used in a Verilog model are de ined by the Verilog language and not by the user. =here are net data types3 or e'ample wire3 and a register data type called reg. " model with a signal whose type is one o the net data types has a corresponding electrical wire in the implied modeled circuit. Eb>ects3 that is signals3

o type reg hold their value over simulation delta cycles and should not be con used with the modeling o a hardware register. Verilog may be pre erred because o itAs simplicity. #esign reusability VD#@. Procedures and unctions may be placed in a package so that they are avail able to any design2unit that wishes to use them. Verilog. =here is no concept o packages in Verilog. !unctions and procedures used within a model must be de ined in the module. =o make unctions and procedures generally accessible rom di erent module statements the unctions and procedures must be placed in a separate system ile and included using the Ginclude compiler directive. 12. !hat are di""erent styles o" Verilog coding I mean gate0level5continuous level and others ex(lain in detail? 13. &an you tell me some o" system tasks and their (ur(ose? <display3 <displayb3 <displayh3 <displayo3 <write3 <writeb3 <writeh3 <writeo. =he most use ul o these is <display.=his can be used or displaying strings3 e'pression or values o variables. Dere are some e'amples o usage. <display71Dello oni18. 222 output6 Dello oni <display7<time8 II current simulation time. 222 output6 0O, counter * 0Ab(,. <display71 =he count is Ub13 counter8. 222 output6 =he count is ,,(, <reset resets the simulation back to time ,. <stop halts the simulator and puts it in interactive mode where the user can enter commands. < inish e'its the simulator back to the operating system 17. &an you list out some o" enhancements in Verilog 2;;1? In earlier version o Verilog 3we use AorA to speci y more than one element in sensitivity list . In Verilog -,,(3 we can use comma as shown in the e'ample below. II Verilog -k e'ample or usage o comma always Q 7i(3i-3i/3i08 Verilog -,,( allows us to use star in sensitive list instead o listing all the variables in FDS o combo logics . =his removes typo mistakes and thus avoids simulation and synthesis mismatches3 Verilog -,,( allows port direction and data type in the port list o modules as shown in the e'ample below module memory 7

input r3 input wr3 input RL6,S data_in3 input R/6,S addr3 output RL6,S data_out 8. 18.!rite a Verilog code "or synchronous and asynchronous reset? Synchronous reset3 synchronous means clock dependent so reset must not be present in sensitivity disk eg6 always Q 7posedge clk 8 begin i 7reset8 . . . end "synchronous means clock independent so reset must be present in sensitivity list. &g "lways Q7posedge clock or posedge reset8 begin i 7reset8 . . . end 19. !hat is (li?why is it used? Programming @anguage Inter ace 7P@I8 o Verilog D#@ is a mechanism to inter ace Verilog programs with programs written in 5 language. It also provides mechanism to access internal databases o the simulator rom the 5 program. P@I is used or implementing system calls which would have been hard to do otherwise 7or impossible8 using Verilog synta'. Er3 in other words3 you can take advantage o both the paradigms 2 parallel and hardware related eatures o Verilog and sequential low o 5 2 using P@I. 2;. :here is a triangle and on it there are 3 ants one on each corner and are "ree to move along sides o" triangle what is (ro#a#ility that they will collide? "nts can move only along edges o triangle in either o direction3 let[s say one is represented by ( and another by ,3 since there are / sides eight combinations are possible3 when all ants are going in same direction they won[t collide that is ((( or ,,, so probability o collision is -IN*(I0 21. :ell me a#out "ile I=>? 21.!hat is di""erence #etween "ree e de(osit and "orce? <deposit7variable3 value8.

=his system task sets a Verilog register or net to the speci ied value. variable is the register or net to be changed. value is the new value or the register or net. =he value remains until there is a subsequent driver transaction or another <deposit task or the same register or net. =his system task operates identically to the :odelSim orce 2deposit command. =he orce command has 2 ree4e3 2drive3 and 2deposit options. $hen none o these is speci ied3 then 2 ree4e is assumed or unresolved signals and 2drive is assumed or resolved signals. =his is designed to provide compatibility with orce iles. ?ut i you pre er 2 ree4e as the de ault or both resolved and unresolved signals. Verilog interview Questions 22.!ill case in"er (riority register i" yes how give an exam(le? yes case can in er priority register depending on coding style reg r. II Priority encoded mu'3 always Q 7a or b or c or select-8 begin r * c. case 7select-8 -Ab,,6 r * a. -Ab,(6 r * b. endcase end Verilog interview Questions 23.&asex5 di""erence5which is (re"era#le5why? 5"S&\ 6 Special version o the case statement which uses a \ logic value to represent donAt2care bits. 5"S&9 6 Special version o the case statement which uses \ or 9 logic values to represent donAt2 care bits. 5"S&\ should be used or case statements with wildcard don[t cares3 otherwise use o 5"S& is required. 5"S&9 should never be used. =his is because6 #on[t cares are not allowed in the 1case1 statement. =here ore case' or case4 are required. 5ase' will automatically match any ' or 4 with anything in the case statement. 5ase4 will only match 4[s 22 '[s require an absolute match. Verilog interview Questions 21.'iven the "ollowing Verilog code5 what value o" ?a? is dis(layed?

always Q7clk8 begin a * ,. a )* (. <display7a8. end =his is a tricky one] Verilog scheduling semantics basically imply a our2level deep queue or the current simulation time6 (6 "ctive &vents 7blocking statements8 -6 Inactive &vents 7+, delays3 etc8 /6 Bon2?locking "ssign ;pdates 7non2blocking statements8 06 :onitor &vents 7<display3 <monitor3 etc8. Since the 1a * ,1 is an active event3 it is scheduled into the (st 1queue1. =he 1a )* (1 is a non2blocking event3 so itAs placed into the /rd queue. !inally3 the display statement is placed into the 0th queue. Enly events in the active queue are completed this sim cycle3 so the 1a * ,1 happens3 and then the display shows a * ,. I we were to look at the value o a in the ne't sim cycle3 it would show (. 22. !hat is the di""erence #etween the "ollowing two lines o" Verilog code? +J a * b. a * +J b. +J a * b. $ait ive time units be ore doing the action or 1a * b.1. a * +J b. =he value o b is calculated and stored in an internal temp register3" ter ive time units3 assign this stored value to a. 23.!hat is the di""erence #etween@ c A "oo ? a @ #B and i" C"oo. c A aB else c A #B =he % merges answers i the condition is 1'13 so or instance i oo * (Ab'3 a * Ab(,3 and b * Ab((3 youAd get c * Ab('. En the other hand3 i treats 9s or \s as !"@S&3 so youAd always get c * b. 27.!hat are Intertial and :rans(ort /elays ?? 28.!hat does )timescale 1 ns= 1 (s signi"y in a verilog code? Atimescale directive is a compiler directive.It is used to measure simulation time or delay time. ;sage 6 Gtimescale I re erence_time_unit 6 Speci ies the unit o measurement or times and delays. time_precision6 speci ies the precision to which the delays are rounded o .

29. !hat is the di""erence #etween AAA and AA ? output o 1**1 can be (3 , or 9. output o 1***1 can only be , or (. $hen you are comparing - nos using 1**1 and i oneIboth the numbers have one or more bits as 1'1 then the output would be 191 . ?ut i use 1***1 outpout would be , or (. e.g " * /Ab(', ? * /Ab(,' " ** ? will give 9 as output. " *** ? will give , as output. 1**1 is used or comparison o only (As and ,As .It canAt compare 9s. I any bit o the input is 9 output will be 9 1***1 is used or comparison o 9 also. 3;.How to generate sine wav using verilog coding style? "6 =he easiest and e icient way to generate sine wave is using 5EF#I5 "lgorithm. 31. !hat is the di""erence #etween wire and reg? Bet types6 7wire3tri8Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. Fegister type6 7reg3 integer3 time3 real3 real time8 represents abstract data storage element. "ssigned values only within an always statement or an initial statement. =he main di erence between wire and reg is wire cannot hold 7store8 the value when there no connection between a and b like a2Hb3 i there is no connection in a and b3 wire loose value. ?ut reg can hold the value even i there in no connection. #e ault values6wire is \3reg is '. 32 .How do you im(lement the #i0directional (orts in Verilog H/$? module bidirec 7oe3 clk3 inp3 outp3 bidir8. II Port #eclaration input oe. input clk. input RL6,S inp. output RL6,S outp. inout RL6,S bidir. reg RL6,S a. reg RL6,S b. assign bidir * oe % a 6 NAb\ . assign outp * b. II "lways 5onstruct always Q 7posedge clk8 begin

b )* bidir. a )* inp. end endmodule 33.How to write *,M is verilog? there r mainly 0 ways - write sm code (8 using ( process where all input decoder3 present state3 and output decoder r combine in one process. -8 using - process where all comb ckt and sequential ckt separated in di erent process /8 using - process where input decoder and persent state r combine and output decoder seperated in other process 08 using / process where all three3 input decoder3 present state and output decoder r separated in / process. &lick to view more 31.what is verilog case C1. ? wire R/6,S '. always Q7...8 begin case 7(Ab(8 'R,S6 SE:&=DIBM(. 'R(S6 SE:&=DIBM-. 'R-S6 SE:&=DIBM/. 'R/S6 SE:&=DIBM0. endcase end =he case statement walks down the list o cases and e'ecutes the irst one that matches. So here3 i the lowest (2bit o ' is bit -3 then something/ is the statement that will get e'ecuted 7or selected by the logic8. 32. !hy is it that ?i" C2D#;1 6 2D#1;.---? doesnDt run the true case? =his is a popular coding error. Cou used the bit wise "B# operator 7K8 where you meant to use the logical "B# operator 7KK8. 33.!hat are /i""erent ty(es o" Verilog ,imulators ? =here are mainly two types o simulators available. &vent #riven 5ycle ?ased

&vent2based Simulator6 =his #igital @ogic Simulation method sacri ices per ormance or rich unctionality6 every active signal is calculated or every device it propagates through during a clock cycle. !ull &vent2based simulators support 02-N states. simulation o ?ehavioral D#@3 F=@ D#@3 gate3 and transistor representations. ull timing calculations or all devices. and the ull D#@ standard. &vent2based simulators are like a Swiss "rmy kni e with many di erent eatures but none are particularly ast. 5ycle ?ased Simulator6 =his is a #igital @ogic Simulation method that eliminates unnecessary calculations to achieve huge per ormance gains in veri ying ?oolean logic6 (.8 Fesults are only e'amined at the end o every clock cycle. and -.8 =he digital logic is the only part o the design simulated 7no timing calculations8. ?y limiting the calculations3 5ycle based Simulators can provide huge increases in per ormance over conventional &vent2based simulators. 5ycle based simulators are more like a high speed electric carving kni e in comparison because they ocus on a subset o the biggest problem6 logic veri ication. 5ycle based simulators are almost invariably used along with Static =iming veri ier to compensate or the lost timing in ormation coverage. 37.!hat is &onstrained0Eandom Veri"ication ? Introduction "s "SI5 and system2on2chip 7So58 designs continue to increase in si4e and comple'ity3 there is an equal or greater increase in the si4e o the veri ication e ort required to achieve unctional coverage goals. =his has created a trend in F=@ veri ication techniques to employ constrained2random veri ication3 which shi ts the emphasis rom hand2authored tests to utili4ation o compute resources. $ith the corresponding emergence o aster3 more comple' bus standards to handle the massive volume o data tra ic there has also been a renewed signi icance or veri ication IP to speed the time taken to develop advanced testbench environments that include randomi4ation o bus tra ic. #irected2=est :ethodology ?uilding a directed veri ication environment with a comprehensive set o directed tests is e'tremely time2consuming and di icult. Since directed tests only cover conditions that have been anticipated by the veri ication team3 they do a poor >ob o covering corner cases. =his can lead to costly re2spins or3 worse still3 missed market windows. =raditionally veri ication IP works in a directed2test environment by acting on speci ic testbench commands such as read3 write or burst to generate transactions or whichever

protocol is being tested. =his directed tra ic is used to veri y that an inter ace behaves as e'pected in response to valid transactions and error conditions. =he drawback is that3 in this directed methodology3 the task o writing the command code and checking the responses across the ull breadth o a protocol is an overwhelming task. =he veri ication team requently runs out o time be ore a mandated tape2out date3 leading to poorly tested inter aces. Dowever3 the bigger issue is that directed tests only test or predicted behavior and it is typically the un oreseen that trips up design teams and leads to e'tremely costly bugs ound in silicon. 5onstrained2Fandom Veri ication :ethodology =he advent o constrained2random veri ication gives veri ication engineers an e ective method to achieve coverage goals aster and also help ind corner2case problems. It shi ts the emphasis rom writing an enormous number o directed tests to writing a smaller set o constrained2random scenarios that let the compute resources do the work. 5overage goals are achieved not by the sheer weight o manual labor required to hand2write directed tests but by the number o processors that can be utili4ed to run random seeds. =his signi icantly reduces the time required to achieve the coverage goals. Scoreboards are used to veri y that data has success ully reached its destination3 while monitors snoop the inter aces to provide coverage in ormation. Bew or revised constraints ocus veri ication on the uncovered parts o the design under test. "s veri ication progresses3 the simulation tool identi ies the best seeds3 which are then retained as regression tests to create a set o scenarios3 constraints3 and seeds that provide high coverage o the design.