COMSATS Institute of Information Technology

Kamra Road, Attock

Department of Electrical Engineering

Course Title: Digital System Design

Course Code: EEE-344
Class: BEE-VI
Course Instructor: Mr. Wasiq Ali
Lab Instructor: Engr. Shahzad

Lab#12: Convolutional Encoders

Group Members:
Name Registration No.
Maaz Ahmad CIIT/FA14-BEE-003/ATK
Talha Nadeem CIIT/FA14-BEE-007/ATK
Objective: To implement convolutional encoder via RTL coding level.
Convolutional Encoder:
In telecommunication, a convolutional code is a type of error-correcting code that generates
parity symbols via the sliding application of a Boolean polynomial function to a data stream. The
sliding application represents the 'convolution' of the encoder over the data, which gives rise to
the term 'convolutional coding.' The sliding nature of the convolutional codes
facilitates trellis decoding using a time-invariant trellis. Time invariant trellis decoding allows
convolutional codes to be maximum-likelihood soft-decision decoded with reasonable
complexity.

Procedure:
First of all, open Xilinx ISE and make new project.
Select device XC6SLX16 and add Verilog module file.
Write code to implement convolutional encoder and run it.
Make RTL file and save it.
Create Verilog fixture file and add all the input schemes with 100ns delay.
Observe wave diagram and verify your theoretical results and save it.
Open user constraints and assign I/Os to have result for convolutional encoder and save
it.
Re-run the code and generate bit file.
Connect the hardware and open configure target device.
First auto-connect the cable in the window of iMPACT software and then add your
Xilinx device.
Program it and test your results practically and match it with wave diagrams results.
Repeat this experiment for other convolutional encoder equations.

Conclusion:
In this experiment we learnt about the syntax of convolutional encoder using RTL
modeling and observed the behavior of comparator practically on Spartan 6 FPGA kit.
Task: Convolutional Encoder RTL Image:
module CE_VM(output reg
// Sequential Logic
y0, output reg y1,input clk,
always@(posedge clk)
input rst, input x,output reg
begin
a,
if(rst)
output reg b,output reg c);
begin
initial begin
a<=0;
a=1'b0;
b<=0;
b=1'b0;
c<=0;
c=1'b0;
end
end
// Combinational Logic
begin
always@(*)
a<=x;
begin
b<=a;
y0=x^b^c;
c<=b;
y1=x^a^c;
end
end
end
endmodule
Verilog Fixture Input:
initial begin begin
// Initialize // Add repeat(60)
Inputs stimulus here #20 x=~x;
clk = 0; end
rst = 0; end
x = 0; always initial begin
#20 #5 rst=1;
// Wait 100 clk=~clk; #2 rst=0;
ns for global reset to finish End
#100; initial

Wave Diagram: