The UNIVERSITY of NOTTINGHAM MALAYSIA CAMPUS

DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

HARDWARE DESCRIPTION LANGUAGES FOR PROGRAMMABLE LOGIC

MODULE CODES: H64HDL and H64HDP

Intro to VHDL Laboratory

Cascade Hexadecimal Counter Using VHDL Entry Only

1. EQUIPMENT LIST

• PC (running Windows 2000 or XP)

• Xilinx ISE 10.1 software
• Xilinx Spartan-3E Starter Kit including:
� Xilinx Spartan-3E Starter Board
� 5V power supply unit
� USB or JTAG cable
� Spartan-3E Starter Kit Board User Guide (Available in WebCT)

2. COURSE REQUIREMENTS
This Laboratory forms part of the Intro to HDL lab. There is no assessment towards this
lab. This will be a good starting point for the actual lab exercise. No formal report is
needed.
The software used for this laboratory is the Xilinx ISE (Version 10.1) set of tools, which
can be accessed via the computers in Micro processor Laboratory (Room DA19). If you
encounter any software problems then contact Mr. Noor Hashimi Mohammad Nor (Room
DA19a).

NOTE: Please ensure that you have read through all source codes and fully understood
them before this lab session!

AIM
The aim of this Laboratory is to
o Provide familiarity with VHDL syntax.
o Familiarise yourself with the Xilinx ISE Series software.
o Provide experience in de-bugging and extending a design following the
design stages listed above.
Provide practical experience in digital hardware design

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Testbench Code:
-- VHDL Test Bench Created from source file top_level.vhd -- 16:30:29 11/07/2006
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE tb_arch OF testbench IS

COMPONENT top_level
PORT(
reset : IN std_logic;
enable : IN std_logic;
systemclock : IN std_logic;
an : OUT std_logic_vector(3 downto 0);
ca : OUT std_logic;
cb : OUT std_logic;
cc : OUT std_logic;
cd : OUT std_logic;
ce : OUT std_logic;
cf : OUT std_logic;
cg : OUT std_logic
);
END COMPONENT;

SIGNAL tb_reset : std_logic;

SIGNAL tb_enable : std_logic;
SIGNAL tb_systemclock : std_logic;
SIGNAL tb_An : std_logic_vector(3 downto 0);
SIGNAL tb_ca : std_logic;
SIGNAL tb_cb : std_logic;
SIGNAL tb_cc : std_logic;
SIGNAL tb_cd : std_logic;
SIGNAL tb_ce : std_logic;
SIGNAL tb_cf : std_logic;
SIGNAL tb_cg : std_logic;
constant period : time := 100 ns;
BEGIN

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 uut: top_level PORT MAP(
reset => tb_reset,
enable => tb_enable,
systemclock => tb_systemclock,
an => tb_An,
ca => tb_ca,
cb => tb_cb,
cc => tb_cc,
cd => tb_cd,
ce => tb_ce,
cf => tb_cf,
cg => tb_cg
);

process
begin
tb_systemclock <= '1';
wait for period/2;
tb_systemclock <= '0';
wait for period/2;
end process;
-- produce reset signal
process
begin
tb_reset <= '1';
wait for 1.5*period;
tb_reset <= '0';
wait;
end process;
-- produce enable signal
process
begin
tb_enable <= '0';
wait for 2.5*period;
tb_enable <= '1';
wait;
end process;
END tb_arch;

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Top level Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Top_level is
Port ( Reset : in std_logic;
Enable : in std_logic;
Systemclock : in std_logic;
An : out std_logic_vector(3 downto 0);
Ca : out std_logic;
Cb : out std_logic;
Cc : out std_logic;
Cd : out std_logic;
Ce : out std_logic;
Cf : out std_logic;
Cg : out std_logic);
end Top_level;

architecture Top_level_Arch of Top_level is

component Clock_Divider
Port(
ClockIn: in std_logic;
ClockOut: out std_Logic);
end component;

component Cascade
port(
Reset, Enable, Clock: in std_logic;
Count3, Count2, Count1, Count0: out std_Logic_vector(3 downto 0));

end component;

component d4to7
port(
Q: in std_logic_vector (3 downto 0);
Seg: out std_logic_vector (6 downto 0));
end component;

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 component Scan4Digit
Port(
Digit3, Digit2, Digit1, Digit0 : in std_logic_vector(6 downto 0);
Clock : in std_logic;
An : out std_logic_vector (3 downto 0);
Ca, Cb, Cc, Cd, Ce, Cf, Cg : out std_logic);
end component;

signal iClock: std_logic;

signal iCount0, iCount1, iCount2, iCount3: std_logic_vector (3 downto 0);
signal iSeg0, iSeg1, iSeg2, iSeg3: std_logic_vector (6 downto 0);
begin
-- Clock signal, iClock, is generated for cascade counter
U1: Clock_Divider port map (
ClockIn => SystemClock,
ClockOut => iClock);

-- Cascade counter
U2: Cascade port map (
Reset => Reset,
Enable => Enable,
Clock => iClock,
Count3 => iCount3,
Count2 => iCount2,
Count1 => iCount1,
Count0 => iCount0);

-- Hexdec to 7-segment decoder

U3: d4to7 port map (
q => iCount0,
seg => iSeg0);
U4: d4to7 port map (
q => iCount1,
seg => iSeg1);
U5: d4to7 port map (
q => iCount2,
seg => iSeg2);
U6: d4to7 port map (
q => iCount3,
seg => iSeg3);

-- Send the 7-segment decoder outputs to 7-segment display

U7: Scan4Digit port map (
Digit3 => iSeg3,
Digit2 => iSeg2,
Digit1 => iSeg1,
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 Digit0 => iSeg0,
Clock => SystemClock,
An => An,
Ca => Ca,
Cb => Cb,
Cc => Cc,
Cd => Cd,
Ce => Ce,
Cf => Cf,
Cg => Cg);

end Top_Level_Arch;

Cascade Counter Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cascade is
Port ( Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Count3, Count2, Count1, Count0: out std_Logic_vector(3 downto 0));
end cascade;

architecture Cascade_arch of cascade is

component counter
port(
Clock: in std_logic;
Enable: in std_logic;
Reset: in std_logic;
Count: out std_logic_vector(3 downto 0);
CascadeOut: out std_logic);
end component;

component counter_ext
port(
CascadeIn : in std_logic;
Reset : in std_logic;
Count: out std_logic_vector(3 downto 0);
CascadeOut: out std_logic);
end component;

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 signal iCascadeOut0,iCascadeOut1, iCascadeOut2, iCascadeOut3 : std_logic;
begin
-- Cascade counter
U1: counter port map (
Clock => Clock,
Enable => Enable,
Reset => Reset,
Count => Count0,
CascadeOut => iCascadeOut0 );

U2: counter_ext port map (

CascadeIn => iCascadeOut0,
Reset => Reset,
Count => Count1,
CascadeOut => iCascadeOut1 );

U3: counter_ext port map (

CascadeIn => iCascadeOut1,
Reset => Reset,
Count => Count2,
CascadeOut => iCascadeOut2 );

U4: counter_ext port map (

CascadeIn => iCascadeOut2,
Reset => Reset,
Count => Count3,
CascadeOut => iCascadeOut3 );

end Cascade_arch;

Counter Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity Counter is
Port ( Clock : in std_logic;
Enable : in std_logic;
Reset : in std_logic;
Count : out std_logic_vector(3 downto 0);
Cascadeout : out std_logic);
end Counter;

architecture Archit_counter of Counter is

signal iCount:std_logic_vector(3 downto 0);

constant MaxCount:std_logic_vector:="1110";

begin
process(Clock)
begin
if Clock'event and Clock='1' then
if Reset='1' then -- Synchronous reset (active high)
iCount<=(others=>'0');
CascadeOut<='0';
elsif Enable = '1' then -- if we are enabled
if iCount=MaxCount then -- if we've hit max count
iCount<=(others=>'0'); --set all bits to zero
CascadeOut <='1'; --cascade out
else
iCount<= iCount + '1'; --normal count
CascadeOut<='0';
end if;
end if; -- end enable dependence
end if; -- end of clocked section
end process;
Count <= iCount;

end Archit_counter;

Counter_Cascading Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity counter_ext is

Port ( CascadeIn : in std_logic;

Reset : in std_logic;
CascadeOut : out std_logic;
Count : out std_logic_vector(3 downto 0));

end counter_ext;

architecture counter_ext_arch of counter_ext is

signal iCount:std_logic_vector(3 downto 0);

constant MaxCount:std_logic_vector:="1110";

begin
Process (CascadeIn, Reset)
Begin

if Reset='1' then
iCount<=(others=>'0');
CascadeOut<='0';
elsif iCount = MaxCount then
iCount<=(others=>'0'); --set all bits to zero
CascadeOut <='1'; --cascade out

elsif cascadeIn = '1' then

iCount<= iCount + '1'; --normal count
CascadeOut<='0';
end if;
end process;

end counter_ext_arch;

Clock Divider Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Clock_divider is
Port ( ClockIn : in std_logic;

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 ClockOut : out std_logic);
end Clock_divider;

architecture Clock_divider_Arch of Clock_divider is

signal iCount24: std_logic_vector (23 downto 0) := (others => '0');

begin
-- Generate a clock signal with the frequency of 50MHz/(2**24) (2.98Hz)
-- based on system clock (50MHz).
-- This clock signal will be used for the clock of our cascade counter
process(ClockIn)
begin
if ClockIn'event and ClockIn='1' then
iCount24 <= iCount24 + '1';
end if;
end process;
ClockOut <= iCount24(23);

end Clock_divider_Arch;

D4 to 7 Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity D4to7 is
Port ( Q : in std_logic_vector(3 downto 0);
Seg : out std_logic_vector(6 downto 0));
end D4to7;

architecture D4to7_Arch of D4to7 is

-- Segment encoding
-- a
-- ---
-- f | | b
-- --- <- g
-- e | | c
-- ---
-- d

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begin
-- Conditional signal assignments
-- LED seg order=a,b,c,d,e,f,g =seg6,seg5,seg4,seg3,seg2,seg1,seg0
Seg<= "1111110" when q = "0000" else
"0110000" when q = "0001" else
"1101101" when q = "0010" else
"1111001" when q = "0011" else
"0110011" when q = "0100" else
"1011011" when q = "0101" else
"1011111" when q = "0110" else
"1110000" when q = "0111" else
"1111111" when q = "1000" else
"1111011" when q = "1001" else
"1110111" when q = "1010" else
"0011111" when q = "1011" else
"1001110" when q = "1100" else
"0111101" when q = "1101" else
"1001111" when q = "1110" else
"1000111" when q = "1111" else
"0000000";
end D4to7_Arch;

Scan4Digit Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Scan4Digit is
Port ( Digit0 : in std_logic_vector (6 downto 0);
Digit1 : in std_logic_vector(6 downto 0);
Digit2 : in std_logic_vector(6 downto 0);
Digit3 : in std_logic_vector(6 downto 0);
Clock : in std_logic;
An : out std_logic_vector(3 downto 0);
Ca : out std_logic;
Cb : out std_logic;
Cc : out std_logic;
Cd : out std_logic;

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 Ce : out std_logic;
Cf : out std_logic;
Cg : out std_logic);
end Scan4Digit;

architecture Scan4Digit_Arch of Scan4Digit is

signal iCount16: std_logic_vector (15 downto 0) := (others=>'0');

signal iDigitOut: std_logic_vector (6 downto 0);

begin
-- Generate the scan clock 50MHz/2**16 (763Hz)
process(Clock)
begin
if Clock'event and Clock='1' then
iCount16 <= iCount16 + '1';
end if;
end process;
--Send four digits to four 7-segment display using scan mode
with iCount16 (15 downto 14) select
iDigitOut <= Digit0 when "00", -- Connect Digit0 to the 7-segment display
Digit1 when "01", -- Connect Digit1 to the 7-segment display
Digit2 when "10", -- Connect Digit2 to the 7-segment display
Digit3 when "11", -- Connect Digit3 to the 7-segment display
Digit0 when others;
with iCount16 (15 downto 14) select
An <= "1110" when "00", -- with AN0 low only
"1101" when "01", -- with AN1 low only
"1011" when "10", -- with AN2 low only
"0111" when "11", -- with AN3 low only
"1110" when others;

Ca <= iDigitOut(6);
Cb <= iDigitOut(5);
Cc <= iDigitOut(4);
Cd <= iDigitOut(3);
Ce <= iDigitOut(2);
Cf <= iDigitOut(1);
Cg <= iDigitOut(0);

end Scan4Digit_Arch;

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