4BIT ALU DESIGN

M.
TECH-ECE-VLSI & EMBEDDED SYSTEMS STRUCTURAL DIGITAL SYSTEM DESIGN LAB
Design of 4 Bit Subtractor using Structural Modeling

Style -
AIM:
AIM To simulate the design of 4bit subtractor using structural modeling style
Apparatus: Pc installed with xilinx tool
Circuit diagram:
VHDL Code :
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SVIT ANANTAPUR
M.TECH-ECE-VLSI & EMBEDDED SYSTEMS STRUCTURAL DIGITAL SYSTEM DESIGN LAB
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity subtractor_4bit is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
borrow : out STD_LOGIC;
diff : out STD_LOGIC_VECTOR(3 downto 0)
);
end subtractor_4bit;
architecture subtractor_4bit_arc of subtractor_4bit is
Component fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end component;
signal s : std_logic_vector (2 downto 0);

signal l : std_logic_vector (3 downto 0);
begin

l <= not b;

u0 : fa port map (a(0),l(0),'1',diff(0),s(0));
u1 : fa port map (a(1),l(1),s(0),diff(1),s(1));
u2 : fa port map (a(2),l(2),s(1),diff(2),s(2));
ue : fa port map (a(3),l(3),s(2),diff(3),borrow);

end subtractor_4bit_arc;
---------------- Full Adder Design ----------------------

library IEEE;
entity fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end fa;
architecture fa_arc of fa is
begin

sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
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SVIT ANANTAPUR

end fa_arc;
OUTPUT WAVEFORM:
Output Waveform : 4 Bit Subtractor

Design
2. VHDL code for booth multiplier

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SVIT ANANTAPUR
AIM: To write a vhdl code for booth multiplier
Apparatus: Pc linked with xilinx tool
Circuit diagram:
VHDL CODE:
4
SVIT ANANTAPUR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity booths is
GENERIC(k : POSITIVE := 7); --input number word length less one
Port ( a,b : in STD_LOGIC_VECTOR (k downto 0);
mul : out STD_LOGIC_VECTOR (2*k+1 downto 0));
end booths;
architecture Behavioral of booths is
begin
process(a,b)
variable m: std_logic_vector (2*k+1 downto 0);
variable s: std_logic;
begin
m:="00000000"&b;
s:='0';
for i in 0 to k loop
if(m(0)='0' and s='1') then
m(k downto k-3):= m(k downto k-3)+a;
s:=m(0);
m(k-1 downto 0):=m(k downto 1);
elsif(m(0)='1' and s='0') then
m(k downto k-3):= m(k downto k-3)-a;
s:=m(0);
else
s:=m(0);
end if;
end loop;
mul<=m;
end process;
end Behavioral;
B)library IEEE;
entity Testbench_di_Booth is
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SVIT ANANTAPUR
end Testbench_di_Booth;
architecture behavior of Testbench_di_Booth is
component booths
GENERIC(k : POSITIVE := 7); --input number word length less one
Port( a,b : in STD_LOGIC_VECTOR (k downto 0);
mul : out STD_LOGIC_VECTOR (2*k+1 downto 0));
end component;
--Inputs
signal A : STD_LOGIC_VECTOR (7 downto 0):= "00000011";
signal B : STD_LOGIC_VECTOR (7 downto 0):= "00000100";
--Outputs
signal MUL : STD_LOGIC_VECTOR(15 downto 0);
begin
--Instantiate the UnitUnder Test (UUT)
uut: booths PORT MAP
(a => A,
b => B,
mul => MUL);
--Stimulus process
stim_proc: process
begin
--insert stimulus here
A<="00000011"; B<="00000100"; wait for 500 fs;
A<="00000110"; B<="00000111"; wait for 500 fs;
A<="00001011"; B<="00000100"; wait for 500 fs;
wait;
end process;
end;
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SVIT ANANTAPUR
OUTPUT WAVEFORM:
3. VHDL Code for 4-bit ALU
Aim: To write a vhdl code for 4bit alu

CIRCUIT DIAGRAM:
VHDL CODE:
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SVIT ANANTAPUR
library IEEE;
use IEEE.NUMERIC_STD.ALL;

entity alu is
Port ( inp_a : in signed(3 downto 0);
inp_b : in signed(3 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
out_alu : out signed(3 downto 0));
end alu;

architecture Behavioral of alu is
begin
process(inp_a, inp_b, sel)
begin
case sel is
when "000" =>
out_alu<= inp_a + inp_b; --addition
when "001" =>
out_alu<= inp_a - inp_b; --subtraction
when "010" =>
out_alu<= inp_a - 1; --sub 1
when "011" =>
out_alu<= inp_a + 1; --add 1
when "100" =>
out_alu<= inp_a and inp_b; --AND gate
when "101" =>
out_alu<= inp_a or inp_b; --OR gate
when "110" =>
out_alu<= not inp_a ; --NOT gate
when "111" =>
out_alu<= inp_a xor inp_b; --XOR gate
when others =>
NULL;
end case;

end process;

end Behavioral;
Testbench VHDL Code for 4-Bit ALU

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY Tb_alu IS
END Tb_alu;

ARCHITECTURE behavior OF Tb_alu IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT alu
PORT(
inp_a : IN signed(3 downto 0);
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SVIT ANANTAPUR
inp_b : IN signed(3 downto 0);

sel : IN std_logic_vector(2 downto 0);
out_alu : OUT signed(3 downto 0)
);
END COMPONENT;

--Inputs
signal inp_a : signed(3 downto 0) := (others => '0');
signal inp_b : signed(3 downto 0) := (others => '0');
signal sel : std_logic_vector(2 downto 0) := (others => '0');

--Outputs
signal out_alu : signed(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
inp_a => inp_a,
inp_b => inp_b,
sel => sel,
out_alu => out_alu
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

-- insert stimulus here

inp_a <= "1001";
inp_b <= "1111";

sel <= "000";
wait for 100 ns;
sel <= "001";
wait for 100 ns;
sel <= "010";
wait for 100 ns;
sel <= "011";
wait for 100 ns;
sel <= "100";
wait for 100 ns;
sel <= "101";
wait for 100 ns;
sel <= "110";
wait for 100 ns;
sel <= "111";
end process;

END;
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SVIT ANANTAPUR
OUTPUT WAVEFORM:
Simulation Result for 4-bit ALU
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4. Design of 4 Bit Serial IN - Serial OUT Shift Register

using Behavior Modeling Style-
AIM: To simulate the design of 4 bit serial in -serial out shift

register using behavior modeling style
Circuit diagram:
VHDL Code-
library IEEE;
entity siso_behavior is
port(
din : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end siso_behavior;
architecture siso_behavior_arc of siso_behavior is
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SVIT ANANTAPUR
begin
siso : process (clk,din,reset) is

variable s : std_logic_vector(3 downto 0) := "0000" ;
begin
if (reset='1') then
s := "0000";
elsif (rising_edge (clk)) then
s := (din & s(3 downto 1));
dout <= s(0);
end if;
end process siso;
end siso_behavior_arc;
Output waveform:
Output Waveform : Serial IN - Serial OUT Shift Register
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SVIT ANANTAPUR
5. Design of 4 Bit Serial IN - Parallel OUT Shift

Register using Behavior Modeling Style -
Aim: To simulate and design of 4bit serial in- parallel out shift register
using behavior modeling style

Circuit diagram:
VHDL Code -
library IEEE;
entity sipo_behavior is
port(
din : in STD_LOGIC;
clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end sipo_behavior;
architecture sipo_behavior_arc of sipo_behavior is

begin
sipo : process (clk,din,reset) is

variable s : std_logic_vector(3 downto 0) := "0000" ;
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begin
if (reset='1') then
s := "0000";
s := (din & s(3 downto 1));
end if;
dout <= s;
end process sipo;
end sipo_behavior_arc;
Output waveform:
Output Waveform : Serial IN - Parallel OUT Shift

Register
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SVIT ANANTAPUR
6.Design of Parallel IN - Serial OUT Shift Register

using Behavior Modeling Style -
AIM: To simulate and design of parallel in -serial out shift

Circuit diagram:
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SVIT ANANTAPUR
VHDL Code-
library IEEE;
entity parallel_in_serial_out is
port(
clk : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC
);
end parallel_in_serial_out;
architecture piso_arc of parallel_in_serial_out is

begin
piso : process (clk,reset,load,din) is

variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
temp := din ;
dout <= temp(3);
temp := temp(2 downto 0) & '0';
end if;
end process piso;
end piso_arc;
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SVIT ANANTAPUR
Output waveform:
Output Waveform : Parallel IN - Serial OUT Shift Register
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SVIT ANANTAPUR
7.Design of 4 Bit Parallel IN - Parallel OUT Shift

Register using Behavior Modeling Style .
Aim: To simulate and design of 4 bit parallel in - parallel out shift


Circuit diagram:
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SVIT ANANTAPUR
VHDL Code.
library IEEE;
entity pipo_behavior is
port(
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end pipo_behavior;
architecture pipo_behavior_arc of pipo_behavior is

begin
pipo : process (clk,din,reset) is

begin
if (reset='1') then
dout <= "0000";
dout <= din;
end if;
end process pipo;
end pipo_behavior_arc;
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SVIT ANANTAPUR
Output waveform:
Output Waveform : 4 Bit parallel IN - Parallel OUT Shift

Register
8. VHDL Code for 4 bit Ring Counter
Aim: To write a code for 4 bit ring counter

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SVIT ANANTAPUR
Circuit diagram:
VHDL CODE:
library IEEE;

entity Ring_counter is
Port ( CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Ring_counter;

architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector(3 downto 0):= "0000";
begin
process(CLOCK,RESET)
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge(CLOCK) then
q_tmp(1) <= q_tmp(0);
q_tmp(2) <= q_tmp(1);
q_tmp(3) <= q_tmp(2);
q_tmp(0) <= q_tmp(3);
end if;
end process;
Q <= q_tmp;
end Behavioral;
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SVIT ANANTAPUR
Output waveform:
9:VHDL code for up counter:
Aim: To write a vhdl code for up counter

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SVIT ANANTAPUR
Circuit diagram:
VHDL CODE:
library IEEE;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: VHDL code for up counter
entity UP_COUNTER is
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end UP_COUNTER;
architecture Behavioral of UP_COUNTER is

signal counter_up: std_logic_vector(3 downto 0);
begin
-- up counter
process(clk,reset)
begin
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SVIT ANANTAPUR
if(rising_edge(clk)) then
if(reset='1') then
counter_up <= x"0";
else
counter_up <= counter_up + x"1";
end if;
end if;
end process;
counter <= counter_up;
end Behavioral;
Testbench VHDL code for the up-counter:
library IEEE;
-- VHDL project: Testbench VHDL code for up counter
entity tb_counters is
end tb_counters;
architecture Behavioral of tb_counters is
component UP_COUNTER
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end component;
signal reset,clk: std_logic;
signal counter:std_logic_vector(3 downto 0);
begin
dut: UP_COUNTER port map (clk => clk, reset=>reset, counter => counter);
-- Clock process definitions
clock_process :process
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SVIT ANANTAPUR
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process;
end Behavioral;
Output waveform:
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SVIT ANANTAPUR
10. VHDL code for down counter:
Aim: To write a vhdl code for down counter

Apparatus: Pc linked with xlinx tool
Circuit diagram:
VHDL CODE:
library IEEE;
-- VHDL project: VHDL code for down counter
entity DOWN_COUNTER is
counter: out std_logic_vector(3 downto 0) -- output 4-bit
counter
);
end DOWN_COUNTER;
architecture Behavioral of DOWN_COUNTER is
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SVIT ANANTAPUR
signal counter_down: std_logic_vector(3 downto 0);

begin
-- down counter
process(clk,reset)
begin
if(reset='1') then
counter_down <= x"F";
else
counter_down <= counter_down - x"1";
end if;
end if;
end process;
counter <= counter_down;
end Behavioral;
Output waveform:
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SVIT ANANTAPUR
11. 4-bit Ring Counter using D

FlipFlop
Aim: To simulate and design a 4 bit ring counter using D flipflop

Circuit diagram:
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SVIT ANANTAPUR
VHDL CODE:
library IEEE;

entity Ring_counter is
Port ( CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
end Ring_counter;

architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector(3 downto 0):= "0000";
begin
process(CLOCK,RESET)
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge(CLOCK) then
q_tmp(1) <= q_tmp(0);
q_tmp(2) <= q_tmp(1);
q_tmp(3) <= q_tmp(2);
q_tmp(0) <= q_tmp(3);
end if;
end process;
Q <= q_tmp;
end Behavioral;
Output waveform:
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SVIT ANANTAPUR
12. 4-bit Johnson Counter using D

FlipFlop
Aim: To simulate and design a 4 bit johnson counter using D flip flop
Circuit diagram:
VHDL Code :
library IEEE;

entity Johnson_counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
end Johnson_counter;

architecture Behavioral of Johnson_counter is
signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk,rst)
begin
if rst = '1' then
temp <= "0000";
elsif Rising_edge(clk) then
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SVIT ANANTAPUR
temp(1) <= temp(0);

temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= not temp(3);
end if;
end process;
Q <= temp;
end Behavioral;
Output waveform:
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SVIT ANANTAPUR
13.VHDL code for Data Memory of the

MIPS processor:
Aim : To write vhdl code for data memory of the MIPS processor
Architecture:
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SVIT ANANTAPUR
VHDL CODE:
library IEEE;
USE IEEE.numeric_std.all;
-- VHDL code for the data Memory of the MIPS Processor
entity Data_Memory_VHDL is
port (
clk: in std_logic;
mem_access_addr: in std_logic_Vector(15 downto 0);
mem_write_data: in std_logic_Vector(15 downto 0);
mem_write_en,mem_read:in std_logic;
mem_read_data: out std_logic_Vector(15 downto 0)
);
end Data_Memory_VHDL;
architecture Behavioral of Data_Memory_VHDL is

signal i: integer;
signal ram_addr: std_logic_vector(7 downto 0);
type data_mem is array (0 to 255 ) of std_logic_vector (15 downto 0);
signal RAM: data_mem :=((others=> (others=>'0')));
begin
ram_addr <= mem_access_addr(8 downto 1);

process(clk)
begin
if (mem_write_en='1') then
ram(to_integer(unsigned(ram_addr))) <= mem_write_data;
end if;
end if;
end process;
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SVIT ANANTAPUR
mem_read_data <= ram(to_integer(unsigned(ram_addr))) when (mem_read='1')

else x"0000";
end Behavioral;
Output waveform:
14.VHDL code for ALU of the MIPS

processor:
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SVIT ANANTAPUR
Aim: To write a vhdl code for alu of the MIPS processor

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_signed.all;
-- VHDL code for ALU of the MIPS Processor
entity ALU_VHDL is
port(
a,b : in std_logic_vector(15 downto 0); -- src1, src2
alu_control : in std_logic_vector(2 downto 0); -- function select
alu_result: out std_logic_vector(15 downto 0); -- ALU Output Result
zero: out std_logic -- Zero Flag
);
end ALU_VHDL;
architecture Behavioral of ALU_VHDL is

signal result: std_logic_vector(15 downto 0);
begin
process(alu_control,a,b)
begin
case alu_control is
when "000" =>
result <= a + b; -- add
when "001" =>
result <= a - b; -- sub
when "010" =>
result <= a and b; -- and
when "011" =>
result <= a or b; -- or
when "100" =>
if (a<b) then
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SVIT ANANTAPUR
result <= x"0001";

else
result <= x"0000";
end if;
when others => result <= a + b; -- add
end case;
end process;
zero <= '1' when result=x"0000" else '0';
alu_result <= result;
end Behavioral;
Output waveform:
15. VHDL code for ALU Control

Unit of the MIPS processor:
Aim: To write the vhdl code for alu control unit of the MIPS processor
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SVIT ANANTAPUR
VHDL CODE:
library IEEE;
-- VHDL code for ALU Control Unit of the MIPS Processor
entity ALU_Control_VHDL is
port(
ALU_Control: out std_logic_vector(2 downto 0);
ALUOp : in std_logic_vector(1 downto 0);
ALU_Funct : in std_logic_vector(2 downto 0)
);
end ALU_Control_VHDL;
architecture Behavioral of ALU_Control_VHDL is

begin
process(ALUOp,ALU_Funct)
begin
case ALUOp is
when "00" =>
ALU_Control <= ALU_Funct(2 downto 0);
when "01" =>
ALU_Control <= "001";
when "10" =>
when "11" =>
when others => ALU_Control <= "000";
end case;
end process;
end Behavioral;
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SVIT ANANTAPUR
Output waveform:
16.VHDL code for Register File of the

MIPS processor:
Aim: To write the vhdl code for register file of the MIPS processor
VHDL CODE:
library IEEE;
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SVIT ANANTAPUR
-- VHDL code for the register file of the MIPS Processor

entity register_file_VHDL is
port (
clk,rst: in std_logic;
reg_write_en: in std_logic;
reg_write_dest: in std_logic_vector(2 downto 0);
reg_write_data: in std_logic_vector(15 downto 0);
reg_read_addr_1: in std_logic_vector(2 downto 0);
reg_read_data_1: out std_logic_vector(15 downto 0);
reg_read_addr_2: in std_logic_vector(2 downto 0);
reg_read_data_2: out std_logic_vector(15 downto 0)
);
end register_file_VHDL;
architecture Behavioral of register_file_VHDL is

type reg_type is array (0 to 7 ) of std_logic_vector (15 downto 0);
signal reg_array: reg_type;
begin
process(clk,rst)
begin
if(rst='1') then
reg_array(0) <= x"0001";
reg_array(1) <= x"0002";
reg_array(2) <= x"0003";
reg_array(3) <= x"0004";
reg_array(4) <= x"0005";
reg_array(5) <= x"0006";
reg_array(6) <= x"0007";
reg_array(7) <= x"0008";
elsif(rising_edge(clk)) then
if(reg_write_en='1') then
reg_array(to_integer(unsigned(reg_write_dest))) <= reg_write_data;
end if;
end if;
end process;
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SVIT ANANTAPUR
reg_read_data_1 <= x"0000" when reg_read_addr_1 = "000" else

reg_array(to_integer(unsigned(reg_read_addr_1)));
reg_read_data_2 <= x"0000" when reg_read_addr_2 = "000" else
reg_array(to_integer(unsigned(reg_read_addr_2)));
end Behavioral;
Output waveform:
17:VHDL code for Control Unit of the

MIPS processor:
Aim: To write the vhdl code for control unit of the MIPS SOFTWARE
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SVIT ANANTAPUR
VHDL CODE:
library IEEE;
-- VHDL code for Control Unit of the MIPS Processor
entity control_unit_VHDL is
port (
opcode: in std_logic_vector(2 downto 0);
reset: in std_logic;
reg_dst,mem_to_reg,alu_op: out std_logic_vector(1 downto 0);
jump,branch,mem_read,mem_write,alu_src,reg_write,sign_or_zero: out std_logic
);
end control_unit_VHDL;
architecture Behavioral of control_unit_VHDL is
begin
process(reset,opcode)
begin
if(reset = '1') then
reg_dst <= "00";
mem_to_reg <= "00";
alu_op <= "00";
jump <= '0';
branch <= '0';
mem_read <= '0';
mem_write <= '0';
alu_src <= '0';
reg_write <= '0';
sign_or_zero <= '1';
else
case opcode is
when "000" => -- add
reg_dst <= "01";
mem_to_reg <= "00";
alu_op <= "00";
jump <= '0';
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SVIT ANANTAPUR
branch <= '0';

mem_read <= '0';
mem_write <= '0';
alu_src <= '0';
reg_write <= '1';
when "001" => -- sliu
reg_dst <= "00";
mem_to_reg <= "00";
alu_op <= "10";
jump <= '0';
branch <= '0';
mem_read <= '0';
mem_write <= '0';
alu_src <= '1';
reg_write <= '1';
when "010" => -- j
reg_dst <= "00";
mem_to_reg <= "00";
alu_op <= "00";
jump <= '1';
branch <= '0';
mem_read <= '0';
mem_write <= '0';
alu_src <= '0';
reg_write <= '0';
when "011" =>-- jal
reg_dst <= "10";
mem_to_reg <= "10";
alu_op <= "00";
jump <= '1';
branch <= '0';
mem_read <= '0';
mem_write <= '0';
alu_src <= '0';
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SVIT ANANTAPUR
reg_write <= '1';

when "100" =>-- lw
reg_dst <= "00";
mem_to_reg <= "01";
alu_op <= "11";
jump <= '0';
branch <= '0';
mem_read <= '1';
mem_write <= '0';
alu_src <= '1';
reg_write <= '1';
when "101" => -- sw
reg_dst <= "00";
mem_to_reg <= "00";
alu_op <= "11";
jump <= '0';
branch <= '0';
mem_read <= '0';
mem_write <= '1';
alu_src <= '1';
reg_write <= '0';
when "110" => -- beq
reg_dst <= "00";
mem_to_reg <= "00";
alu_op <= "01";
jump <= '0';
branch <= '1';
mem_read <= '0';
mem_write <= '0';
alu_src <= '0';
reg_write <= '0';
when "111" =>-- addi
reg_dst <= "00";
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SVIT ANANTAPUR
mem_to_reg <= "00";

alu_op <= "11";
jump <= '0';
branch <= '0';
mem_read <= '0';
mem_write <= '0';
alu_src <= '1';
reg_write <= '1';
when others =>
reg_dst <= "01";
mem_to_reg <= "00";
alu_op <= "00";
jump <= '0';
branch <= '0';
mem_read <= '0';
mem_write <= '0';
alu_src <= '0';
reg_write <= '1';
end case;
end if;
end process;
end Behavioral;
44
SVIT ANANTAPUR
Output waveform:
18. VHDL code for Instruction

Memory of the MIPS processor:
Aim: To write the vhdl code for instruction memory for the MIPS
PROCESSOR

VHDL CODE:
library IEEE;
45
SVIT ANANTAPUR
-- VHDL code for the Instruction Memory of the MIPS Processor

entity Instruction_Memory_VHDL is
port (
pc: in std_logic_vector(15 downto 0);
instruction: out std_logic_vector(15 downto 0)
);
end Instruction_Memory_VHDL;
architecture Behavioral of Instruction_Memory_VHDL is

signal rom_addr: std_logic_vector(3 downto 0);
-- lw $3, 0($0) -- pc=0
-- Loop: sltiu $1, $3, 11= pc = 2
-- beq $1, $0, Skip = 4 --PCnext=PC_current+2+BranchAddr
-- add $4, $4, $3 = 6
-- addi $3, $3, 1 = 8
-- beq $0, $0, Loop--a
-- Skip c = 12 = 4 + 2 + br
type ROM_type is array (0 to 15 ) of std_logic_vector(15 downto 0);
constant rom_data: ROM_type:=(
"1000000110000000",
"0010110010001011",
"1100010000000011",
"0001000111000000",
"1110110110000001",
"1100000001111011",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000"
);
begin
46
SVIT ANANTAPUR
rom_addr <= pc(4 downto 1);

instruction <= rom_data(to_integer(unsigned(rom_addr))) when pc < x"0020"
else x"0000";
end Behavioral;
Output waveform:
19.VHDL code for the MIPS

Processor:
Aim: TO write the vhdl code for the MIPS PROCESSOR

Apparatus: Linked pc with xilinx tool
VHDL CODE:
47
SVIT ANANTAPUR
library IEEE;
use IEEE.std_logic_signed.all;
entity MIPS_VHDL is
port (
clk,reset: in std_logic;
pc_out, alu_result: out std_logic_vector(15 downto 0)
);
end MIPS_VHDL;
architecture Behavioral of MIPS_VHDL is

signal pc_current: std_logic_vector(15 downto 0);
signal pc_next,pc2: std_logic_vector(15 downto 0);
signal instr: std_logic_vector(15 downto 0);
signal reg_dst,mem_to_reg,alu_op: std_logic_vector(1 downto 0);
signal jump,branch,mem_read,mem_write,alu_src,reg_write: std_logic;
signal reg_write_dest: std_logic_vector(2 downto 0);
signal reg_write_data: std_logic_vector(15 downto 0);
signal reg_read_addr_1: std_logic_vector(2 downto 0);
signal reg_read_data_1: std_logic_vector(15 downto 0);
signal reg_read_addr_2: std_logic_vector(2 downto 0);
signal reg_read_data_2: std_logic_vector(15 downto 0);
signal sign_ext_im,read_data2,zero_ext_im,imm_ext: std_logic_vector(15 downto
0);
signal JRControl: std_logic;
signal ALU_Control: std_logic_vector(2 downto 0);
signal ALU_out: std_logic_vector(15 downto 0);
signal zero_flag: std_logic;
signal im_shift_1, PC_j, PC_beq, PC_4beq,PC_4beqj,PC_jr: std_logic_vector(15
downto 0);
signal beq_control: std_logic;
signal jump_shift_1: std_logic_vector(14 downto 0);
signal mem_read_data: std_logic_vector(15 downto 0);
signal no_sign_ext: std_logic_vector(15 downto 0);
signal sign_or_zero: std_logic;
signal tmp1: std_logic_vector(8 downto 0);
begin
48
SVIT ANANTAPUR
-- PC of the MIPS Processor in VHDL

process(clk,reset)
begin
if(reset='1') then
pc_current <= x"0000";
pc_current <= pc_next;
end if;
end process;
-- PC + 2
pc2 <= pc_current + x"0002";
-- instruction memory of the MIPS Processor in VHDL
Instruction_Memory: entity work.Instruction_Memory_VHDL
port map
(
pc=> pc_current,
instruction => instr
);
-- jump shift left 1
jump_shift_1 <= instr(13 downto 0) & '0';
-- control unit of the MIPS Processor in VHDL
control: entity work.control_unit_VHDL
port map
(reset => reset,
opcode => instr(15 downto 13),
reg_dst => reg_dst,
mem_to_reg => mem_to_reg,
alu_op => alu_op,
jump => jump,
branch => branch,
mem_read => mem_read,
mem_write => mem_write,
alu_src => alu_src,
reg_write => reg_write,
sign_or_zero => sign_or_zero
);
-- multiplexer regdest
49
SVIT ANANTAPUR
reg_write_dest <= "111" when reg_dst= "10" else

instr(6 downto 4) when reg_dst= "01" else
instr(9 downto 7);
-- register file instantiation of the MIPS Processor in VHDL
reg_read_addr_1 <= instr(12 downto 10);
reg_read_addr_2 <= instr(9 downto 7);
register_file: entity work.register_file_VHDL
port map
(
clk => clk,
rst => reset,
reg_write_en => reg_write,
reg_write_dest => reg_write_dest,
reg_write_data => reg_write_data,
reg_read_addr_1 => reg_read_addr_1,
reg_read_data_1 => reg_read_data_1,
reg_read_addr_2 => reg_read_addr_2,
reg_read_data_2 => reg_read_data_2
);
-- sign extend
tmp1 <= (others => instr(6));
sign_ext_im <= tmp1 & instr(6 downto 0);
zero_ext_im <= "000000000"& instr(6 downto 0);
imm_ext <= sign_ext_im when sign_or_zero='1' else zero_ext_im;
-- JR control unit of the MIPS Processor in VHDL
JRControl <= '1' when ((alu_op="00") and (instr(3 downto 0)="1000")) else
'0';
-- ALU control unit of the MIPS Processor in VHDL
ALUControl: entity work.ALU_Control_VHDL port map
(
ALUOp => alu_op,
ALU_Funct => instr(2 downto 0),
ALU_Control => ALU_Control
);
-- multiplexer alu_src
read_data2 <= imm_ext when alu_src='1' else reg_read_data_2;
-- ALU unit of the MIPS Processor in VHDL
50
SVIT ANANTAPUR
alu: entity work.ALU_VHDL port map

(
a => reg_read_data_1,
b => read_data2,
alu_control => ALU_Control,
alu_result => ALU_out,
zero => zero_flag
);
-- immediate shift 1
im_shift_1 <= imm_ext(14 downto 0) & '0';
no_sign_ext <= (not im_shift_1) + x"0001";
-- PC beq add
PC_beq <= (pc2 - no_sign_ext) when im_shift_1(15) = '1' else (pc2
+im_shift_1);
-- beq control
beq_control <= branch and zero_flag;
-- PC_beq
PC_4beq <= PC_beq when beq_control='1' else pc2;
-- PC_j
PC_j <= pc2(15) & jump_shift_1;
-- PC_4beqj
PC_4beqj <= PC_j when jump = '1' else PC_4beq;
-- PC_jr
PC_jr <= reg_read_data_1;
-- PC_next
pc_next <= PC_jr when (JRControl='1') else PC_4beqj;
-- data memory of the MIPS Processor in VHDL
data_memory: entity work.Data_Memory_VHDL port map
(
clk => clk,
mem_access_addr => ALU_out,
mem_write_data => reg_read_data_2,
mem_write_en => mem_write,
mem_read => mem_read,
mem_read_data => mem_read_data
);
-- write back of the MIPS Processor in VHDL
51
SVIT ANANTAPUR
reg_write_data <= pc2 when (mem_to_reg = "10") else

mem_read_data when (mem_to_reg = "01") else ALU_out;
-- output
pc_out <= pc_current;
alu_result <= ALU_out;
end Behavioral;
Output waveform:
20.VHDL code for traffic light

controller
AIM: To write VHDL code for traffic light controller
Apparatus: Linked pc with xilinx tool
52
SVIT ANANTAPUR
Circuit diagram:
VHDL CODE:
library IEEE;
-- Traffic ligh system for a intersection between
highway and farm way
-- There is a sensor on the farm way side, when there
are vehicles,
-- Traffic light turns to YELLOW, then GREEN to let the
vehicles cross the highway
-- Otherwise, always green light on Highway and Red
light on farm way
entity traffic_light_controller is
port ( sensor : in STD_LOGIC; -- Sensor
clk : in STD_LOGIC; -- clock
rst_n: in STD_LOGIC; -- reset active low
53
SVIT ANANTAPUR
light_highway : out STD_LOGIC_VECTOR(2 downto

0); -- light outputs of high way
light_farm: out STD_LOGIC_VECTOR(2 downto 0)--
light outputs of farm way
--RED_YELLOW_GREEN
);
end traffic_light_controller;
architecture traffic_light of traffic_light_controller
is
signal counter_1s: std_logic_vector(27 downto 0):=
x"0000000";
signal delay_count:std_logic_vector(3 downto 0):= x"0";
signal delay_10s, delay_3s_F,delay_3s_H,
RED_LIGHT_ENABLE,
YELLOW_LIGHT1_ENABLE,YELLOW_LIGHT2_ENABLE:
std_logic:='0';
signal clk_1s_enable: std_logic; -- 1s clock enable
type FSM_States is (HGRE_FRED, HYEL_FRED, HRED_FGRE,
HRED_FYEL);
-- HGRE_FRED : Highway green and farm red
-- HYEL_FRED : Highway yellow and farm red
-- HRED_FGRE : Highway red and farm green
-- HRED_FYEL : Highway red and farm yellow
signal current_state, next_state: FSM_States;
begin
-- next state FSM sequential logic
process(clk,rst_n)
begin
if(rst_n='0') then
current_state <= HGRE_FRED;
current_state <= next_state;
end if;
end process;
-- FSM combinational logic
process(current_state,sensor,delay_3s_F,delay_3s_H,dela
y_10s)
54
SVIT ANANTAPUR
begin
case current_state is
when HGRE_FRED => -- When Green light on Highway and
Red light on Farm way
RED_LIGHT_ENABLE <= '0';-- disable RED light delay
counting
YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light
Highway delay counting
Farmway delay counting
light_highway <= "001"; -- Green light on Highway
light_farm <= "100"; -- Red light on Farm way
if(sensor = '1') then -- if vehicle is detected on
farm way by sensors
next_state <= HYEL_FRED;
-- High way turns to Yellow light
else
next_state <= HGRE_FRED;
-- Otherwise, remains GREEN ON highway and RED on
Farm way
end if;
when HYEL_FRED => -- When Yellow light on Highway and
Red light on Farm way
light_highway <= "010";-- Yellow light on Highway
light_farm <= "100";-- Red light on Farm way
RED_LIGHT_ENABLE <= '0';-- disable RED light delay
counting
YELLOW_LIGHT1_ENABLE <= '1';-- enable YELLOW light
if(delay_3s_H='1') then
-- if Yellow light delay counts to 3s,
-- turn Highway to RED,
-- Farm way to green light
next_state <= HRED_FGRE;
else
55
SVIT ANANTAPUR
next_state <= HYEL_FRED;

-- Remains Yellow on highway and Red on Farm way
-- if Yellow light not yet in 3s
end if;
when HRED_FGRE =>
light_highway <= "100";-- RED light on Highway
light_farm <= "001";-- GREEN light on Farm way
RED_LIGHT_ENABLE <= '1';-- enable RED light delay
counting
if(delay_10s='1') then
-- if RED light on highway is 10s, Farm way turns to
Yellow
next_state <= HRED_FYEL;
else
next_state <= HRED_FGRE;
-- Remains if delay counts for RED light on highway
not enough 10s
end if;
when HRED_FYEL =>
light_highway <= "100";-- RED light on Highway
light_farm <= "010";-- Yellow light on Farm way
RED_LIGHT_ENABLE <= '0'; -- disable RED light delay
counting
YELLOW_LIGHT2_ENABLE <= '1';-- enable YELLOW light
if(delay_3s_F='1') then
-- if delay for Yellow light is 3s,
-- turn highway to GREEN light
-- Farm way to RED Light
next_state <= HGRE_FRED;
else
56
SVIT ANANTAPUR
next_state <= HRED_FYEL;

-- if not enough 3s, remain the same state
end if;
when others => next_state <= HGRE_FRED; -- Green on
highway, red on farm way
end case;
end process;
-- Delay counts for Yellow and RED light
process(clk)
begin
if(clk_1s_enable='1') then
if(RED_LIGHT_ENABLE='1' or YELLOW_LIGHT1_ENABLE='1' or
YELLOW_LIGHT2_ENABLE='1') then
delay_count <= delay_count + x"1";
if((delay_count = x"9") and RED_LIGHT_ENABLE ='1')
then
delay_10s <= '1';
delay_3s_H <= '0';
delay_3s_F <= '0';
delay_count <= x"0";
elsif((delay_count = x"2") and YELLOW_LIGHT1_ENABLE=
'1') then
delay_10s <= '0';
delay_3s_H <= '1';
delay_3s_F <= '0';
elsif((delay_count = x"2") and YELLOW_LIGHT2_ENABLE=
'1') then
delay_10s <= '0';
delay_3s_H <= '0';
delay_3s_F <= '1';
else
delay_10s <= '0';
delay_3s_H <= '0';
delay_3s_F <= '0';
57
SVIT ANANTAPUR
end if;
end if;
end if;
end if;
end process;
-- create delay 1s
process(clk)
begin
counter_1s <= counter_1s + x"0000001";
if(counter_1s >= x"0000003") then -- x"0004" is for
simulation
-- change to x"2FAF080" for 50 MHz clock running real
FPGA
counter_1s <= x"0000000";
end if;
end if;
end process;
clk_1s_enable <= '1' when counter_1s = x"0003" else
'0'; -- x"0002" is for simulation
-- x"2FAF080" for 50Mhz clock on FPGA
end traffic_light;
VHDL Testbench code for traffic light controller:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Testbench VHDL code for traffic light controller
ENTITY tb_traffic_light_controller IS
END tb_traffic_light_controller;
ARCHITECTURE behavior OF tb_traffic_light_controller IS

-- Component Declaration for the traffic light controller
COMPONENT traffic_light_controller
PORT(
sensor : IN std_logic;
clk : IN std_logic;
rst_n : IN std_logic;
light_highway : OUT std_logic_vector(2 downto 0);
light_farm : OUT std_logic_vector(2 downto 0)
58
SVIT ANANTAPUR
);
END COMPONENT;
signal sensor : std_logic := '0';
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
--Outputs
signal light_highway : std_logic_vector(2 downto 0);
signal light_farm : std_logic_vector(2 downto 0);
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the traffic light controller
trafficlightcontroller : traffic_light_controller PORT MAP (
sensor => sensor,
clk => clk,
rst_n => rst_n,
light_highway => light_highway,
light_farm => light_farm
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
rst_n <= '0';
sensor <= '0';
wait for clk_period*10;
rst_n <= '1';
sensor <= '1';
sensor <= '0';
wait;
end process;
END;
Output waveform:
59
SVIT ANANTAPUR
60
SVIT ANANTAPUR
MINI PROJECT
Bluetooth Based Wireless Home Automation System

Using Spartan3an FPGA Starter Kit
ABSTRACT
Technology advancements have made possible the implementation of
embedded systems within home appliances. This has added new capabilities
and features, however, most of the time, the implementations are proprietary
and networking is not always possible. Yet there is an increasing demand for
smart homes, where appliances react automatically to changing
environmental conditions and can be easily controlled through one common
device. This paper presents a possible solution whereby the user controls
devices by employing a central Field Programmable Gate Array (FPGA)
controller to which the devices and sensors are interfaced. Control is
communicated to the FPGA from a mobile phone through
its Bluetooth interface. This results in a simple, cost effective, and flexible
system, making it a good candidate for future smart home solutions.
61
SVIT ANANTAPUR
Demonstration Video
BLOCK DIAGRAM
Home Section
Introduction
The Bluetooth wireless technology is set to revolutionize the way people
perceive digital devices in our homes and ofﬁce environment. Now they are
no longer just the individual devices; instead, with the embedded Bluetooth
technology, they form a network in which appliances can communicate with
each other. This wireless technology is especially useful in home
environment, where there exists hardly any infrastructure to interconnect
intelligent appliances. It could be suitably used for home automation in a
cost-effective manner. Operating over unlicensed, universally available
frequency of 2.4 GHz, it can link digital devices within a range of 10 m
(expandable to 100 m, by increasing the transmitted power) at the speed of 1
Mbps. Building upon this theme; we propose a home automation system
based on Bluetooth . technology There are certain issues involved in the
design of a home automation system. The system should be scalable, so that
new device can easily be integrated into it. It should provide a user-friendly
interface on the host side, so that the devices can be setup, monitored and
controlled. The interface should also provide some diagnostic services so
62
SVIT ANANTAPUR
those problems with the system, if any, can be tracked down. The overall
system should be fast enough to realize the true power of wireless
technology. It should also be cost effective in order to justify its application
in home automation.
The system developed consists of android mobile phone and a FPGA based
Door Lock open/close system and relay on/off to control electrical Appliance,
that is able to communicate with the host through the Bluetooth link.
Host and client modules in Bluetooth piconet

Bluetooth home automation mobile software
The Bluetooth home automation mobile software module provides two main

services to the users, namely:
 Device Registration
 Device Control
Hardware design and development
A Door Lock open/close system and relay on/off to control electrical
Appliance circuitry has been developed to demonstrate the feasibility and
effectiveness of the application. The hardware interface component of
the Bluetooth based home automation system consists of a FPGA with
stepper motor, relay interface and an RS232 link between the FPGA and
the Bluetooth .
Tool required
 Software: Xilinx ISE 10.1i or above
 Language: VHDL
 Hardware:
1.Spartan3an FPGA kit
2. Bluetooth Module
3.JTAG Cable
4. Serial Cable
5.Stepper Motor
6.Relay
Bluetooth Based Wireless Home Automation System Output

Image
63
SVIT ANANTAPUR

Source Code
library IEEE;
entity uart_stepper is
port ( clk : in std_logic;
din : in std_logic;
relay : out std_logic:='0';
count : out STD_LOGIC_vector(3 downto 0)
);
end uart_stepper;
architecture Behavioral of uart_stepper is
type state is (ready,b0);
signal ps : state := ready;
signal start,stop : std_logic;
64
SVIT ANANTAPUR
signal store : std_logic_vector(7 downto 0) := "10101010";
type state1 is (a0,a1);
signal ps1,ps2 : state1 := a0;
signal s_count:std_logic_vector(3 downto 0);
begin
process(clk)
variable i : integer := 0 ;
begin
if clk'event and clk = '1' then
if ps = ready then
start <= din;
end if;
if start = '0' then
ps <= b0;
elsif start = '1' then
ps <= ready;
end if;
------------------------------------------1
if ps = b0 then
i := i + 1;
65
SVIT ANANTAPUR
if i = 2600 then
start <= din;
end if;
if i = 7800 then
store(0) <= din;
end if;
if i = 13000 then
store(1) <= din;
end if;
if i = 18200 then
store(2) <= din;
end if;
if i = 23400 then
store(3) <= din;
end if;
if i = 28600 then
store(4) <= din;
end if;
if i = 33800 then
store(5) <= din;
end if;
if i = 39000 then
66
SVIT ANANTAPUR
store(6) <= din;
end if;
if i = 44200 then
store(7) <= din;
end if;
if i = 49400 then
stop <= din;
end if;
if i = 54600 then
i := 0 ;
ps <= ready ;
end if;
end if;
end if;
end process;
process(clk,store)
variable j,k,l,m:integer:=0;
begin
if clk'event and clk = '1' then
if store = x"33" then
67
SVIT ANANTAPUR
if(ps1=a0)then
j:=j+1;
if(j=500000)then
s_count<="1000";
end if;
if(j=1000000)then
s_count<="0100";
end if;
if(j=1500000)then
s_count<="0010";
end if;
if(j=2000000)then
s_count<="0001";
j:=0;
if k
68
SVIT ANANTAPUR
Conclusion
Home Automation is undeniably a resource which can make a home

environment automated. People can control their electrical devices via these
Home Automation devices and set up the controlling actions in the mobile.
We think this product have high potential for marketing in the future.
69
SVIT ANANTAPUR

4BIT ALU DESIGN

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4BIT ALU DESIGN

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M.

TECH-ECE-VLSI & EMBEDDED SYSTEMS STRUCTURAL DIGITAL SYSTEM DESIGN LAB

Design of 4 Bit Subtractor using Structural Modeling

architecture subtractor_4bit_arc of subtractor_4bit is

signal s : std_logic_vector (2 downto 0);

end subtractor_4bit_arc;

---------------- Full Adder Design ----------------------

Output Waveform : 4 Bit Subtractor

2. VHDL code for booth multiplier

AIM: To write a vhdl code for booth multiplier

Apparatus: Pc linked with xilinx tool

3. VHDL Code for 4-bit ALU

Aim: To write a vhdl code for 4bit alu

Testbench VHDL Code for 4-Bit ALU

inp_b : IN signed(3 downto 0);

Simulation Result for 4-bit ALU

4. Design of 4 Bit Serial IN - Serial OUT Shift Register

AIM: To simulate the design of 4 bit serial in -serial out shift

Apparatus: Pc linked with xilinx tool

architecture siso_behavior_arc of siso_behavior is

siso : process (clk,din,reset) is

Output Waveform : Serial IN - Serial OUT Shift Register

5. Design of 4 Bit Serial IN - Parallel OUT Shift

Apparatus: Pc linked with xilinx tool

architecture sipo_behavior_arc of sipo_behavior is

sipo : process (clk,din,reset) is

Output Waveform : Serial IN - Parallel OUT Shift

6.Design of Parallel IN - Serial OUT Shift Register

AIM: To simulate and design of parallel in -serial out shift

Apparatus: Pc linked with xilinx tool

architecture piso_arc of parallel_in_serial_out is

piso : process (clk,reset,load,din) is

Output Waveform : Parallel IN - Serial OUT Shift Register

7.Design of 4 Bit Parallel IN - Parallel OUT Shift

Aim: To simulate and design of 4 bit parallel in - parallel out shift

Apparatus: Pc linked with xilinx tool

architecture pipo_behavior_arc of pipo_behavior is

pipo : process (clk,din,reset) is

Output Waveform : 4 Bit parallel IN - Parallel OUT Shift

8. VHDL Code for 4 bit Ring Counter

Aim: To write a code for 4 bit ring counter

9:VHDL code for up counter:

Aim: To write a vhdl code for up counter

architecture Behavioral of UP_COUNTER is

architecture Behavioral of tb_counters is

10. VHDL code for down counter:

Aim: To write a vhdl code for down counter

architecture Behavioral of DOWN_COUNTER is

signal counter_down: std_logic_vector(3 downto 0);

11. 4-bit Ring Counter using D

Aim: To simulate and design a 4 bit ring counter using D flipflop

12. 4-bit Johnson Counter using D

temp(1) <= temp(0);

13.VHDL code for Data Memory of the

architecture Behavioral of Data_Memory_VHDL is

ram_addr <= mem_access_addr(8 downto 1);

mem_read_data <= ram(to_integer(unsigned(ram_addr))) when (mem_read='1')

14.VHDL code for ALU of the MIPS

Aim: To write a vhdl code for alu of the MIPS processor

architecture Behavioral of ALU_VHDL is

result <= x"0001";

15. VHDL code for ALU Control

architecture Behavioral of ALU_Control_VHDL is