EXPERIMENT 7

AIM - design synthesize and stimulate 2*4 and 3*8 decoder

ACTIVITY 1

2*4 DECODER :VHDL CODE :library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity hp_deco_24 is
Port ( X,Y : in STD_LOGIC;
O : out STD_LOGIC_vector(3 downto 0));
end hp_deco_24;
architecture Behavioral of hp_deco_24 is
begin
O(3) <= (not X) and (not Y);
O(2) <= (not X) and Y;
O(1) <= X and (not Y);
O(0) <= X and Y;
end Behavioral;

TEST BENCH CODE:-- Create Date: 00:44:14 04/14/2015

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hp_deco24_tb IS
END hp_deco24_tb;
ARCHITECTURE behavior OF hp_deco24_tb IS
COMPONENT hp_deco_24
PORT(
X : IN std_logic;
Y : IN std_logic;

O : OUT std_logic_vector(3 downto 0)

);
END COMPONENT;
signal X : std_logic := '0';
signal Y : std_logic := '0';
--Outputs
signal O : std_logic_vector(3 downto 0);
BEGIN
uut: hp_deco_24 PORT MAP (
X => X,
Y => Y,
O => O
);
stim_proc : process
-- Stimulus process
begin
-- hold reset state for 100 ns.
X<='0';Y<='0'; wait for 100 ns;
X<='0';Y<='1'; wait for 100 ns;
X<='1';Y<='0'; wait for 100 ns;
X<='1';Y<='1';
wait;
end process;
END;

Synthesis result

:-

BELS
LUT2

4
4

IO BUFFERS
OBUF
IBUF
DELAY

6
4
2
7.167 ns

ACTIVITY 2
3*8 DECODER:CODElibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hp_deco_38 is
Port ( a,b,c : in STD_LOGIC;
z : out STD_LOGIC_vector(7 downto 0));
end hp_deco_38;
architecture Behavioral of hp_deco_38 is
component hp_deco_24
port (X, Y: in STD_LOGIC;
O: out STD_LOGIC_vector(3 downto 0));
end component;
signal X1: STD_LOGIC_vector(3 downto 0);
begin
hpdeco24:hp_deco_24 port map(X => a, Y => b, O(3 downto 0) => X1 (3 downto
0));
z(0) <= X1(0) and c;
z(1) <= X1(1) and c;
z(2) <= X1(2) and c;
z(3) <= X1(3) and c;
z(4) <= X1(0) and (not c);

z(5) <= X1(1) and (not c);

z(6) <= X1(2) and (not c);
z(7) <= X1(3) and (not c);
end Behavioral ;

TEST BENCH :LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
ENTITY decoder_38_tb IS
END decoder_38_tb;
ARCHITECTURE behavior OF decoder_38_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hp_deco_38
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
z : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
--Outputs
signal z : std_logic_vector(7 downto 0);
BEGIN
uut: hp_deco_38 PORT MAP (
a => a,
b => b,

c => c,
z => z
);
-- Simulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a<='0';b<='0';c<='0';
wait for 100 ns;
a<='0';b<='0';c<='1'; wait for 100 ns;
a<='0';b<='1';c<='0'; wait for 100 ns
a<='0';b<='1';c<='1';
wait for 100 ns;
a<='1';b<='0';c<='0';
wait for 100 ns;
a<='1';b<='0';c<='1';
wait for 100 ns;
a<='1';b<='1';c<='0';
wait for 100 ns;
a<='1';b<='1';c<='1';
-- insert stimulus here
wait;
end process;
END;
RESULT

synthesis table :BELS

LUT3
IO BUFFERS
IBUF
OBUF
DELAY

8
8
11
3
8
7.337 ns

CONCLUSION :- It was my pleasure to learn and stimulate decoder under the

guidance of Mr Sujeet sir .
With the help of prior theoretical knowledge of decoder (2*4 and
3*8) we were able
perform it on Xilinx software.